From b3fe634c8b7f7d3ddc517290a2da908728a13a4b Mon Sep 17 00:00:00 2001 From: Ryan Houdek Date: Mon, 14 Sep 2026 15:12:03 -0700 Subject: [PATCH] OpcodeDispatcher: Remove SRC_RAX from moffset MOV --- FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp | 6 +++--- FEXCore/Source/Interface/Core/X86Tables/BaseTables.cpp | 8 ++++---- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp index af0a809c8..88ca02a47 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp @@ -1318,18 +1318,18 @@ void OpDispatchBuilder::MOVOffsetOp(OpcodeArgs) { // Source is memory(literal) // Dest is GPR auto Src = LoadSourceGPR(Op, Op->Src[0], Op->Flags, {.ForceLoad = true}); - StoreResultGPR(Op, Op->Dest, Src); + StoreGPRResultWithZExtSemantics(X86State::REG_RAX, Src, OpSizeFromDst(Op)); break; } case 0xA2: case 0xA3: { // Source is GPR // Dest is memory(literal) - Ref Src = LoadSourceGPR(Op, Op->Src[0], Op->Flags, {.AllowUpperGarbage = true}); + Ref Src = LoadGPRRegister(X86State::REG_RAX); // This one is a bit special since the destination is a literal // So the destination gets stored in Src[1] - StoreResultGPR(Op, Op->Src[1], Src); + StoreResultGPR(Op, Op->Src[0], Src); break; } } diff --git a/FEXCore/Source/Interface/Core/X86Tables/BaseTables.cpp b/FEXCore/Source/Interface/Core/X86Tables/BaseTables.cpp index bfc5e2f2a..e8a27ccee 100644 --- a/FEXCore/Source/Interface/Core/X86Tables/BaseTables.cpp +++ b/FEXCore/Source/Interface/Core/X86Tables/BaseTables.cpp @@ -144,13 +144,13 @@ constexpr std::array Primary_ArchSelect_LUT = {{ }, // ENTRY_A2 { - {"MOV", TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_SF_SRC_RAX | FLAGS_MEM_OFFSET, 4, { .OpDispatch = &IR::OpDispatchBuilder::MOVOffsetOp } }, - {"MOV", TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_SF_SRC_RAX | FLAGS_MEM_OFFSET, 8, { .OpDispatch = &IR::OpDispatchBuilder::MOVOffsetOp } }, + {"MOV", TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_MEM_OFFSET, 4, { .OpDispatch = &IR::OpDispatchBuilder::MOVOffsetOp } }, + {"MOV", TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_MEM_OFFSET, 8, { .OpDispatch = &IR::OpDispatchBuilder::MOVOffsetOp } }, }, // ENTRY_A3 { - {"MOV", TYPE_INST, FLAGS_SF_SRC_RAX | FLAGS_MEM_OFFSET | FLAGS_LITERAL_PATCHABLE, 4, { .OpDispatch = &IR::OpDispatchBuilder::MOVOffsetOp } }, - {"MOV", TYPE_INST, FLAGS_SF_SRC_RAX | FLAGS_MEM_OFFSET | FLAGS_LITERAL_PATCHABLE, 8, { .OpDispatch = &IR::OpDispatchBuilder::MOVOffsetOp } }, + {"MOV", TYPE_INST, FLAGS_MEM_OFFSET | FLAGS_LITERAL_PATCHABLE, 4, { .OpDispatch = &IR::OpDispatchBuilder::MOVOffsetOp } }, + {"MOV", TYPE_INST, FLAGS_MEM_OFFSET | FLAGS_LITERAL_PATCHABLE, 8, { .OpDispatch = &IR::OpDispatchBuilder::MOVOffsetOp } }, }, // ENTRY_CE {