steam-frame/FEX-Emu--FEX
1
0 Fork 0
mirror of https://github.com/FEX-Emu/FEX.git synced 2026-10-14 08:00:50 +02:00
Code Issues Packages Projects Releases 67 Wiki Activity

Fixes issues with PSLLDQ and PSRLDQ

Browse Source 
These are whole vector shift instructions and they shift by bytes rather
than bits.
You only get an immediate offset for the instruction.
Implements two new IR ops to account for these instructions

This also doesn't match AArch64 behaviour 100%, requires two
instructions to emulate rather than the single one on the x86-side
This commit is contained in:
Ryan Houdek authored and Stefanos Kornilios Mitsis Poiitidis committed 2020-03-06 07:55:59 +02:00
1 parent af6eefb495
commit afdbd9ebdc
6 files changed
+93 -8
Download Patch File Download Diff File Expand all files Collapse all files

No files matched your search

Source/Interface/Core/Interpreter/InterpreterCore.cpp
+19
View File
@@ -1022,6 +1022,25 @@ void InterpreterCore::ExecuteCode(FEXCore::Core::InternalThreadState *Thread) {
memcpy(GDP, &Dst, 16);
break;
}
case IR::OP_VSLI: {
auto Op = IROp->C<IR::IROp_VSLI>();
__uint128_t Src1 = *GetSrc<__uint128_t*>(Op->Header.Args[0]);
__uint128_t Src2 = Op->ByteShift;
__uint128_t Dst = Src1 << (Src2 * 8);
memcpy(GDP, &Dst, 16);
break;
}
case IR::OP_VSRI: {
auto Op = IROp->C<IR::IROp_VSRI>();
__uint128_t Src1 = *GetSrc<__uint128_t*>(Op->Header.Args[0]);
__uint128_t Src2 = Op->ByteShift;
__uint128_t Dst = Src1 >> (Src2 * 8);
memcpy(GDP, &Dst, 16);
break;
}
#define DO_VECTOR_OP(size, type, func) \
case size: { \
auto *Dst_d = reinterpret_cast<type*>(Tmp); \