From 1fb2419be21319d29893b1d27def586c3c636e1a Mon Sep 17 00:00:00 2001 From: LC Date: Mon, 22 Jun 2026 09:47:43 -0400 Subject: [PATCH] Vector: Remove unused OpcodeArgs parameter from SHUFOpImpl No behavior change, just a reduction in noise. --- FEXCore/Source/Interface/Core/OpcodeDispatcher.h | 2 +- .../Source/Interface/Core/OpcodeDispatcher/AVX_128.cpp | 4 ++-- FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp | 8 ++++---- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher.h b/FEXCore/Source/Interface/Core/OpcodeDispatcher.h index ecfad62a5..482ccce8a 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher.h +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher.h @@ -1418,7 +1418,7 @@ private: Ref PSRLDOpImpl(OpcodeArgs, IR::OpSize ElementSize, Ref Src, Ref ShiftVec); - Ref SHUFOpImpl(OpcodeArgs, IR::OpSize DstSize, IR::OpSize ElementSize, Ref Src1, Ref Src2, uint8_t Shuffle); + Ref SHUFOpImpl(IR::OpSize DstSize, IR::OpSize ElementSize, Ref Src1, Ref Src2, uint8_t Shuffle); void VMASKMOVOpImpl(OpcodeArgs, IR::OpSize ElementSize, IR::OpSize DataSize, bool IsStore, const X86Tables::DecodedOperand& MaskOp, const X86Tables::DecodedOperand& DataOp); diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher/AVX_128.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher/AVX_128.cpp index 1d399b0aa..1247e0dea 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher/AVX_128.cpp +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher/AVX_128.cpp @@ -1399,13 +1399,13 @@ void OpDispatchBuilder::AVX128_VSHUF(OpcodeArgs, IR::OpSize ElementSize) { auto Src2 = AVX128_LoadSource_WithOpSize(Op, Op->Src[1], Op->Flags, !Is128Bit); RefPair Result {}; - Result.Low = SHUFOpImpl(Op, OpSize::i128Bit, ElementSize, Src1.Low, Src2.Low, Shuffle); + Result.Low = SHUFOpImpl(OpSize::i128Bit, ElementSize, Src1.Low, Src2.Low, Shuffle); if (Is128Bit) { Result.High = LoadZeroVector(OpSize::i128Bit); } else { const uint8_t ShiftAmount = ElementSize == OpSize::i32Bit ? 0 : 2; - Result.High = SHUFOpImpl(Op, OpSize::i128Bit, ElementSize, Src1.High, Src2.High, Shuffle >> ShiftAmount); + Result.High = SHUFOpImpl(OpSize::i128Bit, ElementSize, Src1.High, Src2.High, Shuffle >> ShiftAmount); } AVX128_StoreResult_WithOpSize(Op, Op->Dest, Result); } diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp index 37e34320e..943172c1e 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp @@ -1764,7 +1764,7 @@ void OpDispatchBuilder::VPSHUFWOp(OpcodeArgs, IR::OpSize ElementSize, bool Low) StoreResultFPR(Op, Result); } -Ref OpDispatchBuilder::SHUFOpImpl(OpcodeArgs, IR::OpSize DstSize, IR::OpSize ElementSize, Ref Src1, Ref Src2, uint8_t Shuffle) { +Ref OpDispatchBuilder::SHUFOpImpl(IR::OpSize DstSize, IR::OpSize ElementSize, Ref Src1, Ref Src2, uint8_t Shuffle) { // Since 256-bit variants and up don't lane cross, we can construct // everything in terms of the 128-variant, as each lane is essentially // its own 128-bit segment. @@ -1976,7 +1976,7 @@ void OpDispatchBuilder::SHUFOp(OpcodeArgs, IR::OpSize ElementSize) { Ref Src2Node = LoadSourceFPR(Op, Op->Src[0], Op->Flags); uint8_t Shuffle = Op->Src[1].Literal(); - Ref Result = SHUFOpImpl(Op, OpSizeFromDst(Op), ElementSize, Src1Node, Src2Node, Shuffle); + Ref Result = SHUFOpImpl(OpSizeFromDst(Op), ElementSize, Src1Node, Src2Node, Shuffle); StoreResult_WithAVXInsert(VectorOpType::SSE, RegClass::FPR, Op, Result); } @@ -1985,7 +1985,7 @@ void OpDispatchBuilder::VSHUFOp(OpcodeArgs, IR::OpSize ElementSize) { Ref Src2Node = LoadSourceFPR(Op, Op->Src[1], Op->Flags); uint8_t Shuffle = Op->Src[2].Literal(); - Ref Result = SHUFOpImpl(Op, OpSizeFromDst(Op), ElementSize, Src1Node, Src2Node, Shuffle); + Ref Result = SHUFOpImpl(OpSizeFromDst(Op), ElementSize, Src1Node, Src2Node, Shuffle); StoreResultFPR(Op, Result); } @@ -5178,7 +5178,7 @@ void OpDispatchBuilder::VPERMILImmOp(OpcodeArgs, IR::OpSize ElementSize) { Ref Result {}; if (ElementSize == OpSize::i64Bit) { - Result = SHUFOpImpl(Op, DstSize, ElementSize, Src, Src, Selector); + Result = SHUFOpImpl(DstSize, ElementSize, Src, Src, Selector); } else { if (Is256Bit) { auto UpperLane = _VDupElement(OpSize::i256Bit, OpSize::i128Bit, Src, 1);