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FEX: Adds instruction count CI
Implements CI for tracking instruction counts for generate blocks of code when transforming from x86 to ARM64 assembly. This will end up encompassing every instruction in our instruction tables similarly to how our assembly tests try to test everything in our instruction tables. Incidentally, the data for this CI is generated using our assembly tests. By enabling disassembly and instruction stats when executing a suite of instructions, this gives the stats that can be added to a json file. The current implementation only implements the SecondGroup table of instructions because it is a relatively small table and has known inefficiencies in the instruction implementations. As this gets merged I will be adding more tables of instructions to additional json files for testing. These JSON files will support adjusting CPU features regardless of the host features so it can test implementations depending on different CPU features. This will let us test things like one instruction having different "optimal" implementations depending on if it supports SVE128, SVE256, SVEI8MM, etc. This initial instruction auditing is what found the bug in our vector shift instructions by size of zero. If inspecting the result of the CI run, you can tell that these instructions still aren't "optimal" because they are doing loads and stores that can be eliminated. The "Optimal" in the JSON is purely for human readable and grepping ability to see what is optimal versus not. Same with the "Comment" section. According to my auditing spreadsheet, the total number of instructions that will end up in these json files will be about 1000, but we will likely end up with more since there will be edge cases that can be more optimal depending on arguments.
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Ryan Houdek committed
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@@ -0,0 +1,432 @@
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#include "DummyHandlers.h"
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#include "FEXCore/Core/Context.h"
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#include "FEXCore/Debug/InternalThreadState.h"
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#include <FEXCore/Config/Config.h>
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#include <FEXCore/Utils/Allocator.h>
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#include <FEXCore/Utils/File.h>
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#include <FEXCore/Utils/FileLoading.h>
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#include <FEXCore/Utils/LogManager.h>
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namespace CodeSize {
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class CodeSizeValidation final {
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public:
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struct InstructionStats {
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uint64_t GuestCodeInstructions{};
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uint64_t HostCodeInstructions{};
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uint64_t HeaderSize{};
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uint64_t TailSize{};
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};
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using CodeLines = fextl::vector<fextl::string>;
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using InstructionData = std::pair<InstructionStats, CodeLines>;
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bool ParseMessage(char const *Message);
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InstructionData *GetDataForRIP(uint64_t RIP) {
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return &RIPToStats[RIP];
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}
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bool InfoPrintingDisabled() const {
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return SetupInfoDisabled;
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}
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void CalculateBaseStats(FEXCore::Context::Context *CTX, FEXCore::Core::InternalThreadState *Thread);
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private:
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void ClearStats() {
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RIPToStats.clear();
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}
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void SetBaseStats(InstructionStats const &NewBase) {
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BaseStats = NewBase;
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}
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void CalculateDifferenceBetweenStats(InstructionData *Nop, InstructionData *Fence);
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uint64_t CurrentRIPParse{};
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bool ConsumingDisassembly{};
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InstructionData *CurrentStats{};
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InstructionStats BaseStats{};
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fextl::unordered_map<uint64_t, InstructionData> RIPToStats;
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bool SetupInfoDisabled{};
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};
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constexpr std::string_view RIPMessage = "RIP: 0x";
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constexpr std::string_view GuestCodeMessage = "Guest Code instructions: ";
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constexpr std::string_view HostCodeMessage = "Host Code instructions: ";
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constexpr std::string_view DisassembleBeginMessage = "Disassemble Begin";
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constexpr std::string_view DisassembleEndMessage = "Disassemble End";
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constexpr std::string_view BlowUpMsg = "Blow-up Amt: ";
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bool CodeSizeValidation::ParseMessage(char const *Message) {
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// std::string_view doesn't have contains until c++23.
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std::string_view MessageView {Message};
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if (MessageView.find(RIPMessage) != MessageView.npos) {
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// New RIP found
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std::string_view RIPView = std::string_view{Message + RIPMessage.size()};
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std::from_chars(RIPView.data(), RIPView.end(), CurrentRIPParse, 16);
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CurrentStats = &RIPToStats[CurrentRIPParse];
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return false;
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}
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if (MessageView.find(GuestCodeMessage) != MessageView.npos) {
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std::string_view CodeSizeView = std::string_view{Message + GuestCodeMessage.size()};
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std::from_chars(CodeSizeView.data(), CodeSizeView.end(), CurrentStats->first.GuestCodeInstructions);
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return false;
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}
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if (MessageView.find(HostCodeMessage) != MessageView.npos) {
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std::string_view CodeSizeView = std::string_view{Message + HostCodeMessage.size()};
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std::from_chars(CodeSizeView.data(), CodeSizeView.end(), CurrentStats->first.HostCodeInstructions);
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CurrentStats->first.HostCodeInstructions -= BaseStats.HostCodeInstructions;
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return false;
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}
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if (MessageView.find(DisassembleBeginMessage) != MessageView.npos) {
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ConsumingDisassembly = true;
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// Just so the output isn't a mess.
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return false;
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}
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if (MessageView.find(DisassembleEndMessage) != MessageView.npos) {
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ConsumingDisassembly = false;
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// Just so the output isn't a mess.
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// Remove the header and tails.
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if (BaseStats.HeaderSize) {
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CurrentStats->second.erase(CurrentStats->second.begin(), CurrentStats->second.begin() + BaseStats.HeaderSize);
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}
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if (BaseStats.TailSize) {
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CurrentStats->second.erase(CurrentStats->second.end() - BaseStats.TailSize, CurrentStats->second.end());
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}
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return false;
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}
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if (MessageView.find(BlowUpMsg) != MessageView.npos) {
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return false;
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}
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if (ConsumingDisassembly) {
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// Currently consuming disassembly. Each line will be a single line of disassembly.
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CurrentStats->second.push_back(Message);
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return false;
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}
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return true;
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}
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void CodeSizeValidation::CalculateDifferenceBetweenStats(InstructionData *Nop, InstructionData *Fence) {
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// Expected format.
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// adr x0, #-0x4 (addr 0x7fffe9880054)
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// str x0, [x28, #184]
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// dmb sy
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// ldr x0, pc+8 (addr 0x7fffe988006c)
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// blr x0
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// unallocated (Unallocated)
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// udf #0x7fff
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// unallocated (Unallocated)
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// udf #0x0
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//
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// First two lines are the header.
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// Next comes the implementation (0 instruction size for nop, 1 instruction for fence)
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// After that is the tail.
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const auto &NOPCode = Nop->second;
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const auto &FENCECode = Fence->second;
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LOGMAN_THROW_A_FMT(NOPCode.size() < FENCECode.size(), "NOP code must be smaller than fence!");
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for (size_t i = 0; i < NOPCode.size(); ++i) {
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const auto &NOPLine = NOPCode.at(i);
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const auto &FENCELine = FENCECode.at(i);
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const auto NOPmnemonic = std::string_view(NOPLine.data(), NOPLine.find(' '));
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const auto FENCEmnemonic = std::string_view(FENCELine.data(), FENCELine.find(' '));
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if (NOPmnemonic != FENCEmnemonic) {
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// Headersize of a block is now `i` number of instructions.
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Nop->first.HeaderSize = i;
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// Tail size is going to be the remaining size
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Nop->first.TailSize = NOPCode.size() - i;
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break;
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}
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}
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SetBaseStats(Nop->first);
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}
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void CodeSizeValidation::CalculateBaseStats(FEXCore::Context::Context *CTX, FEXCore::Core::InternalThreadState *Thread) {
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SetupInfoDisabled = true;
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// Known hardcoded instructions that will generate blocks of particular sizes.
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// NOP will never generate any instructions.
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constexpr static uint8_t NOP[] = {
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0x90,
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};
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// MFENCE will always generate a block with one instruction.
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constexpr static uint8_t MFENCE[] = {
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0x0f, 0xae, 0xf0,
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};
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// Compile the NOP.
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CTX->CompileRIP(Thread, (uint64_t)NOP);
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// Gather the stats for the NOP.
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auto NOPStats = GetDataForRIP((uint64_t)NOP);
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// Compile MFence
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CTX->CompileRIP(Thread, (uint64_t)MFENCE);
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// Get MFence stats.
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auto MFENCEStats = GetDataForRIP((uint64_t)MFENCE);
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// Now scan the difference in disasembly between NOP and MFENCE to remove the header and tail.
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// Just searching for first instruction change.
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CalculateDifferenceBetweenStats(NOPStats, MFENCEStats);
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// Now that the stats have been cleared. Clear our currentStats.
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ClearStats();
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// Invalidate the code ranges to be safe.
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CTX->InvalidateGuestCodeRange(Thread, (uint64_t)NOP, sizeof(NOP));
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CTX->InvalidateGuestCodeRange(Thread, (uint64_t)MFENCE, sizeof(MFENCE));
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SetupInfoDisabled = false;
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}
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static CodeSizeValidation Validation{};
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}
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void MsgHandler(LogMan::DebugLevels Level, char const *Message) {
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const char *CharLevel{nullptr};
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switch (Level) {
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case LogMan::NONE:
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CharLevel = "NONE";
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break;
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case LogMan::ASSERT:
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CharLevel = "ASSERT";
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break;
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case LogMan::ERROR:
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CharLevel = "ERROR";
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break;
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case LogMan::DEBUG:
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CharLevel = "DEBUG";
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break;
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case LogMan::INFO:
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CharLevel = "Info";
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// Disassemble information is sent through the Info log level.
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if (!CodeSize::Validation.ParseMessage(Message)) {
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return;
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}
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if (CodeSize::Validation.InfoPrintingDisabled()) {
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return;
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}
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break;
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default:
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CharLevel = "???";
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break;
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}
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fextl::fmt::print("[{}] {}\n", CharLevel, Message);
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}
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void AssertHandler(char const *Message) {
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fextl::fmt::print("[ASSERT] {}\n", Message);
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// make sure buffers are flushed
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fflush(nullptr);
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}
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struct TestInfo {
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char TestInst[32];
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uint64_t Optimal;
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int64_t ExpectedInstructionCount;
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uint64_t CodeSize;
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uint32_t Cookie;
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uint8_t Code[];
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};
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struct TestHeader {
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uint64_t Bitness;
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uint64_t NumTests{};
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uint64_t EnabledHostFeatures;
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uint64_t DisabledHostFeatures;
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TestInfo Tests[];
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};
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static fextl::vector<char> TestData;
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static TestHeader const *TestHeaderData{};
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static bool TestInstructions(FEXCore::Context::Context *CTX, FEXCore::Core::InternalThreadState *Thread, const char *UpdatedInstructionCountsPath) {
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LogMan::Msg::IFmt("Compiling code");
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// Tell FEXCore to compile all the instructions upfront.
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TestInfo const *CurrentTest = &TestHeaderData->Tests[0];
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for (size_t i = 0; i < TestHeaderData->NumTests; ++i) {
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uint64_t CodeRIP = (uint64_t)&CurrentTest->Code[0];
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// Compile the INST.
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CTX->CompileRIP(Thread, CodeRIP);
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// Go to the next test.
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CurrentTest = reinterpret_cast<TestInfo const*>(&CurrentTest->Code[CurrentTest->CodeSize]);
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}
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bool TestsPassed {true};
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bool InstructionCountChanged {};
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// Get all the data for the instructions compiled.
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CurrentTest = &TestHeaderData->Tests[0];
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for (size_t i = 0; i < TestHeaderData->NumTests; ++i) {
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uint64_t CodeRIP = (uint64_t)CurrentTest->Code;
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// Get the instruction stats.
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auto INSTStats = CodeSize::Validation.GetDataForRIP(CodeRIP);
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LogMan::Msg::IFmt("Testing instruction '{}': {} host instructions", CurrentTest->TestInst, INSTStats->first.HostCodeInstructions);
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// Show the code if we know the implementation isn't optimal or if the count of instructions changed to something we didn't expect.
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bool ShouldShowCode = CurrentTest->Optimal == 0 ||
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INSTStats->first.HostCodeInstructions != CurrentTest->ExpectedInstructionCount;
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if (ShouldShowCode) {
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for (auto Line : INSTStats->second) {
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LogMan::Msg::EFmt("\t{}", Line);
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}
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}
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if (INSTStats->first.HostCodeInstructions != CurrentTest->ExpectedInstructionCount) {
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LogMan::Msg::EFmt("Fail: '{}': {} host instructions", CurrentTest->TestInst, INSTStats->first.HostCodeInstructions);
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LogMan::Msg::EFmt("Fail: Test took {} instructions but we expected {} instructions!", INSTStats->first.HostCodeInstructions, CurrentTest->ExpectedInstructionCount);
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InstructionCountChanged = true;
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if (CurrentTest->Optimal) {
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// Don't count the test as a failure if it's known non-optimal.
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TestsPassed = false;
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}
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}
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// Go to the next test.
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CurrentTest = reinterpret_cast<TestInfo const*>(&CurrentTest->Code[CurrentTest->CodeSize]);
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}
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if (UpdatedInstructionCountsPath) {
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// Unlink the file.
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unlink(UpdatedInstructionCountsPath);
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if (!InstructionCountChanged) {
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// If no instruction count changed then just return the results.
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return TestsPassed;
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}
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FEXCore::File::File FD(UpdatedInstructionCountsPath, FEXCore::File::FileModes::WRITE | FEXCore::File::FileModes::CREATE | FEXCore::File::FileModes::TRUNCATE);
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if (!FD.IsValid()) {
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// If we couldn't open the file then early exit this.
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LogMan::Msg::EFmt("Couldn't open {} for updating instruction counts", UpdatedInstructionCountsPath);
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return TestsPassed;
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}
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FD.Write("{\n", 2);
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CurrentTest = &TestHeaderData->Tests[0];
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for (size_t i = 0; i < TestHeaderData->NumTests; ++i) {
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uint64_t CodeRIP = (uint64_t)CurrentTest->Code;
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// Get the instruction stats.
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auto INSTStats = CodeSize::Validation.GetDataForRIP(CodeRIP);
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if (INSTStats->first.HostCodeInstructions != CurrentTest->ExpectedInstructionCount) {
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FD.Write(fextl::fmt::format("\t\"{}\": {},\n", CurrentTest->TestInst, INSTStats->first.HostCodeInstructions));
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}
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// Go to the next test.
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CurrentTest = reinterpret_cast<TestInfo const*>(&CurrentTest->Code[CurrentTest->CodeSize]);
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}
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// Print a null member
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FD.Write(fextl::fmt::format("\t\"\": \"\""));
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FD.Write("}\n", 2);
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}
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return TestsPassed;
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}
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bool LoadTests(const char *Path) {
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if (!FEXCore::FileLoading::LoadFile(TestData, Path)) {
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return false;
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}
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TestHeaderData = reinterpret_cast<TestHeader const*>(TestData.data());
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return true;
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}
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int main(int argc, char **argv, char **const envp) {
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FEXCore::Allocator::GLIBCScopedFault GLIBFaultScope;
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LogMan::Throw::InstallHandler(AssertHandler);
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LogMan::Msg::InstallHandler(MsgHandler);
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FEXCore::Config::Initialize();
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FEXCore::Config::Load();
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FEXCore::Config::ReloadMetaLayer();
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if (argc < 2) {
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LogMan::Msg::EFmt("Usage: {} <Test binary> [Changed instruction count.json]", argv[0]);
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return 1;
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}
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if (!LoadTests(argv[1])) {
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LogMan::Msg::EFmt("Couldn't load tests from {}", argv[1]);
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return 1;
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}
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// Setup configurations that this tool needs
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// Maximum one instruction.
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FEXCore::Config::EraseSet(FEXCore::Config::CONFIG_MAXINST, "1");
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// IRJIT. Only works on JITs.
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FEXCore::Config::EraseSet(FEXCore::Config::CONFIG_CORE, fextl::fmt::format("{}", static_cast<uint64_t>(FEXCore::Config::CONFIG_IRJIT)));
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// Enable block disassembly.
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FEXCore::Config::EraseSet(FEXCore::Config::CONFIG_DISASSEMBLE, fextl::fmt::format("{}", static_cast<uint64_t>(FEXCore::Config::Disassemble::BLOCKS | FEXCore::Config::Disassemble::STATS)));
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// Choose bitness.
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FEXCore::Config::EraseSet(FEXCore::Config::CONFIG_IS64BIT_MODE, TestHeaderData->Bitness == 64 ? "1" : 0);
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// Host feature override. Only supports overriding SVE width.
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enum HostFeatures {
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FEATURE_SVE128 = (1U << 0),
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FEATURE_SVE256 = (1U << 1),
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};
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uint64_t SVEWidth = 0;
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uint64_t HostFeatureControl{};
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if (TestHeaderData->EnabledHostFeatures & FEATURE_SVE128) {
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HostFeatureControl |= static_cast<uint64_t>(FEXCore::Config::HostFeatures::ENABLESVE);
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SVEWidth = 128;
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}
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if (TestHeaderData->EnabledHostFeatures & FEATURE_SVE256) {
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HostFeatureControl |= static_cast<uint64_t>(FEXCore::Config::HostFeatures::ENABLEAVX);
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SVEWidth = 256;
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}
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if (TestHeaderData->DisabledHostFeatures & FEATURE_SVE128) {
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HostFeatureControl |= static_cast<uint64_t>(FEXCore::Config::HostFeatures::DISABLESVE);
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}
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if (TestHeaderData->DisabledHostFeatures & FEATURE_SVE256) {
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HostFeatureControl |= static_cast<uint64_t>(FEXCore::Config::HostFeatures::DISABLEAVX);
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}
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FEXCore::Config::EraseSet(FEXCore::Config::CONFIG_HOSTFEATURES, fextl::fmt::format("{}", HostFeatureControl));
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FEXCore::Config::EraseSet(FEXCore::Config::CONFIG_FORCESVEWIDTH, fextl::fmt::format("{}", SVEWidth));
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// Initialize static tables.
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FEXCore::Context::InitializeStaticTables(TestHeaderData->Bitness == 64 ? FEXCore::Context::MODE_64BIT : FEXCore::Context::MODE_32BIT);
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// Create FEXCore context.
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auto CTX = FEXCore::Context::Context::CreateNewContext();
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CTX->InitializeContext();
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auto SignalDelegation = FEX::DummyHandlers::CreateSignalDelegator();
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auto SyscallHandler = FEX::DummyHandlers::CreateSyscallHandler();
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CTX->SetSignalDelegator(SignalDelegation.get());
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CTX->SetSyscallHandler(SyscallHandler.get());
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auto ParentThread = CTX->InitCore(0, 0);
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// Calculate the base stats for instruction testing.
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CodeSize::Validation.CalculateBaseStats(CTX.get(), ParentThread);
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// Test all the instructions.
|
||||
return TestInstructions(CTX.get(), ParentThread, argc >= 2 ? argv[2] : nullptr) ? 0 : 1;
|
||||
}
|
||||
Reference in new issue
Block a user