Merge pull request #4414 from pmatos/AddrMode-DeusEx

Fix address modes calculation on 32bit guests

FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp

@@ -27,7 +27,6 @@ $end_info$
 
 #include <algorithm>
 #include <array>
-#include <bit>
 #include <cstdint>
 #include <tuple>
 
@@ -2479,7 +2478,7 @@ void OpDispatchBuilder::BTOp(OpcodeArgs, uint32_t SrcIndex, BTAction Action) {
 
       if (DestIsLockedMem(Op)) {
         HandledLock = true;
-        Value = _AtomicFetchCLR(OpSize::i8Bit, BitMask, LoadEffectiveAddress(Address, true));
+        Value = _AtomicFetchCLR(OpSize::i8Bit, BitMask, LoadEffectiveAddress(this, Address, CTX->GetGPROpSize(), true));
       } else {
         Value = _LoadMemAutoTSO(GPRClass, OpSize::i8Bit, Address, OpSize::i8Bit);
 
@@ -2494,7 +2493,7 @@ void OpDispatchBuilder::BTOp(OpcodeArgs, uint32_t SrcIndex, BTAction Action) {
 
       if (DestIsLockedMem(Op)) {
         HandledLock = true;
-        Value = _AtomicFetchOr(OpSize::i8Bit, BitMask, LoadEffectiveAddress(Address, true));
+        Value = _AtomicFetchOr(OpSize::i8Bit, BitMask, LoadEffectiveAddress(this, Address, CTX->GetGPROpSize(), true));
       } else {
         Value = _LoadMemAutoTSO(GPRClass, OpSize::i8Bit, Address, OpSize::i8Bit);
 
@@ -2509,7 +2508,7 @@ void OpDispatchBuilder::BTOp(OpcodeArgs, uint32_t SrcIndex, BTAction Action) {
 
       if (DestIsLockedMem(Op)) {
         HandledLock = true;
-        Value = _AtomicFetchXor(OpSize::i8Bit, BitMask, LoadEffectiveAddress(Address, true));
+        Value = _AtomicFetchXor(OpSize::i8Bit, BitMask, LoadEffectiveAddress(this, Address, CTX->GetGPROpSize(), true));
       } else {
         Value = _LoadMemAutoTSO(GPRClass, OpSize::i8Bit, Address, OpSize::i8Bit);
 
@@ -4142,155 +4141,6 @@ void OpDispatchBuilder::UpdatePrefixFromSegment(Ref Segment, uint32_t SegmentReg
   }
 }
 
-Ref OpDispatchBuilder::LoadEffectiveAddress(AddressMode A, bool AddSegmentBase, bool AllowUpperGarbage) {
-  const auto GPRSize = CTX->GetGPROpSize();
-  Ref Tmp = A.Base;
-
-  if (A.Offset) {
-    Ref Offset = _Constant(A.Offset);
-    Tmp = Tmp ? _Add(GPRSize, Tmp, Offset) : Offset;
-  }
-
-  if (A.Index) {
-    if (A.IndexScale != 1) {
-      LOGMAN_THROW_A_FMT((A.IndexScale & (A.IndexScale - 1)) == 0, "power of two");
-      uint32_t Log2 = FEXCore::ilog2(A.IndexScale);
-
-      if (Tmp) {
-        Tmp = _AddShift(GPRSize, Tmp, A.Index, ShiftType::LSL, Log2);
-      } else {
-        Tmp = _Lshl(GPRSize, A.Index, _Constant(Log2));
-      }
-    } else {
-      Tmp = Tmp ? _Add(GPRSize, Tmp, A.Index) : A.Index;
-    }
-  }
-
-  // For 64-bit AddrSize can be 32-bit or 64-bit
-  // For 32-bit AddrSize can be 32-bit or 16-bit
-  //
-  // If the AddrSize is not the GPRSize then we need to clear the upper bits.
-  if ((A.AddrSize < GPRSize) && !AllowUpperGarbage && Tmp) {
-    Tmp = _Bfe(GPRSize, IR::OpSizeAsBits(A.AddrSize), 0, Tmp);
-  }
-
-  if (A.Segment && AddSegmentBase) {
-    Tmp = Tmp ? _Add(GPRSize, Tmp, A.Segment) : A.Segment;
-  }
-
-  return Tmp ?: _Constant(0);
-}
-
-AddressMode OpDispatchBuilder::SelectAddressMode(AddressMode A, bool AtomicTSO, bool Vector, IR::OpSize AccessSize) {
-  auto SoftwareAddressCalculation = [this, &A]() -> AddressMode {
-    return {
-      .Base = LoadEffectiveAddress(A, true),
-      .Index = InvalidNode,
-    };
-  };
-
-  const auto GPRSize = CTX->GetGPROpSize();
-  const auto Is32Bit = GPRSize == OpSize::i32Bit;
-  const auto GPRSizeMatchesAddrSize = A.AddrSize == GPRSize;
-  const auto OffsetIndexToLargeFor32Bit = Is32Bit && (A.Offset <= -16384 || A.Offset >= 16384);
-  if (!GPRSizeMatchesAddrSize || OffsetIndexToLargeFor32Bit) {
-    // If address size doesn't match GPR size then no optimizations can occur.
-    return SoftwareAddressCalculation();
-  }
-
-  // Loadstore rules:
-  // Non-TSO GPR:
-  // * LDR/STR:   [Reg]
-  // * LDR/STR:   [Reg + Reg, {Shift <AccessSize>}]
-  //   * Can't use with 32-bit
-  // * LDR/STR:   [Reg + [0,4095] * <AccessSize>]
-  //   * Imm must be smaller than 16k with 32-bit
-  // * LDUR/STUR: [Reg + [-256, 255]]
-  //
-  // TSO GPR:
-  // * ARMv8.0:
-  //  LDAR/STLR: [Reg]
-  // * FEAT_LRCPC:
-  //  LDAPR: [Reg]
-  // * FEAT_LRCPC2:
-  //  LDAPUR/STLUR: [Reg + [-256, 255]]
-  //
-  // Non-TSO Vector:
-  // * LDR/STR: [Reg + [0,4095] * <AccessSize>]
-  // * LDUR/STUR: [Reg + [-256,255]]
-  //
-  // TSO Vector:
-  // * ARMv8.0:
-  //   Just DMB + previous
-  // * FEAT_LRCPC3 (Unsupported by FEXCore currently):
-  //   LDAPUR/STLUR: [Reg + [-256,255]]
-
-  const auto AccessSizeAsImm = OpSizeToSize(AccessSize);
-  const bool OffsetIsSIMM9 = A.Offset && A.Offset >= -256 && A.Offset <= 255;
-  const bool OffsetIsUnsignedScaled = A.Offset > 0 && (A.Offset & (AccessSizeAsImm - 1)) == 0 && (A.Offset / AccessSizeAsImm) <= 4095;
-
-  auto InlineImmOffsetLoadstore = [this](AddressMode A) -> AddressMode {
-    // Peel off the offset
-    AddressMode B = A;
-    B.Offset = 0;
-
-    return {
-      .Base = LoadEffectiveAddress(B, true /* AddSegmentBase */, false),
-      .Index = _InlineConstant(A.Offset),
-      .IndexType = MEM_OFFSET_SXTX,
-      .IndexScale = 1,
-    };
-  };
-
-  auto ScaledRegisterLoadstore = [this, &GPRSize](AddressMode A) -> AddressMode {
-    if (A.Index && A.Segment) {
-      A.Base = _Add(GPRSize, A.Base, A.Segment);
-    } else if (A.Segment) {
-      A.Index = A.Segment;
-      A.IndexScale = 1;
-    }
-    return A;
-  };
-
-  if (AtomicTSO) {
-    if (!Vector) {
-      if (CTX->HostFeatures.SupportsTSOImm9 && OffsetIsSIMM9) {
-        return InlineImmOffsetLoadstore(A);
-      }
-    } else {
-      // TODO: LRCPC3 support for vector Imm9.
-    }
-  } else {
-    if (OffsetIsSIMM9 || OffsetIsUnsignedScaled) {
-      return InlineImmOffsetLoadstore(A);
-    } else if (!Is32Bit && A.Base && (A.Index || A.Segment) & !A.Offset && (A.IndexScale == 1 || A.IndexScale == AccessSizeAsImm)) {
-      return ScaledRegisterLoadstore(A);
-    }
-  }
-
-  if (Vector || !AtomicTSO) {
-    if ((A.Base || A.Segment) && A.Offset) {
-      const bool Const_16K = A.Offset > -16384 && A.Offset < 16384 && GPRSizeMatchesAddrSize && Is32Bit;
-
-      if (!Is32Bit || Const_16K) {
-        // Peel off the offset
-        AddressMode B = A;
-        B.Offset = 0;
-
-        return {
-          .Base = LoadEffectiveAddress(B, true /* AddSegmentBase */, false),
-          .Index = _Constant(A.Offset),
-          .IndexType = MEM_OFFSET_SXTX,
-          .IndexScale = 1,
-        };
-      }
-    }
-  }
-
-  // Fallback on software address calculation
-  return SoftwareAddressCalculation();
-}
-
 AddressMode OpDispatchBuilder::DecodeAddress(const X86Tables::DecodedOp& Op, const X86Tables::DecodedOperand& Operand,
                                              MemoryAccessType AccessType, bool IsLoad) {
   const auto GPRSize = CTX->GetGPROpSize();
@@ -4388,7 +4238,7 @@ Ref OpDispatchBuilder::LoadSource_WithOpSize(RegisterClassType Class, const X86T
 
   if ((IsOperandMem(Operand, true) && LoadData) || ForceLoad) {
     if (OpSize == OpSize::f80Bit) {
-      Ref MemSrc = LoadEffectiveAddress(A, true);
+      Ref MemSrc = LoadEffectiveAddress(this, A, CTX->GetGPROpSize(), true);
       if (CTX->HostFeatures.SupportsSVE128 || CTX->HostFeatures.SupportsSVE256) {
         return _LoadMemX87SVEOptPredicate(OpSize::i128Bit, OpSize::i16Bit, MemSrc);
       } else {
@@ -4400,7 +4250,7 @@ Ref OpDispatchBuilder::LoadSource_WithOpSize(RegisterClassType Class, const X86T
 
     return _LoadMemAutoTSO(Class, OpSize, A, Align == OpSize::iInvalid ? OpSize : Align);
   } else {
-    return LoadEffectiveAddress(A, false, AllowUpperGarbage);
+    return LoadEffectiveAddress(this, A, CTX->GetGPROpSize(), false, AllowUpperGarbage);
   }
 }
 
@@ -4521,7 +4371,7 @@ void OpDispatchBuilder::StoreResult_WithOpSize(FEXCore::IR::RegisterClassType Cl
   AddressMode A = DecodeAddress(Op, Operand, AccessType, false /* IsLoad */);
 
   if (OpSize == OpSize::f80Bit) {
-    Ref MemStoreDst = LoadEffectiveAddress(A, true);
+    Ref MemStoreDst = LoadEffectiveAddress(this, A, CTX->GetGPROpSize(), true);
     if (CTX->HostFeatures.SupportsSVE128 || CTX->HostFeatures.SupportsSVE256) {
       _StoreMemX87SVEOptPredicate(OpSize::i128Bit, OpSize::i16Bit, Src, MemStoreDst);
     } else {
@@ -5579,9 +5429,9 @@ void InstallOpcodeHandlers(Context::OperatingMode Mode) {
 
     // 1 = Invalid
 
-    {OPDReg(0xD9, 2) | 0x00, 8, &OpDispatchBuilder::Bind<&OpDispatchBuilder::FSTF64, OpSize::i32Bit>},
+    {OPDReg(0xD9, 2) | 0x00, 8, &OpDispatchBuilder::Bind<&OpDispatchBuilder::FST, OpSize::i32Bit>},
 
-    {OPDReg(0xD9, 3) | 0x00, 8, &OpDispatchBuilder::Bind<&OpDispatchBuilder::FSTF64, OpSize::i32Bit>},
+    {OPDReg(0xD9, 3) | 0x00, 8, &OpDispatchBuilder::Bind<&OpDispatchBuilder::FST, OpSize::i32Bit>},
 
     {OPDReg(0xD9, 4) | 0x00, 8, &OpDispatchBuilder::X87LDENVF64},
 
@@ -5676,7 +5526,7 @@ void InstallOpcodeHandlers(Context::OperatingMode Mode) {
 
     // 6 = Invalid
 
-    {OPDReg(0xDB, 7) | 0x00, 8, &OpDispatchBuilder::Bind<&OpDispatchBuilder::FSTF64, OpSize::f80Bit>},
+    {OPDReg(0xDB, 7) | 0x00, 8, &OpDispatchBuilder::Bind<&OpDispatchBuilder::FST, OpSize::f80Bit>},
 
 
     {OPD(0xDB, 0xC0), 8, &OpDispatchBuilder::X87FCMOV},
@@ -5727,9 +5577,9 @@ void InstallOpcodeHandlers(Context::OperatingMode Mode) {
 
     {OPDReg(0xDD, 1) | 0x00, 8, &OpDispatchBuilder::Bind<&OpDispatchBuilder::FISTF64, true>},
 
-    {OPDReg(0xDD, 2) | 0x00, 8, &OpDispatchBuilder::Bind<&OpDispatchBuilder::FSTF64, OpSize::i64Bit>},
+    {OPDReg(0xDD, 2) | 0x00, 8, &OpDispatchBuilder::Bind<&OpDispatchBuilder::FST, OpSize::i64Bit>},
 
-    {OPDReg(0xDD, 3) | 0x00, 8, &OpDispatchBuilder::Bind<&OpDispatchBuilder::FSTF64, OpSize::i64Bit>},
+    {OPDReg(0xDD, 3) | 0x00, 8, &OpDispatchBuilder::Bind<&OpDispatchBuilder::FST, OpSize::i64Bit>},
 
     {OPDReg(0xDD, 4) | 0x00, 8, &OpDispatchBuilder::X87FRSTOR},