diff --git a/External/FEXCore/Source/Interface/Core/JIT/x86_64/VectorOps.cpp b/External/FEXCore/Source/Interface/Core/JIT/x86_64/VectorOps.cpp
index fa22527ac..4759c89fb 100644
--- a/External/FEXCore/Source/Interface/Core/JIT/x86_64/VectorOps.cpp
+++ b/External/FEXCore/Source/Interface/Core/JIT/x86_64/VectorOps.cpp
@@ -837,6 +837,7 @@ DEF_OP(VFSub) {
   const auto OpSize = IROp->Size;
 
   const auto ElementSize = Op->Header.ElementSize;
+  const auto Is256Bit = OpSize == Core::CPUState::XMM_AVX_REG_SIZE;
   const auto IsScalar = ElementSize == OpSize;
 
   const auto Dst = GetDst(Node);
@@ -858,17 +859,21 @@ DEF_OP(VFSub) {
         break;
     }
   } else {
-    const auto DstYMM = ToYMM(Dst);
-    const auto Vector1YMM = ToYMM(Vector1);
-    const auto Vector2YMM = ToYMM(Vector2);
-
     switch (ElementSize) {
       case 4: {
-        vsubps(DstYMM, Vector1YMM, Vector2YMM);
+        if (Is256Bit) {
+          vsubps(ToYMM(Dst), ToYMM(Vector1), ToYMM(Vector2));
+        } else {
+          vsubps(Dst, Vector1, Vector2);
+        }
         break;
       }
       case 8: {
-        vsubpd(DstYMM, Vector1YMM, Vector2YMM);
+        if (Is256Bit) {
+          vsubpd(ToYMM(Dst), ToYMM(Vector1), ToYMM(Vector2));
+        } else {
+          vsubpd(Dst, Vector1, Vector2);
+        }
         break;
       }
       default: