diff --git a/unittests/InstructionCountCI/Secondary_REP.json b/unittests/InstructionCountCI/Secondary_REP.json
index 3e69c8260..b84e3965f 100644
--- a/unittests/InstructionCountCI/Secondary_REP.json
+++ b/unittests/InstructionCountCI/Secondary_REP.json
@@ -67,28 +67,27 @@
       ]
     },
     "cvtsi2ss xmm0, eax": {
-      "ExpectedInstructionCount": 3,
-      "Optimal": "No",
+      "ExpectedInstructionCount": 2,
+      "Optimal": "Yes",
       "Comment": [
         "With AFP mode FEX can remove an insert after the operation.",
         "0xf3 0x0f 0x2a"
       ],
       "ExpectedArm64ASM": [
-        "ubfx x20, x4, #0, #32",
-        "scvtf s4, w20",
+        "scvtf s4, w4",
         "mov v16.s[0], v4.s[0]"
       ]
     },
     "cvtsi2ss xmm0, dword [rax]": {
       "ExpectedInstructionCount": 3,
-      "Optimal": "No",
+      "Optimal": "Yes",
       "Comment": [
         "With AFP mode FEX can remove an insert after the operation.",
         "0xf3 0x0f 0x2a"
       ],
       "ExpectedArm64ASM": [
-        "ldr w20, [x4]",
-        "scvtf s4, w20",
+        "ldr s4, [x4]",
+        "scvtf s4, s4",
         "mov v16.s[0], v4.s[0]"
       ]
     },
diff --git a/unittests/InstructionCountCI/Secondary_REPNE.json b/unittests/InstructionCountCI/Secondary_REPNE.json
index b9225306c..cb6f15724 100644
--- a/unittests/InstructionCountCI/Secondary_REPNE.json
+++ b/unittests/InstructionCountCI/Secondary_REPNE.json
@@ -52,15 +52,14 @@
       ]
     },
     "cvtsi2sd xmm0, eax": {
-      "ExpectedInstructionCount": 3,
-      "Optimal": "No",
+      "ExpectedInstructionCount": 2,
+      "Optimal": "Yes",
       "Comment": [
         "With AFP mode FEX can remove an insert after the operation.",
         "0xf2 0x0f 0x2a"
       ],
       "ExpectedArm64ASM": [
-        "ubfx x20, x4, #0, #32",
-        "scvtf d4, w20",
+        "scvtf d4, w4",
         "mov v16.d[0], v4.d[0]"
       ]
     },
@@ -97,8 +96,8 @@
         "0xf2 0x0f 0x2a"
       ],
       "ExpectedArm64ASM": [
-        "ldr x20, [x4]",
-        "scvtf d4, x20",
+        "ldr d4, [x4]",
+        "scvtf d4, d4",
         "mov v16.d[0], v4.d[0]"
       ]
     },
diff --git a/unittests/InstructionCountCI/VEX_map1.json b/unittests/InstructionCountCI/VEX_map1.json
index 2b569c336..1502774f8 100644
--- a/unittests/InstructionCountCI/VEX_map1.json
+++ b/unittests/InstructionCountCI/VEX_map1.json
@@ -3604,15 +3604,14 @@
       ]
     },
     "vcvtsi2ss xmm0, xmm1, eax": {
-      "ExpectedInstructionCount": 6,
+      "ExpectedInstructionCount": 5,
       "Optimal": "No",
       "Comment": [
         "Map 1 0b10 0x2A 128-bit"
       ],
       "ExpectedArm64ASM": [
         "mov z4.d, p7/m, z17.d",
-        "ubfx x20, x4, #0, #32",
-        "scvtf s5, w20",
+        "scvtf s5, w4",
         "mov v4.s[0], v5.s[0]",
         "mov v4.16b, v4.16b",
         "mov z16.d, p7/m, z4.d"
@@ -3633,15 +3632,14 @@
       ]
     },
     "vcvtsi2sd xmm0, xmm1, eax": {
-      "ExpectedInstructionCount": 6,
+      "ExpectedInstructionCount": 5,
       "Optimal": "No",
       "Comment": [
         "Map 1 0b11 0x2A 128-bit"
       ],
       "ExpectedArm64ASM": [
         "mov z4.d, p7/m, z17.d",
-        "ubfx x20, x4, #0, #32",
-        "scvtf d5, w20",
+        "scvtf d5, w4",
         "mov v4.d[0], v5.d[0]",
         "mov v4.16b, v4.16b",
         "mov z16.d, p7/m, z4.d"