From a8d32b9a2f00a292ed22cab9f7c688704e2a7d1f Mon Sep 17 00:00:00 2001 From: Alyssa Rosenzweig Date: Fri, 24 May 2024 09:26:02 -0400 Subject: [PATCH] InstCountCI: Update Signed-off-by: Alyssa Rosenzweig --- unittests/InstructionCountCI/Atomics.json | 8 +- .../InstructionCountCI/FEXOpt/MultiInst.json | 105 +- .../InstructionCountCI/FEXOpt/libnss.json | 2348 ++++++++--------- .../InstructionCountCI/FlagM/Atomics.json | 8 +- .../InstructionCountCI/FlagM/FlagOpts.json | 4 +- .../InstructionCountCI/FlagM/HotBlocks.json | 41 +- .../FlagM/HotBlocks_32Bit.json | 58 +- .../FlagM/HotBlocks_AFP.json | 6 +- .../InstructionCountCI/FlagM/Primary.json | 180 +- .../FlagM/PrimaryGroup.json | 233 +- .../FlagM/Primary_32Bit.json | 8 +- .../InstructionCountCI/FlagM/Secondary.json | 79 +- unittests/InstructionCountCI/FlagM/x87.json | 62 +- unittests/InstructionCountCI/H0F3A.json | 368 ++- unittests/InstructionCountCI/Primary.json | 231 +- .../InstructionCountCI/PrimaryGroup.json | 273 +- .../InstructionCountCI/Primary_32Bit.json | 8 +- unittests/InstructionCountCI/Secondary.json | 78 +- unittests/InstructionCountCI/VEX_map1.json | 14 +- unittests/InstructionCountCI/VEX_map3.json | 7 +- unittests/InstructionCountCI/x87.json | 62 +- 21 files changed, 2056 insertions(+), 2125 deletions(-) diff --git a/unittests/InstructionCountCI/Atomics.json b/unittests/InstructionCountCI/Atomics.json index 9baf143c5..fbaf4b03f 100644 --- a/unittests/InstructionCountCI/Atomics.json +++ b/unittests/InstructionCountCI/Atomics.json @@ -373,10 +373,10 @@ "ExpectedInstructionCount": 4, "Comment": "0x0f 0xc1", "ExpectedArm64ASM": [ - "mov x20, x7", - "ldaddal x20, x7, [x4]", - "eor w27, w7, w20", - "adds x26, x7, x20" + "ldaddal x7, x20, [x4]", + "eor w27, w20, w7", + "adds x26, x20, x7", + "mov x7, x20" ] }, "lock add byte [rax], 1": { diff --git a/unittests/InstructionCountCI/FEXOpt/MultiInst.json b/unittests/InstructionCountCI/FEXOpt/MultiInst.json index 5f1272541..6de64d742 100644 --- a/unittests/InstructionCountCI/FEXOpt/MultiInst.json +++ b/unittests/InstructionCountCI/FEXOpt/MultiInst.json @@ -1024,7 +1024,7 @@ ] }, "Sekiro spill block": { - "ExpectedInstructionCount": 153, + "ExpectedInstructionCount": 154, "Comment": [ "This block of code came from the settings screen when it loaded", "It was originally at RIP: 0x14232cca0 and has been deobfuscated" @@ -1205,8 +1205,7 @@ "lsl w4, w4, #26", "sub w10, w10, w4", "mov w5, w9", - "ldr x20, [x8, #96]", - "mov x4, x20", + "ldr x4, [x8, #96]", "asr w5, w5, #25", "add w19, w19, w5", "lsl w5, w5, #25", @@ -1214,95 +1213,97 @@ "sub w9, w9, w5", "asr w6, w6, #26", "add w29, w29, w6", - "mov w21, w10", - "str w21, [x20]", + "mov w20, w10", + "str w20, [x4]", "mov w12, w29", "lsl w6, w6, #26", "asr w12, w12, #25", "sub w19, w19, w6", "add w16, w16, w12", - "mov w21, w9", - "str w21, [x20, #4]", + "mov w20, w9", + "str w20, [x4, #4]", "mov w13, w16", "lsl w12, w12, #25", "asr w13, w13, #26", "sub w29, w29, w12", "add w17, w17, w13", - "mov w21, w19", - "str w21, [x20, #8]", + "mov w20, w19", + "str w20, [x4, #8]", "lsl w13, w13, #26", "mov w14, w17", "asr w14, w14, #25", "sub w16, w16, w13", "add w15, w15, w14", - "mov w21, w29", - "str w21, [x20, #12]", - "mov w21, w15", - "str w21, [x8, #112]", - "mov x10, x20", + "mov w20, w29", + "str w20, [x4, #12]", + "mov w20, w15", + "str w20, [x8, #112]", + "mov x10, x4", "asr w15, w15, #26", "add w7, w7, w15", - "mov w21, w16", - "str w21, [x20, #16]", - "mov w21, w7", - "str w21, [x8, #120]", + "mov w20, w16", + "str w20, [x4, #16]", + "mov w20, w7", + "str w20, [x8, #120]", "asr w7, w7, #25", "add w11, w11, w7", - "mov w21, w11", - "str w21, [x8]", + "mov w20, w11", + "str w20, [x8]", "asr w11, w11, #26", - "ldr w21, [x8, #104]", - "add w21, w21, w11", - "str w21, [x8, #104]", + "ldr w20, [x8, #104]", + "add w20, w20, w11", + "str w20, [x8, #104]", "lsl w14, w14, #25", "ldr w5, [x8, #104]", "sub w17, w17, w14", - "mov w21, w17", - "str w21, [x20, #20]", - "ldr w4, [x8, #112]", + "mov w20, w17", + "str w20, [x4, #20]", + "ldr w20, [x8, #112]", + "mov x21, x4", + "mov x4, x20", "lsl w15, w15, #26", - "sub w4, w4, w15", + "sub w4, w20, w15", "lsl w7, w7, #25", - "mov w21, w4", - "str w21, [x20, #24]", + "mov w20, w4", + "str w20, [x21, #24]", "ldr w4, [x8, #120]", "sub w4, w4, w7", "lsl w11, w11, #26", - "mov w21, w4", - "str w21, [x20, #28]", + "mov w20, w4", + "str w20, [x21, #28]", "ldr w4, [x8]", "sub w4, w4, w11", - "mov w21, w4", - "str w21, [x20, #32]", + "mov w20, w4", + "str w20, [x21, #32]", "mov x4, x5", "and w4, w5, #0xfe000000", "sub w5, w5, w4", - "mov w21, w5", - "str w21, [x20, #36]", + "mov w20, w5", + "str w20, [x21, #36]", "mvn w27, w8", "adds x26, x8, #0x18 (24)", "mov x8, x26", "ldr x29, [x26]", - "add x20, x26, #0x8 (8)", - "mov x8, x20", + "add x8, x26, #0x8 (8)", "ldr x19, [x26, #8]", - "add x21, x20, #0x8 (8)", - "mov x8, x21", - "ldr x17, [x20, #8]", - "add x20, x21, #0x8 (8)", + "add x20, x8, #0x8 (8)", + "mov x21, x8", "mov x8, x20", - "ldr x16, [x21, #8]", - "add x21, x20, #0x8 (8)", - "mov x8, x21", - "ldr x11, [x20, #8]", - "add x20, x21, #0x8 (8)", + "ldr x17, [x21, #8]", + "add x8, x20, #0x8 (8)", + "ldr x16, [x20, #8]", + "add x20, x8, #0x8 (8)", + "mov x21, x8", "mov x8, x20", - "ldr x10, [x21, #8]", - "add x21, x20, #0x8 (8)", - "mov x8, x21", - "ldr x9, [x20, #8]", - "add x8, x21, #0x8 (8)", - "ldr x7, [x21, #8]", + "ldr x11, [x21, #8]", + "add x8, x20, #0x8 (8)", + "ldr x10, [x20, #8]", + "add x20, x8, #0x8 (8)", + "mov x21, x8", + "mov x8, x20", + "ldr x9, [x21, #8]", + "add x8, x20, #0x8 (8)", + "ldr x7, [x20, #8]", "add x8, x8, #0x8 (8)" ] } diff --git a/unittests/InstructionCountCI/FEXOpt/libnss.json b/unittests/InstructionCountCI/FEXOpt/libnss.json index 0fd3a1537..956dde0fd 100644 --- a/unittests/InstructionCountCI/FEXOpt/libnss.json +++ b/unittests/InstructionCountCI/FEXOpt/libnss.json @@ -16,7 +16,7 @@ "Comment": [], "Instructions": { "libnss3 sha": { - "ExpectedInstructionCount": 2391, + "ExpectedInstructionCount": 2375, "Comment": [ "This block of code comes from libnss3 which causes panic spilling in FEX's RA.", "This code is hit in steamwebhelper calling in to this function.", @@ -228,283 +228,279 @@ "ldr q16, [x29, x20, sxtx]", "add v16.4s, v16.4s, v24.4s", "unimplemented (Unimplemented)", - "mov w20, v19.s[1]", - "mov w21, v19.s[0]", + "mov w21, v19.s[1]", + "mov w22, v19.s[0]", + "mov w23, v18.s[1]", + "and w24, w21, w22", + "bic w23, w23, w21", + "eor w23, w24, w23", + "ror w24, w21, #6", + "eor w24, w24, w21, ror #11", + "eor w24, w24, w21, ror #25", + "add w23, w23, w24", + "mov w24, v16.s[0]", + "add w23, w23, w24", + "mov w24, v18.s[0]", + "add w23, w23, w24", + "mov w24, v19.s[3]", + "mov w25, v19.s[2]", + "mov w30, v18.s[3]", + "and w18, w25, w30", + "orr w30, w25, w30", + "and w30, w24, w30", + "orr w30, w30, w18", + "add w30, w23, w30", + "ror w18, w24, #2", + "eor w18, w18, w24, ror #13", + "eor w18, w18, w24, ror #22", + "add w30, w30, w18", + "mov w18, v18.s[2]", + "add w23, w23, w18", + "and w21, w23, w21", + "bic w22, w22, w23", + "eor w21, w21, w22", + "ror w22, w23, #6", + "eor w22, w22, w23, ror #11", + "eor w22, w22, w23, ror #25", + "add w21, w21, w22", + "mov w22, v16.s[1]", + "add w21, w21, w22", "mov w22, v18.s[1]", - "and w23, w20, w21", - "bic w22, w22, w20", - "eor w22, w23, w22", - "ror w23, w20, #6", - "eor w23, w23, w20, ror #11", - "eor w23, w23, w20, ror #25", - "add w22, w22, w23", - "mov w23, v16.s[0]", - "add w22, w22, w23", - "mov w23, v18.s[0]", - "add w22, w22, w23", - "mov w23, v19.s[3]", - "mov w24, v19.s[2]", - "mov w25, v18.s[3]", - "and w30, w24, w25", - "orr w25, w24, w25", - "and w25, w23, w25", - "orr w25, w25, w30", - "add w25, w22, w25", - "ror w30, w23, #2", - "eor w30, w30, w23, ror #13", - "eor w30, w30, w23, ror #22", - "add w25, w25, w30", - "mov w30, v18.s[2]", - "add w22, w22, w30", - "and w20, w22, w20", - "bic w21, w21, w22", - "eor w20, w20, w21", - "ror w21, w22, #6", - "eor w21, w21, w22, ror #11", - "eor w21, w21, w22, ror #25", - "add w20, w20, w21", - "mov w21, v16.s[1]", - "add w20, w20, w21", - "mov w21, v18.s[1]", - "add w20, w20, w21", - "and w21, w23, w24", - "orr w23, w23, w24", - "and w23, w25, w23", - "orr w21, w23, w21", - "add w21, w20, w21", - "ror w23, w25, #2", - "eor w23, w23, w25, ror #13", - "eor w23, w23, w25, ror #22", - "add w21, w21, w23", - "mov w23, v18.s[3]", - "add w20, w20, w23", + "add w21, w21, w22", + "and w22, w24, w25", + "orr w24, w24, w25", + "and w24, w30, w24", + "orr w22, w24, w22", + "add w22, w21, w22", + "ror w24, w30, #2", + "eor w24, w24, w30, ror #13", + "eor w24, w24, w30, ror #22", + "add w22, w22, w24", + "mov w24, v18.s[3]", + "add w21, w21, w24", "mov v4.16b, v18.16b", - "mov v4.s[3], w21", - "mov v4.s[2], w25", - "mov v4.s[1], w20", + "mov v4.s[3], w22", + "mov v4.s[2], w30", + "mov v4.s[1], w21", "mov v20.16b, v4.16b", - "mov v20.s[0], w22", + "mov v20.s[0], w23", "ldr x0, [x28, #1760]", "ldr q4, [x0, #224]", "tbl v16.16b, {v16.16b}, v4.16b", - "mov w20, v20.s[1]", - "mov w21, v20.s[0]", + "mov w21, v20.s[1]", + "mov w22, v20.s[0]", + "mov w23, v19.s[1]", + "and w24, w21, w22", + "bic w23, w23, w21", + "eor w23, w24, w23", + "ror w24, w21, #6", + "eor w24, w24, w21, ror #11", + "eor w24, w24, w21, ror #25", + "add w23, w23, w24", + "mov w24, v16.s[0]", + "add w23, w23, w24", + "mov w24, v19.s[0]", + "add w23, w23, w24", + "mov w24, v20.s[3]", + "mov w25, v20.s[2]", + "mov w30, v19.s[3]", + "and w18, w25, w30", + "orr w30, w25, w30", + "and w30, w24, w30", + "orr w30, w30, w18", + "add w30, w23, w30", + "ror w18, w24, #2", + "eor w18, w18, w24, ror #13", + "eor w18, w18, w24, ror #22", + "add w30, w30, w18", + "mov w18, v19.s[2]", + "add w23, w23, w18", + "and w21, w23, w21", + "bic w22, w22, w23", + "eor w21, w21, w22", + "ror w22, w23, #6", + "eor w22, w22, w23, ror #11", + "eor w22, w22, w23, ror #25", + "add w21, w21, w22", + "mov w22, v16.s[1]", + "add w21, w21, w22", "mov w22, v19.s[1]", - "and w23, w20, w21", - "bic w22, w22, w20", - "eor w22, w23, w22", - "ror w23, w20, #6", - "eor w23, w23, w20, ror #11", - "eor w23, w23, w20, ror #25", - "add w22, w22, w23", - "mov w23, v16.s[0]", - "add w22, w22, w23", - "mov w23, v19.s[0]", - "add w22, w22, w23", - "mov w23, v20.s[3]", - "mov w24, v20.s[2]", - "mov w25, v19.s[3]", - "and w30, w24, w25", - "orr w25, w24, w25", - "and w25, w23, w25", - "orr w25, w25, w30", - "add w25, w22, w25", - "ror w30, w23, #2", - "eor w30, w30, w23, ror #13", - "eor w30, w30, w23, ror #22", - "add w25, w25, w30", - "mov w30, v19.s[2]", - "add w22, w22, w30", - "and w20, w22, w20", - "bic w21, w21, w22", - "eor w20, w20, w21", - "ror w21, w22, #6", - "eor w21, w21, w22, ror #11", - "eor w21, w21, w22, ror #25", - "add w20, w20, w21", - "mov w21, v16.s[1]", - "add w20, w20, w21", - "mov w21, v19.s[1]", - "add w20, w20, w21", - "and w21, w23, w24", - "orr w23, w23, w24", - "and w23, w25, w23", - "orr w21, w23, w21", - "add w21, w20, w21", - "ror w23, w25, #2", - "eor w23, w23, w25, ror #13", - "eor w23, w23, w25, ror #22", - "add w21, w21, w23", - "mov w23, v19.s[3]", - "add w20, w20, w23", + "add w21, w21, w22", + "and w22, w24, w25", + "orr w24, w24, w25", + "and w24, w30, w24", + "orr w22, w24, w22", + "add w22, w21, w22", + "ror w24, w30, #2", + "eor w24, w24, w30, ror #13", + "eor w24, w24, w30, ror #22", + "add w22, w22, w24", + "mov w24, v19.s[3]", + "add w21, w21, w24", "mov v5.16b, v19.16b", - "mov v5.s[3], w21", - "mov v5.s[2], w25", - "mov v5.s[1], w20", + "mov v5.s[3], w22", + "mov v5.s[2], w30", + "mov v5.s[1], w21", "mov v17.16b, v5.16b", - "mov v17.s[0], w22", + "mov v17.s[0], w23", "mov v16.16b, v21.16b", "ext v16.16b, v22.16b, v21.16b, #4", "add v24.4s, v24.4s, v16.4s", - "mov w20, #0x1000", - "movk w20, #0x1, lsl #16", "ldr q16, [x29, x20, sxtx]", - "mov w20, v21.s[2]", - "mov w21, v21.s[3]", - "mov w22, v24.s[0]", - "ror w23, w20, #17", - "ror w24, w20, #19", - "eor w23, w23, w24", - "lsr w20, w20, #10", - "eor w20, w23, w20", - "add w20, w22, w20", - "mov w22, v24.s[1]", - "ror w23, w21, #17", - "ror w24, w21, #19", - "eor w23, w23, w24", + "mov w21, v21.s[2]", + "mov w22, v21.s[3]", + "mov w23, v24.s[0]", + "ror w24, w21, #17", + "ror w25, w21, #19", + "eor w24, w24, w25", "lsr w21, w21, #10", - "eor w21, w23, w21", - "add w21, w22, w21", - "mov w22, v24.s[2]", - "ror w23, w20, #17", - "ror w24, w20, #19", - "eor w23, w23, w24", - "lsr w24, w20, #10", - "eor w23, w23, w24", - "add w22, w22, w23", - "mov w23, v24.s[3]", + "eor w21, w24, w21", + "add w21, w23, w21", + "mov w23, v24.s[1]", + "ror w24, w22, #17", + "ror w25, w22, #19", + "eor w24, w24, w25", + "lsr w22, w22, #10", + "eor w22, w24, w22", + "add w22, w23, w22", + "mov w23, v24.s[2]", "ror w24, w21, #17", "ror w25, w21, #19", "eor w24, w24, w25", "lsr w25, w21, #10", "eor w24, w24, w25", "add w23, w23, w24", + "mov w24, v24.s[3]", + "ror w25, w22, #17", + "ror w30, w22, #19", + "eor w25, w25, w30", + "lsr w30, w22, #10", + "eor w25, w25, w30", + "add w24, w24, w25", "mov v5.16b, v24.16b", - "mov v5.s[3], w23", - "mov v5.s[2], w22", - "mov v5.s[1], w21", + "mov v5.s[3], w24", + "mov v5.s[2], w23", + "mov v5.s[1], w22", "mov v24.16b, v5.16b", - "mov v24.s[0], w20", + "mov v24.s[0], w21", "add v16.4s, v16.4s, v23.4s", "unimplemented (Unimplemented)", - "mov w20, v17.s[1]", - "mov w21, v17.s[0]", - "mov w22, v20.s[1]", - "and w23, w20, w21", - "bic w22, w22, w20", - "eor w22, w23, w22", - "ror w23, w20, #6", - "eor w23, w23, w20, ror #11", - "eor w23, w23, w20, ror #25", - "add w22, w22, w23", - "mov w23, v16.s[0]", - "add w22, w22, w23", - "mov w23, v20.s[0]", - "add w22, w22, w23", - "mov w23, v17.s[3]", - "mov w24, v17.s[2]", - "mov w25, v20.s[3]", - "and w30, w24, w25", - "orr w25, w24, w25", - "and w25, w23, w25", - "orr w25, w25, w30", - "add w25, w22, w25", - "ror w30, w23, #2", - "eor w30, w30, w23, ror #13", - "eor w30, w30, w23, ror #22", - "add w25, w25, w30", - "mov w30, v20.s[2]", - "add w22, w22, w30", - "and w20, w22, w20", - "bic w21, w21, w22", - "eor w20, w20, w21", - "ror w21, w22, #6", - "eor w21, w21, w22, ror #11", - "eor w21, w21, w22, ror #25", - "add w20, w20, w21", - "mov w21, v16.s[1]", - "add w20, w20, w21", - "mov w21, v20.s[1]", - "add w20, w20, w21", - "and w21, w23, w24", - "orr w23, w23, w24", - "and w23, w25, w23", - "orr w21, w23, w21", - "add w21, w20, w21", - "ror w23, w25, #2", - "eor w23, w23, w25, ror #13", - "eor w23, w23, w25, ror #22", - "add w21, w21, w23", - "mov w23, v20.s[3]", - "add w20, w20, w23", - "mov v5.16b, v20.16b", - "mov v5.s[3], w21", - "mov v5.s[2], w25", - "mov v5.s[1], w20", - "mov v20.16b, v5.16b", - "mov v20.s[0], w22", - "tbl v16.16b, {v16.16b}, v4.16b", - "mov w20, v20.s[1]", - "mov w21, v20.s[0]", - "mov w22, v17.s[1]", - "and w23, w20, w21", - "bic w22, w22, w20", - "eor w22, w23, w22", - "ror w23, w20, #6", - "eor w23, w23, w20, ror #11", - "eor w23, w23, w20, ror #25", - "add w22, w22, w23", - "mov w23, v16.s[0]", - "add w22, w22, w23", - "mov w23, v17.s[0]", - "add w22, w22, w23", - "mov w23, v20.s[3]", - "mov w24, v20.s[2]", - "mov w25, v17.s[3]", - "and w30, w24, w25", - "orr w25, w24, w25", - "and w25, w23, w25", - "orr w25, w25, w30", - "add w25, w22, w25", - "ror w30, w23, #2", - "eor w30, w30, w23, ror #13", - "eor w30, w30, w23, ror #22", - "add w25, w25, w30", - "mov w30, v17.s[2]", - "add w22, w22, w30", - "and w20, w22, w20", - "bic w21, w21, w22", - "eor w20, w20, w21", - "ror w21, w22, #6", - "eor w21, w21, w22, ror #11", - "eor w21, w21, w22, ror #25", - "add w20, w20, w21", - "mov w21, v16.s[1]", - "add w20, w20, w21", "mov w21, v17.s[1]", - "add w20, w20, w21", - "and w21, w23, w24", - "orr w23, w23, w24", - "and w23, w25, w23", - "orr w21, w23, w21", - "add w21, w20, w21", - "ror w23, w25, #2", - "eor w23, w23, w25, ror #13", - "eor w23, w23, w25, ror #22", - "add w21, w21, w23", - "mov w23, v17.s[3]", - "add w20, w20, w23", + "mov w22, v17.s[0]", + "mov w23, v20.s[1]", + "and w24, w21, w22", + "bic w23, w23, w21", + "eor w23, w24, w23", + "ror w24, w21, #6", + "eor w24, w24, w21, ror #11", + "eor w24, w24, w21, ror #25", + "add w23, w23, w24", + "mov w24, v16.s[0]", + "add w23, w23, w24", + "mov w24, v20.s[0]", + "add w23, w23, w24", + "mov w24, v17.s[3]", + "mov w25, v17.s[2]", + "mov w30, v20.s[3]", + "and w18, w25, w30", + "orr w30, w25, w30", + "and w30, w24, w30", + "orr w30, w30, w18", + "add w30, w23, w30", + "ror w18, w24, #2", + "eor w18, w18, w24, ror #13", + "eor w18, w18, w24, ror #22", + "add w30, w30, w18", + "mov w18, v20.s[2]", + "add w23, w23, w18", + "and w21, w23, w21", + "bic w22, w22, w23", + "eor w21, w21, w22", + "ror w22, w23, #6", + "eor w22, w22, w23, ror #11", + "eor w22, w22, w23, ror #25", + "add w21, w21, w22", + "mov w22, v16.s[1]", + "add w21, w21, w22", + "mov w22, v20.s[1]", + "add w21, w21, w22", + "and w22, w24, w25", + "orr w24, w24, w25", + "and w24, w30, w24", + "orr w22, w24, w22", + "add w22, w21, w22", + "ror w24, w30, #2", + "eor w24, w24, w30, ror #13", + "eor w24, w24, w30, ror #22", + "add w22, w22, w24", + "mov w24, v20.s[3]", + "add w21, w21, w24", + "mov v5.16b, v20.16b", + "mov v5.s[3], w22", + "mov v5.s[2], w30", + "mov v5.s[1], w21", + "mov v20.16b, v5.16b", + "mov v20.s[0], w23", + "tbl v16.16b, {v16.16b}, v4.16b", + "mov w21, v20.s[1]", + "mov w22, v20.s[0]", + "mov w23, v17.s[1]", + "and w24, w21, w22", + "bic w23, w23, w21", + "eor w23, w24, w23", + "ror w24, w21, #6", + "eor w24, w24, w21, ror #11", + "eor w24, w24, w21, ror #25", + "add w23, w23, w24", + "mov w24, v16.s[0]", + "add w23, w23, w24", + "mov w24, v17.s[0]", + "add w23, w23, w24", + "mov w24, v20.s[3]", + "mov w25, v20.s[2]", + "mov w30, v17.s[3]", + "and w18, w25, w30", + "orr w30, w25, w30", + "and w30, w24, w30", + "orr w30, w30, w18", + "add w30, w23, w30", + "ror w18, w24, #2", + "eor w18, w18, w24, ror #13", + "eor w18, w18, w24, ror #22", + "add w30, w30, w18", + "mov w18, v17.s[2]", + "add w23, w23, w18", + "and w21, w23, w21", + "bic w22, w22, w23", + "eor w21, w21, w22", + "ror w22, w23, #6", + "eor w22, w22, w23, ror #11", + "eor w22, w22, w23, ror #25", + "add w21, w21, w22", + "mov w22, v16.s[1]", + "add w21, w21, w22", + "mov w22, v17.s[1]", + "add w21, w21, w22", + "and w22, w24, w25", + "orr w24, w24, w25", + "and w24, w30, w24", + "orr w22, w24, w22", + "add w22, w21, w22", + "ror w24, w30, #2", + "eor w24, w24, w30, ror #13", + "eor w24, w24, w30, ror #22", + "add w22, w22, w24", + "mov w24, v17.s[3]", + "add w21, w21, w24", "mov v5.16b, v17.16b", - "mov v5.s[3], w21", - "mov v5.s[2], w25", - "mov v5.s[1], w20", + "mov v5.s[3], w22", + "mov v5.s[2], w30", + "mov v5.s[1], w21", "mov v17.16b, v5.16b", - "mov v17.s[0], w22", + "mov v17.s[0], w23", "mov v16.16b, v24.16b", "ext v16.16b, v21.16b, v24.16b, #4", "add v23.4s, v23.4s, v16.4s", - "mov w20, #0x1000", - "movk w20, #0x1, lsl #16", "ldr q16, [x29, x20, sxtx]", "mov w20, v24.s[2]", "mov w21, v24.s[3]", @@ -663,43 +659,353 @@ "mov w20, #0x1000", "movk w20, #0x1, lsl #16", "ldr q16, [x29, x20, sxtx]", - "mov w20, v23.s[2]", - "mov w21, v23.s[3]", - "mov w22, v22.s[0]", - "ror w23, w20, #17", - "ror w24, w20, #19", - "eor w23, w23, w24", - "lsr w20, w20, #10", - "eor w20, w23, w20", - "add w20, w22, w20", - "mov w22, v22.s[1]", - "ror w23, w21, #17", - "ror w24, w21, #19", - "eor w23, w23, w24", + "mov w21, v23.s[2]", + "mov w22, v23.s[3]", + "mov w23, v22.s[0]", + "ror w24, w21, #17", + "ror w25, w21, #19", + "eor w24, w24, w25", "lsr w21, w21, #10", - "eor w21, w23, w21", - "add w21, w22, w21", - "mov w22, v22.s[2]", - "ror w23, w20, #17", - "ror w24, w20, #19", - "eor w23, w23, w24", - "lsr w24, w20, #10", - "eor w23, w23, w24", - "add w22, w22, w23", - "mov w23, v22.s[3]", + "eor w21, w24, w21", + "add w21, w23, w21", + "mov w23, v22.s[1]", + "ror w24, w22, #17", + "ror w25, w22, #19", + "eor w24, w24, w25", + "lsr w22, w22, #10", + "eor w22, w24, w22", + "add w22, w23, w22", + "mov w23, v22.s[2]", "ror w24, w21, #17", "ror w25, w21, #19", "eor w24, w24, w25", "lsr w25, w21, #10", "eor w24, w24, w25", "add w23, w23, w24", + "mov w24, v22.s[3]", + "ror w25, w22, #17", + "ror w30, w22, #19", + "eor w25, w25, w30", + "lsr w30, w22, #10", + "eor w25, w25, w30", + "add w24, w24, w25", "mov v5.16b, v22.16b", + "mov v5.s[3], w24", + "mov v5.s[2], w23", + "mov v5.s[1], w22", + "mov v22.16b, v5.16b", + "mov v22.s[0], w21", + "add v16.4s, v16.4s, v21.4s", + "unimplemented (Unimplemented)", + "mov w21, v17.s[1]", + "mov w22, v17.s[0]", + "mov w23, v20.s[1]", + "and w24, w21, w22", + "bic w23, w23, w21", + "eor w23, w24, w23", + "ror w24, w21, #6", + "eor w24, w24, w21, ror #11", + "eor w24, w24, w21, ror #25", + "add w23, w23, w24", + "mov w24, v16.s[0]", + "add w23, w23, w24", + "mov w24, v20.s[0]", + "add w23, w23, w24", + "mov w24, v17.s[3]", + "mov w25, v17.s[2]", + "mov w30, v20.s[3]", + "and w18, w25, w30", + "orr w30, w25, w30", + "and w30, w24, w30", + "orr w30, w30, w18", + "add w30, w23, w30", + "ror w18, w24, #2", + "eor w18, w18, w24, ror #13", + "eor w18, w18, w24, ror #22", + "add w30, w30, w18", + "mov w18, v20.s[2]", + "add w23, w23, w18", + "and w21, w23, w21", + "bic w22, w22, w23", + "eor w21, w21, w22", + "ror w22, w23, #6", + "eor w22, w22, w23, ror #11", + "eor w22, w22, w23, ror #25", + "add w21, w21, w22", + "mov w22, v16.s[1]", + "add w21, w21, w22", + "mov w22, v20.s[1]", + "add w21, w21, w22", + "and w22, w24, w25", + "orr w24, w24, w25", + "and w24, w30, w24", + "orr w22, w24, w22", + "add w22, w21, w22", + "ror w24, w30, #2", + "eor w24, w24, w30, ror #13", + "eor w24, w24, w30, ror #22", + "add w22, w22, w24", + "mov w24, v20.s[3]", + "add w21, w21, w24", + "mov v5.16b, v20.16b", + "mov v5.s[3], w22", + "mov v5.s[2], w30", + "mov v5.s[1], w21", + "mov v20.16b, v5.16b", + "mov v20.s[0], w23", + "tbl v16.16b, {v16.16b}, v4.16b", + "mov w21, v20.s[1]", + "mov w22, v20.s[0]", + "mov w23, v17.s[1]", + "and w24, w21, w22", + "bic w23, w23, w21", + "eor w23, w24, w23", + "ror w24, w21, #6", + "eor w24, w24, w21, ror #11", + "eor w24, w24, w21, ror #25", + "add w23, w23, w24", + "mov w24, v16.s[0]", + "add w23, w23, w24", + "mov w24, v17.s[0]", + "add w23, w23, w24", + "mov w24, v20.s[3]", + "mov w25, v20.s[2]", + "mov w30, v17.s[3]", + "and w18, w25, w30", + "orr w30, w25, w30", + "and w30, w24, w30", + "orr w30, w30, w18", + "add w30, w23, w30", + "ror w18, w24, #2", + "eor w18, w18, w24, ror #13", + "eor w18, w18, w24, ror #22", + "add w30, w30, w18", + "mov w18, v17.s[2]", + "add w23, w23, w18", + "and w21, w23, w21", + "bic w22, w22, w23", + "eor w21, w21, w22", + "ror w22, w23, #6", + "eor w22, w22, w23, ror #11", + "eor w22, w22, w23, ror #25", + "add w21, w21, w22", + "mov w22, v16.s[1]", + "add w21, w21, w22", + "mov w22, v17.s[1]", + "add w21, w21, w22", + "and w22, w24, w25", + "orr w24, w24, w25", + "and w24, w30, w24", + "orr w22, w24, w22", + "add w22, w21, w22", + "ror w24, w30, #2", + "eor w24, w24, w30, ror #13", + "eor w24, w24, w30, ror #22", + "add w22, w22, w24", + "mov w24, v17.s[3]", + "add w21, w21, w24", + "mov v5.16b, v17.16b", + "mov v5.s[3], w22", + "mov v5.s[2], w30", + "mov v5.s[1], w21", + "mov v17.16b, v5.16b", + "mov v17.s[0], w23", + "mov v16.16b, v22.16b", + "ext v16.16b, v23.16b, v22.16b, #4", + "add v21.4s, v21.4s, v16.4s", + "ldr q16, [x29, x20, sxtx]", + "mov w21, v22.s[2]", + "mov w22, v22.s[3]", + "mov w23, v21.s[0]", + "ror w24, w21, #17", + "ror w25, w21, #19", + "eor w24, w24, w25", + "lsr w21, w21, #10", + "eor w21, w24, w21", + "add w21, w23, w21", + "mov w23, v21.s[1]", + "ror w24, w22, #17", + "ror w25, w22, #19", + "eor w24, w24, w25", + "lsr w22, w22, #10", + "eor w22, w24, w22", + "add w22, w23, w22", + "mov w23, v21.s[2]", + "ror w24, w21, #17", + "ror w25, w21, #19", + "eor w24, w24, w25", + "lsr w25, w21, #10", + "eor w24, w24, w25", + "add w23, w23, w24", + "mov w24, v21.s[3]", + "ror w25, w22, #17", + "ror w30, w22, #19", + "eor w25, w25, w30", + "lsr w30, w22, #10", + "eor w25, w25, w30", + "add w24, w24, w25", + "mov v5.16b, v21.16b", + "mov v5.s[3], w24", + "mov v5.s[2], w23", + "mov v5.s[1], w22", + "mov v21.16b, v5.16b", + "mov v21.s[0], w21", + "add v16.4s, v16.4s, v24.4s", + "unimplemented (Unimplemented)", + "mov w21, v17.s[1]", + "mov w22, v17.s[0]", + "mov w23, v20.s[1]", + "and w24, w21, w22", + "bic w23, w23, w21", + "eor w23, w24, w23", + "ror w24, w21, #6", + "eor w24, w24, w21, ror #11", + "eor w24, w24, w21, ror #25", + "add w23, w23, w24", + "mov w24, v16.s[0]", + "add w23, w23, w24", + "mov w24, v20.s[0]", + "add w23, w23, w24", + "mov w24, v17.s[3]", + "mov w25, v17.s[2]", + "mov w30, v20.s[3]", + "and w18, w25, w30", + "orr w30, w25, w30", + "and w30, w24, w30", + "orr w30, w30, w18", + "add w30, w23, w30", + "ror w18, w24, #2", + "eor w18, w18, w24, ror #13", + "eor w18, w18, w24, ror #22", + "add w30, w30, w18", + "mov w18, v20.s[2]", + "add w23, w23, w18", + "and w21, w23, w21", + "bic w22, w22, w23", + "eor w21, w21, w22", + "ror w22, w23, #6", + "eor w22, w22, w23, ror #11", + "eor w22, w22, w23, ror #25", + "add w21, w21, w22", + "mov w22, v16.s[1]", + "add w21, w21, w22", + "mov w22, v20.s[1]", + "add w21, w21, w22", + "and w22, w24, w25", + "orr w24, w24, w25", + "and w24, w30, w24", + "orr w22, w24, w22", + "add w22, w21, w22", + "ror w24, w30, #2", + "eor w24, w24, w30, ror #13", + "eor w24, w24, w30, ror #22", + "add w22, w22, w24", + "mov w24, v20.s[3]", + "add w21, w21, w24", + "mov v5.16b, v20.16b", + "mov v5.s[3], w22", + "mov v5.s[2], w30", + "mov v5.s[1], w21", + "mov v20.16b, v5.16b", + "mov v20.s[0], w23", + "tbl v16.16b, {v16.16b}, v4.16b", + "mov w21, v20.s[1]", + "mov w22, v20.s[0]", + "mov w23, v17.s[1]", + "and w24, w21, w22", + "bic w23, w23, w21", + "eor w23, w24, w23", + "ror w24, w21, #6", + "eor w24, w24, w21, ror #11", + "eor w24, w24, w21, ror #25", + "add w23, w23, w24", + "mov w24, v16.s[0]", + "add w23, w23, w24", + "mov w24, v17.s[0]", + "add w23, w23, w24", + "mov w24, v20.s[3]", + "mov w25, v20.s[2]", + "mov w30, v17.s[3]", + "and w18, w25, w30", + "orr w30, w25, w30", + "and w30, w24, w30", + "orr w30, w30, w18", + "add w30, w23, w30", + "ror w18, w24, #2", + "eor w18, w18, w24, ror #13", + "eor w18, w18, w24, ror #22", + "add w30, w30, w18", + "mov w18, v17.s[2]", + "add w23, w23, w18", + "and w21, w23, w21", + "bic w22, w22, w23", + "eor w21, w21, w22", + "ror w22, w23, #6", + "eor w22, w22, w23, ror #11", + "eor w22, w22, w23, ror #25", + "add w21, w21, w22", + "mov w22, v16.s[1]", + "add w21, w21, w22", + "mov w22, v17.s[1]", + "add w21, w21, w22", + "and w22, w24, w25", + "orr w24, w24, w25", + "and w24, w30, w24", + "orr w22, w24, w22", + "add w22, w21, w22", + "ror w24, w30, #2", + "eor w24, w24, w30, ror #13", + "eor w24, w24, w30, ror #22", + "add w22, w22, w24", + "mov w24, v17.s[3]", + "add w21, w21, w24", + "mov v5.16b, v17.16b", + "mov v5.s[3], w22", + "mov v5.s[2], w30", + "mov v5.s[1], w21", + "mov v17.16b, v5.16b", + "mov v17.s[0], w23", + "mov v16.16b, v21.16b", + "ext v16.16b, v22.16b, v21.16b, #4", + "add v24.4s, v24.4s, v16.4s", + "ldr q16, [x29, x20, sxtx]", + "mov w20, v21.s[2]", + "mov w21, v21.s[3]", + "mov w22, v24.s[0]", + "ror w23, w20, #17", + "ror w24, w20, #19", + "eor w23, w23, w24", + "lsr w20, w20, #10", + "eor w20, w23, w20", + "add w20, w22, w20", + "mov w22, v24.s[1]", + "ror w23, w21, #17", + "ror w24, w21, #19", + "eor w23, w23, w24", + "lsr w21, w21, #10", + "eor w21, w23, w21", + "add w21, w22, w21", + "mov w22, v24.s[2]", + "ror w23, w20, #17", + "ror w24, w20, #19", + "eor w23, w23, w24", + "lsr w24, w20, #10", + "eor w23, w23, w24", + "add w22, w22, w23", + "mov w23, v24.s[3]", + "ror w24, w21, #17", + "ror w25, w21, #19", + "eor w24, w24, w25", + "lsr w25, w21, #10", + "eor w24, w24, w25", + "add w23, w23, w24", + "mov v5.16b, v24.16b", "mov v5.s[3], w23", "mov v5.s[2], w22", "mov v5.s[1], w21", - "mov v22.16b, v5.16b", - "mov v22.s[0], w20", - "add v16.4s, v16.4s, v21.4s", + "mov v24.16b, v5.16b", + "mov v24.s[0], w20", + "add v16.4s, v16.4s, v23.4s", "unimplemented (Unimplemented)", "mov w20, v17.s[1]", "mov w21, v17.s[0]", @@ -814,11 +1120,321 @@ "mov v5.s[1], w20", "mov v17.16b, v5.16b", "mov v17.s[0], w22", + "mov v16.16b, v24.16b", + "ext v16.16b, v21.16b, v24.16b, #4", + "add v23.4s, v23.4s, v16.4s", + "mov w20, #0x1000", + "movk w20, #0x1, lsl #16", + "ldr q16, [x29, x20, sxtx]", + "mov w21, v24.s[2]", + "mov w22, v24.s[3]", + "mov w23, v23.s[0]", + "ror w24, w21, #17", + "ror w25, w21, #19", + "eor w24, w24, w25", + "lsr w21, w21, #10", + "eor w21, w24, w21", + "add w21, w23, w21", + "mov w23, v23.s[1]", + "ror w24, w22, #17", + "ror w25, w22, #19", + "eor w24, w24, w25", + "lsr w22, w22, #10", + "eor w22, w24, w22", + "add w22, w23, w22", + "mov w23, v23.s[2]", + "ror w24, w21, #17", + "ror w25, w21, #19", + "eor w24, w24, w25", + "lsr w25, w21, #10", + "eor w24, w24, w25", + "add w23, w23, w24", + "mov w24, v23.s[3]", + "ror w25, w22, #17", + "ror w30, w22, #19", + "eor w25, w25, w30", + "lsr w30, w22, #10", + "eor w25, w25, w30", + "add w24, w24, w25", + "mov v5.16b, v23.16b", + "mov v5.s[3], w24", + "mov v5.s[2], w23", + "mov v5.s[1], w22", + "mov v23.16b, v5.16b", + "mov v23.s[0], w21", + "add v16.4s, v16.4s, v22.4s", + "unimplemented (Unimplemented)", + "mov w21, v17.s[1]", + "mov w22, v17.s[0]", + "mov w23, v20.s[1]", + "and w24, w21, w22", + "bic w23, w23, w21", + "eor w23, w24, w23", + "ror w24, w21, #6", + "eor w24, w24, w21, ror #11", + "eor w24, w24, w21, ror #25", + "add w23, w23, w24", + "mov w24, v16.s[0]", + "add w23, w23, w24", + "mov w24, v20.s[0]", + "add w23, w23, w24", + "mov w24, v17.s[3]", + "mov w25, v17.s[2]", + "mov w30, v20.s[3]", + "and w18, w25, w30", + "orr w30, w25, w30", + "and w30, w24, w30", + "orr w30, w30, w18", + "add w30, w23, w30", + "ror w18, w24, #2", + "eor w18, w18, w24, ror #13", + "eor w18, w18, w24, ror #22", + "add w30, w30, w18", + "mov w18, v20.s[2]", + "add w23, w23, w18", + "and w21, w23, w21", + "bic w22, w22, w23", + "eor w21, w21, w22", + "ror w22, w23, #6", + "eor w22, w22, w23, ror #11", + "eor w22, w22, w23, ror #25", + "add w21, w21, w22", + "mov w22, v16.s[1]", + "add w21, w21, w22", + "mov w22, v20.s[1]", + "add w21, w21, w22", + "and w22, w24, w25", + "orr w24, w24, w25", + "and w24, w30, w24", + "orr w22, w24, w22", + "add w22, w21, w22", + "ror w24, w30, #2", + "eor w24, w24, w30, ror #13", + "eor w24, w24, w30, ror #22", + "add w22, w22, w24", + "mov w24, v20.s[3]", + "add w21, w21, w24", + "mov v5.16b, v20.16b", + "mov v5.s[3], w22", + "mov v5.s[2], w30", + "mov v5.s[1], w21", + "mov v20.16b, v5.16b", + "mov v20.s[0], w23", + "tbl v16.16b, {v16.16b}, v4.16b", + "mov w21, v20.s[1]", + "mov w22, v20.s[0]", + "mov w23, v17.s[1]", + "and w24, w21, w22", + "bic w23, w23, w21", + "eor w23, w24, w23", + "ror w24, w21, #6", + "eor w24, w24, w21, ror #11", + "eor w24, w24, w21, ror #25", + "add w23, w23, w24", + "mov w24, v16.s[0]", + "add w23, w23, w24", + "mov w24, v17.s[0]", + "add w23, w23, w24", + "mov w24, v20.s[3]", + "mov w25, v20.s[2]", + "mov w30, v17.s[3]", + "and w18, w25, w30", + "orr w30, w25, w30", + "and w30, w24, w30", + "orr w30, w30, w18", + "add w30, w23, w30", + "ror w18, w24, #2", + "eor w18, w18, w24, ror #13", + "eor w18, w18, w24, ror #22", + "add w30, w30, w18", + "mov w18, v17.s[2]", + "add w23, w23, w18", + "and w21, w23, w21", + "bic w22, w22, w23", + "eor w21, w21, w22", + "ror w22, w23, #6", + "eor w22, w22, w23, ror #11", + "eor w22, w22, w23, ror #25", + "add w21, w21, w22", + "mov w22, v16.s[1]", + "add w21, w21, w22", + "mov w22, v17.s[1]", + "add w21, w21, w22", + "and w22, w24, w25", + "orr w24, w24, w25", + "and w24, w30, w24", + "orr w22, w24, w22", + "add w22, w21, w22", + "ror w24, w30, #2", + "eor w24, w24, w30, ror #13", + "eor w24, w24, w30, ror #22", + "add w22, w22, w24", + "mov w24, v17.s[3]", + "add w21, w21, w24", + "mov v5.16b, v17.16b", + "mov v5.s[3], w22", + "mov v5.s[2], w30", + "mov v5.s[1], w21", + "mov v17.16b, v5.16b", + "mov v17.s[0], w23", + "mov v16.16b, v23.16b", + "ext v16.16b, v24.16b, v23.16b, #4", + "add v22.4s, v22.4s, v16.4s", + "ldr q16, [x29, x20, sxtx]", + "mov w21, v23.s[2]", + "mov w22, v23.s[3]", + "mov w23, v22.s[0]", + "ror w24, w21, #17", + "ror w25, w21, #19", + "eor w24, w24, w25", + "lsr w21, w21, #10", + "eor w21, w24, w21", + "add w21, w23, w21", + "mov w23, v22.s[1]", + "ror w24, w22, #17", + "ror w25, w22, #19", + "eor w24, w24, w25", + "lsr w22, w22, #10", + "eor w22, w24, w22", + "add w22, w23, w22", + "mov w23, v22.s[2]", + "ror w24, w21, #17", + "ror w25, w21, #19", + "eor w24, w24, w25", + "lsr w25, w21, #10", + "eor w24, w24, w25", + "add w23, w23, w24", + "mov w24, v22.s[3]", + "ror w25, w22, #17", + "ror w30, w22, #19", + "eor w25, w25, w30", + "lsr w30, w22, #10", + "eor w25, w25, w30", + "add w24, w24, w25", + "mov v5.16b, v22.16b", + "mov v5.s[3], w24", + "mov v5.s[2], w23", + "mov v5.s[1], w22", + "mov v22.16b, v5.16b", + "mov v22.s[0], w21", + "add v16.4s, v16.4s, v21.4s", + "unimplemented (Unimplemented)", + "mov w21, v17.s[1]", + "mov w22, v17.s[0]", + "mov w23, v20.s[1]", + "and w24, w21, w22", + "bic w23, w23, w21", + "eor w23, w24, w23", + "ror w24, w21, #6", + "eor w24, w24, w21, ror #11", + "eor w24, w24, w21, ror #25", + "add w23, w23, w24", + "mov w24, v16.s[0]", + "add w23, w23, w24", + "mov w24, v20.s[0]", + "add w23, w23, w24", + "mov w24, v17.s[3]", + "mov w25, v17.s[2]", + "mov w30, v20.s[3]", + "and w18, w25, w30", + "orr w30, w25, w30", + "and w30, w24, w30", + "orr w30, w30, w18", + "add w30, w23, w30", + "ror w18, w24, #2", + "eor w18, w18, w24, ror #13", + "eor w18, w18, w24, ror #22", + "add w30, w30, w18", + "mov w18, v20.s[2]", + "add w23, w23, w18", + "and w21, w23, w21", + "bic w22, w22, w23", + "eor w21, w21, w22", + "ror w22, w23, #6", + "eor w22, w22, w23, ror #11", + "eor w22, w22, w23, ror #25", + "add w21, w21, w22", + "mov w22, v16.s[1]", + "add w21, w21, w22", + "mov w22, v20.s[1]", + "add w21, w21, w22", + "and w22, w24, w25", + "orr w24, w24, w25", + "and w24, w30, w24", + "orr w22, w24, w22", + "add w22, w21, w22", + "ror w24, w30, #2", + "eor w24, w24, w30, ror #13", + "eor w24, w24, w30, ror #22", + "add w22, w22, w24", + "mov w24, v20.s[3]", + "add w21, w21, w24", + "mov v5.16b, v20.16b", + "mov v5.s[3], w22", + "mov v5.s[2], w30", + "mov v5.s[1], w21", + "mov v20.16b, v5.16b", + "mov v20.s[0], w23", + "tbl v16.16b, {v16.16b}, v4.16b", + "mov w21, v20.s[1]", + "mov w22, v20.s[0]", + "mov w23, v17.s[1]", + "and w24, w21, w22", + "bic w23, w23, w21", + "eor w23, w24, w23", + "ror w24, w21, #6", + "eor w24, w24, w21, ror #11", + "eor w24, w24, w21, ror #25", + "add w23, w23, w24", + "mov w24, v16.s[0]", + "add w23, w23, w24", + "mov w24, v17.s[0]", + "add w23, w23, w24", + "mov w24, v20.s[3]", + "mov w25, v20.s[2]", + "mov w30, v17.s[3]", + "and w18, w25, w30", + "orr w30, w25, w30", + "and w30, w24, w30", + "orr w30, w30, w18", + "add w30, w23, w30", + "ror w18, w24, #2", + "eor w18, w18, w24, ror #13", + "eor w18, w18, w24, ror #22", + "add w30, w30, w18", + "mov w18, v17.s[2]", + "add w23, w23, w18", + "and w21, w23, w21", + "bic w22, w22, w23", + "eor w21, w21, w22", + "ror w22, w23, #6", + "eor w22, w22, w23, ror #11", + "eor w22, w22, w23, ror #25", + "add w21, w21, w22", + "mov w22, v16.s[1]", + "add w21, w21, w22", + "mov w22, v17.s[1]", + "add w21, w21, w22", + "and w22, w24, w25", + "orr w24, w24, w25", + "and w24, w30, w24", + "orr w22, w24, w22", + "add w22, w21, w22", + "ror w24, w30, #2", + "eor w24, w24, w30, ror #13", + "eor w24, w24, w30, ror #22", + "add w22, w22, w24", + "mov w24, v17.s[3]", + "add w21, w21, w24", + "mov v5.16b, v17.16b", + "mov v5.s[3], w22", + "mov v5.s[2], w30", + "mov v5.s[1], w21", + "mov v17.16b, v5.16b", + "mov v17.s[0], w23", "mov v16.16b, v22.16b", "ext v16.16b, v23.16b, v22.16b, #4", "add v21.4s, v21.4s, v16.4s", - "mov w20, #0x1000", - "movk w20, #0x1, lsl #16", "ldr q16, [x29, x20, sxtx]", "mov w20, v22.s[2]", "mov w21, v22.s[3]", @@ -977,947 +1593,315 @@ "mov w20, #0x1000", "movk w20, #0x1, lsl #16", "ldr q16, [x29, x20, sxtx]", - "mov w20, v21.s[2]", - "mov w21, v21.s[3]", - "mov w22, v24.s[0]", - "ror w23, w20, #17", - "ror w24, w20, #19", - "eor w23, w23, w24", - "lsr w20, w20, #10", - "eor w20, w23, w20", - "add w20, w22, w20", - "mov w22, v24.s[1]", - "ror w23, w21, #17", - "ror w24, w21, #19", - "eor w23, w23, w24", + "mov w21, v21.s[2]", + "mov w22, v21.s[3]", + "mov w23, v24.s[0]", + "ror w24, w21, #17", + "ror w25, w21, #19", + "eor w24, w24, w25", "lsr w21, w21, #10", - "eor w21, w23, w21", - "add w21, w22, w21", - "mov w22, v24.s[2]", - "ror w23, w20, #17", - "ror w24, w20, #19", - "eor w23, w23, w24", - "lsr w24, w20, #10", - "eor w23, w23, w24", - "add w22, w22, w23", - "mov w23, v24.s[3]", + "eor w21, w24, w21", + "add w21, w23, w21", + "mov w23, v24.s[1]", + "ror w24, w22, #17", + "ror w25, w22, #19", + "eor w24, w24, w25", + "lsr w22, w22, #10", + "eor w22, w24, w22", + "add w22, w23, w22", + "mov w23, v24.s[2]", "ror w24, w21, #17", "ror w25, w21, #19", "eor w24, w24, w25", "lsr w25, w21, #10", "eor w24, w24, w25", "add w23, w23, w24", + "mov w24, v24.s[3]", + "ror w25, w22, #17", + "ror w30, w22, #19", + "eor w25, w25, w30", + "lsr w30, w22, #10", + "eor w25, w25, w30", + "add w24, w24, w25", "mov v5.16b, v24.16b", - "mov v5.s[3], w23", - "mov v5.s[2], w22", - "mov v5.s[1], w21", + "mov v5.s[3], w24", + "mov v5.s[2], w23", + "mov v5.s[1], w22", "mov v24.16b, v5.16b", - "mov v24.s[0], w20", + "mov v24.s[0], w21", "add v16.4s, v16.4s, v23.4s", "unimplemented (Unimplemented)", - "mov w20, v17.s[1]", - "mov w21, v17.s[0]", - "mov w22, v20.s[1]", - "and w23, w20, w21", - "bic w22, w22, w20", - "eor w22, w23, w22", - "ror w23, w20, #6", - "eor w23, w23, w20, ror #11", - "eor w23, w23, w20, ror #25", - "add w22, w22, w23", - "mov w23, v16.s[0]", - "add w22, w22, w23", - "mov w23, v20.s[0]", - "add w22, w22, w23", - "mov w23, v17.s[3]", - "mov w24, v17.s[2]", - "mov w25, v20.s[3]", - "and w30, w24, w25", - "orr w25, w24, w25", - "and w25, w23, w25", - "orr w25, w25, w30", - "add w25, w22, w25", - "ror w30, w23, #2", - "eor w30, w30, w23, ror #13", - "eor w30, w30, w23, ror #22", - "add w25, w25, w30", - "mov w30, v20.s[2]", - "add w22, w22, w30", - "and w20, w22, w20", - "bic w21, w21, w22", - "eor w20, w20, w21", - "ror w21, w22, #6", - "eor w21, w21, w22, ror #11", - "eor w21, w21, w22, ror #25", - "add w20, w20, w21", - "mov w21, v16.s[1]", - "add w20, w20, w21", - "mov w21, v20.s[1]", - "add w20, w20, w21", - "and w21, w23, w24", - "orr w23, w23, w24", - "and w23, w25, w23", - "orr w21, w23, w21", - "add w21, w20, w21", - "ror w23, w25, #2", - "eor w23, w23, w25, ror #13", - "eor w23, w23, w25, ror #22", - "add w21, w21, w23", - "mov w23, v20.s[3]", - "add w20, w20, w23", - "mov v5.16b, v20.16b", - "mov v5.s[3], w21", - "mov v5.s[2], w25", - "mov v5.s[1], w20", - "mov v20.16b, v5.16b", - "mov v20.s[0], w22", - "tbl v16.16b, {v16.16b}, v4.16b", - "mov w20, v20.s[1]", - "mov w21, v20.s[0]", - "mov w22, v17.s[1]", - "and w23, w20, w21", - "bic w22, w22, w20", - "eor w22, w23, w22", - "ror w23, w20, #6", - "eor w23, w23, w20, ror #11", - "eor w23, w23, w20, ror #25", - "add w22, w22, w23", - "mov w23, v16.s[0]", - "add w22, w22, w23", - "mov w23, v17.s[0]", - "add w22, w22, w23", - "mov w23, v20.s[3]", - "mov w24, v20.s[2]", - "mov w25, v17.s[3]", - "and w30, w24, w25", - "orr w25, w24, w25", - "and w25, w23, w25", - "orr w25, w25, w30", - "add w25, w22, w25", - "ror w30, w23, #2", - "eor w30, w30, w23, ror #13", - "eor w30, w30, w23, ror #22", - "add w25, w25, w30", - "mov w30, v17.s[2]", - "add w22, w22, w30", - "and w20, w22, w20", - "bic w21, w21, w22", - "eor w20, w20, w21", - "ror w21, w22, #6", - "eor w21, w21, w22, ror #11", - "eor w21, w21, w22, ror #25", - "add w20, w20, w21", - "mov w21, v16.s[1]", - "add w20, w20, w21", "mov w21, v17.s[1]", - "add w20, w20, w21", - "and w21, w23, w24", - "orr w23, w23, w24", - "and w23, w25, w23", - "orr w21, w23, w21", - "add w21, w20, w21", - "ror w23, w25, #2", - "eor w23, w23, w25, ror #13", - "eor w23, w23, w25, ror #22", - "add w21, w21, w23", - "mov w23, v17.s[3]", - "add w20, w20, w23", + "mov w22, v17.s[0]", + "mov w23, v20.s[1]", + "and w24, w21, w22", + "bic w23, w23, w21", + "eor w23, w24, w23", + "ror w24, w21, #6", + "eor w24, w24, w21, ror #11", + "eor w24, w24, w21, ror #25", + "add w23, w23, w24", + "mov w24, v16.s[0]", + "add w23, w23, w24", + "mov w24, v20.s[0]", + "add w23, w23, w24", + "mov w24, v17.s[3]", + "mov w25, v17.s[2]", + "mov w30, v20.s[3]", + "and w18, w25, w30", + "orr w30, w25, w30", + "and w30, w24, w30", + "orr w30, w30, w18", + "add w30, w23, w30", + "ror w18, w24, #2", + "eor w18, w18, w24, ror #13", + "eor w18, w18, w24, ror #22", + "add w30, w30, w18", + "mov w18, v20.s[2]", + "add w23, w23, w18", + "and w21, w23, w21", + "bic w22, w22, w23", + "eor w21, w21, w22", + "ror w22, w23, #6", + "eor w22, w22, w23, ror #11", + "eor w22, w22, w23, ror #25", + "add w21, w21, w22", + "mov w22, v16.s[1]", + "add w21, w21, w22", + "mov w22, v20.s[1]", + "add w21, w21, w22", + "and w22, w24, w25", + "orr w24, w24, w25", + "and w24, w30, w24", + "orr w22, w24, w22", + "add w22, w21, w22", + "ror w24, w30, #2", + "eor w24, w24, w30, ror #13", + "eor w24, w24, w30, ror #22", + "add w22, w22, w24", + "mov w24, v20.s[3]", + "add w21, w21, w24", + "mov v5.16b, v20.16b", + "mov v5.s[3], w22", + "mov v5.s[2], w30", + "mov v5.s[1], w21", + "mov v20.16b, v5.16b", + "mov v20.s[0], w23", + "tbl v16.16b, {v16.16b}, v4.16b", + "mov w21, v20.s[1]", + "mov w22, v20.s[0]", + "mov w23, v17.s[1]", + "and w24, w21, w22", + "bic w23, w23, w21", + "eor w23, w24, w23", + "ror w24, w21, #6", + "eor w24, w24, w21, ror #11", + "eor w24, w24, w21, ror #25", + "add w23, w23, w24", + "mov w24, v16.s[0]", + "add w23, w23, w24", + "mov w24, v17.s[0]", + "add w23, w23, w24", + "mov w24, v20.s[3]", + "mov w25, v20.s[2]", + "mov w30, v17.s[3]", + "and w18, w25, w30", + "orr w30, w25, w30", + "and w30, w24, w30", + "orr w30, w30, w18", + "add w30, w23, w30", + "ror w18, w24, #2", + "eor w18, w18, w24, ror #13", + "eor w18, w18, w24, ror #22", + "add w30, w30, w18", + "mov w18, v17.s[2]", + "add w23, w23, w18", + "and w21, w23, w21", + "bic w22, w22, w23", + "eor w21, w21, w22", + "ror w22, w23, #6", + "eor w22, w22, w23, ror #11", + "eor w22, w22, w23, ror #25", + "add w21, w21, w22", + "mov w22, v16.s[1]", + "add w21, w21, w22", + "mov w22, v17.s[1]", + "add w21, w21, w22", + "and w22, w24, w25", + "orr w24, w24, w25", + "and w24, w30, w24", + "orr w22, w24, w22", + "add w22, w21, w22", + "ror w24, w30, #2", + "eor w24, w24, w30, ror #13", + "eor w24, w24, w30, ror #22", + "add w22, w22, w24", + "mov w24, v17.s[3]", + "add w21, w21, w24", "mov v5.16b, v17.16b", - "mov v5.s[3], w21", - "mov v5.s[2], w25", - "mov v5.s[1], w20", + "mov v5.s[3], w22", + "mov v5.s[2], w30", + "mov v5.s[1], w21", "mov v17.16b, v5.16b", - "mov v17.s[0], w22", + "mov v17.s[0], w23", "mov v16.16b, v24.16b", "ext v16.16b, v21.16b, v24.16b, #4", "add v23.4s, v23.4s, v16.4s", - "mov w20, #0x1000", - "movk w20, #0x1, lsl #16", "ldr q16, [x29, x20, sxtx]", - "mov w20, v24.s[2]", - "mov w21, v24.s[3]", - "mov w22, v23.s[0]", - "ror w23, w20, #17", - "ror w24, w20, #19", - "eor w23, w23, w24", - "lsr w20, w20, #10", - "eor w20, w23, w20", - "add w20, w22, w20", - "mov w22, v23.s[1]", - "ror w23, w21, #17", - "ror w24, w21, #19", - "eor w23, w23, w24", + "mov w21, v24.s[2]", + "mov w22, v24.s[3]", + "mov w23, v23.s[0]", + "ror w24, w21, #17", + "ror w25, w21, #19", + "eor w24, w24, w25", "lsr w21, w21, #10", - "eor w21, w23, w21", - "add w21, w22, w21", - "mov w22, v23.s[2]", - "ror w23, w20, #17", - "ror w24, w20, #19", - "eor w23, w23, w24", - "lsr w24, w20, #10", - "eor w23, w23, w24", - "add w22, w22, w23", - "mov w23, v23.s[3]", + "eor w21, w24, w21", + "add w21, w23, w21", + "mov w23, v23.s[1]", + "ror w24, w22, #17", + "ror w25, w22, #19", + "eor w24, w24, w25", + "lsr w22, w22, #10", + "eor w22, w24, w22", + "add w22, w23, w22", + "mov w23, v23.s[2]", "ror w24, w21, #17", "ror w25, w21, #19", "eor w24, w24, w25", "lsr w25, w21, #10", "eor w24, w24, w25", "add w23, w23, w24", + "mov w24, v23.s[3]", + "ror w25, w22, #17", + "ror w30, w22, #19", + "eor w25, w25, w30", + "lsr w30, w22, #10", + "eor w25, w25, w30", + "add w24, w24, w25", "mov v5.16b, v23.16b", - "mov v5.s[3], w23", - "mov v5.s[2], w22", - "mov v5.s[1], w21", + "mov v5.s[3], w24", + "mov v5.s[2], w23", + "mov v5.s[1], w22", "mov v23.16b, v5.16b", - "mov v23.s[0], w20", + "mov v23.s[0], w21", "add v16.4s, v16.4s, v22.4s", "unimplemented (Unimplemented)", - "mov w20, v17.s[1]", - "mov w21, v17.s[0]", - "mov w22, v20.s[1]", - "and w23, w20, w21", - "bic w22, w22, w20", - "eor w22, w23, w22", - "ror w23, w20, #6", - "eor w23, w23, w20, ror #11", - "eor w23, w23, w20, ror #25", - "add w22, w22, w23", - "mov w23, v16.s[0]", - "add w22, w22, w23", - "mov w23, v20.s[0]", - "add w22, w22, w23", - "mov w23, v17.s[3]", - "mov w24, v17.s[2]", - "mov w25, v20.s[3]", - "and w30, w24, w25", - "orr w25, w24, w25", - "and w25, w23, w25", - "orr w25, w25, w30", - "add w25, w22, w25", - "ror w30, w23, #2", - "eor w30, w30, w23, ror #13", - "eor w30, w30, w23, ror #22", - "add w25, w25, w30", - "mov w30, v20.s[2]", - "add w22, w22, w30", - "and w20, w22, w20", - "bic w21, w21, w22", - "eor w20, w20, w21", - "ror w21, w22, #6", - "eor w21, w21, w22, ror #11", - "eor w21, w21, w22, ror #25", - "add w20, w20, w21", - "mov w21, v16.s[1]", - "add w20, w20, w21", - "mov w21, v20.s[1]", - "add w20, w20, w21", - "and w21, w23, w24", - "orr w23, w23, w24", - "and w23, w25, w23", - "orr w21, w23, w21", - "add w21, w20, w21", - "ror w23, w25, #2", - "eor w23, w23, w25, ror #13", - "eor w23, w23, w25, ror #22", - "add w21, w21, w23", - "mov w23, v20.s[3]", - "add w20, w20, w23", - "mov v5.16b, v20.16b", - "mov v5.s[3], w21", - "mov v5.s[2], w25", - "mov v5.s[1], w20", - "mov v20.16b, v5.16b", - "mov v20.s[0], w22", - "tbl v16.16b, {v16.16b}, v4.16b", - "mov w20, v20.s[1]", - "mov w21, v20.s[0]", - "mov w22, v17.s[1]", - "and w23, w20, w21", - "bic w22, w22, w20", - "eor w22, w23, w22", - "ror w23, w20, #6", - "eor w23, w23, w20, ror #11", - "eor w23, w23, w20, ror #25", - "add w22, w22, w23", - "mov w23, v16.s[0]", - "add w22, w22, w23", - "mov w23, v17.s[0]", - "add w22, w22, w23", - "mov w23, v20.s[3]", - "mov w24, v20.s[2]", - "mov w25, v17.s[3]", - "and w30, w24, w25", - "orr w25, w24, w25", - "and w25, w23, w25", - "orr w25, w25, w30", - "add w25, w22, w25", - "ror w30, w23, #2", - "eor w30, w30, w23, ror #13", - "eor w30, w30, w23, ror #22", - "add w25, w25, w30", - "mov w30, v17.s[2]", - "add w22, w22, w30", - "and w20, w22, w20", - "bic w21, w21, w22", - "eor w20, w20, w21", - "ror w21, w22, #6", - "eor w21, w21, w22, ror #11", - "eor w21, w21, w22, ror #25", - "add w20, w20, w21", - "mov w21, v16.s[1]", - "add w20, w20, w21", "mov w21, v17.s[1]", - "add w20, w20, w21", - "and w21, w23, w24", - "orr w23, w23, w24", - "and w23, w25, w23", - "orr w21, w23, w21", - "add w21, w20, w21", - "ror w23, w25, #2", - "eor w23, w23, w25, ror #13", - "eor w23, w23, w25, ror #22", - "add w21, w21, w23", - "mov w23, v17.s[3]", - "add w20, w20, w23", + "mov w22, v17.s[0]", + "mov w23, v20.s[1]", + "and w24, w21, w22", + "bic w23, w23, w21", + "eor w23, w24, w23", + "ror w24, w21, #6", + "eor w24, w24, w21, ror #11", + "eor w24, w24, w21, ror #25", + "add w23, w23, w24", + "mov w24, v16.s[0]", + "add w23, w23, w24", + "mov w24, v20.s[0]", + "add w23, w23, w24", + "mov w24, v17.s[3]", + "mov w25, v17.s[2]", + "mov w30, v20.s[3]", + "and w18, w25, w30", + "orr w30, w25, w30", + "and w30, w24, w30", + "orr w30, w30, w18", + "add w30, w23, w30", + "ror w18, w24, #2", + "eor w18, w18, w24, ror #13", + "eor w18, w18, w24, ror #22", + "add w30, w30, w18", + "mov w18, v20.s[2]", + "add w23, w23, w18", + "and w21, w23, w21", + "bic w22, w22, w23", + "eor w21, w21, w22", + "ror w22, w23, #6", + "eor w22, w22, w23, ror #11", + "eor w22, w22, w23, ror #25", + "add w21, w21, w22", + "mov w22, v16.s[1]", + "add w21, w21, w22", + "mov w22, v20.s[1]", + "add w21, w21, w22", + "and w22, w24, w25", + "orr w24, w24, w25", + "and w24, w30, w24", + "orr w22, w24, w22", + "add w22, w21, w22", + "ror w24, w30, #2", + "eor w24, w24, w30, ror #13", + "eor w24, w24, w30, ror #22", + "add w22, w22, w24", + "mov w24, v20.s[3]", + "add w21, w21, w24", + "mov v5.16b, v20.16b", + "mov v5.s[3], w22", + "mov v5.s[2], w30", + "mov v5.s[1], w21", + "mov v20.16b, v5.16b", + "mov v20.s[0], w23", + "tbl v16.16b, {v16.16b}, v4.16b", + "mov w21, v20.s[1]", + "mov w22, v20.s[0]", + "mov w23, v17.s[1]", + "and w24, w21, w22", + "bic w23, w23, w21", + "eor w23, w24, w23", + "ror w24, w21, #6", + "eor w24, w24, w21, ror #11", + "eor w24, w24, w21, ror #25", + "add w23, w23, w24", + "mov w24, v16.s[0]", + "add w23, w23, w24", + "mov w24, v17.s[0]", + "add w23, w23, w24", + "mov w24, v20.s[3]", + "mov w25, v20.s[2]", + "mov w30, v17.s[3]", + "and w18, w25, w30", + "orr w30, w25, w30", + "and w30, w24, w30", + "orr w30, w30, w18", + "add w30, w23, w30", + "ror w18, w24, #2", + "eor w18, w18, w24, ror #13", + "eor w18, w18, w24, ror #22", + "add w30, w30, w18", + "mov w18, v17.s[2]", + "add w23, w23, w18", + "and w21, w23, w21", + "bic w22, w22, w23", + "eor w21, w21, w22", + "ror w22, w23, #6", + "eor w22, w22, w23, ror #11", + "eor w22, w22, w23, ror #25", + "add w21, w21, w22", + "mov w22, v16.s[1]", + "add w21, w21, w22", + "mov w22, v17.s[1]", + "add w21, w21, w22", + "and w22, w24, w25", + "orr w24, w24, w25", + "and w24, w30, w24", + "orr w22, w24, w22", + "add w22, w21, w22", + "ror w24, w30, #2", + "eor w24, w24, w30, ror #13", + "eor w24, w24, w30, ror #22", + "add w22, w22, w24", + "mov w24, v17.s[3]", + "add w21, w21, w24", "mov v5.16b, v17.16b", - "mov v5.s[3], w21", - "mov v5.s[2], w25", - "mov v5.s[1], w20", + "mov v5.s[3], w22", + "mov v5.s[2], w30", + "mov v5.s[1], w21", "mov v17.16b, v5.16b", - "mov v17.s[0], w22", + "mov v17.s[0], w23", "mov v16.16b, v23.16b", "ext v16.16b, v24.16b, v23.16b, #4", "add v22.4s, v22.4s, v16.4s", - "mov w20, #0x1000", - "movk w20, #0x1, lsl #16", - "ldr q16, [x29, x20, sxtx]", - "mov w20, v23.s[2]", - "mov w21, v23.s[3]", - "mov w22, v22.s[0]", - "ror w23, w20, #17", - "ror w24, w20, #19", - "eor w23, w23, w24", - "lsr w20, w20, #10", - "eor w20, w23, w20", - "add w20, w22, w20", - "mov w22, v22.s[1]", - "ror w23, w21, #17", - "ror w24, w21, #19", - "eor w23, w23, w24", - "lsr w21, w21, #10", - "eor w21, w23, w21", - "add w21, w22, w21", - "mov w22, v22.s[2]", - "ror w23, w20, #17", - "ror w24, w20, #19", - "eor w23, w23, w24", - "lsr w24, w20, #10", - "eor w23, w23, w24", - "add w22, w22, w23", - "mov w23, v22.s[3]", - "ror w24, w21, #17", - "ror w25, w21, #19", - "eor w24, w24, w25", - "lsr w25, w21, #10", - "eor w24, w24, w25", - "add w23, w23, w24", - "mov v5.16b, v22.16b", - "mov v5.s[3], w23", - "mov v5.s[2], w22", - "mov v5.s[1], w21", - "mov v22.16b, v5.16b", - "mov v22.s[0], w20", - "add v16.4s, v16.4s, v21.4s", - "unimplemented (Unimplemented)", - "mov w20, v17.s[1]", - "mov w21, v17.s[0]", - "mov w22, v20.s[1]", - "and w23, w20, w21", - "bic w22, w22, w20", - "eor w22, w23, w22", - "ror w23, w20, #6", - "eor w23, w23, w20, ror #11", - "eor w23, w23, w20, ror #25", - "add w22, w22, w23", - "mov w23, v16.s[0]", - "add w22, w22, w23", - "mov w23, v20.s[0]", - "add w22, w22, w23", - "mov w23, v17.s[3]", - "mov w24, v17.s[2]", - "mov w25, v20.s[3]", - "and w30, w24, w25", - "orr w25, w24, w25", - "and w25, w23, w25", - "orr w25, w25, w30", - "add w25, w22, w25", - "ror w30, w23, #2", - "eor w30, w30, w23, ror #13", - "eor w30, w30, w23, ror #22", - "add w25, w25, w30", - "mov w30, v20.s[2]", - "add w22, w22, w30", - "and w20, w22, w20", - "bic w21, w21, w22", - "eor w20, w20, w21", - "ror w21, w22, #6", - "eor w21, w21, w22, ror #11", - "eor w21, w21, w22, ror #25", - "add w20, w20, w21", - "mov w21, v16.s[1]", - "add w20, w20, w21", - "mov w21, v20.s[1]", - "add w20, w20, w21", - "and w21, w23, w24", - "orr w23, w23, w24", - "and w23, w25, w23", - "orr w21, w23, w21", - "add w21, w20, w21", - "ror w23, w25, #2", - "eor w23, w23, w25, ror #13", - "eor w23, w23, w25, ror #22", - "add w21, w21, w23", - "mov w23, v20.s[3]", - "add w20, w20, w23", - "mov v5.16b, v20.16b", - "mov v5.s[3], w21", - "mov v5.s[2], w25", - "mov v5.s[1], w20", - "mov v20.16b, v5.16b", - "mov v20.s[0], w22", - "tbl v16.16b, {v16.16b}, v4.16b", - "mov w20, v20.s[1]", - "mov w21, v20.s[0]", - "mov w22, v17.s[1]", - "and w23, w20, w21", - "bic w22, w22, w20", - "eor w22, w23, w22", - "ror w23, w20, #6", - "eor w23, w23, w20, ror #11", - "eor w23, w23, w20, ror #25", - "add w22, w22, w23", - "mov w23, v16.s[0]", - "add w22, w22, w23", - "mov w23, v17.s[0]", - "add w22, w22, w23", - "mov w23, v20.s[3]", - "mov w24, v20.s[2]", - "mov w25, v17.s[3]", - "and w30, w24, w25", - "orr w25, w24, w25", - "and w25, w23, w25", - "orr w25, w25, w30", - "add w25, w22, w25", - "ror w30, w23, #2", - "eor w30, w30, w23, ror #13", - "eor w30, w30, w23, ror #22", - "add w25, w25, w30", - "mov w30, v17.s[2]", - "add w22, w22, w30", - "and w20, w22, w20", - "bic w21, w21, w22", - "eor w20, w20, w21", - "ror w21, w22, #6", - "eor w21, w21, w22, ror #11", - "eor w21, w21, w22, ror #25", - "add w20, w20, w21", - "mov w21, v16.s[1]", - "add w20, w20, w21", - "mov w21, v17.s[1]", - "add w20, w20, w21", - "and w21, w23, w24", - "orr w23, w23, w24", - "and w23, w25, w23", - "orr w21, w23, w21", - "add w21, w20, w21", - "ror w23, w25, #2", - "eor w23, w23, w25, ror #13", - "eor w23, w23, w25, ror #22", - "add w21, w21, w23", - "mov w23, v17.s[3]", - "add w20, w20, w23", - "mov v5.16b, v17.16b", - "mov v5.s[3], w21", - "mov v5.s[2], w25", - "mov v5.s[1], w20", - "mov v17.16b, v5.16b", - "mov v17.s[0], w22", - "mov v16.16b, v22.16b", - "ext v16.16b, v23.16b, v22.16b, #4", - "add v21.4s, v21.4s, v16.4s", - "mov w20, #0x1000", - "movk w20, #0x1, lsl #16", - "ldr q16, [x29, x20, sxtx]", - "mov w20, v22.s[2]", - "mov w21, v22.s[3]", - "mov w22, v21.s[0]", - "ror w23, w20, #17", - "ror w24, w20, #19", - "eor w23, w23, w24", - "lsr w20, w20, #10", - "eor w20, w23, w20", - "add w20, w22, w20", - "mov w22, v21.s[1]", - "ror w23, w21, #17", - "ror w24, w21, #19", - "eor w23, w23, w24", - "lsr w21, w21, #10", - "eor w21, w23, w21", - "add w21, w22, w21", - "mov w22, v21.s[2]", - "ror w23, w20, #17", - "ror w24, w20, #19", - "eor w23, w23, w24", - "lsr w24, w20, #10", - "eor w23, w23, w24", - "add w22, w22, w23", - "mov w23, v21.s[3]", - "ror w24, w21, #17", - "ror w25, w21, #19", - "eor w24, w24, w25", - "lsr w25, w21, #10", - "eor w24, w24, w25", - "add w23, w23, w24", - "mov v5.16b, v21.16b", - "mov v5.s[3], w23", - "mov v5.s[2], w22", - "mov v5.s[1], w21", - "mov v21.16b, v5.16b", - "mov v21.s[0], w20", - "add v16.4s, v16.4s, v24.4s", - "unimplemented (Unimplemented)", - "mov w20, v17.s[1]", - "mov w21, v17.s[0]", - "mov w22, v20.s[1]", - "and w23, w20, w21", - "bic w22, w22, w20", - "eor w22, w23, w22", - "ror w23, w20, #6", - "eor w23, w23, w20, ror #11", - "eor w23, w23, w20, ror #25", - "add w22, w22, w23", - "mov w23, v16.s[0]", - "add w22, w22, w23", - "mov w23, v20.s[0]", - "add w22, w22, w23", - "mov w23, v17.s[3]", - "mov w24, v17.s[2]", - "mov w25, v20.s[3]", - "and w30, w24, w25", - "orr w25, w24, w25", - "and w25, w23, w25", - "orr w25, w25, w30", - "add w25, w22, w25", - "ror w30, w23, #2", - "eor w30, w30, w23, ror #13", - "eor w30, w30, w23, ror #22", - "add w25, w25, w30", - "mov w30, v20.s[2]", - "add w22, w22, w30", - "and w20, w22, w20", - "bic w21, w21, w22", - "eor w20, w20, w21", - "ror w21, w22, #6", - "eor w21, w21, w22, ror #11", - "eor w21, w21, w22, ror #25", - "add w20, w20, w21", - "mov w21, v16.s[1]", - "add w20, w20, w21", - "mov w21, v20.s[1]", - "add w20, w20, w21", - "and w21, w23, w24", - "orr w23, w23, w24", - "and w23, w25, w23", - "orr w21, w23, w21", - "add w21, w20, w21", - "ror w23, w25, #2", - "eor w23, w23, w25, ror #13", - "eor w23, w23, w25, ror #22", - "add w21, w21, w23", - "mov w23, v20.s[3]", - "add w20, w20, w23", - "mov v5.16b, v20.16b", - "mov v5.s[3], w21", - "mov v5.s[2], w25", - "mov v5.s[1], w20", - "mov v20.16b, v5.16b", - "mov v20.s[0], w22", - "tbl v16.16b, {v16.16b}, v4.16b", - "mov w20, v20.s[1]", - "mov w21, v20.s[0]", - "mov w22, v17.s[1]", - "and w23, w20, w21", - "bic w22, w22, w20", - "eor w22, w23, w22", - "ror w23, w20, #6", - "eor w23, w23, w20, ror #11", - "eor w23, w23, w20, ror #25", - "add w22, w22, w23", - "mov w23, v16.s[0]", - "add w22, w22, w23", - "mov w23, v17.s[0]", - "add w22, w22, w23", - "mov w23, v20.s[3]", - "mov w24, v20.s[2]", - "mov w25, v17.s[3]", - "and w30, w24, w25", - "orr w25, w24, w25", - "and w25, w23, w25", - "orr w25, w25, w30", - "add w25, w22, w25", - "ror w30, w23, #2", - "eor w30, w30, w23, ror #13", - "eor w30, w30, w23, ror #22", - "add w25, w25, w30", - "mov w30, v17.s[2]", - "add w22, w22, w30", - "and w20, w22, w20", - "bic w21, w21, w22", - "eor w20, w20, w21", - "ror w21, w22, #6", - "eor w21, w21, w22, ror #11", - "eor w21, w21, w22, ror #25", - "add w20, w20, w21", - "mov w21, v16.s[1]", - "add w20, w20, w21", - "mov w21, v17.s[1]", - "add w20, w20, w21", - "and w21, w23, w24", - "orr w23, w23, w24", - "and w23, w25, w23", - "orr w21, w23, w21", - "add w21, w20, w21", - "ror w23, w25, #2", - "eor w23, w23, w25, ror #13", - "eor w23, w23, w25, ror #22", - "add w21, w21, w23", - "mov w23, v17.s[3]", - "add w20, w20, w23", - "mov v5.16b, v17.16b", - "mov v5.s[3], w21", - "mov v5.s[2], w25", - "mov v5.s[1], w20", - "mov v17.16b, v5.16b", - "mov v17.s[0], w22", - "mov v16.16b, v21.16b", - "ext v16.16b, v22.16b, v21.16b, #4", - "add v24.4s, v24.4s, v16.4s", - "mov w20, #0x1000", - "movk w20, #0x1, lsl #16", - "ldr q16, [x29, x20, sxtx]", - "mov w20, v21.s[2]", - "mov w21, v21.s[3]", - "mov w22, v24.s[0]", - "ror w23, w20, #17", - "ror w24, w20, #19", - "eor w23, w23, w24", - "lsr w20, w20, #10", - "eor w20, w23, w20", - "add w20, w22, w20", - "mov w22, v24.s[1]", - "ror w23, w21, #17", - "ror w24, w21, #19", - "eor w23, w23, w24", - "lsr w21, w21, #10", - "eor w21, w23, w21", - "add w21, w22, w21", - "mov w22, v24.s[2]", - "ror w23, w20, #17", - "ror w24, w20, #19", - "eor w23, w23, w24", - "lsr w24, w20, #10", - "eor w23, w23, w24", - "add w22, w22, w23", - "mov w23, v24.s[3]", - "ror w24, w21, #17", - "ror w25, w21, #19", - "eor w24, w24, w25", - "lsr w25, w21, #10", - "eor w24, w24, w25", - "add w23, w23, w24", - "mov v5.16b, v24.16b", - "mov v5.s[3], w23", - "mov v5.s[2], w22", - "mov v5.s[1], w21", - "mov v24.16b, v5.16b", - "mov v24.s[0], w20", - "add v16.4s, v16.4s, v23.4s", - "unimplemented (Unimplemented)", - "mov w20, v17.s[1]", - "mov w21, v17.s[0]", - "mov w22, v20.s[1]", - "and w23, w20, w21", - "bic w22, w22, w20", - "eor w22, w23, w22", - "ror w23, w20, #6", - "eor w23, w23, w20, ror #11", - "eor w23, w23, w20, ror #25", - "add w22, w22, w23", - "mov w23, v16.s[0]", - "add w22, w22, w23", - "mov w23, v20.s[0]", - "add w22, w22, w23", - "mov w23, v17.s[3]", - "mov w24, v17.s[2]", - "mov w25, v20.s[3]", - "and w30, w24, w25", - "orr w25, w24, w25", - "and w25, w23, w25", - "orr w25, w25, w30", - "add w25, w22, w25", - "ror w30, w23, #2", - "eor w30, w30, w23, ror #13", - "eor w30, w30, w23, ror #22", - "add w25, w25, w30", - "mov w30, v20.s[2]", - "add w22, w22, w30", - "and w20, w22, w20", - "bic w21, w21, w22", - "eor w20, w20, w21", - "ror w21, w22, #6", - "eor w21, w21, w22, ror #11", - "eor w21, w21, w22, ror #25", - "add w20, w20, w21", - "mov w21, v16.s[1]", - "add w20, w20, w21", - "mov w21, v20.s[1]", - "add w20, w20, w21", - "and w21, w23, w24", - "orr w23, w23, w24", - "and w23, w25, w23", - "orr w21, w23, w21", - "add w21, w20, w21", - "ror w23, w25, #2", - "eor w23, w23, w25, ror #13", - "eor w23, w23, w25, ror #22", - "add w21, w21, w23", - "mov w23, v20.s[3]", - "add w20, w20, w23", - "mov v5.16b, v20.16b", - "mov v5.s[3], w21", - "mov v5.s[2], w25", - "mov v5.s[1], w20", - "mov v20.16b, v5.16b", - "mov v20.s[0], w22", - "tbl v16.16b, {v16.16b}, v4.16b", - "mov w20, v20.s[1]", - "mov w21, v20.s[0]", - "mov w22, v17.s[1]", - "and w23, w20, w21", - "bic w22, w22, w20", - "eor w22, w23, w22", - "ror w23, w20, #6", - "eor w23, w23, w20, ror #11", - "eor w23, w23, w20, ror #25", - "add w22, w22, w23", - "mov w23, v16.s[0]", - "add w22, w22, w23", - "mov w23, v17.s[0]", - "add w22, w22, w23", - "mov w23, v20.s[3]", - "mov w24, v20.s[2]", - "mov w25, v17.s[3]", - "and w30, w24, w25", - "orr w25, w24, w25", - "and w25, w23, w25", - "orr w25, w25, w30", - "add w25, w22, w25", - "ror w30, w23, #2", - "eor w30, w30, w23, ror #13", - "eor w30, w30, w23, ror #22", - "add w25, w25, w30", - "mov w30, v17.s[2]", - "add w22, w22, w30", - "and w20, w22, w20", - "bic w21, w21, w22", - "eor w20, w20, w21", - "ror w21, w22, #6", - "eor w21, w21, w22, ror #11", - "eor w21, w21, w22, ror #25", - "add w20, w20, w21", - "mov w21, v16.s[1]", - "add w20, w20, w21", - "mov w21, v17.s[1]", - "add w20, w20, w21", - "and w21, w23, w24", - "orr w23, w23, w24", - "and w23, w25, w23", - "orr w21, w23, w21", - "add w21, w20, w21", - "ror w23, w25, #2", - "eor w23, w23, w25, ror #13", - "eor w23, w23, w25, ror #22", - "add w21, w21, w23", - "mov w23, v17.s[3]", - "add w20, w20, w23", - "mov v5.16b, v17.16b", - "mov v5.s[3], w21", - "mov v5.s[2], w25", - "mov v5.s[1], w20", - "mov v17.16b, v5.16b", - "mov v17.s[0], w22", - "mov v16.16b, v24.16b", - "ext v16.16b, v21.16b, v24.16b, #4", - "add v23.4s, v23.4s, v16.4s", - "mov w20, #0x1000", - "movk w20, #0x1, lsl #16", - "ldr q16, [x29, x20, sxtx]", - "mov w20, v24.s[2]", - "mov w21, v24.s[3]", - "mov w22, v23.s[0]", - "ror w23, w20, #17", - "ror w24, w20, #19", - "eor w23, w23, w24", - "lsr w20, w20, #10", - "eor w20, w23, w20", - "add w20, w22, w20", - "mov w22, v23.s[1]", - "ror w23, w21, #17", - "ror w24, w21, #19", - "eor w23, w23, w24", - "lsr w21, w21, #10", - "eor w21, w23, w21", - "add w21, w22, w21", - "mov w22, v23.s[2]", - "ror w23, w20, #17", - "ror w24, w20, #19", - "eor w23, w23, w24", - "lsr w24, w20, #10", - "eor w23, w23, w24", - "add w22, w22, w23", - "mov w23, v23.s[3]", - "ror w24, w21, #17", - "ror w25, w21, #19", - "eor w24, w24, w25", - "lsr w25, w21, #10", - "eor w24, w24, w25", - "add w23, w23, w24", - "mov v5.16b, v23.16b", - "mov v5.s[3], w23", - "mov v5.s[2], w22", - "mov v5.s[1], w21", - "mov v23.16b, v5.16b", - "mov v23.s[0], w20", - "add v16.4s, v16.4s, v22.4s", - "unimplemented (Unimplemented)", - "mov w20, v17.s[1]", - "mov w21, v17.s[0]", - "mov w22, v20.s[1]", - "and w23, w20, w21", - "bic w22, w22, w20", - "eor w22, w23, w22", - "ror w23, w20, #6", - "eor w23, w23, w20, ror #11", - "eor w23, w23, w20, ror #25", - "add w22, w22, w23", - "mov w23, v16.s[0]", - "add w22, w22, w23", - "mov w23, v20.s[0]", - "add w22, w22, w23", - "mov w23, v17.s[3]", - "mov w24, v17.s[2]", - "mov w25, v20.s[3]", - "and w30, w24, w25", - "orr w25, w24, w25", - "and w25, w23, w25", - "orr w25, w25, w30", - "add w25, w22, w25", - "ror w30, w23, #2", - "eor w30, w30, w23, ror #13", - "eor w30, w30, w23, ror #22", - "add w25, w25, w30", - "mov w30, v20.s[2]", - "add w22, w22, w30", - "and w20, w22, w20", - "bic w21, w21, w22", - "eor w20, w20, w21", - "ror w21, w22, #6", - "eor w21, w21, w22, ror #11", - "eor w21, w21, w22, ror #25", - "add w20, w20, w21", - "mov w21, v16.s[1]", - "add w20, w20, w21", - "mov w21, v20.s[1]", - "add w20, w20, w21", - "and w21, w23, w24", - "orr w23, w23, w24", - "and w23, w25, w23", - "orr w21, w23, w21", - "add w21, w20, w21", - "ror w23, w25, #2", - "eor w23, w23, w25, ror #13", - "eor w23, w23, w25, ror #22", - "add w21, w21, w23", - "mov w23, v20.s[3]", - "add w20, w20, w23", - "mov v5.16b, v20.16b", - "mov v5.s[3], w21", - "mov v5.s[2], w25", - "mov v5.s[1], w20", - "mov v20.16b, v5.16b", - "mov v20.s[0], w22", - "tbl v16.16b, {v16.16b}, v4.16b", - "mov w20, v20.s[1]", - "mov w21, v20.s[0]", - "mov w22, v17.s[1]", - "and w23, w20, w21", - "bic w22, w22, w20", - "eor w22, w23, w22", - "ror w23, w20, #6", - "eor w23, w23, w20, ror #11", - "eor w23, w23, w20, ror #25", - "add w22, w22, w23", - "mov w23, v16.s[0]", - "add w22, w22, w23", - "mov w23, v17.s[0]", - "add w22, w22, w23", - "mov w23, v20.s[3]", - "mov w24, v20.s[2]", - "mov w25, v17.s[3]", - "and w30, w24, w25", - "orr w25, w24, w25", - "and w25, w23, w25", - "orr w25, w25, w30", - "add w25, w22, w25", - "ror w30, w23, #2", - "eor w30, w30, w23, ror #13", - "eor w30, w30, w23, ror #22", - "add w25, w25, w30", - "mov w30, v17.s[2]", - "add w22, w22, w30", - "and w20, w22, w20", - "bic w21, w21, w22", - "eor w20, w20, w21", - "ror w21, w22, #6", - "eor w21, w21, w22, ror #11", - "eor w21, w21, w22, ror #25", - "add w20, w20, w21", - "mov w21, v16.s[1]", - "add w20, w20, w21", - "mov w21, v17.s[1]", - "add w20, w20, w21", - "and w21, w23, w24", - "orr w23, w23, w24", - "and w23, w25, w23", - "orr w21, w23, w21", - "add w21, w20, w21", - "ror w23, w25, #2", - "eor w23, w23, w25, ror #13", - "eor w23, w23, w25, ror #22", - "add w21, w21, w23", - "mov w23, v17.s[3]", - "add w20, w20, w23", - "mov v5.16b, v17.16b", - "mov v5.s[3], w21", - "mov v5.s[2], w25", - "mov v5.s[1], w20", - "mov v17.16b, v5.16b", - "mov v17.s[0], w22", - "mov v16.16b, v23.16b", - "ext v16.16b, v24.16b, v23.16b, #4", - "add v22.4s, v22.4s, v16.4s", - "mov w20, #0x1000", - "movk w20, #0x1, lsl #16", "ldr q16, [x29, x20, sxtx]", "mov w20, v23.s[2]", "mov w21, v23.s[3]", diff --git a/unittests/InstructionCountCI/FlagM/Atomics.json b/unittests/InstructionCountCI/FlagM/Atomics.json index 8271633e4..55f4557c7 100644 --- a/unittests/InstructionCountCI/FlagM/Atomics.json +++ b/unittests/InstructionCountCI/FlagM/Atomics.json @@ -322,10 +322,10 @@ "ExpectedInstructionCount": 4, "Comment": "0x0f 0xc1", "ExpectedArm64ASM": [ - "mov x20, x7", - "ldaddal x20, x7, [x4]", - "eor w27, w7, w20", - "adds x26, x7, x20" + "ldaddal x7, x20, [x4]", + "eor w27, w20, w7", + "adds x26, x20, x7", + "mov x7, x20" ] }, "lock add byte [rax], 1": { diff --git a/unittests/InstructionCountCI/FlagM/FlagOpts.json b/unittests/InstructionCountCI/FlagM/FlagOpts.json index c67bc54fe..8474bcff0 100644 --- a/unittests/InstructionCountCI/FlagM/FlagOpts.json +++ b/unittests/InstructionCountCI/FlagM/FlagOpts.json @@ -225,8 +225,8 @@ ], "ExpectedArm64ASM": [ "subs x20, x4, x7", - "cset x20, eq", - "bfxil x5, x20, #0, #8", + "cset x21, eq", + "bfxil x5, x21, #0, #8", "mov x26, x5", "cmn wzr, w26, lsl #24" ] diff --git a/unittests/InstructionCountCI/FlagM/HotBlocks.json b/unittests/InstructionCountCI/FlagM/HotBlocks.json index dac2749fe..251bdf14d 100644 --- a/unittests/InstructionCountCI/FlagM/HotBlocks.json +++ b/unittests/InstructionCountCI/FlagM/HotBlocks.json @@ -81,11 +81,11 @@ "mov w10, w5", "mov x6, x9", "mov x4, x7", - "ldr s18, [x6]", - "add x4, x4, #0x20 (32)", + "ldr s18, [x9]", + "add x4, x7, #0x20 (32)", "fmul s0, s18, s16", "mov v18.s[0], v0.s[0]", - "add x6, x6, #0x20 (32)", + "add x6, x9, #0x20 (32)", "sub x20, x4, #0x20 (32)", "ldr s2, [x20]", "fadd s0, s18, s2", @@ -191,7 +191,7 @@ ] }, "bytemark data xor loop": { - "ExpectedInstructionCount": 16, + "ExpectedInstructionCount": 17, "Comment": [ "Saw this in bytemark" ], @@ -207,21 +207,22 @@ "cmp rdi, rax" ], "ExpectedArm64ASM": [ - "mov x20, x4", - "mov x6, x20", - "mov x5, x20", + "mov x6, x4", + "mov x5, x4", "mov x19, x10", - "add x4, x20, #0x1 (1)", - "lsr x6, x20, #6", - "and w5, w20, #0x3f", - "lsl x19, x19, x5", - "add x20, x7, x6, lsl #3", - "ldr x20, [x20]", - "eor x20, x20, x19", + "add x20, x4, #0x1 (1)", + "mov x21, x4", + "mov x4, x20", + "lsr x6, x21, #6", + "and w5, w21, #0x3f", + "lsl x19, x10, x5", "add x21, x7, x6, lsl #3", - "str x20, [x21]", - "eor w27, w11, w4", - "subs x26, x11, x4", + "ldr x21, [x21]", + "eor x21, x21, x19", + "add x22, x7, x6, lsl #3", + "str x21, [x22]", + "eor w27, w11, w20", + "subs x26, x11, x20", "cfinv" ] }, @@ -237,10 +238,10 @@ "cmp r13, qword [rsi+r11*8]" ], "ExpectedArm64ASM": [ - "mov x15, x13", - "add x20, x10, x15, lsl #3", + "add x20, x10, x13, lsl #3", "ldr x17, [x20]", - "orr x15, x15, #0x1", + "mov x15, x13", + "orr x15, x13, #0x1", "add x20, x10, x15, lsl #3", "ldr x20, [x20]", "eor w27, w17, w20", diff --git a/unittests/InstructionCountCI/FlagM/HotBlocks_32Bit.json b/unittests/InstructionCountCI/FlagM/HotBlocks_32Bit.json index 2cc96ac29..eb5ccdab9 100644 --- a/unittests/InstructionCountCI/FlagM/HotBlocks_32Bit.json +++ b/unittests/InstructionCountCI/FlagM/HotBlocks_32Bit.json @@ -80,7 +80,7 @@ ] }, "dxvk hotblock from MGRR": { - "ExpectedInstructionCount": 39, + "ExpectedInstructionCount": 41, "Comment": [ "Hottest block in Metal Gear Rising: Revengeance render thread" ], @@ -110,32 +110,34 @@ "mov w20, #0xffffffdc", "ldr w10, [x9, w20, sxtw]", "mov w20, #0xffffffff", - "adds w21, w4, w20", - "mov x5, x21", + "adds w5, w4, w20", "mvn w27, w6", "adcs w26, w6, w20", "mov x7, x26", "mov w20, #0xffffffd8", - "str w21, [x9, w20, sxtw]", + "str w5, [x9, w20, sxtw]", "mov w20, #0xffffffd4", "str w26, [x9, w20, sxtw]", - "mov x7, x21", - "mov w22, #0xffffffd0", - "str w21, [x9, w22, sxtw]", - "ldr w5, [x9, w20, sxtw]", - "add w20, w10, #0x8 (8)", - "mov w22, w4", - "mov w23, w6", - "mov w24, w21", - "mov w25, w5", - "mov w2, w22", - "mov w3, w23", - "caspal w2, w3, w24, w25, [x20]", + "mov x7, x5", + "mov w21, #0xffffffd0", + "str w5, [x9, w21, sxtw]", + "ldr w20, [x9, w20, sxtw]", + "mov x21, x5", + "mov x5, x20", + "add w22, w10, #0x8 (8)", + "mov w24, w4", + "mov w25, w6", + "mov w0, w21", + "mov w21, w20", + "mov w20, w0", + "mov w2, w24", + "mov w3, w25", + "caspal w2, w3, w20, w21, [x22]", "mov w20, w2", "mov w21, w3", "mrs x0, nzcv", - "cmp w20, w22", - "ccmp w21, w23, #nzcv, eq", + "cmp w20, w24", + "ccmp w21, w25, #nzcv, eq", "rmif x0, #0, #NzCV", "mov w22, w21", "csel x4, x20, x4, ne", @@ -255,13 +257,12 @@ "pop ebp" ], "ExpectedArm64ASM": [ - "mov w20, w8", - "str w9, [x20, #-4]!", - "mov x8, x20", - "mov x9, x20", - "mov x27, x20", - "subs w26, w20, #0x44 (68)", + "str w9, [x8, #-4]!", + "mov x9, x8", + "mov x27, x8", + "subs w26, w8, #0x44 (68)", "cfinv", + "mov x20, x8", "mov x8, x26", "mov w21, #0xffffffbc", "str w5, [x20, w21, sxtw]", @@ -2671,10 +2672,11 @@ "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", - "mov w8, w9", - "ldr w4, [x8, #8]", - "ldr w9, [x8]", - "add x8, x8, #0x4 (4)" + "ldr w4, [x9, #8]", + "mov x8, x9", + "ldr w20, [x9]", + "add x8, x9, #0x4 (4)", + "mov x9, x20" ] } } diff --git a/unittests/InstructionCountCI/FlagM/HotBlocks_AFP.json b/unittests/InstructionCountCI/FlagM/HotBlocks_AFP.json index f1871c91a..0c2ed4052 100644 --- a/unittests/InstructionCountCI/FlagM/HotBlocks_AFP.json +++ b/unittests/InstructionCountCI/FlagM/HotBlocks_AFP.json @@ -58,10 +58,10 @@ "mov w10, w5", "mov x6, x9", "mov x4, x7", - "ldr s18, [x6]", - "add x4, x4, #0x20 (32)", + "ldr s18, [x9]", + "add x4, x7, #0x20 (32)", "fmul s18, s18, s16", - "add x6, x6, #0x20 (32)", + "add x6, x9, #0x20 (32)", "sub x20, x4, #0x20 (32)", "ldr s2, [x20]", "fadd s18, s18, s2", diff --git a/unittests/InstructionCountCI/FlagM/Primary.json b/unittests/InstructionCountCI/FlagM/Primary.json index 73bc78012..66eae54d5 100644 --- a/unittests/InstructionCountCI/FlagM/Primary.json +++ b/unittests/InstructionCountCI/FlagM/Primary.json @@ -104,28 +104,26 @@ ] }, "add al, 1": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 6, "Comment": "0x04", "ExpectedArm64ASM": [ "mov w20, #0x1", "mov x27, x4", - "lsl w0, w27, #24", + "lsl w0, w4, #24", "cmn w0, w20, lsl #24", - "add w26, w27, #0x1 (1)", - "mov x4, x27", + "add w26, w4, #0x1 (1)", "bfxil x4, x26, #0, #8" ] }, "add ax, 1": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 6, "Comment": "0x05", "ExpectedArm64ASM": [ "mov w20, #0x1", "mov x27, x4", - "lsl w0, w27, #16", + "lsl w0, w4, #16", "cmn w0, w20, lsl #16", - "add w26, w27, #0x1 (1)", - "mov x4, x27", + "add w26, w4, #0x1 (1)", "bfxil x4, x26, #0, #16" ] }, @@ -134,7 +132,7 @@ "Comment": "0x05", "ExpectedArm64ASM": [ "mov x27, x4", - "adds w26, w27, #0x1 (1)", + "adds w26, w4, #0x1 (1)", "mov x4, x26" ] }, @@ -143,7 +141,7 @@ "Comment": "0x05", "ExpectedArm64ASM": [ "mov x27, x4", - "adds x26, x27, #0x1 (1)", + "adds x26, x4, #0x1 (1)", "mov x4, x26" ] }, @@ -487,44 +485,42 @@ ] }, "adc al, 1": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 14, "Comment": "0x14", "ExpectedArm64ASM": [ "mov x27, x4", "mov w20, #0x1", "adc w20, wzr, w20", - "add w21, w27, w20", + "add w21, w4, w20", "uxtb w26, w21", "cmp w26, w20", "cset x20, lo", "cmn wzr, w26, lsl #24", "rmif x20, #63, #nzCv", - "eor w20, w27, #0x1", - "eor w21, w26, w27", + "eor w20, w4, #0x1", + "eor w21, w26, w4", "bic w20, w21, w20", "rmif x20, #7, #nzcV", - "mov x4, x27", "bfxil x4, x26, #0, #8" ] }, "adc ax, 1": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 14, "Comment": "0x15", "ExpectedArm64ASM": [ "mov x27, x4", "mov w20, #0x1", "adc w20, wzr, w20", - "add w21, w27, w20", + "add w21, w4, w20", "uxth w26, w21", "cmp w26, w20", "cset x20, lo", "cmn wzr, w26, lsl #16", "rmif x20, #63, #nzCv", - "eor w20, w27, #0x1", - "eor w21, w26, w27", + "eor w20, w4, #0x1", + "eor w21, w26, w4", "bic w20, w21, w20", "rmif x20, #15, #nzcV", - "mov x4, x27", "bfxil x4, x26, #0, #16" ] }, @@ -534,7 +530,7 @@ "ExpectedArm64ASM": [ "mov w20, #0x1", "mov x27, x4", - "adcs w26, w27, w20", + "adcs w26, w4, w20", "mov x4, x26" ] }, @@ -544,7 +540,7 @@ "ExpectedArm64ASM": [ "mov w20, #0x1", "mov x27, x4", - "adcs x26, x27, x20", + "adcs x26, x4, x20", "mov x4, x26" ] }, @@ -749,11 +745,11 @@ ] }, "sbb al, 1": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 13, "Comment": "0x1C", "ExpectedArm64ASM": [ "mov x27, x4", - "uxtb w20, w27", + "uxtb w20, w4", "cset w21, hs", "sub w21, w20, w21", "sub w22, w21, #0x1 (1)", @@ -764,16 +760,15 @@ "rmif x21, #63, #nzCv", "bic w20, w20, w26", "rmif x20, #7, #nzcV", - "mov x4, x27", "bfxil x4, x26, #0, #8" ] }, "sbb ax, 1": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 13, "Comment": "0x1D", "ExpectedArm64ASM": [ "mov x27, x4", - "uxth w20, w27", + "uxth w20, w4", "cset w21, hs", "sub w21, w20, w21", "sub w22, w21, #0x1 (1)", @@ -784,7 +779,6 @@ "rmif x21, #63, #nzCv", "bic w20, w20, w26", "rmif x20, #15, #nzcV", - "mov x4, x27", "bfxil x4, x26, #0, #16" ] }, @@ -795,7 +789,7 @@ "mov w20, #0x1", "mov x27, x4", "cfinv", - "sbcs w26, w27, w20", + "sbcs w26, w4, w20", "cfinv", "mov x4, x26" ] @@ -807,7 +801,7 @@ "mov w20, #0x1", "mov x27, x4", "cfinv", - "sbcs x26, x27, x20", + "sbcs x26, x4, x20", "cfinv", "mov x4, x26" ] @@ -1126,30 +1120,28 @@ ] }, "sub al, 1": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 7, "Comment": "0x2C", "ExpectedArm64ASM": [ "mov w20, #0x1", "mov x27, x4", - "lsl w0, w27, #24", + "lsl w0, w4, #24", "cmp w0, w20, lsl #24", - "sub w26, w27, #0x1 (1)", + "sub w26, w4, #0x1 (1)", "cfinv", - "mov x4, x27", "bfxil x4, x26, #0, #8" ] }, "sub ax, 1": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 7, "Comment": "0x2D", "ExpectedArm64ASM": [ "mov w20, #0x1", "mov x27, x4", - "lsl w0, w27, #16", + "lsl w0, w4, #16", "cmp w0, w20, lsl #16", - "sub w26, w27, #0x1 (1)", + "sub w26, w4, #0x1 (1)", "cfinv", - "mov x4, x27", "bfxil x4, x26, #0, #16" ] }, @@ -1158,7 +1150,7 @@ "Comment": "0x2D", "ExpectedArm64ASM": [ "mov x27, x4", - "subs w26, w27, #0x1 (1)", + "subs w26, w4, #0x1 (1)", "cfinv", "mov x4, x26" ] @@ -1168,7 +1160,7 @@ "Comment": "0x2D", "ExpectedArm64ASM": [ "mov x27, x4", - "subs x26, x27, #0x1 (1)", + "subs x26, x4, #0x1 (1)", "cfinv", "mov x4, x26" ] @@ -1476,9 +1468,9 @@ "ExpectedArm64ASM": [ "mov w20, #0x1", "mov x27, x4", - "lsl w0, w27, #24", + "lsl w0, w4, #24", "cmp w0, w20, lsl #24", - "sub w26, w27, #0x1 (1)", + "sub w26, w4, #0x1 (1)", "cfinv" ] }, @@ -1488,9 +1480,9 @@ "ExpectedArm64ASM": [ "mov w20, #0x1", "mov x27, x4", - "lsl w0, w27, #16", + "lsl w0, w4, #16", "cmp w0, w20, lsl #16", - "sub w26, w27, #0x1 (1)", + "sub w26, w4, #0x1 (1)", "cfinv" ] }, @@ -1499,7 +1491,7 @@ "Comment": "0x3D", "ExpectedArm64ASM": [ "mov x27, x4", - "subs w26, w27, #0x1 (1)", + "subs w26, w4, #0x1 (1)", "cfinv" ] }, @@ -1508,7 +1500,7 @@ "Comment": "0x3D", "ExpectedArm64ASM": [ "mov x27, x4", - "subs x26, x27, #0x1 (1)", + "subs x26, x4, #0x1 (1)", "cfinv" ] }, @@ -1900,10 +1892,10 @@ ] }, "repz cmpsb": { - "ExpectedInstructionCount": 26, + "ExpectedInstructionCount": 27, "Comment": "0xa6", "ExpectedArm64ASM": [ - "cbz x5, #+0x68", + "cbz x5, #+0x6c", "ldrsb x20, [x28, #714]", "lsr x20, x20, #63", "cbz x20, #+0x8", @@ -1923,19 +1915,20 @@ "sub x10, x10, #0x1 (1)", "ccmp x27, x26, #nzcv, ne", "b.eq #-0x18", - "mov x20, x27", - "eor w27, w20, w26", - "lsl w0, w20, #24", + "eor w20, w27, w26", + "mov x21, x27", + "mov x27, x20", + "lsl w0, w21, #24", "cmp w0, w26, lsl #24", - "sub w26, w20, w26", + "sub w26, w21, w26", "cfinv" ] }, "repz cmpsw": { - "ExpectedInstructionCount": 26, + "ExpectedInstructionCount": 27, "Comment": "0xa7", "ExpectedArm64ASM": [ - "cbz x5, #+0x68", + "cbz x5, #+0x6c", "ldrsb x20, [x28, #714]", "lsr x20, x20, #63", "cbz x20, #+0x8", @@ -1955,19 +1948,20 @@ "sub x10, x10, #0x2 (2)", "ccmp x27, x26, #nzcv, ne", "b.eq #-0x18", - "mov x20, x27", - "eor w27, w20, w26", - "lsl w0, w20, #16", + "eor w20, w27, w26", + "mov x21, x27", + "mov x27, x20", + "lsl w0, w21, #16", "cmp w0, w26, lsl #16", - "sub w26, w20, w26", + "sub w26, w21, w26", "cfinv" ] }, "repz cmpsd": { - "ExpectedInstructionCount": 24, + "ExpectedInstructionCount": 25, "Comment": "0xa7", "ExpectedArm64ASM": [ - "cbz x5, #+0x60", + "cbz x5, #+0x64", "ldrsb x20, [x28, #714]", "lsr x20, x20, #63", "cbz x20, #+0x8", @@ -1987,17 +1981,18 @@ "sub x10, x10, #0x4 (4)", "ccmp x27, x26, #nzcv, ne", "b.eq #-0x18", - "mov x20, x27", - "eor w27, w20, w26", - "subs w26, w20, w26", + "eor w20, w27, w26", + "mov x21, x27", + "mov x27, x20", + "subs w26, w21, w26", "cfinv" ] }, "repz cmpsq": { - "ExpectedInstructionCount": 24, + "ExpectedInstructionCount": 25, "Comment": "0xa7", "ExpectedArm64ASM": [ - "cbz x5, #+0x60", + "cbz x5, #+0x64", "ldrsb x20, [x28, #714]", "lsr x20, x20, #63", "cbz x20, #+0x8", @@ -2017,17 +2012,18 @@ "sub x10, x10, #0x8 (8)", "ccmp x27, x26, #nzcv, ne", "b.eq #-0x18", - "mov x20, x27", - "eor w27, w20, w26", - "subs x26, x20, x26", + "eor w20, w27, w26", + "mov x21, x27", + "mov x27, x20", + "subs x26, x21, x26", "cfinv" ] }, "repnz cmpsb": { - "ExpectedInstructionCount": 26, + "ExpectedInstructionCount": 27, "Comment": "0xa6", "ExpectedArm64ASM": [ - "cbz x5, #+0x68", + "cbz x5, #+0x6c", "ldrsb x20, [x28, #714]", "lsr x20, x20, #63", "cbz x20, #+0x8", @@ -2047,19 +2043,20 @@ "sub x10, x10, #0x1 (1)", "ccmp x27, x26, #nZcv, ne", "b.ne #-0x18", - "mov x20, x27", - "eor w27, w20, w26", - "lsl w0, w20, #24", + "eor w20, w27, w26", + "mov x21, x27", + "mov x27, x20", + "lsl w0, w21, #24", "cmp w0, w26, lsl #24", - "sub w26, w20, w26", + "sub w26, w21, w26", "cfinv" ] }, "repnz cmpsw": { - "ExpectedInstructionCount": 26, + "ExpectedInstructionCount": 27, "Comment": "0xa7", "ExpectedArm64ASM": [ - "cbz x5, #+0x68", + "cbz x5, #+0x6c", "ldrsb x20, [x28, #714]", "lsr x20, x20, #63", "cbz x20, #+0x8", @@ -2079,19 +2076,20 @@ "sub x10, x10, #0x2 (2)", "ccmp x27, x26, #nZcv, ne", "b.ne #-0x18", - "mov x20, x27", - "eor w27, w20, w26", - "lsl w0, w20, #16", + "eor w20, w27, w26", + "mov x21, x27", + "mov x27, x20", + "lsl w0, w21, #16", "cmp w0, w26, lsl #16", - "sub w26, w20, w26", + "sub w26, w21, w26", "cfinv" ] }, "repnz cmpsd": { - "ExpectedInstructionCount": 24, + "ExpectedInstructionCount": 25, "Comment": "0xa7", "ExpectedArm64ASM": [ - "cbz x5, #+0x60", + "cbz x5, #+0x64", "ldrsb x20, [x28, #714]", "lsr x20, x20, #63", "cbz x20, #+0x8", @@ -2111,17 +2109,18 @@ "sub x10, x10, #0x4 (4)", "ccmp x27, x26, #nZcv, ne", "b.ne #-0x18", - "mov x20, x27", - "eor w27, w20, w26", - "subs w26, w20, w26", + "eor w20, w27, w26", + "mov x21, x27", + "mov x27, x20", + "subs w26, w21, w26", "cfinv" ] }, "repnz cmpsq": { - "ExpectedInstructionCount": 24, + "ExpectedInstructionCount": 25, "Comment": "0xa7", "ExpectedArm64ASM": [ - "cbz x5, #+0x60", + "cbz x5, #+0x64", "ldrsb x20, [x28, #714]", "lsr x20, x20, #63", "cbz x20, #+0x8", @@ -2141,9 +2140,10 @@ "sub x10, x10, #0x8 (8)", "ccmp x27, x26, #nZcv, ne", "b.ne #-0x18", - "mov x20, x27", - "eor w27, w20, w26", - "subs x26, x20, x26", + "eor w20, w27, w26", + "mov x21, x27", + "mov x27, x20", + "subs x26, x21, x26", "cfinv" ] }, diff --git a/unittests/InstructionCountCI/FlagM/PrimaryGroup.json b/unittests/InstructionCountCI/FlagM/PrimaryGroup.json index 537ac5096..5f39d3d1a 100644 --- a/unittests/InstructionCountCI/FlagM/PrimaryGroup.json +++ b/unittests/InstructionCountCI/FlagM/PrimaryGroup.json @@ -12,15 +12,14 @@ }, "Instructions": { "add al, 1": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x80 /0", "ExpectedArm64ASM": [ "mov w20, #0x1", "mov x27, x4", - "lsl w0, w27, #24", + "lsl w0, w4, #24", "cmn w0, w20, lsl #24", - "add w26, w27, #0x1 (1)", - "mov x4, x27", + "add w26, w4, #0x1 (1)", "bfxil x4, x26, #0, #8" ] }, @@ -34,32 +33,31 @@ ] }, "adc al, 1": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 14, "Comment": "GROUP1 0x80 /2", "ExpectedArm64ASM": [ "mov x27, x4", "mov w20, #0x1", "adc w20, wzr, w20", - "add w21, w27, w20", + "add w21, w4, w20", "uxtb w26, w21", "cmp w26, w20", "cset x20, lo", "cmn wzr, w26, lsl #24", "rmif x20, #63, #nzCv", - "eor w20, w27, #0x1", - "eor w21, w26, w27", + "eor w20, w4, #0x1", + "eor w21, w26, w4", "bic w20, w21, w20", "rmif x20, #7, #nzcV", - "mov x4, x27", "bfxil x4, x26, #0, #8" ] }, "sbb al, 1": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 13, "Comment": "GROUP1 0x80 /3", "ExpectedArm64ASM": [ "mov x27, x4", - "uxtb w20, w27", + "uxtb w20, w4", "cset w21, hs", "sub w21, w20, w21", "sub w22, w21, #0x1 (1)", @@ -70,7 +68,6 @@ "rmif x21, #63, #nzCv", "bic w20, w20, w26", "rmif x20, #7, #nzcV", - "mov x4, x27", "bfxil x4, x26, #0, #8" ] }, @@ -84,16 +81,15 @@ ] }, "sub al, 1": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 7, "Comment": "GROUP1 0x80 /5", "ExpectedArm64ASM": [ "mov w20, #0x1", "mov x27, x4", - "lsl w0, w27, #24", + "lsl w0, w4, #24", "cmp w0, w20, lsl #24", - "sub w26, w27, #0x1 (1)", + "sub w26, w4, #0x1 (1)", "cfinv", - "mov x4, x27", "bfxil x4, x26, #0, #8" ] }, @@ -112,9 +108,9 @@ "ExpectedArm64ASM": [ "mov w20, #0x1", "mov x27, x4", - "lsl w0, w27, #24", + "lsl w0, w4, #24", "cmp w0, w20, lsl #24", - "sub w26, w27, #0x1 (1)", + "sub w26, w4, #0x1 (1)", "cfinv" ] }, @@ -222,15 +218,14 @@ ] }, "add ax, 256": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x81 /0", "ExpectedArm64ASM": [ "mov w20, #0x100", "mov x27, x4", - "lsl w0, w27, #16", + "lsl w0, w4, #16", "cmn w0, w20, lsl #16", - "add w26, w27, #0x100 (256)", - "mov x4, x27", + "add w26, w4, #0x100 (256)", "bfxil x4, x26, #0, #16" ] }, @@ -239,7 +234,7 @@ "Comment": "GROUP1 0x81 /0", "ExpectedArm64ASM": [ "mov x27, x4", - "adds w26, w27, #0x100 (256)", + "adds w26, w4, #0x100 (256)", "mov x4, x26" ] }, @@ -248,7 +243,7 @@ "Comment": "GROUP1 0x81 /0", "ExpectedArm64ASM": [ "mov x27, x4", - "adds x26, x27, #0x100 (256)", + "adds x26, x4, #0x100 (256)", "mov x4, x26" ] }, @@ -276,7 +271,7 @@ "ExpectedArm64ASM": [ "mov w20, #0x100", "mov x27, x4", - "adcs w26, w27, w20", + "adcs w26, w4, w20", "mov x4, x26" ] }, @@ -286,7 +281,7 @@ "ExpectedArm64ASM": [ "mov w20, #0x100", "mov x27, x4", - "adcs x26, x27, x20", + "adcs x26, x4, x20", "mov x4, x26" ] }, @@ -297,7 +292,7 @@ "mov w20, #0x100", "mov x27, x4", "cfinv", - "sbcs w26, w27, w20", + "sbcs w26, w4, w20", "cfinv", "mov x4, x26" ] @@ -309,7 +304,7 @@ "mov w20, #0x100", "mov x27, x4", "cfinv", - "sbcs x26, x27, x20", + "sbcs x26, x4, x20", "cfinv", "mov x4, x26" ] @@ -335,7 +330,7 @@ "Comment": "GROUP1 0x81 /5", "ExpectedArm64ASM": [ "mov x27, x4", - "subs w26, w27, #0x100 (256)", + "subs w26, w4, #0x100 (256)", "cfinv", "mov x4, x26" ] @@ -345,7 +340,7 @@ "Comment": "GROUP1 0x81 /5", "ExpectedArm64ASM": [ "mov x27, x4", - "subs x26, x27, #0x100 (256)", + "subs x26, x4, #0x100 (256)", "cfinv", "mov x4, x26" ] @@ -373,7 +368,7 @@ "Comment": "GROUP1 0x81 /7", "ExpectedArm64ASM": [ "mov x27, x4", - "subs w26, w27, #0x100 (256)", + "subs w26, w4, #0x100 (256)", "cfinv" ] }, @@ -382,20 +377,19 @@ "Comment": "GROUP1 0x81 /7", "ExpectedArm64ASM": [ "mov x27, x4", - "subs x26, x27, #0x100 (256)", + "subs x26, x4, #0x100 (256)", "cfinv" ] }, "add ax, -256": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x81 /0", "ExpectedArm64ASM": [ "mov w20, #0xff00", "mov x27, x4", - "lsl w0, w27, #16", + "lsl w0, w4, #16", "cmn w0, w20, lsl #16", - "add w26, w27, w20", - "mov x4, x27", + "add w26, w4, w20", "bfxil x4, x26, #0, #16" ] }, @@ -405,7 +399,7 @@ "ExpectedArm64ASM": [ "mov w20, #0xffffff00", "mov x27, x4", - "adds w26, w27, w20", + "adds w26, w4, w20", "mov x4, x26" ] }, @@ -414,7 +408,7 @@ "Comment": "GROUP1 0x81 /0", "ExpectedArm64ASM": [ "mov x27, x4", - "subs x26, x27, #0x100 (256)", + "subs x26, x4, #0x100 (256)", "mov x4, x26" ] }, @@ -442,7 +436,7 @@ "ExpectedArm64ASM": [ "mov w20, #0xffffff00", "mov x27, x4", - "adcs w26, w27, w20", + "adcs w26, w4, w20", "mov x4, x26" ] }, @@ -452,7 +446,7 @@ "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffff00", "mov x27, x4", - "adcs x26, x27, x20", + "adcs x26, x4, x20", "mov x4, x26" ] }, @@ -463,7 +457,7 @@ "mov w20, #0xffffff00", "mov x27, x4", "cfinv", - "sbcs w26, w27, w20", + "sbcs w26, w4, w20", "cfinv", "mov x4, x26" ] @@ -475,7 +469,7 @@ "mov x20, #0xffffffffffffff00", "mov x27, x4", "cfinv", - "sbcs x26, x27, x20", + "sbcs x26, x4, x20", "cfinv", "mov x4, x26" ] @@ -502,7 +496,7 @@ "ExpectedArm64ASM": [ "mov w20, #0xffffff00", "mov x27, x4", - "subs w26, w27, w20", + "subs w26, w4, w20", "cfinv", "mov x4, x26" ] @@ -512,7 +506,7 @@ "Comment": "GROUP1 0x81 /5", "ExpectedArm64ASM": [ "mov x27, x4", - "adds x26, x27, #0x100 (256)", + "adds x26, x4, #0x100 (256)", "cfinv", "mov x4, x26" ] @@ -541,7 +535,7 @@ "ExpectedArm64ASM": [ "mov w20, #0xffffff00", "mov x27, x4", - "subs w26, w27, w20", + "subs w26, w4, w20", "cfinv" ] }, @@ -550,20 +544,19 @@ "Comment": "GROUP1 0x81 /7", "ExpectedArm64ASM": [ "mov x27, x4", - "adds x26, x27, #0x100 (256)", + "adds x26, x4, #0x100 (256)", "cfinv" ] }, "add ax, 1": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x83 /0", "ExpectedArm64ASM": [ "mov w20, #0x1", "mov x27, x4", - "lsl w0, w27, #16", + "lsl w0, w4, #16", "cmn w0, w20, lsl #16", - "add w26, w27, #0x1 (1)", - "mov x4, x27", + "add w26, w4, #0x1 (1)", "bfxil x4, x26, #0, #16" ] }, @@ -572,7 +565,7 @@ "Comment": "GROUP1 0x83 /0", "ExpectedArm64ASM": [ "mov x27, x4", - "adds w26, w27, #0x1 (1)", + "adds w26, w4, #0x1 (1)", "mov x4, x26" ] }, @@ -581,7 +574,7 @@ "Comment": "GROUP1 0x83 /0", "ExpectedArm64ASM": [ "mov x27, x4", - "adds x26, x27, #0x1 (1)", + "adds x26, x4, #0x1 (1)", "mov x4, x26" ] }, @@ -609,7 +602,7 @@ "ExpectedArm64ASM": [ "mov w20, #0x1", "mov x27, x4", - "adcs w26, w27, w20", + "adcs w26, w4, w20", "mov x4, x26" ] }, @@ -619,7 +612,7 @@ "ExpectedArm64ASM": [ "mov w20, #0x1", "mov x27, x4", - "adcs x26, x27, x20", + "adcs x26, x4, x20", "mov x4, x26" ] }, @@ -630,7 +623,7 @@ "mov w20, #0x1", "mov x27, x4", "cfinv", - "sbcs w26, w27, w20", + "sbcs w26, w4, w20", "cfinv", "mov x4, x26" ] @@ -642,7 +635,7 @@ "mov w20, #0x1", "mov x27, x4", "cfinv", - "sbcs x26, x27, x20", + "sbcs x26, x4, x20", "cfinv", "mov x4, x26" ] @@ -668,7 +661,7 @@ "Comment": "GROUP1 0x83 /5", "ExpectedArm64ASM": [ "mov x27, x4", - "subs w26, w27, #0x1 (1)", + "subs w26, w4, #0x1 (1)", "cfinv", "mov x4, x26" ] @@ -678,7 +671,7 @@ "Comment": "GROUP1 0x83 /5", "ExpectedArm64ASM": [ "mov x27, x4", - "subs x26, x27, #0x1 (1)", + "subs x26, x4, #0x1 (1)", "cfinv", "mov x4, x26" ] @@ -706,7 +699,7 @@ "Comment": "GROUP1 0x83 /7", "ExpectedArm64ASM": [ "mov x27, x4", - "subs w26, w27, #0x1 (1)", + "subs w26, w4, #0x1 (1)", "cfinv" ] }, @@ -715,7 +708,7 @@ "Comment": "GROUP1 0x83 /7", "ExpectedArm64ASM": [ "mov x27, x4", - "subs x26, x27, #0x1 (1)", + "subs x26, x4, #0x1 (1)", "cfinv" ] }, @@ -1402,12 +1395,12 @@ "ExpectedInstructionCount": 6, "Comment": "GROUP2 0xd1 /2", "ExpectedArm64ASM": [ - "mov x20, x4", - "cset w21, hs", - "orr x4, x21, x20, lsl #1", - "rmif x20, #62, #nzCv", - "eor x20, x4, x20", - "rmif x20, #63, #nzcV" + "cset w20, hs", + "orr x20, x20, x4, lsl #1", + "rmif x4, #62, #nzCv", + "eor x21, x20, x4", + "rmif x21, #63, #nzcV", + "mov x4, x20" ] }, "rcr ax, 1": { @@ -1919,30 +1912,30 @@ "ExpectedInstructionCount": 9, "Comment": "GROUP2 0xd3 /4", "ExpectedArm64ASM": [ - "mov x20, x4", - "lsl w4, w20, w5", + "lsl w20, w4, w5", "cbz w5, #+0x1c", - "ands w26, w4, w4", + "ands w26, w20, w20", "neg w0, w5", - "lsr w0, w20, w0", - "eor w2, w20, w4", + "lsr w0, w4, w0", + "eor w2, w4, w20", "rmif x0, #63, #nzCv", - "rmif x2, #31, #nzcV" + "rmif x2, #31, #nzcV", + "mov x4, x20" ] }, "shl rax, cl": { "ExpectedInstructionCount": 9, "Comment": "GROUP2 0xd3 /4", "ExpectedArm64ASM": [ - "mov x20, x4", - "lsl x4, x20, x5", + "lsl x20, x4, x5", "cbz x5, #+0x1c", - "ands x26, x4, x4", + "ands x26, x20, x20", "neg x0, x5", - "lsr x0, x20, x0", - "eor x2, x20, x4", + "lsr x0, x4, x0", + "eor x2, x4, x20", "rmif x0, #63, #nzCv", - "rmif x2, #63, #nzcV" + "rmif x2, #63, #nzcV", + "mov x4, x20" ] }, "shr ax, cl": { @@ -1966,30 +1959,30 @@ "ExpectedInstructionCount": 9, "Comment": "GROUP2 0xd3 /5", "ExpectedArm64ASM": [ - "mov x20, x4", - "lsr w4, w20, w5", + "lsr w20, w4, w5", "cbz w5, #+0x1c", - "ands w26, w4, w4", + "ands w26, w20, w20", "sub x0, x5, #0x1 (1)", - "lsr w0, w20, w0", - "eor w2, w20, w4", + "lsr w0, w4, w0", + "eor w2, w4, w20", "rmif x0, #63, #nzCv", - "rmif x2, #31, #nzcV" + "rmif x2, #31, #nzcV", + "mov x4, x20" ] }, "shr rax, cl": { "ExpectedInstructionCount": 9, "Comment": "GROUP2 0xd3 /5", "ExpectedArm64ASM": [ - "mov x20, x4", - "lsr x4, x20, x5", + "lsr x20, x4, x5", "cbz x5, #+0x1c", - "ands x26, x4, x4", + "ands x26, x20, x20", "sub x0, x5, #0x1 (1)", - "lsr x0, x20, x0", - "eor x2, x20, x4", + "lsr x0, x4, x0", + "eor x2, x4, x20", "rmif x0, #63, #nzCv", - "rmif x2, #63, #nzcV" + "rmif x2, #63, #nzcV", + "mov x4, x20" ] }, "sar ax, cl": { @@ -2011,26 +2004,26 @@ "ExpectedInstructionCount": 7, "Comment": "GROUP2 0xd3 /7", "ExpectedArm64ASM": [ - "mov x20, x4", - "asr w4, w20, w5", + "asr w20, w4, w5", "cbz w5, #+0x14", - "ands w26, w4, w4", + "ands w26, w20, w20", "sub x0, x5, #0x1 (1)", - "lsr w0, w20, w0", - "rmif x0, #63, #nzCv" + "lsr w0, w4, w0", + "rmif x0, #63, #nzCv", + "mov x4, x20" ] }, "sar rax, cl": { "ExpectedInstructionCount": 7, "Comment": "GROUP2 0xd3 /7", "ExpectedArm64ASM": [ - "mov x20, x4", - "asr x4, x20, x5", + "asr x20, x4, x5", "cbz x5, #+0x14", - "ands x26, x4, x4", + "ands x26, x20, x20", "sub x0, x5, #0x1 (1)", - "lsr x0, x20, x0", - "rmif x0, #63, #nzCv" + "lsr x0, x4, x0", + "rmif x0, #63, #nzCv", + "mov x4, x20" ] }, "test bl, 1": { @@ -2049,14 +2042,13 @@ ] }, "neg bl": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 5, "Comment": "GROUP2 0xf6 /3", "ExpectedArm64ASM": [ "mov x27, x7", - "cmp wzr, w27, lsl #24", - "neg w26, w27", + "cmp wzr, w7, lsl #24", + "neg w26, w7", "cfinv", - "mov x7, x27", "bfxil x7, x26, #0, #8" ] }, @@ -2168,14 +2160,13 @@ ] }, "neg bx": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 5, "Comment": "GROUP2 0xf7 /2", "ExpectedArm64ASM": [ "mov x27, x7", - "cmp wzr, w27, lsl #16", - "neg w26, w27", + "cmp wzr, w7, lsl #16", + "neg w26, w7", "cfinv", - "mov x7, x27", "bfxil x7, x26, #0, #16" ] }, @@ -2184,7 +2175,7 @@ "Comment": "GROUP2 0xf7 /2", "ExpectedArm64ASM": [ "mov x27, x7", - "negs w26, w27", + "negs w26, w7", "cfinv", "mov x7, x26" ] @@ -2194,7 +2185,7 @@ "Comment": "GROUP2 0xf7 /2", "ExpectedArm64ASM": [ "mov x27, x7", - "negs x26, x27", + "negs x26, x7", "cfinv", "mov x7, x26" ] @@ -2230,9 +2221,9 @@ "ExpectedInstructionCount": 5, "Comment": "GROUP2 0xf7 /3", "ExpectedArm64ASM": [ - "mov x20, x4", - "mul x4, x7, x20", - "umulh x6, x7, x20", + "mul x20, x7, x4", + "umulh x6, x7, x4", + "mov x4, x20", "cmp x6, #0x0 (0)", "ccmn xzr, #0, #nzCV, eq" ] @@ -2337,9 +2328,9 @@ "ExpectedInstructionCount": 5, "Comment": "GROUP4 0xfe /0", "ExpectedArm64ASM": [ - "mov x27, x4", "cset w20, hs", - "adds w26, w27, #0x1 (1)", + "mov x27, x4", + "adds w26, w4, #0x1 (1)", "rmif x20, #63, #nzCv", "mov x4, x26" ] @@ -2348,9 +2339,9 @@ "ExpectedInstructionCount": 5, "Comment": "GROUP4 0xfe /0", "ExpectedArm64ASM": [ - "mov x27, x4", "cset w20, hs", - "adds x26, x27, #0x1 (1)", + "mov x27, x4", + "adds x26, x4, #0x1 (1)", "rmif x20, #63, #nzCv", "mov x4, x26" ] @@ -2371,9 +2362,9 @@ "ExpectedInstructionCount": 5, "Comment": "GROUP4 0xfe /1", "ExpectedArm64ASM": [ - "mov x27, x4", "cset w20, hs", - "subs w26, w27, #0x1 (1)", + "mov x27, x4", + "subs w26, w4, #0x1 (1)", "rmif x20, #63, #nzCv", "mov x4, x26" ] @@ -2382,9 +2373,9 @@ "ExpectedInstructionCount": 5, "Comment": "GROUP4 0xfe /1", "ExpectedArm64ASM": [ - "mov x27, x4", "cset w20, hs", - "subs x26, x27, #0x1 (1)", + "mov x27, x4", + "subs x26, x4, #0x1 (1)", "rmif x20, #63, #nzCv", "mov x4, x26" ] diff --git a/unittests/InstructionCountCI/FlagM/Primary_32Bit.json b/unittests/InstructionCountCI/FlagM/Primary_32Bit.json index bc89f7790..8a7fa140c 100644 --- a/unittests/InstructionCountCI/FlagM/Primary_32Bit.json +++ b/unittests/InstructionCountCI/FlagM/Primary_32Bit.json @@ -195,9 +195,9 @@ "ExpectedInstructionCount": 5, "Comment": "0x40", "ExpectedArm64ASM": [ - "mov w27, w4", "cset w20, hs", - "adds w26, w27, #0x1 (1)", + "mov x27, x4", + "adds w26, w4, #0x1 (1)", "rmif x20, #63, #nzCv", "mov x4, x26" ] @@ -232,9 +232,9 @@ "ExpectedInstructionCount": 5, "Comment": "0x48", "ExpectedArm64ASM": [ - "mov w27, w4", "cset w20, hs", - "subs w26, w27, #0x1 (1)", + "mov x27, x4", + "subs w26, w4, #0x1 (1)", "rmif x20, #63, #nzCv", "mov x4, x26" ] diff --git a/unittests/InstructionCountCI/FlagM/Secondary.json b/unittests/InstructionCountCI/FlagM/Secondary.json index e12e33122..2fd8181e5 100644 --- a/unittests/InstructionCountCI/FlagM/Secondary.json +++ b/unittests/InstructionCountCI/FlagM/Secondary.json @@ -830,23 +830,23 @@ "ExpectedInstructionCount": 17, "Comment": "0x0f 0xad", "ExpectedArm64ASM": [ - "mov x20, x4", - "and x21, x5, #0x3f", - "neg x22, x21", - "lsl x23, x20, x21", - "lsr x22, x7, x22", - "orr x22, x23, x22", - "mrs x23, nzcv", - "cmp x21, #0x0 (0)", - "csel x4, x20, x22, eq", - "msr nzcv, x23", - "cbz x21, #+0x1c", - "ands x26, x4, x4", - "neg x0, x21", - "lsr x0, x20, x0", - "eor x2, x20, x4", + "and x20, x5, #0x3f", + "neg x21, x20", + "lsl x22, x4, x20", + "lsr x21, x7, x21", + "orr x21, x22, x21", + "mrs x22, nzcv", + "cmp x20, #0x0 (0)", + "csel x21, x4, x21, eq", + "msr nzcv, x22", + "cbz x20, #+0x1c", + "ands x26, x21, x21", + "neg x0, x20", + "lsr x0, x4, x0", + "eor x2, x4, x21", "rmif x0, #63, #nzCv", - "rmif x2, #63, #nzcV" + "rmif x2, #63, #nzcV", + "mov x4, x21" ] }, "bts ax, bx": { @@ -1067,27 +1067,26 @@ ] }, "cmpxchg rcx, rbx": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 5, "ExpectedArm64ASM": [ - "mov x20, x5", - "eor w27, w4, w20", - "subs x26, x4, x20", + "eor w27, w4, w5", + "subs x26, x4, x5", "cfinv", - "mov x4, x20", - "csel x5, x7, x20, eq" + "mov x4, x5", + "csel x5, x7, x5, eq" ] }, "cmpxchg [rax], rbx": { "ExpectedInstructionCount": 7, "Comment": "0x0f 0xb1", "ExpectedArm64ASM": [ - "mov x20, x4", - "mov x1, x20", - "casal x1, x7, [x20]", - "mov x4, x1", - "eor w27, w20, w4", - "subs x26, x20, x4", - "cfinv" + "mov x1, x4", + "casal x1, x7, [x4]", + "mov x20, x1", + "eor w27, w4, w20", + "subs x26, x4, x20", + "cfinv", + "mov x4, x20" ] }, "cmpxchg al, bl": { @@ -1184,14 +1183,13 @@ ] }, "cmpxchg rax, rbx": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "0x0f 0xb1", "ExpectedArm64ASM": [ - "mov x20, x7", "mov w27, #0x0", "subs x26, x4, x4", "cfinv", - "mov x4, x20" + "mov x4, x7" ] }, "btr ax, bx": { @@ -1596,13 +1594,12 @@ ] }, "xadd rax, rbx": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "0x0f 0xc1", "ExpectedArm64ASM": [ - "mov x20, x4", - "eor w27, w20, w7", - "adds x26, x20, x7", - "mov x7, x20", + "eor w27, w4, w7", + "adds x26, x4, x7", + "mov x7, x4", "mov x4, x26" ] }, @@ -1610,10 +1607,10 @@ "ExpectedInstructionCount": 4, "Comment": "0x0f 0xc1", "ExpectedArm64ASM": [ - "mov x20, x7", - "ldaddal x20, x7, [x4]", - "eor w27, w7, w20", - "adds x26, x7, x20" + "ldaddal x7, x20, [x4]", + "eor w27, w20, w7", + "adds x26, x20, x7", + "mov x7, x20" ] }, "pmovmskb eax, mm0": { diff --git a/unittests/InstructionCountCI/FlagM/x87.json b/unittests/InstructionCountCI/FlagM/x87.json index d7d8cfd3f..4a89587b7 100644 --- a/unittests/InstructionCountCI/FlagM/x87.json +++ b/unittests/InstructionCountCI/FlagM/x87.json @@ -6782,7 +6782,7 @@ ] }, "fild dword [rax]": { - "ExpectedInstructionCount": 35, + "ExpectedInstructionCount": 34, "Comment": [ "0xdf !11b /5" ], @@ -6799,29 +6799,28 @@ "ldr w21, [x4]", "mov w22, #0x0", "sxtw x21, w21", - "mrs x22, nzcv", + "mrs x23, nzcv", "cmp x21, #0x0 (0)", - "mov w23, #0x8000", - "csel x23, x23, xzr, lt", + "mov w24, #0x8000", + "csel x24, x24, xzr, lt", "cneg x21, x21, mi", - "mov w24, #0x3f", + "mov w25, #0x3f", "mov x0, #0x3f", - "clz x25, x21", - "sub x25, x0, x25", - "sub x24, x24, x25", - "lsl x25, x21, x24", - "mov w30, #0x403e", - "sub x24, x30, x24", - "mov w30, #0x0", + "clz x30, x21", + "sub x30, x0, x30", + "sub x25, x25, x30", + "lsl x30, x21, x25", + "mov w18, #0x403e", + "sub x25, x18, x25", "cmp x21, #0x0 (0)", - "csel x21, x30, x24, eq", - "orr x21, x23, x21", - "fmov d2, x25", + "csel x21, x22, x25, eq", + "orr x21, x24, x21", + "fmov d2, x30", "fmov d3, x21", "mov v2.d[1], v3.d[0]", "add x0, x28, x20, lsl #4", "str q2, [x0, #768]", - "msr nzcv, x22" + "msr nzcv, x23" ] }, "fisttp dword [rax]": { @@ -16474,7 +16473,7 @@ ] }, "fild word [rax]": { - "ExpectedInstructionCount": 35, + "ExpectedInstructionCount": 34, "Comment": [ "0xdf !11b /0" ], @@ -16491,29 +16490,28 @@ "ldrh w21, [x4]", "mov w22, #0x0", "sxth x21, w21", - "mrs x22, nzcv", + "mrs x23, nzcv", "cmp x21, #0x0 (0)", - "mov w23, #0x8000", - "csel x23, x23, xzr, lt", + "mov w24, #0x8000", + "csel x24, x24, xzr, lt", "cneg x21, x21, mi", - "mov w24, #0x3f", + "mov w25, #0x3f", "mov x0, #0x3f", - "clz x25, x21", - "sub x25, x0, x25", - "sub x24, x24, x25", - "lsl x25, x21, x24", - "mov w30, #0x403e", - "sub x24, x30, x24", - "mov w30, #0x0", + "clz x30, x21", + "sub x30, x0, x30", + "sub x25, x25, x30", + "lsl x30, x21, x25", + "mov w18, #0x403e", + "sub x25, x18, x25", "cmp x21, #0x0 (0)", - "csel x21, x30, x24, eq", - "orr x21, x23, x21", - "fmov d2, x25", + "csel x21, x22, x25, eq", + "orr x21, x24, x21", + "fmov d2, x30", "fmov d3, x21", "mov v2.d[1], v3.d[0]", "add x0, x28, x20, lsl #4", "str q2, [x0, #768]", - "msr nzcv, x22" + "msr nzcv, x23" ] }, "fisttp word [rax]": { diff --git a/unittests/InstructionCountCI/H0F3A.json b/unittests/InstructionCountCI/H0F3A.json index 64e7d0c47..d115cc000 100644 --- a/unittests/InstructionCountCI/H0F3A.json +++ b/unittests/InstructionCountCI/H0F3A.json @@ -1338,259 +1338,235 @@ ] }, "sha1rnds4 xmm0, xmm1, 00b": { - "ExpectedInstructionCount": 57, + "ExpectedInstructionCount": 51, "Comment": [ "0x66 0x0f 0x3a 0xcc" ], "ExpectedArm64ASM": [ "mov w20, #0x7999", "movk w20, #0x5a82, lsl #16", - "mov w20, v17.s[3]", - "mov w21, v16.s[3]", - "mov w22, v16.s[2]", - "mov w23, v16.s[1]", - "mov w24, v16.s[0]", - "and w25, w22, w23", - "bic w30, w24, w22", - "eor w25, w25, w30", - "ror w30, w21, #27", - "add w25, w25, w30", - "add w20, w25, w20", - "mov w25, #0x7999", - "movk w25, #0x5a82, lsl #16", - "add w20, w20, w25", + "mov w21, v17.s[3]", + "mov w22, v16.s[3]", + "mov w23, v16.s[2]", + "mov w24, v16.s[1]", + "mov w25, v16.s[0]", + "and w30, w23, w24", + "bic w18, w25, w23", + "eor w30, w30, w18", + "ror w18, w22, #27", + "add w30, w30, w18", + "add w21, w30, w21", + "add w21, w21, w20", + "ror w23, w23, #2", + "mov w30, v17.s[2]", + "add w25, w30, w25", + "and w30, w22, w23", + "bic w18, w24, w22", + "eor w30, w30, w18", + "ror w18, w21, #27", + "add w30, w30, w18", + "add w25, w30, w25", + "add w25, w25, w20", "ror w22, w22, #2", - "mov w25, v17.s[2]", - "add w24, w25, w24", - "and w25, w21, w22", - "bic w30, w23, w21", - "eor w25, w25, w30", - "ror w30, w20, #27", - "add w25, w25, w30", - "add w24, w25, w24", - "mov w25, #0x7999", - "movk w25, #0x5a82, lsl #16", - "add w24, w24, w25", + "mov w30, v17.s[1]", + "add w24, w30, w24", + "and w30, w21, w22", + "bic w18, w23, w21", + "eor w30, w30, w18", + "ror w18, w25, #27", + "add w30, w30, w18", + "add w24, w30, w24", + "add w24, w24, w20", "ror w21, w21, #2", - "mov w25, v17.s[1]", - "add w23, w25, w23", - "and w25, w20, w21", - "bic w30, w22, w20", - "eor w25, w25, w30", - "ror w30, w24, #27", - "add w25, w25, w30", - "add w23, w25, w23", - "mov w25, #0x7999", - "movk w25, #0x5a82, lsl #16", - "add w23, w23, w25", - "ror w20, w20, #2", "mov w30, v17.s[0]", - "add w22, w30, w22", - "and w30, w24, w20", - "bic w21, w21, w24", - "eor w21, w30, w21", - "ror w30, w23, #27", - "add w21, w21, w30", - "add w21, w21, w22", - "add w21, w21, w25", - "ror w22, w24, #2", + "add w23, w30, w23", + "and w30, w25, w21", + "bic w22, w22, w25", + "eor w22, w30, w22", + "ror w30, w24, #27", + "add w22, w22, w30", + "add w22, w22, w23", + "add w20, w22, w20", + "ror w22, w25, #2", "mov v2.16b, v16.16b", - "mov v2.s[3], w21", - "mov v2.s[2], w23", + "mov v2.s[3], w20", + "mov v2.s[2], w24", "mov v2.s[1], w22", "mov v16.16b, v2.16b", - "mov v16.s[0], w20" + "mov v16.s[0], w21" ] }, "sha1rnds4 xmm0, xmm1, 01b": { - "ExpectedInstructionCount": 53, + "ExpectedInstructionCount": 47, "Comment": [ "0x66 0x0f 0x3a 0xcc" ], "ExpectedArm64ASM": [ "mov w20, #0xeba1", "movk w20, #0x6ed9, lsl #16", - "mov w20, v17.s[3]", - "mov w21, v16.s[3]", - "mov w22, v16.s[2]", - "mov w23, v16.s[1]", - "mov w24, v16.s[0]", - "eor w25, w22, w23", - "eor w25, w25, w24", - "ror w30, w21, #27", - "add w25, w25, w30", - "add w20, w25, w20", - "mov w25, #0xeba1", - "movk w25, #0x6ed9, lsl #16", - "add w20, w20, w25", + "mov w21, v17.s[3]", + "mov w22, v16.s[3]", + "mov w23, v16.s[2]", + "mov w24, v16.s[1]", + "mov w25, v16.s[0]", + "eor w30, w23, w24", + "eor w30, w30, w25", + "ror w18, w22, #27", + "add w30, w30, w18", + "add w21, w30, w21", + "add w21, w21, w20", + "ror w23, w23, #2", + "mov w30, v17.s[2]", + "add w25, w30, w25", + "eor w30, w22, w23", + "eor w30, w30, w24", + "ror w18, w21, #27", + "add w30, w30, w18", + "add w25, w30, w25", + "add w25, w25, w20", "ror w22, w22, #2", - "mov w25, v17.s[2]", - "add w24, w25, w24", - "eor w25, w21, w22", - "eor w25, w25, w23", - "ror w30, w20, #27", - "add w25, w25, w30", - "add w24, w25, w24", - "mov w25, #0xeba1", - "movk w25, #0x6ed9, lsl #16", - "add w24, w24, w25", + "mov w30, v17.s[1]", + "add w24, w30, w24", + "eor w30, w21, w22", + "eor w30, w30, w23", + "ror w18, w25, #27", + "add w30, w30, w18", + "add w24, w30, w24", + "add w24, w24, w20", "ror w21, w21, #2", - "mov w25, v17.s[1]", - "add w23, w25, w23", - "eor w25, w20, w21", - "eor w25, w25, w22", - "ror w30, w24, #27", - "add w25, w25, w30", - "add w23, w25, w23", - "mov w25, #0xeba1", - "movk w25, #0x6ed9, lsl #16", - "add w23, w23, w25", - "ror w20, w20, #2", "mov w30, v17.s[0]", - "add w22, w30, w22", - "eor w30, w24, w20", - "eor w21, w30, w21", - "ror w30, w23, #27", - "add w21, w21, w30", - "add w21, w21, w22", - "add w21, w21, w25", - "ror w22, w24, #2", + "add w23, w30, w23", + "eor w30, w25, w21", + "eor w22, w30, w22", + "ror w30, w24, #27", + "add w22, w22, w30", + "add w22, w22, w23", + "add w20, w22, w20", + "ror w22, w25, #2", "mov v2.16b, v16.16b", - "mov v2.s[3], w21", - "mov v2.s[2], w23", + "mov v2.s[3], w20", + "mov v2.s[2], w24", "mov v2.s[1], w22", "mov v16.16b, v2.16b", - "mov v16.s[0], w20" + "mov v16.s[0], w21" ] }, "sha1rnds4 xmm0, xmm1, 10b": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 55, "Comment": [ "0x66 0x0f 0x3a 0xcc" ], "ExpectedArm64ASM": [ "mov w20, #0xbcdc", "movk w20, #0x8f1b, lsl #16", - "mov w20, v17.s[3]", - "mov w21, v16.s[3]", - "mov w22, v16.s[2]", - "mov w23, v16.s[1]", - "mov w24, v16.s[0]", - "and w25, w23, w24", - "orr w30, w23, w24", - "and w30, w22, w30", - "orr w25, w30, w25", - "ror w30, w21, #27", - "add w25, w25, w30", - "add w20, w25, w20", - "mov w25, #0xbcdc", - "movk w25, #0x8f1b, lsl #16", - "add w20, w20, w25", + "mov w21, v17.s[3]", + "mov w22, v16.s[3]", + "mov w23, v16.s[2]", + "mov w24, v16.s[1]", + "mov w25, v16.s[0]", + "and w30, w24, w25", + "orr w18, w24, w25", + "and w18, w23, w18", + "orr w30, w18, w30", + "ror w18, w22, #27", + "add w30, w30, w18", + "add w21, w30, w21", + "add w21, w21, w20", + "ror w23, w23, #2", + "mov w30, v17.s[2]", + "add w25, w30, w25", + "and w30, w23, w24", + "orr w18, w23, w24", + "and w18, w22, w18", + "orr w30, w18, w30", + "ror w18, w21, #27", + "add w30, w30, w18", + "add w25, w30, w25", + "add w25, w25, w20", "ror w22, w22, #2", - "mov w25, v17.s[2]", - "add w24, w25, w24", - "and w25, w22, w23", - "orr w30, w22, w23", - "and w30, w21, w30", - "orr w25, w30, w25", - "ror w30, w20, #27", - "add w25, w25, w30", - "add w24, w25, w24", - "mov w25, #0xbcdc", - "movk w25, #0x8f1b, lsl #16", - "add w24, w24, w25", + "mov w30, v17.s[1]", + "add w24, w30, w24", + "and w30, w22, w23", + "orr w18, w22, w23", + "and w18, w21, w18", + "orr w30, w18, w30", + "ror w18, w25, #27", + "add w30, w30, w18", + "add w24, w30, w24", + "add w24, w24, w20", "ror w21, w21, #2", - "mov w25, v17.s[1]", - "add w23, w25, w23", - "and w25, w21, w22", - "orr w30, w21, w22", - "and w30, w20, w30", - "orr w25, w30, w25", - "ror w30, w24, #27", - "add w25, w25, w30", - "add w23, w25, w23", - "mov w25, #0xbcdc", - "movk w25, #0x8f1b, lsl #16", - "add w23, w23, w25", - "ror w20, w20, #2", "mov w30, v17.s[0]", - "add w22, w30, w22", - "and w30, w20, w21", - "orr w21, w20, w21", - "and w21, w24, w21", - "orr w21, w21, w30", - "ror w30, w23, #27", - "add w21, w21, w30", - "add w21, w21, w22", - "add w21, w21, w25", - "ror w22, w24, #2", + "add w23, w30, w23", + "and w30, w21, w22", + "orr w22, w21, w22", + "and w22, w25, w22", + "orr w22, w22, w30", + "ror w30, w24, #27", + "add w22, w22, w30", + "add w22, w22, w23", + "add w20, w22, w20", + "ror w22, w25, #2", "mov v2.16b, v16.16b", - "mov v2.s[3], w21", - "mov v2.s[2], w23", + "mov v2.s[3], w20", + "mov v2.s[2], w24", "mov v2.s[1], w22", "mov v16.16b, v2.16b", - "mov v16.s[0], w20" + "mov v16.s[0], w21" ] }, "sha1rnds4 xmm0, xmm1, 11b": { - "ExpectedInstructionCount": 53, + "ExpectedInstructionCount": 47, "Comment": [ "0x66 0x0f 0x3a 0xcc" ], "ExpectedArm64ASM": [ "mov w20, #0xc1d6", "movk w20, #0xca62, lsl #16", - "mov w20, v17.s[3]", - "mov w21, v16.s[3]", - "mov w22, v16.s[2]", - "mov w23, v16.s[1]", - "mov w24, v16.s[0]", - "eor w25, w22, w23", - "eor w25, w25, w24", - "ror w30, w21, #27", - "add w25, w25, w30", - "add w20, w25, w20", - "mov w25, #0xc1d6", - "movk w25, #0xca62, lsl #16", - "add w20, w20, w25", + "mov w21, v17.s[3]", + "mov w22, v16.s[3]", + "mov w23, v16.s[2]", + "mov w24, v16.s[1]", + "mov w25, v16.s[0]", + "eor w30, w23, w24", + "eor w30, w30, w25", + "ror w18, w22, #27", + "add w30, w30, w18", + "add w21, w30, w21", + "add w21, w21, w20", + "ror w23, w23, #2", + "mov w30, v17.s[2]", + "add w25, w30, w25", + "eor w30, w22, w23", + "eor w30, w30, w24", + "ror w18, w21, #27", + "add w30, w30, w18", + "add w25, w30, w25", + "add w25, w25, w20", "ror w22, w22, #2", - "mov w25, v17.s[2]", - "add w24, w25, w24", - "eor w25, w21, w22", - "eor w25, w25, w23", - "ror w30, w20, #27", - "add w25, w25, w30", - "add w24, w25, w24", - "mov w25, #0xc1d6", - "movk w25, #0xca62, lsl #16", - "add w24, w24, w25", + "mov w30, v17.s[1]", + "add w24, w30, w24", + "eor w30, w21, w22", + "eor w30, w30, w23", + "ror w18, w25, #27", + "add w30, w30, w18", + "add w24, w30, w24", + "add w24, w24, w20", "ror w21, w21, #2", - "mov w25, v17.s[1]", - "add w23, w25, w23", - "eor w25, w20, w21", - "eor w25, w25, w22", - "ror w30, w24, #27", - "add w25, w25, w30", - "add w23, w25, w23", - "mov w25, #0xc1d6", - "movk w25, #0xca62, lsl #16", - "add w23, w23, w25", - "ror w20, w20, #2", "mov w30, v17.s[0]", - "add w22, w30, w22", - "eor w30, w24, w20", - "eor w21, w30, w21", - "ror w30, w23, #27", - "add w21, w21, w30", - "add w21, w21, w22", - "add w21, w21, w25", - "ror w22, w24, #2", + "add w23, w30, w23", + "eor w30, w25, w21", + "eor w22, w30, w22", + "ror w30, w24, #27", + "add w22, w22, w30", + "add w22, w22, w23", + "add w20, w22, w20", + "ror w22, w25, #2", "mov v2.16b, v16.16b", - "mov v2.s[3], w21", - "mov v2.s[2], w23", + "mov v2.s[3], w20", + "mov v2.s[2], w24", "mov v2.s[1], w22", "mov v16.16b, v2.16b", - "mov v16.s[0], w20" + "mov v16.s[0], w21" ] } } diff --git a/unittests/InstructionCountCI/Primary.json b/unittests/InstructionCountCI/Primary.json index d79f941b8..1b5bbc3f8 100644 --- a/unittests/InstructionCountCI/Primary.json +++ b/unittests/InstructionCountCI/Primary.json @@ -103,28 +103,26 @@ ] }, "add al, 1": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 6, "Comment": "0x04", "ExpectedArm64ASM": [ "mov w20, #0x1", "mov x27, x4", - "lsl w0, w27, #24", + "lsl w0, w4, #24", "cmn w0, w20, lsl #24", - "add w26, w27, #0x1 (1)", - "mov x4, x27", + "add w26, w4, #0x1 (1)", "bfxil x4, x26, #0, #8" ] }, "add ax, 1": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 6, "Comment": "0x05", "ExpectedArm64ASM": [ "mov w20, #0x1", "mov x27, x4", - "lsl w0, w27, #16", + "lsl w0, w4, #16", "cmn w0, w20, lsl #16", - "add w26, w27, #0x1 (1)", - "mov x4, x27", + "add w26, w4, #0x1 (1)", "bfxil x4, x26, #0, #16" ] }, @@ -133,7 +131,7 @@ "Comment": "0x05", "ExpectedArm64ASM": [ "mov x27, x4", - "adds w26, w27, #0x1 (1)", + "adds w26, w4, #0x1 (1)", "mov x4, x26" ] }, @@ -142,7 +140,7 @@ "Comment": "0x05", "ExpectedArm64ASM": [ "mov x27, x4", - "adds x26, x27, #0x1 (1)", + "adds x26, x4, #0x1 (1)", "mov x4, x26" ] }, @@ -498,49 +496,47 @@ ] }, "adc al, 1": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 17, "Comment": "0x14", "ExpectedArm64ASM": [ "mov x27, x4", "mov w20, #0x1", "adc w20, wzr, w20", - "add w21, w27, w20", + "add w21, w4, w20", "uxtb w26, w21", "cmp w26, w20", "cset x20, lo", "cmn wzr, w26, lsl #24", "mrs x21, nzcv", "orr w20, w21, w20, lsl #29", - "eor w21, w27, #0x1", - "eor w22, w26, w27", + "eor w21, w4, #0x1", + "eor w22, w26, w4", "bic w21, w22, w21", "ubfx x21, x21, #7, #1", "orr w20, w20, w21, lsl #28", - "mov x4, x27", "bfxil x4, x26, #0, #8", "msr nzcv, x20" ] }, "adc ax, 1": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 17, "Comment": "0x15", "ExpectedArm64ASM": [ "mov x27, x4", "mov w20, #0x1", "adc w20, wzr, w20", - "add w21, w27, w20", + "add w21, w4, w20", "uxth w26, w21", "cmp w26, w20", "cset x20, lo", "cmn wzr, w26, lsl #16", "mrs x21, nzcv", "orr w20, w21, w20, lsl #29", - "eor w21, w27, #0x1", - "eor w22, w26, w27", + "eor w21, w4, #0x1", + "eor w22, w26, w4", "bic w21, w22, w21", "ubfx x21, x21, #15, #1", "orr w20, w20, w21, lsl #28", - "mov x4, x27", "bfxil x4, x26, #0, #16", "msr nzcv, x20" ] @@ -551,7 +547,7 @@ "ExpectedArm64ASM": [ "mov w20, #0x1", "mov x27, x4", - "adcs w26, w27, w20", + "adcs w26, w4, w20", "mov x4, x26" ] }, @@ -561,7 +557,7 @@ "ExpectedArm64ASM": [ "mov w20, #0x1", "mov x27, x4", - "adcs x26, x27, x20", + "adcs x26, x4, x20", "mov x4, x26" ] }, @@ -800,11 +796,11 @@ ] }, "sbb al, 1": { - "ExpectedInstructionCount": 17, + "ExpectedInstructionCount": 16, "Comment": "0x1C", "ExpectedArm64ASM": [ "mov x27, x4", - "uxtb w20, w27", + "uxtb w20, w4", "cset w21, hs", "sub w21, w20, w21", "sub w22, w21, #0x1 (1)", @@ -817,17 +813,16 @@ "bic w20, w20, w26", "ubfx x20, x20, #7, #1", "orr w20, w21, w20, lsl #28", - "mov x4, x27", "bfxil x4, x26, #0, #8", "msr nzcv, x20" ] }, "sbb ax, 1": { - "ExpectedInstructionCount": 17, + "ExpectedInstructionCount": 16, "Comment": "0x1D", "ExpectedArm64ASM": [ "mov x27, x4", - "uxth w20, w27", + "uxth w20, w4", "cset w21, hs", "sub w21, w20, w21", "sub w22, w21, #0x1 (1)", @@ -840,7 +835,6 @@ "bic w20, w20, w26", "ubfx x20, x20, #15, #1", "orr w20, w21, w20, lsl #28", - "mov x4, x27", "bfxil x4, x26, #0, #16", "msr nzcv, x20" ] @@ -854,7 +848,7 @@ "mrs x21, nzcv", "eor w21, w21, #0x20000000", "msr nzcv, x21", - "sbcs w26, w27, w20", + "sbcs w26, w4, w20", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "mov x4, x26", @@ -870,7 +864,7 @@ "mrs x21, nzcv", "eor w21, w21, #0x20000000", "msr nzcv, x21", - "sbcs x26, x27, x20", + "sbcs x26, x4, x20", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "mov x4, x26", @@ -1221,33 +1215,31 @@ ] }, "sub al, 1": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 9, "Comment": "0x2C", "ExpectedArm64ASM": [ "mov w20, #0x1", "mov x27, x4", - "lsl w0, w27, #24", + "lsl w0, w4, #24", "cmp w0, w20, lsl #24", - "sub w26, w27, #0x1 (1)", + "sub w26, w4, #0x1 (1)", "mrs x20, nzcv", "eor w20, w20, #0x20000000", - "mov x4, x27", "bfxil x4, x26, #0, #8", "msr nzcv, x20" ] }, "sub ax, 1": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 9, "Comment": "0x2D", "ExpectedArm64ASM": [ "mov w20, #0x1", "mov x27, x4", - "lsl w0, w27, #16", + "lsl w0, w4, #16", "cmp w0, w20, lsl #16", - "sub w26, w27, #0x1 (1)", + "sub w26, w4, #0x1 (1)", "mrs x20, nzcv", "eor w20, w20, #0x20000000", - "mov x4, x27", "bfxil x4, x26, #0, #16", "msr nzcv, x20" ] @@ -1257,7 +1249,7 @@ "Comment": "0x2D", "ExpectedArm64ASM": [ "mov x27, x4", - "subs w26, w27, #0x1 (1)", + "subs w26, w4, #0x1 (1)", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "mov x4, x26", @@ -1269,7 +1261,7 @@ "Comment": "0x2D", "ExpectedArm64ASM": [ "mov x27, x4", - "subs x26, x27, #0x1 (1)", + "subs x26, x4, #0x1 (1)", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "mov x4, x26", @@ -1603,9 +1595,9 @@ "ExpectedArm64ASM": [ "mov w20, #0x1", "mov x27, x4", - "lsl w0, w27, #24", + "lsl w0, w4, #24", "cmp w0, w20, lsl #24", - "sub w26, w27, #0x1 (1)", + "sub w26, w4, #0x1 (1)", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" @@ -1617,9 +1609,9 @@ "ExpectedArm64ASM": [ "mov w20, #0x1", "mov x27, x4", - "lsl w0, w27, #16", + "lsl w0, w4, #16", "cmp w0, w20, lsl #16", - "sub w26, w27, #0x1 (1)", + "sub w26, w4, #0x1 (1)", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" @@ -1630,7 +1622,7 @@ "Comment": "0x3D", "ExpectedArm64ASM": [ "mov x27, x4", - "subs w26, w27, #0x1 (1)", + "subs w26, w4, #0x1 (1)", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" @@ -1641,7 +1633,7 @@ "Comment": "0x3D", "ExpectedArm64ASM": [ "mov x27, x4", - "subs x26, x27, #0x1 (1)", + "subs x26, x4, #0x1 (1)", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" @@ -1915,13 +1907,14 @@ ] }, "xchg bl, cl": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 5, "Comment": "0x86", "ExpectedArm64ASM": [ "mov x20, x5", + "bfxil x20, x7, #0, #8", + "mov x21, x5", "mov x5, x20", - "bfxil x5, x7, #0, #8", - "bfxil x7, x20, #0, #8" + "bfxil x7, x21, #0, #8" ] }, "xchg [rax], cl": { @@ -1933,13 +1926,14 @@ ] }, "xchg bx, cx": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 5, "Comment": "0x87", "ExpectedArm64ASM": [ "mov x20, x5", + "bfxil x20, x7, #0, #16", + "mov x21, x5", "mov x5, x20", - "bfxil x5, x7, #0, #16", - "bfxil x7, x20, #0, #16" + "bfxil x7, x21, #0, #16" ] }, "xchg [rax], cx": { @@ -1951,12 +1945,13 @@ ] }, "xchg ebx, ecx": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 4, "Comment": "0x87", "ExpectedArm64ASM": [ - "mov x20, x5", - "mov w5, w7", - "mov w7, w20" + "mov w20, w7", + "mov x21, x5", + "mov x5, x20", + "mov w7, w21" ] }, "xchg [rax], ecx": { @@ -1970,9 +1965,9 @@ "ExpectedInstructionCount": 3, "Comment": "0x87", "ExpectedArm64ASM": [ - "mov x20, x7", - "mov x7, x5", - "mov x5, x20" + "mov x20, x5", + "mov x5, x7", + "mov x7, x20" ] }, "xchg [rax], rcx": { @@ -2435,31 +2430,33 @@ ] }, "xchg ax, bx": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 5, "Comment": "0x90", "ExpectedArm64ASM": [ "mov x20, x7", + "bfxil x20, x4, #0, #16", + "mov x21, x7", "mov x7, x20", - "bfxil x7, x4, #0, #16", - "bfxil x4, x20, #0, #16" + "bfxil x4, x21, #0, #16" ] }, "xchg eax, ebx": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 4, "Comment": "0x90", "ExpectedArm64ASM": [ - "mov x20, x7", - "mov w7, w4", - "mov w4, w20" + "mov w20, w4", + "mov x21, x7", + "mov x7, x20", + "mov w4, w21" ] }, "xchg rax, rbx": { "ExpectedInstructionCount": 3, "Comment": "0x90", "ExpectedArm64ASM": [ - "mov x20, x4", - "mov x4, x7", - "mov x7, x20" + "mov x20, x7", + "mov x7, x4", + "mov x4, x20" ] }, "nop": { @@ -3240,10 +3237,10 @@ ] }, "repz cmpsb": { - "ExpectedInstructionCount": 28, + "ExpectedInstructionCount": 29, "Comment": "0xa6", "ExpectedArm64ASM": [ - "cbz x5, #+0x70", + "cbz x5, #+0x74", "ldrsb x20, [x28, #714]", "lsr x20, x20, #63", "cbz x20, #+0x8", @@ -3263,21 +3260,22 @@ "sub x10, x10, #0x1 (1)", "ccmp x27, x26, #nzcv, ne", "b.eq #-0x18", - "mov x20, x27", - "eor w27, w20, w26", - "lsl w0, w20, #24", + "eor w20, w27, w26", + "mov x21, x27", + "mov x27, x20", + "lsl w0, w21, #24", "cmp w0, w26, lsl #24", - "sub w26, w20, w26", + "sub w26, w21, w26", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" ] }, "repz cmpsw": { - "ExpectedInstructionCount": 28, + "ExpectedInstructionCount": 29, "Comment": "0xa7", "ExpectedArm64ASM": [ - "cbz x5, #+0x70", + "cbz x5, #+0x74", "ldrsb x20, [x28, #714]", "lsr x20, x20, #63", "cbz x20, #+0x8", @@ -3297,21 +3295,22 @@ "sub x10, x10, #0x2 (2)", "ccmp x27, x26, #nzcv, ne", "b.eq #-0x18", - "mov x20, x27", - "eor w27, w20, w26", - "lsl w0, w20, #16", + "eor w20, w27, w26", + "mov x21, x27", + "mov x27, x20", + "lsl w0, w21, #16", "cmp w0, w26, lsl #16", - "sub w26, w20, w26", + "sub w26, w21, w26", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" ] }, "repz cmpsd": { - "ExpectedInstructionCount": 26, + "ExpectedInstructionCount": 27, "Comment": "0xa7", "ExpectedArm64ASM": [ - "cbz x5, #+0x68", + "cbz x5, #+0x6c", "ldrsb x20, [x28, #714]", "lsr x20, x20, #63", "cbz x20, #+0x8", @@ -3331,19 +3330,20 @@ "sub x10, x10, #0x4 (4)", "ccmp x27, x26, #nzcv, ne", "b.eq #-0x18", - "mov x20, x27", - "eor w27, w20, w26", - "subs w26, w20, w26", + "eor w20, w27, w26", + "mov x21, x27", + "mov x27, x20", + "subs w26, w21, w26", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" ] }, "repz cmpsq": { - "ExpectedInstructionCount": 26, + "ExpectedInstructionCount": 27, "Comment": "0xa7", "ExpectedArm64ASM": [ - "cbz x5, #+0x68", + "cbz x5, #+0x6c", "ldrsb x20, [x28, #714]", "lsr x20, x20, #63", "cbz x20, #+0x8", @@ -3363,19 +3363,20 @@ "sub x10, x10, #0x8 (8)", "ccmp x27, x26, #nzcv, ne", "b.eq #-0x18", - "mov x20, x27", - "eor w27, w20, w26", - "subs x26, x20, x26", + "eor w20, w27, w26", + "mov x21, x27", + "mov x27, x20", + "subs x26, x21, x26", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" ] }, "repnz cmpsb": { - "ExpectedInstructionCount": 28, + "ExpectedInstructionCount": 29, "Comment": "0xa6", "ExpectedArm64ASM": [ - "cbz x5, #+0x70", + "cbz x5, #+0x74", "ldrsb x20, [x28, #714]", "lsr x20, x20, #63", "cbz x20, #+0x8", @@ -3395,21 +3396,22 @@ "sub x10, x10, #0x1 (1)", "ccmp x27, x26, #nZcv, ne", "b.ne #-0x18", - "mov x20, x27", - "eor w27, w20, w26", - "lsl w0, w20, #24", + "eor w20, w27, w26", + "mov x21, x27", + "mov x27, x20", + "lsl w0, w21, #24", "cmp w0, w26, lsl #24", - "sub w26, w20, w26", + "sub w26, w21, w26", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" ] }, "repnz cmpsw": { - "ExpectedInstructionCount": 28, + "ExpectedInstructionCount": 29, "Comment": "0xa7", "ExpectedArm64ASM": [ - "cbz x5, #+0x70", + "cbz x5, #+0x74", "ldrsb x20, [x28, #714]", "lsr x20, x20, #63", "cbz x20, #+0x8", @@ -3429,21 +3431,22 @@ "sub x10, x10, #0x2 (2)", "ccmp x27, x26, #nZcv, ne", "b.ne #-0x18", - "mov x20, x27", - "eor w27, w20, w26", - "lsl w0, w20, #16", + "eor w20, w27, w26", + "mov x21, x27", + "mov x27, x20", + "lsl w0, w21, #16", "cmp w0, w26, lsl #16", - "sub w26, w20, w26", + "sub w26, w21, w26", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" ] }, "repnz cmpsd": { - "ExpectedInstructionCount": 26, + "ExpectedInstructionCount": 27, "Comment": "0xa7", "ExpectedArm64ASM": [ - "cbz x5, #+0x68", + "cbz x5, #+0x6c", "ldrsb x20, [x28, #714]", "lsr x20, x20, #63", "cbz x20, #+0x8", @@ -3463,19 +3466,20 @@ "sub x10, x10, #0x4 (4)", "ccmp x27, x26, #nZcv, ne", "b.ne #-0x18", - "mov x20, x27", - "eor w27, w20, w26", - "subs w26, w20, w26", + "eor w20, w27, w26", + "mov x21, x27", + "mov x27, x20", + "subs w26, w21, w26", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" ] }, "repnz cmpsq": { - "ExpectedInstructionCount": 26, + "ExpectedInstructionCount": 27, "Comment": "0xa7", "ExpectedArm64ASM": [ - "cbz x5, #+0x68", + "cbz x5, #+0x6c", "ldrsb x20, [x28, #714]", "lsr x20, x20, #63", "cbz x20, #+0x8", @@ -3495,9 +3499,10 @@ "sub x10, x10, #0x8 (8)", "ccmp x27, x26, #nZcv, ne", "b.ne #-0x18", - "mov x20, x27", - "eor w27, w20, w26", - "subs x26, x20, x26", + "eor w20, w27, w26", + "mov x21, x27", + "mov x27, x20", + "subs x26, x21, x26", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" diff --git a/unittests/InstructionCountCI/PrimaryGroup.json b/unittests/InstructionCountCI/PrimaryGroup.json index ec55a9e35..545366f09 100644 --- a/unittests/InstructionCountCI/PrimaryGroup.json +++ b/unittests/InstructionCountCI/PrimaryGroup.json @@ -15,15 +15,14 @@ ], "Instructions": { "add al, 1": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x80 /0", "ExpectedArm64ASM": [ "mov w20, #0x1", "mov x27, x4", - "lsl w0, w27, #24", + "lsl w0, w4, #24", "cmn w0, w20, lsl #24", - "add w26, w27, #0x1 (1)", - "mov x4, x27", + "add w26, w4, #0x1 (1)", "bfxil x4, x26, #0, #8" ] }, @@ -37,35 +36,34 @@ ] }, "adc al, 1": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 17, "Comment": "GROUP1 0x80 /2", "ExpectedArm64ASM": [ "mov x27, x4", "mov w20, #0x1", "adc w20, wzr, w20", - "add w21, w27, w20", + "add w21, w4, w20", "uxtb w26, w21", "cmp w26, w20", "cset x20, lo", "cmn wzr, w26, lsl #24", "mrs x21, nzcv", "orr w20, w21, w20, lsl #29", - "eor w21, w27, #0x1", - "eor w22, w26, w27", + "eor w21, w4, #0x1", + "eor w22, w26, w4", "bic w21, w22, w21", "ubfx x21, x21, #7, #1", "orr w20, w20, w21, lsl #28", - "mov x4, x27", "bfxil x4, x26, #0, #8", "msr nzcv, x20" ] }, "sbb al, 1": { - "ExpectedInstructionCount": 17, + "ExpectedInstructionCount": 16, "Comment": "GROUP1 0x80 /3", "ExpectedArm64ASM": [ "mov x27, x4", - "uxtb w20, w27", + "uxtb w20, w4", "cset w21, hs", "sub w21, w20, w21", "sub w22, w21, #0x1 (1)", @@ -78,7 +76,6 @@ "bic w20, w20, w26", "ubfx x20, x20, #7, #1", "orr w20, w21, w20, lsl #28", - "mov x4, x27", "bfxil x4, x26, #0, #8", "msr nzcv, x20" ] @@ -93,17 +90,16 @@ ] }, "sub al, 1": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 9, "Comment": "GROUP1 0x80 /5", "ExpectedArm64ASM": [ "mov w20, #0x1", "mov x27, x4", - "lsl w0, w27, #24", + "lsl w0, w4, #24", "cmp w0, w20, lsl #24", - "sub w26, w27, #0x1 (1)", + "sub w26, w4, #0x1 (1)", "mrs x20, nzcv", "eor w20, w20, #0x20000000", - "mov x4, x27", "bfxil x4, x26, #0, #8", "msr nzcv, x20" ] @@ -123,9 +119,9 @@ "ExpectedArm64ASM": [ "mov w20, #0x1", "mov x27, x4", - "lsl w0, w27, #24", + "lsl w0, w4, #24", "cmp w0, w20, lsl #24", - "sub w26, w27, #0x1 (1)", + "sub w26, w4, #0x1 (1)", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" @@ -245,15 +241,14 @@ ] }, "add ax, 256": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x81 /0", "ExpectedArm64ASM": [ "mov w20, #0x100", "mov x27, x4", - "lsl w0, w27, #16", + "lsl w0, w4, #16", "cmn w0, w20, lsl #16", - "add w26, w27, #0x100 (256)", - "mov x4, x27", + "add w26, w4, #0x100 (256)", "bfxil x4, x26, #0, #16" ] }, @@ -262,7 +257,7 @@ "Comment": "GROUP1 0x81 /0", "ExpectedArm64ASM": [ "mov x27, x4", - "adds w26, w27, #0x100 (256)", + "adds w26, w4, #0x100 (256)", "mov x4, x26" ] }, @@ -271,7 +266,7 @@ "Comment": "GROUP1 0x81 /0", "ExpectedArm64ASM": [ "mov x27, x4", - "adds x26, x27, #0x100 (256)", + "adds x26, x4, #0x100 (256)", "mov x4, x26" ] }, @@ -299,7 +294,7 @@ "ExpectedArm64ASM": [ "mov w20, #0x100", "mov x27, x4", - "adcs w26, w27, w20", + "adcs w26, w4, w20", "mov x4, x26" ] }, @@ -309,7 +304,7 @@ "ExpectedArm64ASM": [ "mov w20, #0x100", "mov x27, x4", - "adcs x26, x27, x20", + "adcs x26, x4, x20", "mov x4, x26" ] }, @@ -322,7 +317,7 @@ "mrs x21, nzcv", "eor w21, w21, #0x20000000", "msr nzcv, x21", - "sbcs w26, w27, w20", + "sbcs w26, w4, w20", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "mov x4, x26", @@ -338,7 +333,7 @@ "mrs x21, nzcv", "eor w21, w21, #0x20000000", "msr nzcv, x21", - "sbcs x26, x27, x20", + "sbcs x26, x4, x20", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "mov x4, x26", @@ -366,7 +361,7 @@ "Comment": "GROUP1 0x81 /5", "ExpectedArm64ASM": [ "mov x27, x4", - "subs w26, w27, #0x100 (256)", + "subs w26, w4, #0x100 (256)", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "mov x4, x26", @@ -378,7 +373,7 @@ "Comment": "GROUP1 0x81 /5", "ExpectedArm64ASM": [ "mov x27, x4", - "subs x26, x27, #0x100 (256)", + "subs x26, x4, #0x100 (256)", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "mov x4, x26", @@ -408,7 +403,7 @@ "Comment": "GROUP1 0x81 /7", "ExpectedArm64ASM": [ "mov x27, x4", - "subs w26, w27, #0x100 (256)", + "subs w26, w4, #0x100 (256)", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" @@ -419,22 +414,21 @@ "Comment": "GROUP1 0x81 /7", "ExpectedArm64ASM": [ "mov x27, x4", - "subs x26, x27, #0x100 (256)", + "subs x26, x4, #0x100 (256)", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" ] }, "add ax, -256": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x81 /0", "ExpectedArm64ASM": [ "mov w20, #0xff00", "mov x27, x4", - "lsl w0, w27, #16", + "lsl w0, w4, #16", "cmn w0, w20, lsl #16", - "add w26, w27, w20", - "mov x4, x27", + "add w26, w4, w20", "bfxil x4, x26, #0, #16" ] }, @@ -444,7 +438,7 @@ "ExpectedArm64ASM": [ "mov w20, #0xffffff00", "mov x27, x4", - "adds w26, w27, w20", + "adds w26, w4, w20", "mov x4, x26" ] }, @@ -453,7 +447,7 @@ "Comment": "GROUP1 0x81 /0", "ExpectedArm64ASM": [ "mov x27, x4", - "subs x26, x27, #0x100 (256)", + "subs x26, x4, #0x100 (256)", "mov x4, x26" ] }, @@ -481,7 +475,7 @@ "ExpectedArm64ASM": [ "mov w20, #0xffffff00", "mov x27, x4", - "adcs w26, w27, w20", + "adcs w26, w4, w20", "mov x4, x26" ] }, @@ -491,7 +485,7 @@ "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffff00", "mov x27, x4", - "adcs x26, x27, x20", + "adcs x26, x4, x20", "mov x4, x26" ] }, @@ -504,7 +498,7 @@ "mrs x21, nzcv", "eor w21, w21, #0x20000000", "msr nzcv, x21", - "sbcs w26, w27, w20", + "sbcs w26, w4, w20", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "mov x4, x26", @@ -520,7 +514,7 @@ "mrs x21, nzcv", "eor w21, w21, #0x20000000", "msr nzcv, x21", - "sbcs x26, x27, x20", + "sbcs x26, x4, x20", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "mov x4, x26", @@ -549,7 +543,7 @@ "ExpectedArm64ASM": [ "mov w20, #0xffffff00", "mov x27, x4", - "subs w26, w27, w20", + "subs w26, w4, w20", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "mov x4, x26", @@ -561,7 +555,7 @@ "Comment": "GROUP1 0x81 /5", "ExpectedArm64ASM": [ "mov x27, x4", - "adds x26, x27, #0x100 (256)", + "adds x26, x4, #0x100 (256)", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "mov x4, x26", @@ -592,7 +586,7 @@ "ExpectedArm64ASM": [ "mov w20, #0xffffff00", "mov x27, x4", - "subs w26, w27, w20", + "subs w26, w4, w20", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" @@ -603,22 +597,21 @@ "Comment": "GROUP1 0x81 /7", "ExpectedArm64ASM": [ "mov x27, x4", - "adds x26, x27, #0x100 (256)", + "adds x26, x4, #0x100 (256)", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" ] }, "add ax, 1": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x83 /0", "ExpectedArm64ASM": [ "mov w20, #0x1", "mov x27, x4", - "lsl w0, w27, #16", + "lsl w0, w4, #16", "cmn w0, w20, lsl #16", - "add w26, w27, #0x1 (1)", - "mov x4, x27", + "add w26, w4, #0x1 (1)", "bfxil x4, x26, #0, #16" ] }, @@ -627,7 +620,7 @@ "Comment": "GROUP1 0x83 /0", "ExpectedArm64ASM": [ "mov x27, x4", - "adds w26, w27, #0x1 (1)", + "adds w26, w4, #0x1 (1)", "mov x4, x26" ] }, @@ -636,7 +629,7 @@ "Comment": "GROUP1 0x83 /0", "ExpectedArm64ASM": [ "mov x27, x4", - "adds x26, x27, #0x1 (1)", + "adds x26, x4, #0x1 (1)", "mov x4, x26" ] }, @@ -664,7 +657,7 @@ "ExpectedArm64ASM": [ "mov w20, #0x1", "mov x27, x4", - "adcs w26, w27, w20", + "adcs w26, w4, w20", "mov x4, x26" ] }, @@ -674,7 +667,7 @@ "ExpectedArm64ASM": [ "mov w20, #0x1", "mov x27, x4", - "adcs x26, x27, x20", + "adcs x26, x4, x20", "mov x4, x26" ] }, @@ -687,7 +680,7 @@ "mrs x21, nzcv", "eor w21, w21, #0x20000000", "msr nzcv, x21", - "sbcs w26, w27, w20", + "sbcs w26, w4, w20", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "mov x4, x26", @@ -703,7 +696,7 @@ "mrs x21, nzcv", "eor w21, w21, #0x20000000", "msr nzcv, x21", - "sbcs x26, x27, x20", + "sbcs x26, x4, x20", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "mov x4, x26", @@ -731,7 +724,7 @@ "Comment": "GROUP1 0x83 /5", "ExpectedArm64ASM": [ "mov x27, x4", - "subs w26, w27, #0x1 (1)", + "subs w26, w4, #0x1 (1)", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "mov x4, x26", @@ -743,7 +736,7 @@ "Comment": "GROUP1 0x83 /5", "ExpectedArm64ASM": [ "mov x27, x4", - "subs x26, x27, #0x1 (1)", + "subs x26, x4, #0x1 (1)", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "mov x4, x26", @@ -773,7 +766,7 @@ "Comment": "GROUP1 0x83 /7", "ExpectedArm64ASM": [ "mov x27, x4", - "subs w26, w27, #0x1 (1)", + "subs w26, w4, #0x1 (1)", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" @@ -784,7 +777,7 @@ "Comment": "GROUP1 0x83 /7", "ExpectedArm64ASM": [ "mov x27, x4", - "subs x26, x27, #0x1 (1)", + "subs x26, x4, #0x1 (1)", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" @@ -1665,23 +1658,21 @@ ] }, "rcl rax, 1": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 12, "Comment": "GROUP2 0xd1 /2", "ExpectedArm64ASM": [ - "mov x20, x4", - "cset w21, hs", - "orr x4, x21, x20, lsl #1", - "lsr x21, x20, #63", + "cset w20, hs", + "orr x20, x20, x4, lsl #1", + "lsr x21, x4, #63", "mrs x22, nzcv", "mov w0, w22", "bfi w0, w21, #29, #1", "mov w21, w0", - "eor x20, x4, x20", - "lsr x20, x20, #63", - "mov w0, w21", - "bfi w0, w20, #28, #1", - "mov w20, w0", - "msr nzcv, x20" + "eor x22, x20, x4", + "lsr x22, x22, #63", + "bfi w21, w22, #28, #1", + "mov x4, x20", + "msr nzcv, x21" ] }, "rcr ax, 1": { @@ -2361,36 +2352,36 @@ "ExpectedInstructionCount": 12, "Comment": "GROUP2 0xd3 /4", "ExpectedArm64ASM": [ - "mov x20, x4", - "lsl w4, w20, w5", + "lsl w20, w4, w5", "cbz w5, #+0x28", - "ands w26, w4, w4", + "ands w26, w20, w20", "neg w0, w5", - "lsr w0, w20, w0", - "eor w2, w20, w4", + "lsr w0, w4, w0", + "eor w2, w4, w20", "mrs x1, nzcv", "bfi w1, w0, #29, #1", "lsr w2, w2, #31", "bfi w1, w2, #28, #1", - "msr nzcv, x1" + "msr nzcv, x1", + "mov x4, x20" ] }, "shl rax, cl": { "ExpectedInstructionCount": 12, "Comment": "GROUP2 0xd3 /4", "ExpectedArm64ASM": [ - "mov x20, x4", - "lsl x4, x20, x5", + "lsl x20, x4, x5", "cbz x5, #+0x28", - "ands x26, x4, x4", + "ands x26, x20, x20", "neg x0, x5", - "lsr x0, x20, x0", - "eor x2, x20, x4", + "lsr x0, x4, x0", + "eor x2, x4, x20", "mrs x1, nzcv", "bfi w1, w0, #29, #1", "lsr x2, x2, #63", "bfi w1, w2, #28, #1", - "msr nzcv, x1" + "msr nzcv, x1", + "mov x4, x20" ] }, "shr ax, cl": { @@ -2417,36 +2408,36 @@ "ExpectedInstructionCount": 12, "Comment": "GROUP2 0xd3 /5", "ExpectedArm64ASM": [ - "mov x20, x4", - "lsr w4, w20, w5", + "lsr w20, w4, w5", "cbz w5, #+0x28", - "ands w26, w4, w4", + "ands w26, w20, w20", "sub x0, x5, #0x1 (1)", - "lsr w0, w20, w0", - "eor w2, w20, w4", + "lsr w0, w4, w0", + "eor w2, w4, w20", "mrs x1, nzcv", "bfi w1, w0, #29, #1", "lsr w2, w2, #31", "bfi w1, w2, #28, #1", - "msr nzcv, x1" + "msr nzcv, x1", + "mov x4, x20" ] }, "shr rax, cl": { "ExpectedInstructionCount": 12, "Comment": "GROUP2 0xd3 /5", "ExpectedArm64ASM": [ - "mov x20, x4", - "lsr x4, x20, x5", + "lsr x20, x4, x5", "cbz x5, #+0x28", - "ands x26, x4, x4", + "ands x26, x20, x20", "sub x0, x5, #0x1 (1)", - "lsr x0, x20, x0", - "eor x2, x20, x4", + "lsr x0, x4, x0", + "eor x2, x4, x20", "mrs x1, nzcv", "bfi w1, w0, #29, #1", "lsr x2, x2, #63", "bfi w1, w2, #28, #1", - "msr nzcv, x1" + "msr nzcv, x1", + "mov x4, x20" ] }, "sar ax, cl": { @@ -2470,30 +2461,30 @@ "ExpectedInstructionCount": 9, "Comment": "GROUP2 0xd3 /7", "ExpectedArm64ASM": [ - "mov x20, x4", - "asr w4, w20, w5", + "asr w20, w4, w5", "cbz w5, #+0x1c", - "ands w26, w4, w4", + "ands w26, w20, w20", "sub x0, x5, #0x1 (1)", - "lsr w0, w20, w0", + "lsr w0, w4, w0", "mrs x1, nzcv", "bfi w1, w0, #29, #1", - "msr nzcv, x1" + "msr nzcv, x1", + "mov x4, x20" ] }, "sar rax, cl": { "ExpectedInstructionCount": 9, "Comment": "GROUP2 0xd3 /7", "ExpectedArm64ASM": [ - "mov x20, x4", - "asr x4, x20, x5", + "asr x20, x4, x5", "cbz x5, #+0x1c", - "ands x26, x4, x4", + "ands x26, x20, x20", "sub x0, x5, #0x1 (1)", - "lsr x0, x20, x0", + "lsr x0, x4, x0", "mrs x1, nzcv", "bfi w1, w0, #29, #1", - "msr nzcv, x1" + "msr nzcv, x1", + "mov x4, x20" ] }, "test bl, 1": { @@ -2519,15 +2510,14 @@ ] }, "neg bl": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 7, "Comment": "GROUP2 0xf6 /3", "ExpectedArm64ASM": [ "mov x27, x7", - "cmp wzr, w27, lsl #24", - "neg w26, w27", + "cmp wzr, w7, lsl #24", + "neg w26, w7", "mrs x20, nzcv", "eor w20, w20, #0x20000000", - "mov x7, x27", "bfxil x7, x26, #0, #8", "msr nzcv, x20" ] @@ -2661,15 +2651,14 @@ ] }, "neg bx": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 7, "Comment": "GROUP2 0xf7 /2", "ExpectedArm64ASM": [ "mov x27, x7", - "cmp wzr, w27, lsl #16", - "neg w26, w27", + "cmp wzr, w7, lsl #16", + "neg w26, w7", "mrs x20, nzcv", "eor w20, w20, #0x20000000", - "mov x7, x27", "bfxil x7, x26, #0, #16", "msr nzcv, x20" ] @@ -2679,7 +2668,7 @@ "Comment": "GROUP2 0xf7 /2", "ExpectedArm64ASM": [ "mov x27, x7", - "negs w26, w27", + "negs w26, w7", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "mov x7, x26", @@ -2691,7 +2680,7 @@ "Comment": "GROUP2 0xf7 /2", "ExpectedArm64ASM": [ "mov x27, x7", - "negs x26, x27", + "negs x26, x7", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "mov x7, x26", @@ -2729,9 +2718,9 @@ "ExpectedInstructionCount": 5, "Comment": "GROUP2 0xf7 /3", "ExpectedArm64ASM": [ - "mov x20, x4", - "mul x4, x7, x20", - "umulh x6, x7, x20", + "mul x20, x7, x4", + "umulh x6, x7, x4", + "mov x4, x20", "cmp x6, #0x0 (0)", "ccmn xzr, #0, #nzCV, eq" ] @@ -2818,21 +2807,20 @@ "ExpectedInstructionCount": 24, "Comment": "GROUP2 0xf7 /6", "ExpectedArm64ASM": [ - "mov x20, x4", "cbz x6, #+0x28", "mov x0, x6", - "mov x1, x20", + "mov x1, x4", "mov x2, x7", "ldr x3, [x28, #2448]", "str x30, [sp, #-16]!", "blr x3", "ldr x30, [sp], #16", - "mov x4, x0", + "mov x20, x0", "b #+0x8", - "udiv x4, x20, x7", + "udiv x20, x4, x7", "cbz x6, #+0x28", "mov x0, x6", - "mov x1, x20", + "mov x1, x4", "mov x2, x7", "ldr x3, [x28, #2464]", "str x30, [sp, #-16]!", @@ -2840,8 +2828,9 @@ "ldr x30, [sp], #16", "mov x6, x0", "b #+0xc", - "udiv x0, x20, x7", - "msub x6, x0, x7, x20" + "udiv x0, x4, x7", + "msub x6, x0, x7, x4", + "mov x4, x20" ] }, "idiv bx": { @@ -2888,25 +2877,24 @@ "ExpectedInstructionCount": 28, "Comment": "GROUP2 0xf7 /7", "ExpectedArm64ASM": [ - "mov x20, x4", - "asr x0, x20, #63", + "asr x0, x4, #63", "eor x0, x0, x6", "cbz x0, #+0x28", "mov x0, x6", - "mov x1, x20", + "mov x1, x4", "mov x2, x7", "ldr x3, [x28, #2456]", "str x30, [sp, #-16]!", "blr x3", "ldr x30, [sp], #16", - "mov x4, x0", + "mov x20, x0", "b #+0x8", - "sdiv x4, x20, x7", - "asr x0, x20, #63", + "sdiv x20, x4, x7", + "asr x0, x4, #63", "eor x0, x0, x6", "cbz x0, #+0x28", "mov x0, x6", - "mov x1, x20", + "mov x1, x4", "mov x2, x7", "ldr x3, [x28, #2472]", "str x30, [sp, #-16]!", @@ -2914,8 +2902,9 @@ "ldr x30, [sp], #16", "mov x6, x0", "b #+0xc", - "sdiv x0, x20, x7", - "msub x6, x0, x7, x20" + "sdiv x0, x4, x7", + "msub x6, x0, x7, x4", + "mov x4, x20" ] }, "inc al": { @@ -2970,9 +2959,9 @@ "ExpectedInstructionCount": 9, "Comment": "GROUP4 0xfe /0", "ExpectedArm64ASM": [ - "mov x27, x4", "cset w20, hs", - "adds w26, w27, #0x1 (1)", + "mov x27, x4", + "adds w26, w4, #0x1 (1)", "mrs x21, nzcv", "mov w0, w21", "bfi w0, w20, #29, #1", @@ -2985,9 +2974,9 @@ "ExpectedInstructionCount": 9, "Comment": "GROUP4 0xfe /0", "ExpectedArm64ASM": [ - "mov x27, x4", "cset w20, hs", - "adds x26, x27, #0x1 (1)", + "mov x27, x4", + "adds x26, x4, #0x1 (1)", "mrs x21, nzcv", "mov w0, w21", "bfi w0, w20, #29, #1", @@ -3016,9 +3005,9 @@ "ExpectedInstructionCount": 9, "Comment": "GROUP4 0xfe /1", "ExpectedArm64ASM": [ - "mov x27, x4", "cset w20, hs", - "subs w26, w27, #0x1 (1)", + "mov x27, x4", + "subs w26, w4, #0x1 (1)", "mrs x21, nzcv", "mov w0, w21", "bfi w0, w20, #29, #1", @@ -3031,9 +3020,9 @@ "ExpectedInstructionCount": 9, "Comment": "GROUP4 0xfe /1", "ExpectedArm64ASM": [ - "mov x27, x4", "cset w20, hs", - "subs x26, x27, #0x1 (1)", + "mov x27, x4", + "subs x26, x4, #0x1 (1)", "mrs x21, nzcv", "mov w0, w21", "bfi w0, w20, #29, #1", diff --git a/unittests/InstructionCountCI/Primary_32Bit.json b/unittests/InstructionCountCI/Primary_32Bit.json index cfd49ef80..d57f5ae67 100644 --- a/unittests/InstructionCountCI/Primary_32Bit.json +++ b/unittests/InstructionCountCI/Primary_32Bit.json @@ -202,9 +202,9 @@ "ExpectedInstructionCount": 9, "Comment": "0x40", "ExpectedArm64ASM": [ - "mov w27, w4", "cset w20, hs", - "adds w26, w27, #0x1 (1)", + "mov x27, x4", + "adds w26, w4, #0x1 (1)", "mrs x21, nzcv", "mov w0, w21", "bfi w0, w20, #29, #1", @@ -247,9 +247,9 @@ "ExpectedInstructionCount": 9, "Comment": "0x48", "ExpectedArm64ASM": [ - "mov w27, w4", "cset w20, hs", - "subs w26, w27, #0x1 (1)", + "mov x27, x4", + "subs w26, w4, #0x1 (1)", "mrs x21, nzcv", "mov w0, w21", "bfi w0, w20, #29, #1", diff --git a/unittests/InstructionCountCI/Secondary.json b/unittests/InstructionCountCI/Secondary.json index 75ac04d4d..0d5e5ef3a 100644 --- a/unittests/InstructionCountCI/Secondary.json +++ b/unittests/InstructionCountCI/Secondary.json @@ -1646,26 +1646,26 @@ "ExpectedInstructionCount": 20, "Comment": "0x0f 0xad", "ExpectedArm64ASM": [ - "mov x20, x4", - "and x21, x5, #0x3f", - "neg x22, x21", - "lsl x23, x20, x21", - "lsr x22, x7, x22", - "orr x22, x23, x22", - "mrs x23, nzcv", - "cmp x21, #0x0 (0)", - "csel x4, x20, x22, eq", - "msr nzcv, x23", - "cbz x21, #+0x28", - "ands x26, x4, x4", - "neg x0, x21", - "lsr x0, x20, x0", - "eor x2, x20, x4", + "and x20, x5, #0x3f", + "neg x21, x20", + "lsl x22, x4, x20", + "lsr x21, x7, x21", + "orr x21, x22, x21", + "mrs x22, nzcv", + "cmp x20, #0x0 (0)", + "csel x21, x4, x21, eq", + "msr nzcv, x22", + "cbz x20, #+0x28", + "ands x26, x21, x21", + "neg x0, x20", + "lsr x0, x4, x0", + "eor x2, x4, x21", "mrs x1, nzcv", "bfi w1, w0, #29, #1", "lsr x2, x2, #63", "bfi w1, w2, #28, #1", - "msr nzcv, x1" + "msr nzcv, x1", + "mov x4, x21" ] }, "push gs": { @@ -1972,31 +1972,30 @@ ] }, "cmpxchg rax, rbx": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 6, "Comment": "0x0f 0xb1", "ExpectedArm64ASM": [ - "mov x20, x7", "mov w27, #0x0", "subs x26, x4, x4", - "mrs x21, nzcv", - "eor w21, w21, #0x20000000", - "msr nzcv, x21", - "mov x4, x20" + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20", + "mov x4, x7" ] }, "cmpxchg [rax], rbx": { "ExpectedInstructionCount": 9, "Comment": "0x0f 0xb1", "ExpectedArm64ASM": [ - "mov x20, x4", - "mov x1, x20", - "casal x1, x7, [x20]", - "mov x4, x1", - "eor w27, w20, w4", - "subs x26, x20, x4", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20" + "mov x1, x4", + "casal x1, x7, [x4]", + "mov x20, x1", + "eor w27, w4, w20", + "subs x26, x4, x20", + "mrs x21, nzcv", + "eor w21, w21, #0x20000000", + "msr nzcv, x21", + "mov x4, x20" ] }, "btr ax, bx": { @@ -2586,13 +2585,12 @@ ] }, "xadd rax, rbx": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "0x0f 0xc1", "ExpectedArm64ASM": [ - "mov x20, x4", - "eor w27, w20, w7", - "adds x26, x20, x7", - "mov x7, x20", + "eor w27, w4, w7", + "adds x26, x4, x7", + "mov x7, x4", "mov x4, x26" ] }, @@ -2600,10 +2598,10 @@ "ExpectedInstructionCount": 4, "Comment": "0x0f 0xc1", "ExpectedArm64ASM": [ - "mov x20, x7", - "ldaddal x20, x7, [x4]", - "eor w27, w7, w20", - "adds x26, x7, x20" + "ldaddal x7, x20, [x4]", + "eor w27, w20, w7", + "adds x26, x20, x7", + "mov x7, x20" ] }, "cmpps xmm0, xmm1, 0": { diff --git a/unittests/InstructionCountCI/VEX_map1.json b/unittests/InstructionCountCI/VEX_map1.json index 012b35625..aa2edac8b 100644 --- a/unittests/InstructionCountCI/VEX_map1.json +++ b/unittests/InstructionCountCI/VEX_map1.json @@ -34,15 +34,12 @@ ] }, "vmovups ymm0, ymm0": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 0, "Comment": [ "Spurious moves", "Map 1 0b00 0x10 256-bit" ], - "ExpectedArm64ASM": [ - "mov z2.d, p7/m, z16.d", - "mov z16.d, p7/m, z2.d" - ] + "ExpectedArm64ASM": [] }, "vmovups ymm0, [rax]": { "ExpectedInstructionCount": 1, @@ -73,15 +70,12 @@ ] }, "vmovupd ymm0, ymm0": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 0, "Comment": [ "Spurious moves", "Map 1 0b01 0x10 256-bit" ], - "ExpectedArm64ASM": [ - "mov z2.d, p7/m, z16.d", - "mov z16.d, p7/m, z2.d" - ] + "ExpectedArm64ASM": [] }, "vmovupd ymm0, [rax]": { "ExpectedInstructionCount": 1, diff --git a/unittests/InstructionCountCI/VEX_map3.json b/unittests/InstructionCountCI/VEX_map3.json index 72ab72b8e..afdce6822 100644 --- a/unittests/InstructionCountCI/VEX_map3.json +++ b/unittests/InstructionCountCI/VEX_map3.json @@ -297,14 +297,11 @@ ] }, "vpblendd ymm0, ymm1, 00000000b": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 0, "Comment": [ "Map 3 0b01 0x02 256-bit" ], - "ExpectedArm64ASM": [ - "mov z2.d, p7/m, z16.d", - "mov z16.d, p7/m, z2.d" - ] + "ExpectedArm64ASM": [] }, "vpblendd ymm0, ymm1, 01010101b": { "ExpectedInstructionCount": 50, diff --git a/unittests/InstructionCountCI/x87.json b/unittests/InstructionCountCI/x87.json index dd5134818..cab4c4160 100644 --- a/unittests/InstructionCountCI/x87.json +++ b/unittests/InstructionCountCI/x87.json @@ -6781,7 +6781,7 @@ ] }, "fild dword [rax]": { - "ExpectedInstructionCount": 35, + "ExpectedInstructionCount": 34, "Comment": [ "0xdf !11b /5" ], @@ -6798,29 +6798,28 @@ "ldr w21, [x4]", "mov w22, #0x0", "sxtw x21, w21", - "mrs x22, nzcv", + "mrs x23, nzcv", "cmp x21, #0x0 (0)", - "mov w23, #0x8000", - "csel x23, x23, xzr, lt", + "mov w24, #0x8000", + "csel x24, x24, xzr, lt", "cneg x21, x21, mi", - "mov w24, #0x3f", + "mov w25, #0x3f", "mov x0, #0x3f", - "clz x25, x21", - "sub x25, x0, x25", - "sub x24, x24, x25", - "lsl x25, x21, x24", - "mov w30, #0x403e", - "sub x24, x30, x24", - "mov w30, #0x0", + "clz x30, x21", + "sub x30, x0, x30", + "sub x25, x25, x30", + "lsl x30, x21, x25", + "mov w18, #0x403e", + "sub x25, x18, x25", "cmp x21, #0x0 (0)", - "csel x21, x30, x24, eq", - "orr x21, x23, x21", - "fmov d2, x25", + "csel x21, x22, x25, eq", + "orr x21, x24, x21", + "fmov d2, x30", "fmov d3, x21", "mov v2.d[1], v3.d[0]", "add x0, x28, x20, lsl #4", "str q2, [x0, #768]", - "msr nzcv, x22" + "msr nzcv, x23" ] }, "fisttp dword [rax]": { @@ -16489,7 +16488,7 @@ ] }, "fild word [rax]": { - "ExpectedInstructionCount": 35, + "ExpectedInstructionCount": 34, "Comment": [ "0xdf !11b /0" ], @@ -16506,29 +16505,28 @@ "ldrh w21, [x4]", "mov w22, #0x0", "sxth x21, w21", - "mrs x22, nzcv", + "mrs x23, nzcv", "cmp x21, #0x0 (0)", - "mov w23, #0x8000", - "csel x23, x23, xzr, lt", + "mov w24, #0x8000", + "csel x24, x24, xzr, lt", "cneg x21, x21, mi", - "mov w24, #0x3f", + "mov w25, #0x3f", "mov x0, #0x3f", - "clz x25, x21", - "sub x25, x0, x25", - "sub x24, x24, x25", - "lsl x25, x21, x24", - "mov w30, #0x403e", - "sub x24, x30, x24", - "mov w30, #0x0", + "clz x30, x21", + "sub x30, x0, x30", + "sub x25, x25, x30", + "lsl x30, x21, x25", + "mov w18, #0x403e", + "sub x25, x18, x25", "cmp x21, #0x0 (0)", - "csel x21, x30, x24, eq", - "orr x21, x23, x21", - "fmov d2, x25", + "csel x21, x22, x25, eq", + "orr x21, x24, x21", + "fmov d2, x30", "fmov d3, x21", "mov v2.d[1], v3.d[0]", "add x0, x28, x20, lsl #4", "str q2, [x0, #768]", - "msr nzcv, x22" + "msr nzcv, x23" ] }, "fisttp word [rax]": {