From 6bc808cb066717dbafcacd4b98aa912d48ec77b0 Mon Sep 17 00:00:00 2001 From: LC Date: Wed, 15 Jul 2026 07:49:48 -0400 Subject: [PATCH] VectorOps: Add trivial case handling in VSQXTN2 Lets us generate much more optimal code in the event the destination and lower source are the same. --- FEXCore/Source/Interface/Core/JIT/VectorOps.cpp | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/FEXCore/Source/Interface/Core/JIT/VectorOps.cpp b/FEXCore/Source/Interface/Core/JIT/VectorOps.cpp index f393726d8..aa3b40848 100644 --- a/FEXCore/Source/Interface/Core/JIT/VectorOps.cpp +++ b/FEXCore/Source/Interface/Core/JIT/VectorOps.cpp @@ -3562,9 +3562,13 @@ DEF_OP(VSQXTN2) { mov(Dst.Q(), VectorLower.Q()); ins(ARMEmitter::SubRegSize::i32Bit, Dst, 1, VTMP2, 0); } else { - mov(VTMP1.Q(), VectorLower.Q()); - sqxtn2(SubRegSize, VTMP1, VectorUpper); - mov(Dst.Q(), VTMP1.Q()); + if (Dst == VectorLower) { + sqxtn2(SubRegSize, VectorLower, VectorUpper); + } else { + mov(VTMP1.Q(), VectorLower.Q()); + sqxtn2(SubRegSize, VTMP1, VectorUpper); + mov(Dst.Q(), VTMP1.Q()); + } } } }