From 34a87cc94c5914941f72ecb8fe6a099562c06c5c Mon Sep 17 00:00:00 2001 From: Justin Becker Date: Mon, 27 Jul 2026 15:48:35 -0700 Subject: [PATCH 1/2] Decoder: fix illegal LEA encoding --- .../Interface/Core/X86Tables/BaseTables.cpp | 2 +- unittests/InstructionCountCI/Primary.json | 15 +++++++++++++++ 2 files changed, 16 insertions(+), 1 deletion(-) diff --git a/FEXCore/Source/Interface/Core/X86Tables/BaseTables.cpp b/FEXCore/Source/Interface/Core/X86Tables/BaseTables.cpp index 53ae7e273..d943809bb 100644 --- a/FEXCore/Source/Interface/Core/X86Tables/BaseTables.cpp +++ b/FEXCore/Source/Interface/Core/X86Tables/BaseTables.cpp @@ -318,7 +318,7 @@ const std::array BaseOps = []() consteval { {0x8A, 1, X86InstInfo{"MOV", TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_MODRM, 0}}, {0x8B, 1, X86InstInfo{"MOV", TYPE_INST, FLAGS_MODRM, 0}}, {0x8C, 1, X86InstInfo{"MOV", TYPE_INST, GenFlagsSrcSize(SIZE_16BIT) | FLAGS_MODRM | FLAGS_SF_MOD_DST, 0}}, - {0x8D, 1, X86InstInfo{"LEA", TYPE_INST, GenFlagsSameSize(SIZE_64BITDEF) | FLAGS_MODRM, 0}}, + {0x8D, 1, X86InstInfo{"LEA", TYPE_INST, GenFlagsSameSize(SIZE_64BITDEF) | FLAGS_MODRM | FLAGS_SF_MOD_MEM_ONLY, 0}}, {0x8E, 1, X86InstInfo{"MOV", TYPE_INST, GenFlagsSameSize(SIZE_16BIT) | FLAGS_MODRM, 0}}, {0x8F, 1, X86InstInfo{"POP", TYPE_INST, GenFlagsSameSize(SIZE_64BITDEF) | FLAGS_MODRM | FLAGS_SF_MOD_DST | FLAGS_SF_MOD_ZERO_REG | FLAGS_DEBUG_MEM_ACCESS, 0}}, {0x90, 8, X86InstInfo{"XCHG", TYPE_INST, FLAGS_SF_REX_IN_BYTE | FLAGS_SF_SRC_RAX, 0}}, diff --git a/unittests/InstructionCountCI/Primary.json b/unittests/InstructionCountCI/Primary.json index c98c8ada8..b312846ea 100644 --- a/unittests/InstructionCountCI/Primary.json +++ b/unittests/InstructionCountCI/Primary.json @@ -2461,6 +2461,21 @@ "mov w4, w20" ] }, + "db 0x48, 0x8D, 0xC0": { + "ExpectedInstructionCount": 6, + "Comment": [ + "0x8d", + "LEA rax, rax illegal register to register encoding" + ], + "ExpectedArm64ASM": [ + "mov w20, #0x10000", + "str x20, [x28, #24]", + "mov w0, #0x401", + "str x0, [x28, #1496]", + "ldr x0, [x28, #2968]", + "br x0" + ] + }, "mov cs, ax": { "ExpectedInstructionCount": 4, "Skip": "Yes", From c156498c5c02d0b07328f2e26b18ee13ed1ac59c Mon Sep 17 00:00:00 2001 From: Justin Becker Date: Tue, 11 Aug 2026 16:19:49 -0700 Subject: [PATCH 2/2] Add 16 bit and 32 bit variants --- unittests/InstructionCountCI/Primary.json | 30 +++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/unittests/InstructionCountCI/Primary.json b/unittests/InstructionCountCI/Primary.json index b312846ea..7267b3e79 100644 --- a/unittests/InstructionCountCI/Primary.json +++ b/unittests/InstructionCountCI/Primary.json @@ -2461,6 +2461,36 @@ "mov w4, w20" ] }, + "db 0x66, 0x8D, 0xC0": { + "ExpectedInstructionCount": 6, + "Comment": [ + "0x8d", + "LEA ax, ax illegal register to register encoding" + ], + "ExpectedArm64ASM": [ + "mov w20, #0x10000", + "str x20, [x28, #24]", + "mov w0, #0x401", + "str x0, [x28, #1496]", + "ldr x0, [x28, #2968]", + "br x0" + ] + }, + "db 0x8D, 0xC0": { + "ExpectedInstructionCount": 6, + "Comment": [ + "0x8d", + "LEA eax, eax illegal register to register encoding" + ], + "ExpectedArm64ASM": [ + "mov w20, #0x10000", + "str x20, [x28, #24]", + "mov w0, #0x401", + "str x0, [x28, #1496]", + "ldr x0, [x28, #2968]", + "br x0" + ] + }, "db 0x48, 0x8D, 0xC0": { "ExpectedInstructionCount": 6, "Comment": [