steam-frame/FEX-Emu--FEX
1
0 Fork 0
mirror of https://github.com/FEX-Emu/FEX.git synced 2026-10-14 09:00:40 +02:00
Code Issues Packages Projects Releases 67 Wiki Activity

IR: specify registers, not offsets for SRA

Browse Source 
SRA is fundamentally about hardware registers, not stores into a
software-defined context. So, it should take a register instead of an offset.
This makes all the unaligned special cases unrepresentable (by design).

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
This commit is contained in:
Alyssa Rosenzweig committed 2024-05-08 14:01:42 -04:00
1 parent 1848629ba5
commit a2fc51fc7b
10 files changed
+99 -148
Download Patch File Download Diff File Expand all files Collapse all files

No files matched your search

FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
+8 -15
View File
@@ -3396,8 +3396,8 @@ void OpDispatchBuilder::CMPSOp(OpcodeArgs) {
auto Src2 = _LoadMem(GPRClass, Size, Dest_RSI, Size);
// We'll calculate PF/AF after the loop, so use them as temporaries here.
_StoreRegister(Src1, offsetof(FEXCore::Core::CPUState, pf_raw), GPRClass, CTX->GetGPRSize());
_StoreRegister(Src2, offsetof(FEXCore::Core::CPUState, af_raw), GPRClass, CTX->GetGPRSize());
_StoreRegister(Src1, Core::CPUState::PF_AS_GREG, GPRClass, CTX->GetGPRSize());
_StoreRegister(Src2, Core::CPUState::AF_AS_GREG, GPRClass, CTX->GetGPRSize());
OrderedNode* TailCounter = LoadGPRRegister(X86State::REG_RCX);
@@ -3436,8 +3436,8 @@ void OpDispatchBuilder::CMPSOp(OpcodeArgs) {
// Make sure to start a new block after ending this one
{
// Grab the sources from the last iteration so we can set flags.
auto Src1 = _LoadRegister(offsetof(FEXCore::Core::CPUState, pf_raw), GPRClass, CTX->GetGPRSize());
auto Src2 = _LoadRegister(offsetof(FEXCore::Core::CPUState, af_raw), GPRClass, CTX->GetGPRSize());
auto Src1 = _LoadRegister(Core::CPUState::PF_AS_GREG, GPRClass, CTX->GetGPRSize());
auto Src2 = _LoadRegister(Core::CPUState::AF_AS_GREG, GPRClass, CTX->GetGPRSize());
GenerateFlags_SUB(Op, Src2, Src1);
CalculateDeferredFlags();
}
@@ -4406,7 +4406,7 @@ OrderedNode* OpDispatchBuilder::LoadGPRRegister(uint32_t GPR, int8_t Size, uint8
if (Size == -1) {
Size = GPRSize;
}
OrderedNode* Reg = _LoadRegister(offsetof(FEXCore::Core::CPUState, gregs[GPR]), GPRClass, GPRSize);
OrderedNode* Reg = _LoadRegister(GPR, GPRClass, GPRSize);
if ((!AllowUpperGarbage && (Size != GPRSize)) || Offset != 0) {
// Extract the subregister if requested.
@@ -4422,11 +4422,7 @@ OrderedNode* OpDispatchBuilder::LoadGPRRegister(uint32_t GPR, int8_t Size, uint8
OrderedNode* OpDispatchBuilder::LoadXMMRegister(uint32_t XMM) {
const auto VectorSize = CTX->HostFeatures.SupportsAVX ? 32 : 16;
const auto VectorOffset =
CTX->HostFeatures.SupportsAVX ? offsetof(Core::CPUState, xmm.avx.data[XMM][0]) : offsetof(Core::CPUState, xmm.sse.data[XMM][0]);
OrderedNode* Reg = _LoadRegister(VectorOffset, FPRClass, VectorSize);
return Reg;
return _LoadRegister(XMM, FPRClass, VectorSize);
}
void OpDispatchBuilder::StoreGPRRegister(uint32_t GPR, OrderedNode* const Src, int8_t Size, uint8_t Offset) {
@@ -4442,15 +4438,12 @@ void OpDispatchBuilder::StoreGPRRegister(uint32_t GPR, OrderedNode* const Src, i
Reg = _Bfi(IR::SizeToOpSize(GPRSize), Size * 8, Offset, Reg, Src);
}
_StoreRegister(Reg, offsetof(FEXCore::Core::CPUState, gregs[GPR]), GPRClass, GPRSize);
_StoreRegister(Reg, GPR, GPRClass, GPRSize);
}
void OpDispatchBuilder::StoreXMMRegister(uint32_t XMM, OrderedNode* const Src) {
const auto VectorSize = CTX->HostFeatures.SupportsAVX ? 32 : 16;
const auto VectorOffset =
CTX->HostFeatures.SupportsAVX ? offsetof(Core::CPUState, xmm.avx.data[XMM][0]) : offsetof(Core::CPUState, xmm.sse.data[XMM][0]);
_StoreRegister(Src, VectorOffset, FPRClass, VectorSize);
_StoreRegister(Src, XMM, FPRClass, VectorSize);
}
OrderedNode* OpDispatchBuilder::LoadSource(RegisterClassType Class, const X86Tables::DecodedOp& Op,