From a1d1674033ea6611061b07935fb72820060a0be0 Mon Sep 17 00:00:00 2001 From: lioncash Date: Fri, 26 Nov 2021 11:24:15 -0500 Subject: [PATCH] RegisterAllocatorPass: Convert macro functions into concrete ones Gets rid of some preprocessor leakage across the file and makes the functions more statically typed. --- .../IR/Passes/RegisterAllocationPass.cpp | 42 +++++++++++-------- 1 file changed, 25 insertions(+), 17 deletions(-) diff --git a/External/FEXCore/Source/Interface/IR/Passes/RegisterAllocationPass.cpp b/External/FEXCore/Source/Interface/IR/Passes/RegisterAllocationPass.cpp index 49fc1754b..8e611037b 100644 --- a/External/FEXCore/Source/Interface/IR/Passes/RegisterAllocationPass.cpp +++ b/External/FEXCore/Source/Interface/IR/Passes/RegisterAllocationPass.cpp @@ -279,15 +279,12 @@ namespace { */ RegisterAllocationData* GetAllocationData() override; std::unique_ptr PullAllocationData() override; + private: + using BlockInterferences = std::vector; + uint32_t SpillPointId; - #define INFO_MAKE(id, Class) ((id) | (Class << 24)) - - #define INFO_IDCLASS(info) (info & 0xffff'ffff) - #define INFO_ID(info) (info & 0xff'ffff) - #define INFO_CLASS(info) (info & 0xff00'0000) - std::vector> SpanStart; std::vector> SpanEnd; @@ -295,15 +292,26 @@ namespace { FEXCore::IR::Pass* CompactionPass; bool OptimizeSRA; - void SpillOne(FEXCore::IR::IREmitter *IREmit); - std::vector LiveRanges; - using BlockInterferences = std::vector; - std::unordered_map LocalBlockInterferences; BlockInterferences GlobalBlockInterferences; + [[nodiscard]] static constexpr uint32_t InfoMake(uint32_t id, uint32_t Class) { + return id | (Class << 24); + } + [[nodiscard]] static constexpr uint32_t InfoIDClass(uint32_t info) { + return info & 0xffff'ffff; + } + [[nodiscard]] static constexpr uint32_t InfoID(uint32_t info) { + return info & 0xff'ffff; + } + [[nodiscard]] static constexpr uint32_t InfoClass(uint32_t info) { + return info & 0xff00'0000; + } + + void SpillOne(FEXCore::IR::IREmitter *IREmit); + void CalculateLiveRange(FEXCore::IR::IRListView *IR); void OptimizeStaticRegisters(FEXCore::IR::IRListView *IR); void CalculateBlockInterferences(FEXCore::IR::IRListView *IR); @@ -880,9 +888,9 @@ namespace { if (NodeLiveRange.Begin != ~0U) { LOGMAN_THROW_A_FMT(NodeLiveRange.Begin < NodeLiveRange.End , "Span must Begin before Ending"); - auto Class = GetClass(Graph->AllocData->Map[i]); - SpanStart[NodeLiveRange.Begin].Append(INFO_MAKE(i, Class)); - SpanEnd[NodeLiveRange.End] .Append(INFO_MAKE(i, Class)); + const auto Class = GetClass(Graph->AllocData->Map[i]); + SpanStart[NodeLiveRange.Begin].Append(InfoMake(i, Class)); + SpanEnd[NodeLiveRange.End] .Append(InfoMake(i, Class)); } } @@ -890,16 +898,16 @@ namespace { for (int OpNodeId = 0; OpNodeId < IR->GetSSACount(); OpNodeId++) { // Expire end intervals first SpanEnd[OpNodeId].Iterate([&](uint32_t EdgeInfo) { - Active.Erase(INFO_IDCLASS(EdgeInfo)); + Active.Erase(InfoIDClass(EdgeInfo)); }); // Add starting invervals SpanStart[OpNodeId].Iterate([&](uint32_t EdgeInfo) { // Starts here Active.Iterate([&](uint32_t ActiveInfo) { - if (INFO_CLASS(ActiveInfo) == INFO_CLASS(EdgeInfo)) { - AddInterference(INFO_ID(ActiveInfo), INFO_ID(EdgeInfo)); - AddInterference(INFO_ID(EdgeInfo), INFO_ID(ActiveInfo)); + if (InfoClass(ActiveInfo) == InfoClass(EdgeInfo)) { + AddInterference(InfoID(ActiveInfo), InfoID(EdgeInfo)); + AddInterference(InfoID(EdgeInfo), InfoID(ActiveInfo)); } }); Active.Append(EdgeInfo);