diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp
index 5be9b8459..8889eb907 100644
--- a/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp
+++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp
@@ -2066,26 +2066,17 @@ void OpDispatchBuilder::PINSROp(OpcodeArgs, IR::OpSize ElementSize) {
 
 void OpDispatchBuilder::VPINSRBOp(OpcodeArgs) {
   Ref Result = PINSROpImpl(Op, OpSize::i8Bit, Op->Src[0], Op->Src[1], Op->Src[2]);
-  if (Op->Dest.Data.GPR.GPR == Op->Src[0].Data.GPR.GPR) {
-    Result = _VMov(OpSize::i128Bit, Result);
-  }
   StoreResultFPR(Op, Result);
 }
 
 void OpDispatchBuilder::VPINSRDQOp(OpcodeArgs) {
   const auto SrcSize = OpSizeFromSrc(Op);
   Ref Result = PINSROpImpl(Op, SrcSize, Op->Src[0], Op->Src[1], Op->Src[2]);
-  if (Op->Dest.Data.GPR.GPR == Op->Src[0].Data.GPR.GPR) {
-    Result = _VMov(OpSize::i128Bit, Result);
-  }
   StoreResultFPR(Op, Result);
 }
 
 void OpDispatchBuilder::VPINSRWOp(OpcodeArgs) {
   Ref Result = PINSROpImpl(Op, OpSize::i16Bit, Op->Src[0], Op->Src[1], Op->Src[2]);
-  if (Op->Dest.Data.GPR.GPR == Op->Src[0].Data.GPR.GPR) {
-    Result = _VMov(OpSize::i128Bit, Result);
-  }
   StoreResultFPR(Op, Result);
 }
 
diff --git a/unittests/InstructionCountCI/VEX_map1.json b/unittests/InstructionCountCI/VEX_map1.json
index e7ab79494..1f4e8d239 100644
--- a/unittests/InstructionCountCI/VEX_map1.json
+++ b/unittests/InstructionCountCI/VEX_map1.json
@@ -2615,14 +2615,12 @@
       ]
     },
     "vpinsrw xmm0, xmm0, eax, 000b": {
-      "ExpectedInstructionCount": 3,
+      "ExpectedInstructionCount": 1,
       "Comment": [
         "Map 1 0b01 0xC4 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov v2.16b, v16.16b",
-        "mov v2.h[0], w4",
-        "mov v16.16b, v2.16b"
+        "mov v16.h[0], w4"
       ]
     },
     "vpinsrw xmm0, xmm1, eax, 000b": {
diff --git a/unittests/InstructionCountCI/VEX_map3.json b/unittests/InstructionCountCI/VEX_map3.json
index 0372c517d..21d03beda 100644
--- a/unittests/InstructionCountCI/VEX_map3.json
+++ b/unittests/InstructionCountCI/VEX_map3.json
@@ -3714,14 +3714,12 @@
       ]
     },
     "vpinsrb xmm0, xmm0, eax, 0": {
-      "ExpectedInstructionCount": 3,
+      "ExpectedInstructionCount": 1,
       "Comment": [
         "Map 3 0b01 0x20 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov v2.16b, v16.16b",
-        "mov v2.b[0], w4",
-        "mov v16.16b, v2.16b"
+        "mov v16.b[0], w4"
       ]
     },
     "vpinsrb xmm0, xmm1, eax, 0": {
@@ -3774,14 +3772,12 @@
       ]
     },
     "vpinsrd xmm0, xmm0, eax, 0": {
-      "ExpectedInstructionCount": 3,
+      "ExpectedInstructionCount": 1,
       "Comment": [
         "Map 3 0b01 0x22 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov v2.16b, v16.16b",
-        "mov v2.s[0], w4",
-        "mov v16.16b, v2.16b"
+        "mov v16.s[0], w4"
       ]
     },
     "vpinsrd xmm0, xmm1, eax, 0": {
@@ -3805,14 +3801,12 @@
       ]
     },
     "vpinsrq xmm0, xmm0, rax, 0": {
-      "ExpectedInstructionCount": 3,
+      "ExpectedInstructionCount": 1,
       "Comment": [
         "Map 3 0b01 0x22 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov v2.16b, v16.16b",
-        "mov v2.d[0], x4",
-        "mov v16.16b, v2.16b"
+        "mov v16.d[0], x4"
       ]
     },
     "vpinsrq xmm0, xmm1, rax, 0": {