diff --git a/unittests/InstructionCountCI/FlagM/Atomics.json b/unittests/InstructionCountCI/FlagM/Atomics.json new file mode 100644 index 000000000..e516f6a8c --- /dev/null +++ b/unittests/InstructionCountCI/FlagM/Atomics.json @@ -0,0 +1,2299 @@ +{ + "Features": { + "Bitness": 64, + "EnabledHostFeatures": [ + "FLAGM", + "FLAGM2" + ], + "DisabledHostFeatures": [ + "SVE128", + "SVE256" + ] + }, + "Instructions": { + "lock add byte [rax], cl": { + "ExpectedInstructionCount": 17, + "Optimal": "No", + "Comment": "0x00", + "ExpectedArm64ASM": [ + "uxtb w20, w5", + "ldaddalb w20, w21, [x4]", + "add w22, w21, w20", + "eor w23, w21, w20", + "strb w23, [x28, #708]", + "strb w22, [x28, #706]", + "lsl w23, w22, #24", + "tst w23, w23", + "mrs x23, nzcv", + "ubfx w24, w22, #8, #1", + "orr w23, w23, w24, lsl #29", + "eor w20, w21, w20", + "eor w21, w22, w21", + "bic w20, w21, w20", + "ubfx w20, w20, #7, #1", + "orr w20, w23, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "lock add word [rax], cx": { + "ExpectedInstructionCount": 17, + "Optimal": "No", + "Comment": "0x01", + "ExpectedArm64ASM": [ + "uxth w20, w5", + "ldaddalh w20, w21, [x4]", + "add w22, w21, w20", + "eor w23, w21, w20", + "strb w23, [x28, #708]", + "strb w22, [x28, #706]", + "lsl w23, w22, #16", + "tst w23, w23", + "mrs x23, nzcv", + "ubfx w24, w22, #16, #1", + "orr w23, w23, w24, lsl #29", + "eor w20, w21, w20", + "eor w21, w22, w21", + "bic w20, w21, w20", + "ubfx w20, w20, #15, #1", + "orr w20, w23, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "lock add dword [rax], ecx": { + "ExpectedInstructionCount": 9, + "Optimal": "No", + "Comment": "0x01", + "ExpectedArm64ASM": [ + "mov w20, w5", + "ldaddal w20, w21, [x4]", + "add w22, w21, w20", + "eor w23, w21, w20", + "strb w23, [x28, #708]", + "strb w22, [x28, #706]", + "cmn w21, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "lock or byte [rax], cl": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": "0x08", + "ExpectedArm64ASM": [ + "ldsetalb w5, w20, [x4]", + "orr w20, w20, w5", + "strb w20, [x28, #706]", + "lsl w20, w20, #24", + "tst w20, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "lock or word [rax], cx": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": "0x09", + "ExpectedArm64ASM": [ + "ldsetalh w5, w20, [x4]", + "orr w20, w20, w5", + "strb w20, [x28, #706]", + "lsl w20, w20, #16", + "tst w20, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "lock or dword [rax], ecx": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": "0x09", + "ExpectedArm64ASM": [ + "ldsetal w5, w20, [x4]", + "orr w20, w20, w5", + "strb w20, [x28, #706]", + "tst w20, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "lock adc byte [rax], cl": { + "ExpectedInstructionCount": 26, + "Optimal": "No", + "Comment": "0x10", + "ExpectedArm64ASM": [ + "uxtb w20, w5", + "ldr w21, [x28, #728]", + "ubfx w21, w21, #29, #1", + "add w22, w20, w21", + "ldaddalb w22, w23, [x4]", + "add w22, w23, w22", + "uxtb w22, w22", + "eor w24, w23, w20", + "strb w24, [x28, #708]", + "strb w22, [x28, #706]", + "lsl w24, w22, #24", + "tst w24, w24", + "mrs x24, nzcv", + "cmp w22, w20", + "cset x25, lo", + "cmp w22, w20", + "cset x26, ls", + "cmp x21, #0x1 (1)", + "csel x21, x26, x25, eq", + "orr w21, w24, w21, lsl #29", + "eor w20, w23, w20", + "eor w22, w22, w23", + "bic w20, w22, w20", + "ubfx w20, w20, #7, #1", + "orr w20, w21, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "lock adc word [rax], cx": { + "ExpectedInstructionCount": 26, + "Optimal": "No", + "Comment": "0x11", + "ExpectedArm64ASM": [ + "uxth w20, w5", + "ldr w21, [x28, #728]", + "ubfx w21, w21, #29, #1", + "add w22, w20, w21", + "ldaddalh w22, w23, [x4]", + "add w22, w23, w22", + "uxth w22, w22", + "eor w24, w23, w20", + "strb w24, [x28, #708]", + "strb w22, [x28, #706]", + "lsl w24, w22, #16", + "tst w24, w24", + "mrs x24, nzcv", + "cmp w22, w20", + "cset x25, lo", + "cmp w22, w20", + "cset x26, ls", + "cmp x21, #0x1 (1)", + "csel x21, x26, x25, eq", + "orr w21, w24, w21, lsl #29", + "eor w20, w23, w20", + "eor w22, w22, w23", + "bic w20, w22, w20", + "ubfx w20, w20, #15, #1", + "orr w20, w21, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "lock adc dword [rax], ecx": { + "ExpectedInstructionCount": 13, + "Optimal": "No", + "Comment": "0x11", + "ExpectedArm64ASM": [ + "mov w20, w5", + "ldr w21, [x28, #728]", + "ubfx w22, w21, #29, #1", + "add w22, w20, w22", + "ldaddal w22, w23, [x4]", + "add w22, w23, w22", + "eor w24, w23, w20", + "strb w24, [x28, #708]", + "strb w22, [x28, #706]", + "msr nzcv, x21", + "adcs wzr, w23, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "lock sbb byte [rax], cl": { + "ExpectedInstructionCount": 27, + "Optimal": "No", + "Comment": "0x18", + "ExpectedArm64ASM": [ + "uxtb w20, w5", + "ldr w21, [x28, #728]", + "ubfx w21, w21, #29, #1", + "add w22, w20, w21", + "neg w1, w22", + "ldaddalb w1, w23, [x4]", + "sub w22, w23, w22", + "uxtb w22, w22", + "eor w24, w23, w20", + "strb w24, [x28, #708]", + "strb w22, [x28, #706]", + "lsl w24, w22, #24", + "tst w24, w24", + "mrs x24, nzcv", + "cmp w22, w23", + "cset x25, hi", + "cmp w22, w23", + "cset x26, hs", + "cmp x21, #0x1 (1)", + "csel x21, x26, x25, eq", + "orr w21, w24, w21, lsl #29", + "eor w20, w23, w20", + "eor w22, w22, w23", + "and w20, w22, w20", + "ubfx w20, w20, #7, #1", + "orr w20, w21, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "lock sbb word [rax], cx": { + "ExpectedInstructionCount": 27, + "Optimal": "No", + "Comment": "0x19", + "ExpectedArm64ASM": [ + "uxth w20, w5", + "ldr w21, [x28, #728]", + "ubfx w21, w21, #29, #1", + "add w22, w20, w21", + "neg w1, w22", + "ldaddalh w1, w23, [x4]", + "sub w22, w23, w22", + "uxth w22, w22", + "eor w24, w23, w20", + "strb w24, [x28, #708]", + "strb w22, [x28, #706]", + "lsl w24, w22, #16", + "tst w24, w24", + "mrs x24, nzcv", + "cmp w22, w23", + "cset x25, hi", + "cmp w22, w23", + "cset x26, hs", + "cmp x21, #0x1 (1)", + "csel x21, x26, x25, eq", + "orr w21, w24, w21, lsl #29", + "eor w20, w23, w20", + "eor w22, w22, w23", + "and w20, w22, w20", + "ubfx w20, w20, #15, #1", + "orr w20, w21, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "lock sbb dword [rax], ecx": { + "ExpectedInstructionCount": 16, + "Optimal": "No", + "Comment": "0x19", + "ExpectedArm64ASM": [ + "mov w20, w5", + "ldr w21, [x28, #728]", + "ubfx w22, w21, #29, #1", + "add w22, w20, w22", + "neg w1, w22", + "ldaddal w1, w23, [x4]", + "sub w22, w23, w22", + "eor w24, w23, w20", + "strb w24, [x28, #708]", + "strb w22, [x28, #706]", + "eor w0, w21, #0x20000000", + "msr nzcv, x0", + "sbcs wzr, w23, w20", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "str w20, [x28, #728]" + ] + }, + "lock and byte [rax], cl": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": "0x20", + "ExpectedArm64ASM": [ + "mvn w1, w5", + "ldclralb w1, w20, [x4]", + "and w20, w20, w5", + "strb w20, [x28, #706]", + "lsl w20, w20, #24", + "tst w20, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "lock and word [rax], cx": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": "0x21", + "ExpectedArm64ASM": [ + "mvn w1, w5", + "ldclralh w1, w20, [x4]", + "and w20, w20, w5", + "strb w20, [x28, #706]", + "lsl w20, w20, #16", + "tst w20, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "lock and dword [rax], ecx": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": "0x21", + "ExpectedArm64ASM": [ + "mvn w1, w5", + "ldclral w1, w20, [x4]", + "and w20, w20, w5", + "strb w20, [x28, #706]", + "tst w20, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "lock sub byte [rax], cl": { + "ExpectedInstructionCount": 18, + "Optimal": "No", + "Comment": "0x28", + "ExpectedArm64ASM": [ + "uxtb w20, w5", + "neg w1, w20", + "ldaddalb w1, w21, [x4]", + "sub w22, w21, w20", + "eor w23, w21, w20", + "strb w23, [x28, #708]", + "strb w22, [x28, #706]", + "lsl w23, w22, #24", + "tst w23, w23", + "mrs x23, nzcv", + "ubfx w24, w22, #8, #1", + "orr w23, w23, w24, lsl #29", + "eor w20, w21, w20", + "eor w21, w22, w21", + "and w20, w21, w20", + "ubfx w20, w20, #7, #1", + "orr w20, w23, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "lock sub word [rax], cx": { + "ExpectedInstructionCount": 18, + "Optimal": "No", + "Comment": "0x28", + "ExpectedArm64ASM": [ + "uxth w20, w5", + "neg w1, w20", + "ldaddalh w1, w21, [x4]", + "sub w22, w21, w20", + "eor w23, w21, w20", + "strb w23, [x28, #708]", + "strb w22, [x28, #706]", + "lsl w23, w22, #16", + "tst w23, w23", + "mrs x23, nzcv", + "ubfx w24, w22, #16, #1", + "orr w23, w23, w24, lsl #29", + "eor w20, w21, w20", + "eor w21, w22, w21", + "and w20, w21, w20", + "ubfx w20, w20, #15, #1", + "orr w20, w23, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "lock sub dword [rax], ecx": { + "ExpectedInstructionCount": 11, + "Optimal": "No", + "Comment": "0x29", + "ExpectedArm64ASM": [ + "mov w20, w5", + "neg w1, w20", + "ldaddal w1, w21, [x4]", + "sub w22, w21, w20", + "eor w23, w21, w20", + "strb w23, [x28, #708]", + "strb w22, [x28, #706]", + "cmp w21, w20", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "str w20, [x28, #728]" + ] + }, + "lock xor byte [rax], cl": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": "0x30", + "ExpectedArm64ASM": [ + "ldeoralb w5, w20, [x4]", + "eor w20, w20, w5", + "strb w20, [x28, #706]", + "lsl w20, w20, #24", + "tst w20, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "lock xor word [rax], cx": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": "0x31", + "ExpectedArm64ASM": [ + "ldeoralh w5, w20, [x4]", + "eor w20, w20, w5", + "strb w20, [x28, #706]", + "lsl w20, w20, #16", + "tst w20, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "lock xor dword [rax], ecx": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": "0x31", + "ExpectedArm64ASM": [ + "ldeoral w5, w20, [x4]", + "eor w20, w20, w5", + "strb w20, [x28, #706]", + "tst w20, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "lock add qword [rax], rcx": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": "0x01", + "ExpectedArm64ASM": [ + "ldaddal x5, x20, [x4]", + "add x21, x20, x5", + "eor x22, x20, x5", + "strb w22, [x28, #708]", + "strb w21, [x28, #706]", + "cmn x20, x5", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "xadd byte [rax], bl": { + "ExpectedInstructionCount": 18, + "Optimal": "No", + "Comment": "0x0f 0xc0", + "ExpectedArm64ASM": [ + "uxtb w20, w7", + "ldaddalb w20, w21, [x4]", + "bfxil x7, x21, #0, #8", + "add w22, w21, w20", + "eor w23, w21, w20", + "strb w23, [x28, #708]", + "strb w22, [x28, #706]", + "lsl w23, w22, #24", + "tst w23, w23", + "mrs x23, nzcv", + "ubfx w24, w22, #8, #1", + "orr w23, w23, w24, lsl #29", + "eor w20, w21, w20", + "eor w21, w22, w21", + "bic w20, w21, w20", + "ubfx w20, w20, #7, #1", + "orr w20, w23, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "xadd word [rax], bx": { + "ExpectedInstructionCount": 18, + "Optimal": "No", + "Comment": "0x0f 0xc1", + "ExpectedArm64ASM": [ + "uxth w20, w7", + "ldaddalh w20, w21, [x4]", + "bfxil x7, x21, #0, #16", + "add w22, w21, w20", + "eor w23, w21, w20", + "strb w23, [x28, #708]", + "strb w22, [x28, #706]", + "lsl w23, w22, #16", + "tst w23, w23", + "mrs x23, nzcv", + "ubfx w24, w22, #16, #1", + "orr w23, w23, w24, lsl #29", + "eor w20, w21, w20", + "eor w21, w22, w21", + "bic w20, w21, w20", + "ubfx w20, w20, #15, #1", + "orr w20, w23, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "xadd dword [rax], ebx": { + "ExpectedInstructionCount": 9, + "Optimal": "No", + "Comment": "0x0f 0xc1", + "ExpectedArm64ASM": [ + "mov w20, w7", + "ldaddal w20, w7, [x4]", + "add w21, w7, w20", + "eor w22, w7, w20", + "strb w22, [x28, #708]", + "strb w21, [x28, #706]", + "cmn w7, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "xadd qword [rax], rbx": { + "ExpectedInstructionCount": 9, + "Optimal": "No", + "Comment": "0x0f 0xc1", + "ExpectedArm64ASM": [ + "mov x20, x7", + "ldaddal x20, x7, [x4]", + "add x21, x7, x20", + "eor x22, x7, x20", + "strb w22, [x28, #708]", + "strb w21, [x28, #706]", + "cmn x7, x20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "lock add byte [rax], 1": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": "GROUP1 0x80 /0", + "ExpectedArm64ASM": [ + "mov w20, #0x1", + "ldaddalb w20, w20, [x4]", + "add w21, w20, #0x1 (1)", + "strb w20, [x28, #708]", + "strb w21, [x28, #706]", + "lsl w22, w21, #24", + "tst w22, w22", + "mrs x22, nzcv", + "ubfx w23, w21, #8, #1", + "orr w22, w22, w23, lsl #29", + "bic w20, w21, w20", + "ubfx w20, w20, #7, #1", + "orr w20, w22, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "lock add byte [rax], 0xFF": { + "ExpectedInstructionCount": 15, + "Optimal": "No", + "Comment": "GROUP1 0x80 /0", + "ExpectedArm64ASM": [ + "mov w20, #0xff", + "ldaddalb w20, w20, [x4]", + "add w21, w20, #0xff (255)", + "eor w22, w20, #0xff", + "strb w22, [x28, #708]", + "strb w21, [x28, #706]", + "lsl w22, w21, #24", + "tst w22, w22", + "mrs x22, nzcv", + "ubfx w23, w21, #8, #1", + "orr w22, w22, w23, lsl #29", + "bic w20, w20, w21", + "ubfx w20, w20, #7, #1", + "orr w20, w22, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "lock add word [rax], 0x100": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": "GROUP1 0x81 /0", + "ExpectedArm64ASM": [ + "mov w20, #0x100", + "ldaddalh w20, w20, [x4]", + "add w21, w20, #0x100 (256)", + "strb w20, [x28, #708]", + "strb w21, [x28, #706]", + "lsl w22, w21, #16", + "tst w22, w22", + "mrs x22, nzcv", + "ubfx w23, w21, #16, #1", + "orr w22, w22, w23, lsl #29", + "bic w20, w21, w20", + "ubfx w20, w20, #15, #1", + "orr w20, w22, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "lock add word [rax], 0xFFFF": { + "ExpectedInstructionCount": 15, + "Optimal": "No", + "Comment": "GROUP1 0x81 /0", + "ExpectedArm64ASM": [ + "mov w20, #0xffff", + "ldaddalh w20, w21, [x4]", + "add w20, w21, w20", + "eor w22, w21, #0xffff", + "strb w22, [x28, #708]", + "strb w20, [x28, #706]", + "lsl w22, w20, #16", + "tst w22, w22", + "mrs x22, nzcv", + "ubfx w23, w20, #16, #1", + "orr w22, w22, w23, lsl #29", + "bic w20, w21, w20", + "ubfx w20, w20, #15, #1", + "orr w20, w22, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "lock add dword [rax], 0x100": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": "GROUP1 0x81 /0", + "ExpectedArm64ASM": [ + "mov w20, #0x100", + "ldaddal w20, w20, [x4]", + "add w21, w20, #0x100 (256)", + "strb w20, [x28, #708]", + "strb w21, [x28, #706]", + "cmn w20, #0x100 (256)", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "lock add dword [rax], 0xFFFFFFFF": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": "GROUP1 0x81 /0", + "ExpectedArm64ASM": [ + "mov w20, #0xffff", + "movk w20, #0xffff, lsl #16", + "ldaddal w20, w21, [x4]", + "add w22, w21, w20", + "eor w23, w21, w20", + "strb w23, [x28, #708]", + "strb w22, [x28, #706]", + "cmn w21, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "lock add qword [rax], 0x100": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": "GROUP1 0x81 /0", + "ExpectedArm64ASM": [ + "mov w20, #0x100", + "ldaddal x20, x20, [x4]", + "add x21, x20, #0x100 (256)", + "strb w20, [x28, #708]", + "strb w21, [x28, #706]", + "cmn x20, #0x100 (256)", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "lock add qword [rax], -2147483647": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": "GROUP1 0x81 /0", + "ExpectedArm64ASM": [ + "mov x20, #0xffffffff80000001", + "ldaddal x20, x21, [x4]", + "add x22, x21, x20", + "strb w21, [x28, #708]", + "strb w22, [x28, #706]", + "cmn x21, x20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "lock add word [rax], 1": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": "GROUP1 0x83 /0", + "ExpectedArm64ASM": [ + "mov w20, #0x1", + "ldaddalh w20, w20, [x4]", + "add w21, w20, #0x1 (1)", + "strb w20, [x28, #708]", + "strb w21, [x28, #706]", + "lsl w22, w21, #16", + "tst w22, w22", + "mrs x22, nzcv", + "ubfx w23, w21, #16, #1", + "orr w22, w22, w23, lsl #29", + "bic w20, w21, w20", + "ubfx w20, w20, #15, #1", + "orr w20, w22, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "lock add dword [rax], 1": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": "GROUP1 0x83 /0", + "ExpectedArm64ASM": [ + "mov w20, #0x1", + "ldaddal w20, w20, [x4]", + "add w21, w20, #0x1 (1)", + "strb w20, [x28, #708]", + "strb w21, [x28, #706]", + "cmn w20, #0x1 (1)", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "lock add qword [rax], 1": { + "ExpectedInstructionCount": 8, + "Optimal": "Yes", + "Comment": "GROUP1 0x83 /0", + "ExpectedArm64ASM": [ + "mov w20, #0x1", + "ldaddal x20, x20, [x4]", + "add x21, x20, #0x1 (1)", + "strb w20, [x28, #708]", + "strb w21, [x28, #706]", + "cmn x20, #0x1 (1)", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "lock or byte [rax], 1": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": "GROUP1 0x80 /1", + "ExpectedArm64ASM": [ + "mov w20, #0x1", + "ldsetalb w20, w20, [x4]", + "orr w20, w20, #0x1", + "strb w20, [x28, #706]", + "lsl w20, w20, #24", + "tst w20, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "lock or byte [rax], 0xFF": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": "GROUP1 0x80 /1", + "ExpectedArm64ASM": [ + "mov w20, #0xff", + "ldsetalb w20, w20, [x4]", + "orr w20, w20, #0xff", + "strb w20, [x28, #706]", + "lsl w20, w20, #24", + "tst w20, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "lock or word [rax], 0x100": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": "GROUP1 0x81 /1", + "ExpectedArm64ASM": [ + "mov w20, #0x100", + "ldsetalh w20, w20, [x4]", + "orr w20, w20, #0x100", + "strb w20, [x28, #706]", + "lsl w20, w20, #16", + "tst w20, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "lock or word [rax], 0xFFFF": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": "GROUP1 0x81 /1", + "ExpectedArm64ASM": [ + "mov w20, #0xffff", + "ldsetalh w20, w20, [x4]", + "orr w20, w20, #0xffff", + "strb w20, [x28, #706]", + "lsl w20, w20, #16", + "tst w20, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "lock or dword [rax], 0x100": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": "GROUP1 0x81 /1", + "ExpectedArm64ASM": [ + "mov w20, #0x100", + "ldsetal w20, w20, [x4]", + "orr w20, w20, #0x100", + "strb w20, [x28, #706]", + "tst w20, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "lock or dword [rax], 0xFFFFFFFF": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": "GROUP1 0x81 /1", + "ExpectedArm64ASM": [ + "mov w20, #0xffff", + "movk w20, #0xffff, lsl #16", + "ldsetal w20, w21, [x4]", + "orr w20, w21, w20", + "strb w20, [x28, #706]", + "tst w20, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "lock or qword [rax], 0x100": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": "GROUP1 0x81 /1", + "ExpectedArm64ASM": [ + "mov w20, #0x100", + "ldsetal x20, x20, [x4]", + "orr x20, x20, #0x100", + "strb w20, [x28, #706]", + "tst x20, x20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "lock or qword [rax], -2147483647": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": "GROUP1 0x81 /1", + "ExpectedArm64ASM": [ + "mov x20, #0xffffffff80000001", + "ldsetal x20, x20, [x4]", + "orr x20, x20, #0xffffffff80000001", + "strb w20, [x28, #706]", + "tst x20, x20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "lock or word [rax], 1": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": "GROUP1 0x83 /1", + "ExpectedArm64ASM": [ + "mov w20, #0x1", + "ldsetalh w20, w20, [x4]", + "orr w20, w20, #0x1", + "strb w20, [x28, #706]", + "lsl w20, w20, #16", + "tst w20, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "lock or dword [rax], 1": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": "GROUP1 0x83 /1", + "ExpectedArm64ASM": [ + "mov w20, #0x1", + "ldsetal w20, w20, [x4]", + "orr w20, w20, #0x1", + "strb w20, [x28, #706]", + "tst w20, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "lock or qword [rax], 1": { + "ExpectedInstructionCount": 7, + "Optimal": "Yes", + "Comment": "GROUP1 0x83 /1", + "ExpectedArm64ASM": [ + "mov w20, #0x1", + "ldsetal x20, x20, [x4]", + "orr x20, x20, #0x1", + "strb w20, [x28, #706]", + "tst x20, x20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "lock adc byte [rax], 1": { + "ExpectedInstructionCount": 23, + "Optimal": "No", + "Comment": "GROUP1 0x80 /2", + "ExpectedArm64ASM": [ + "mov w20, #0x1", + "ldr w21, [x28, #728]", + "ubfx w21, w21, #29, #1", + "add w20, w20, w21", + "ldaddalb w20, w22, [x4]", + "add w20, w22, w20", + "uxtb w20, w20", + "strb w22, [x28, #708]", + "strb w20, [x28, #706]", + "lsl w23, w20, #24", + "tst w23, w23", + "mrs x23, nzcv", + "cmp w20, #0x1 (1)", + "cset x24, lo", + "cmp w20, #0x1 (1)", + "cset x25, ls", + "cmp x21, #0x1 (1)", + "csel x21, x25, x24, eq", + "orr w21, w23, w21, lsl #29", + "bic w20, w20, w22", + "ubfx w20, w20, #7, #1", + "orr w20, w21, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "lock adc byte [rax], 0xFF": { + "ExpectedInstructionCount": 24, + "Optimal": "No", + "Comment": "GROUP1 0x80 /2", + "ExpectedArm64ASM": [ + "mov w20, #0xff", + "ldr w21, [x28, #728]", + "ubfx w21, w21, #29, #1", + "add w20, w20, w21", + "ldaddalb w20, w22, [x4]", + "add w20, w22, w20", + "uxtb w20, w20", + "eor w23, w22, #0xff", + "strb w23, [x28, #708]", + "strb w20, [x28, #706]", + "lsl w23, w20, #24", + "tst w23, w23", + "mrs x23, nzcv", + "cmp w20, #0xff (255)", + "cset x24, lo", + "cmp w20, #0xff (255)", + "cset x25, ls", + "cmp x21, #0x1 (1)", + "csel x21, x25, x24, eq", + "orr w21, w23, w21, lsl #29", + "bic w20, w22, w20", + "ubfx w20, w20, #7, #1", + "orr w20, w21, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "lock adc word [rax], 0x100": { + "ExpectedInstructionCount": 23, + "Optimal": "No", + "Comment": "GROUP1 0x81 /2", + "ExpectedArm64ASM": [ + "mov w20, #0x100", + "ldr w21, [x28, #728]", + "ubfx w21, w21, #29, #1", + "add w20, w20, w21", + "ldaddalh w20, w22, [x4]", + "add w20, w22, w20", + "uxth w20, w20", + "strb w22, [x28, #708]", + "strb w20, [x28, #706]", + "lsl w23, w20, #16", + "tst w23, w23", + "mrs x23, nzcv", + "cmp w20, #0x100 (256)", + "cset x24, lo", + "cmp w20, #0x100 (256)", + "cset x25, ls", + "cmp x21, #0x1 (1)", + "csel x21, x25, x24, eq", + "orr w21, w23, w21, lsl #29", + "bic w20, w20, w22", + "ubfx w20, w20, #15, #1", + "orr w20, w21, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "lock adc word [rax], 0xFFFF": { + "ExpectedInstructionCount": 24, + "Optimal": "No", + "Comment": "GROUP1 0x81 /2", + "ExpectedArm64ASM": [ + "mov w20, #0xffff", + "ldr w21, [x28, #728]", + "ubfx w21, w21, #29, #1", + "add w22, w20, w21", + "ldaddalh w22, w23, [x4]", + "add w22, w23, w22", + "uxth w22, w22", + "eor w24, w23, #0xffff", + "strb w24, [x28, #708]", + "strb w22, [x28, #706]", + "lsl w24, w22, #16", + "tst w24, w24", + "mrs x24, nzcv", + "cmp w22, w20", + "cset x25, lo", + "cmp w22, w20", + "cset x20, ls", + "cmp x21, #0x1 (1)", + "csel x20, x20, x25, eq", + "orr w20, w24, w20, lsl #29", + "bic w21, w23, w22", + "ubfx w21, w21, #15, #1", + "orr w20, w20, w21, lsl #28", + "str w20, [x28, #728]" + ] + }, + "lock adc dword [rax], 0x100": { + "ExpectedInstructionCount": 12, + "Optimal": "No", + "Comment": "GROUP1 0x81 /2", + "ExpectedArm64ASM": [ + "mov w20, #0x100", + "ldr w21, [x28, #728]", + "ubfx w22, w21, #29, #1", + "add w22, w20, w22", + "ldaddal w22, w23, [x4]", + "add w22, w23, w22", + "strb w23, [x28, #708]", + "strb w22, [x28, #706]", + "msr nzcv, x21", + "adcs wzr, w23, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "lock adc dword [rax], 0xFFFFFFFF": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": "GROUP1 0x81 /2", + "ExpectedArm64ASM": [ + "mov w20, #0xffff", + "movk w20, #0xffff, lsl #16", + "ldr w21, [x28, #728]", + "ubfx w22, w21, #29, #1", + "add w22, w20, w22", + "ldaddal w22, w23, [x4]", + "add w22, w23, w22", + "eor w24, w23, w20", + "strb w24, [x28, #708]", + "strb w22, [x28, #706]", + "msr nzcv, x21", + "adcs wzr, w23, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "lock adc qword [rax], 0x100": { + "ExpectedInstructionCount": 12, + "Optimal": "No", + "Comment": "GROUP1 0x81 /2", + "ExpectedArm64ASM": [ + "mov w20, #0x100", + "ldr w21, [x28, #728]", + "ubfx w22, w21, #29, #1", + "add x22, x20, x22", + "ldaddal x22, x23, [x4]", + "add x22, x23, x22", + "strb w23, [x28, #708]", + "strb w22, [x28, #706]", + "msr nzcv, x21", + "adcs xzr, x23, x20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "lock adc qword [rax], -2147483647": { + "ExpectedInstructionCount": 12, + "Optimal": "No", + "Comment": "GROUP1 0x81 /2", + "ExpectedArm64ASM": [ + "mov x20, #0xffffffff80000001", + "ldr w21, [x28, #728]", + "ubfx w22, w21, #29, #1", + "add x22, x20, x22", + "ldaddal x22, x23, [x4]", + "add x22, x23, x22", + "strb w23, [x28, #708]", + "strb w22, [x28, #706]", + "msr nzcv, x21", + "adcs xzr, x23, x20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "lock adc word [rax], 1": { + "ExpectedInstructionCount": 23, + "Optimal": "No", + "Comment": "GROUP1 0x83 /2", + "ExpectedArm64ASM": [ + "mov w20, #0x1", + "ldr w21, [x28, #728]", + "ubfx w21, w21, #29, #1", + "add w20, w20, w21", + "ldaddalh w20, w22, [x4]", + "add w20, w22, w20", + "uxth w20, w20", + "strb w22, [x28, #708]", + "strb w20, [x28, #706]", + "lsl w23, w20, #16", + "tst w23, w23", + "mrs x23, nzcv", + "cmp w20, #0x1 (1)", + "cset x24, lo", + "cmp w20, #0x1 (1)", + "cset x25, ls", + "cmp x21, #0x1 (1)", + "csel x21, x25, x24, eq", + "orr w21, w23, w21, lsl #29", + "bic w20, w20, w22", + "ubfx w20, w20, #15, #1", + "orr w20, w21, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "lock adc dword [rax], 1": { + "ExpectedInstructionCount": 12, + "Optimal": "No", + "Comment": "GROUP1 0x83 /2", + "ExpectedArm64ASM": [ + "mov w20, #0x1", + "ldr w21, [x28, #728]", + "ubfx w22, w21, #29, #1", + "add w22, w20, w22", + "ldaddal w22, w23, [x4]", + "add w22, w23, w22", + "strb w23, [x28, #708]", + "strb w22, [x28, #706]", + "msr nzcv, x21", + "adcs wzr, w23, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "lock adc qword [rax], 1": { + "ExpectedInstructionCount": 12, + "Optimal": "Yes", + "Comment": "GROUP1 0x83 /2", + "ExpectedArm64ASM": [ + "mov w20, #0x1", + "ldr w21, [x28, #728]", + "ubfx w22, w21, #29, #1", + "add x22, x20, x22", + "ldaddal x22, x23, [x4]", + "add x22, x23, x22", + "strb w23, [x28, #708]", + "strb w22, [x28, #706]", + "msr nzcv, x21", + "adcs xzr, x23, x20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "lock sbb byte [rax], 1": { + "ExpectedInstructionCount": 24, + "Optimal": "No", + "Comment": "GROUP1 0x80 /3", + "ExpectedArm64ASM": [ + "mov w20, #0x1", + "ldr w21, [x28, #728]", + "ubfx w21, w21, #29, #1", + "add w20, w20, w21", + "neg w1, w20", + "ldaddalb w1, w22, [x4]", + "sub w20, w22, w20", + "uxtb w20, w20", + "strb w22, [x28, #708]", + "strb w20, [x28, #706]", + "lsl w23, w20, #24", + "tst w23, w23", + "mrs x23, nzcv", + "cmp w20, w22", + "cset x24, hi", + "cmp w20, w22", + "cset x25, hs", + "cmp x21, #0x1 (1)", + "csel x21, x25, x24, eq", + "orr w21, w23, w21, lsl #29", + "bic w20, w22, w20", + "ubfx w20, w20, #7, #1", + "orr w20, w21, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "lock sbb byte [rax], 0xFF": { + "ExpectedInstructionCount": 25, + "Optimal": "No", + "Comment": "GROUP1 0x80 /3", + "ExpectedArm64ASM": [ + "mov w20, #0xff", + "ldr w21, [x28, #728]", + "ubfx w21, w21, #29, #1", + "add w20, w20, w21", + "neg w1, w20", + "ldaddalb w1, w22, [x4]", + "sub w20, w22, w20", + "uxtb w20, w20", + "eor w23, w22, #0xff", + "strb w23, [x28, #708]", + "strb w20, [x28, #706]", + "lsl w23, w20, #24", + "tst w23, w23", + "mrs x23, nzcv", + "cmp w20, w22", + "cset x24, hi", + "cmp w20, w22", + "cset x25, hs", + "cmp x21, #0x1 (1)", + "csel x21, x25, x24, eq", + "orr w21, w23, w21, lsl #29", + "bic w20, w20, w22", + "ubfx w20, w20, #7, #1", + "orr w20, w21, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "lock sbb word [rax], 0x100": { + "ExpectedInstructionCount": 24, + "Optimal": "No", + "Comment": "GROUP1 0x81 /3", + "ExpectedArm64ASM": [ + "mov w20, #0x100", + "ldr w21, [x28, #728]", + "ubfx w21, w21, #29, #1", + "add w20, w20, w21", + "neg w1, w20", + "ldaddalh w1, w22, [x4]", + "sub w20, w22, w20", + "uxth w20, w20", + "strb w22, [x28, #708]", + "strb w20, [x28, #706]", + "lsl w23, w20, #16", + "tst w23, w23", + "mrs x23, nzcv", + "cmp w20, w22", + "cset x24, hi", + "cmp w20, w22", + "cset x25, hs", + "cmp x21, #0x1 (1)", + "csel x21, x25, x24, eq", + "orr w21, w23, w21, lsl #29", + "bic w20, w22, w20", + "ubfx w20, w20, #15, #1", + "orr w20, w21, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "lock sbb word [rax], 0xFFFF": { + "ExpectedInstructionCount": 25, + "Optimal": "No", + "Comment": "GROUP1 0x81 /3", + "ExpectedArm64ASM": [ + "mov w20, #0xffff", + "ldr w21, [x28, #728]", + "ubfx w21, w21, #29, #1", + "add w20, w20, w21", + "neg w1, w20", + "ldaddalh w1, w22, [x4]", + "sub w20, w22, w20", + "uxth w20, w20", + "eor w23, w22, #0xffff", + "strb w23, [x28, #708]", + "strb w20, [x28, #706]", + "lsl w23, w20, #16", + "tst w23, w23", + "mrs x23, nzcv", + "cmp w20, w22", + "cset x24, hi", + "cmp w20, w22", + "cset x25, hs", + "cmp x21, #0x1 (1)", + "csel x21, x25, x24, eq", + "orr w21, w23, w21, lsl #29", + "bic w20, w20, w22", + "ubfx w20, w20, #15, #1", + "orr w20, w21, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "lock sbb dword [rax], 0x100": { + "ExpectedInstructionCount": 15, + "Optimal": "No", + "Comment": "GROUP1 0x81 /3", + "ExpectedArm64ASM": [ + "mov w20, #0x100", + "ldr w21, [x28, #728]", + "ubfx w22, w21, #29, #1", + "add w22, w20, w22", + "neg w1, w22", + "ldaddal w1, w23, [x4]", + "sub w22, w23, w22", + "strb w23, [x28, #708]", + "strb w22, [x28, #706]", + "eor w0, w21, #0x20000000", + "msr nzcv, x0", + "sbcs wzr, w23, w20", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "str w20, [x28, #728]" + ] + }, + "lock sbb dword [rax], 0xFFFFFFFF": { + "ExpectedInstructionCount": 17, + "Optimal": "No", + "Comment": "GROUP1 0x81 /3", + "ExpectedArm64ASM": [ + "mov w20, #0xffff", + "movk w20, #0xffff, lsl #16", + "ldr w21, [x28, #728]", + "ubfx w22, w21, #29, #1", + "add w22, w20, w22", + "neg w1, w22", + "ldaddal w1, w23, [x4]", + "sub w22, w23, w22", + "eor w24, w23, w20", + "strb w24, [x28, #708]", + "strb w22, [x28, #706]", + "eor w0, w21, #0x20000000", + "msr nzcv, x0", + "sbcs wzr, w23, w20", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "str w20, [x28, #728]" + ] + }, + "lock sbb qword [rax], 0x100": { + "ExpectedInstructionCount": 15, + "Optimal": "No", + "Comment": "GROUP1 0x81 /3", + "ExpectedArm64ASM": [ + "mov w20, #0x100", + "ldr w21, [x28, #728]", + "ubfx w22, w21, #29, #1", + "add x22, x20, x22", + "neg x1, x22", + "ldaddal x1, x23, [x4]", + "sub x22, x23, x22", + "strb w23, [x28, #708]", + "strb w22, [x28, #706]", + "eor w0, w21, #0x20000000", + "msr nzcv, x0", + "sbcs xzr, x23, x20", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "str w20, [x28, #728]" + ] + }, + "lock sbb qword [rax], -2147483647": { + "ExpectedInstructionCount": 15, + "Optimal": "No", + "Comment": "GROUP1 0x81 /3", + "ExpectedArm64ASM": [ + "mov x20, #0xffffffff80000001", + "ldr w21, [x28, #728]", + "ubfx w22, w21, #29, #1", + "add x22, x20, x22", + "neg x1, x22", + "ldaddal x1, x23, [x4]", + "sub x22, x23, x22", + "strb w23, [x28, #708]", + "strb w22, [x28, #706]", + "eor w0, w21, #0x20000000", + "msr nzcv, x0", + "sbcs xzr, x23, x20", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "str w20, [x28, #728]" + ] + }, + "lock sbb word [rax], 1": { + "ExpectedInstructionCount": 24, + "Optimal": "No", + "Comment": "GROUP1 0x83 /3", + "ExpectedArm64ASM": [ + "mov w20, #0x1", + "ldr w21, [x28, #728]", + "ubfx w21, w21, #29, #1", + "add w20, w20, w21", + "neg w1, w20", + "ldaddalh w1, w22, [x4]", + "sub w20, w22, w20", + "uxth w20, w20", + "strb w22, [x28, #708]", + "strb w20, [x28, #706]", + "lsl w23, w20, #16", + "tst w23, w23", + "mrs x23, nzcv", + "cmp w20, w22", + "cset x24, hi", + "cmp w20, w22", + "cset x25, hs", + "cmp x21, #0x1 (1)", + "csel x21, x25, x24, eq", + "orr w21, w23, w21, lsl #29", + "bic w20, w22, w20", + "ubfx w20, w20, #15, #1", + "orr w20, w21, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "lock sbb dword [rax], 1": { + "ExpectedInstructionCount": 15, + "Optimal": "No", + "Comment": "GROUP1 0x83 /3", + "ExpectedArm64ASM": [ + "mov w20, #0x1", + "ldr w21, [x28, #728]", + "ubfx w22, w21, #29, #1", + "add w22, w20, w22", + "neg w1, w22", + "ldaddal w1, w23, [x4]", + "sub w22, w23, w22", + "strb w23, [x28, #708]", + "strb w22, [x28, #706]", + "eor w0, w21, #0x20000000", + "msr nzcv, x0", + "sbcs wzr, w23, w20", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "str w20, [x28, #728]" + ] + }, + "lock sbb qword [rax], 1": { + "ExpectedInstructionCount": 15, + "Optimal": "Yes", + "Comment": "GROUP1 0x83 /3", + "ExpectedArm64ASM": [ + "mov w20, #0x1", + "ldr w21, [x28, #728]", + "ubfx w22, w21, #29, #1", + "add x22, x20, x22", + "neg x1, x22", + "ldaddal x1, x23, [x4]", + "sub x22, x23, x22", + "strb w23, [x28, #708]", + "strb w22, [x28, #706]", + "eor w0, w21, #0x20000000", + "msr nzcv, x0", + "sbcs xzr, x23, x20", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "str w20, [x28, #728]" + ] + }, + "lock and byte [rax], 1": { + "ExpectedInstructionCount": 9, + "Optimal": "No", + "Comment": "GROUP1 0x80 /4", + "ExpectedArm64ASM": [ + "mov w20, #0x1", + "mvn w1, w20", + "ldclralb w1, w20, [x4]", + "and w20, w20, #0x1", + "strb w20, [x28, #706]", + "lsl w20, w20, #24", + "tst w20, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "lock and byte [rax], 0xFF": { + "ExpectedInstructionCount": 9, + "Optimal": "No", + "Comment": "GROUP1 0x80 /4", + "ExpectedArm64ASM": [ + "mov w20, #0xff", + "mvn w1, w20", + "ldclralb w1, w20, [x4]", + "and w20, w20, #0xff", + "strb w20, [x28, #706]", + "lsl w20, w20, #24", + "tst w20, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "lock and word [rax], 0x100": { + "ExpectedInstructionCount": 9, + "Optimal": "No", + "Comment": "GROUP1 0x81 /4", + "ExpectedArm64ASM": [ + "mov w20, #0x100", + "mvn w1, w20", + "ldclralh w1, w20, [x4]", + "and w20, w20, #0x100", + "strb w20, [x28, #706]", + "lsl w20, w20, #16", + "tst w20, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "lock and word [rax], 0xFFFF": { + "ExpectedInstructionCount": 9, + "Optimal": "No", + "Comment": "GROUP1 0x81 /4", + "ExpectedArm64ASM": [ + "mov w20, #0xffff", + "mvn w1, w20", + "ldclralh w1, w20, [x4]", + "and w20, w20, #0xffff", + "strb w20, [x28, #706]", + "lsl w20, w20, #16", + "tst w20, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "lock and dword [rax], 0x100": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": "GROUP1 0x81 /4", + "ExpectedArm64ASM": [ + "mov w20, #0x100", + "mvn w1, w20", + "ldclral w1, w20, [x4]", + "and w20, w20, #0x100", + "strb w20, [x28, #706]", + "tst w20, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "lock and dword [rax], 0xFFFFFFFF": { + "ExpectedInstructionCount": 9, + "Optimal": "No", + "Comment": "GROUP1 0x81 /4", + "ExpectedArm64ASM": [ + "mov w20, #0xffff", + "movk w20, #0xffff, lsl #16", + "mvn w1, w20", + "ldclral w1, w21, [x4]", + "and w20, w21, w20", + "strb w20, [x28, #706]", + "tst w20, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "lock and qword [rax], 0x100": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": "GROUP1 0x81 /4", + "ExpectedArm64ASM": [ + "mov w20, #0x100", + "mvn x1, x20", + "ldclral x1, x20, [x4]", + "and x20, x20, #0x100", + "strb w20, [x28, #706]", + "tst x20, x20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "lock and qword [rax], -2147483647": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": "GROUP1 0x81 /4", + "ExpectedArm64ASM": [ + "mov x20, #0xffffffff80000001", + "mvn x1, x20", + "ldclral x1, x20, [x4]", + "and x20, x20, #0xffffffff80000001", + "strb w20, [x28, #706]", + "tst x20, x20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "lock and word [rax], 1": { + "ExpectedInstructionCount": 9, + "Optimal": "No", + "Comment": "GROUP1 0x83 /4", + "ExpectedArm64ASM": [ + "mov w20, #0x1", + "mvn w1, w20", + "ldclralh w1, w20, [x4]", + "and w20, w20, #0x1", + "strb w20, [x28, #706]", + "lsl w20, w20, #16", + "tst w20, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "lock and dword [rax], 1": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": "GROUP1 0x83 /4", + "ExpectedArm64ASM": [ + "mov w20, #0x1", + "mvn w1, w20", + "ldclral w1, w20, [x4]", + "and w20, w20, #0x1", + "strb w20, [x28, #706]", + "tst w20, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "lock and qword [rax], 1": { + "ExpectedInstructionCount": 8, + "Optimal": "Yes", + "Comment": "GROUP1 0x83 /4", + "ExpectedArm64ASM": [ + "mov w20, #0x1", + "mvn x1, x20", + "ldclral x1, x20, [x4]", + "and x20, x20, #0x1", + "strb w20, [x28, #706]", + "tst x20, x20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "lock sub byte [rax], 1": { + "ExpectedInstructionCount": 15, + "Optimal": "No", + "Comment": "GROUP1 0x80 /5", + "ExpectedArm64ASM": [ + "mov w20, #0x1", + "neg w1, w20", + "ldaddalb w1, w20, [x4]", + "sub w21, w20, #0x1 (1)", + "strb w20, [x28, #708]", + "strb w21, [x28, #706]", + "lsl w22, w21, #24", + "tst w22, w22", + "mrs x22, nzcv", + "ubfx w23, w21, #8, #1", + "orr w22, w22, w23, lsl #29", + "bic w20, w20, w21", + "ubfx w20, w20, #7, #1", + "orr w20, w22, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "lock sub byte [rax], 0xFF": { + "ExpectedInstructionCount": 16, + "Optimal": "No", + "Comment": "GROUP1 0x80 /5", + "ExpectedArm64ASM": [ + "mov w20, #0xff", + "neg w1, w20", + "ldaddalb w1, w20, [x4]", + "sub w21, w20, #0xff (255)", + "eor w22, w20, #0xff", + "strb w22, [x28, #708]", + "strb w21, [x28, #706]", + "lsl w22, w21, #24", + "tst w22, w22", + "mrs x22, nzcv", + "ubfx w23, w21, #8, #1", + "orr w22, w22, w23, lsl #29", + "bic w20, w21, w20", + "ubfx w20, w20, #7, #1", + "orr w20, w22, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "lock sub word [rax], 0x100": { + "ExpectedInstructionCount": 15, + "Optimal": "No", + "Comment": "GROUP1 0x81 /5", + "ExpectedArm64ASM": [ + "mov w20, #0x100", + "neg w1, w20", + "ldaddalh w1, w20, [x4]", + "sub w21, w20, #0x100 (256)", + "strb w20, [x28, #708]", + "strb w21, [x28, #706]", + "lsl w22, w21, #16", + "tst w22, w22", + "mrs x22, nzcv", + "ubfx w23, w21, #16, #1", + "orr w22, w22, w23, lsl #29", + "bic w20, w20, w21", + "ubfx w20, w20, #15, #1", + "orr w20, w22, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "lock sub word [rax], 0xFFFF": { + "ExpectedInstructionCount": 16, + "Optimal": "No", + "Comment": "GROUP1 0x81 /5", + "ExpectedArm64ASM": [ + "mov w20, #0xffff", + "neg w1, w20", + "ldaddalh w1, w21, [x4]", + "sub w20, w21, w20", + "eor w22, w21, #0xffff", + "strb w22, [x28, #708]", + "strb w20, [x28, #706]", + "lsl w22, w20, #16", + "tst w22, w22", + "mrs x22, nzcv", + "ubfx w23, w20, #16, #1", + "orr w22, w22, w23, lsl #29", + "bic w20, w20, w21", + "ubfx w20, w20, #15, #1", + "orr w20, w22, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "lock sub dword [rax], 0x100": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": "GROUP1 0x81 /5", + "ExpectedArm64ASM": [ + "mov w20, #0x100", + "neg w1, w20", + "ldaddal w1, w20, [x4]", + "sub w21, w20, #0x100 (256)", + "strb w20, [x28, #708]", + "strb w21, [x28, #706]", + "cmp w20, #0x100 (256)", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "str w20, [x28, #728]" + ] + }, + "lock sub dword [rax], 0xFFFFFFFF": { + "ExpectedInstructionCount": 12, + "Optimal": "No", + "Comment": "GROUP1 0x81 /5", + "ExpectedArm64ASM": [ + "mov w20, #0xffff", + "movk w20, #0xffff, lsl #16", + "neg w1, w20", + "ldaddal w1, w21, [x4]", + "sub w22, w21, w20", + "eor w23, w21, w20", + "strb w23, [x28, #708]", + "strb w22, [x28, #706]", + "cmp w21, w20", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "str w20, [x28, #728]" + ] + }, + "lock sub qword [rax], 0x100": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": "GROUP1 0x81 /5", + "ExpectedArm64ASM": [ + "mov w20, #0x100", + "neg x1, x20", + "ldaddal x1, x20, [x4]", + "sub x21, x20, #0x100 (256)", + "strb w20, [x28, #708]", + "strb w21, [x28, #706]", + "cmp x20, #0x100 (256)", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "str w20, [x28, #728]" + ] + }, + "lock sub qword [rax], -2147483647": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": "GROUP1 0x81 /5", + "ExpectedArm64ASM": [ + "mov x20, #0xffffffff80000001", + "neg x1, x20", + "ldaddal x1, x21, [x4]", + "sub x22, x21, x20", + "strb w21, [x28, #708]", + "strb w22, [x28, #706]", + "cmp x21, x20", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "str w20, [x28, #728]" + ] + }, + "lock sub word [rax], 1": { + "ExpectedInstructionCount": 15, + "Optimal": "No", + "Comment": "GROUP1 0x83 /5", + "ExpectedArm64ASM": [ + "mov w20, #0x1", + "neg w1, w20", + "ldaddalh w1, w20, [x4]", + "sub w21, w20, #0x1 (1)", + "strb w20, [x28, #708]", + "strb w21, [x28, #706]", + "lsl w22, w21, #16", + "tst w22, w22", + "mrs x22, nzcv", + "ubfx w23, w21, #16, #1", + "orr w22, w22, w23, lsl #29", + "bic w20, w20, w21", + "ubfx w20, w20, #15, #1", + "orr w20, w22, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "lock sub dword [rax], 1": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": "GROUP1 0x83 /5", + "ExpectedArm64ASM": [ + "mov w20, #0x1", + "neg w1, w20", + "ldaddal w1, w20, [x4]", + "sub w21, w20, #0x1 (1)", + "strb w20, [x28, #708]", + "strb w21, [x28, #706]", + "cmp w20, #0x1 (1)", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "str w20, [x28, #728]" + ] + }, + "lock sub qword [rax], 1": { + "ExpectedInstructionCount": 10, + "Optimal": "Yes", + "Comment": "GROUP1 0x83 /5", + "ExpectedArm64ASM": [ + "mov w20, #0x1", + "neg x1, x20", + "ldaddal x1, x20, [x4]", + "sub x21, x20, #0x1 (1)", + "strb w20, [x28, #708]", + "strb w21, [x28, #706]", + "cmp x20, #0x1 (1)", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "str w20, [x28, #728]" + ] + }, + "lock xor byte [rax], 1": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": "GROUP1 0x80 /6", + "ExpectedArm64ASM": [ + "mov w20, #0x1", + "ldeoralb w20, w20, [x4]", + "eor w20, w20, #0x1", + "strb w20, [x28, #706]", + "lsl w20, w20, #24", + "tst w20, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "lock xor byte [rax], 0xFF": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": "GROUP1 0x80 /6", + "ExpectedArm64ASM": [ + "mov w20, #0xff", + "ldeoralb w20, w20, [x4]", + "eor w20, w20, #0xff", + "strb w20, [x28, #706]", + "lsl w20, w20, #24", + "tst w20, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "lock xor word [rax], 0x100": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": "GROUP1 0x81 /6", + "ExpectedArm64ASM": [ + "mov w20, #0x100", + "ldeoralh w20, w20, [x4]", + "eor w20, w20, #0x100", + "strb w20, [x28, #706]", + "lsl w20, w20, #16", + "tst w20, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "lock xor word [rax], 0xFFFF": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": "GROUP1 0x81 /6", + "ExpectedArm64ASM": [ + "mov w20, #0xffff", + "ldeoralh w20, w20, [x4]", + "eor w20, w20, #0xffff", + "strb w20, [x28, #706]", + "lsl w20, w20, #16", + "tst w20, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "lock xor dword [rax], 0x100": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": "GROUP1 0x81 /6", + "ExpectedArm64ASM": [ + "mov w20, #0x100", + "ldeoral w20, w20, [x4]", + "eor w20, w20, #0x100", + "strb w20, [x28, #706]", + "tst w20, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "lock xor dword [rax], 0xFFFFFFFF": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": "GROUP1 0x81 /6", + "ExpectedArm64ASM": [ + "mov w20, #0xffff", + "movk w20, #0xffff, lsl #16", + "ldeoral w20, w21, [x4]", + "eor w20, w21, w20", + "strb w20, [x28, #706]", + "tst w20, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "lock xor qword [rax], 0x100": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": "GROUP1 0x81 /6", + "ExpectedArm64ASM": [ + "mov w20, #0x100", + "ldeoral x20, x20, [x4]", + "eor x20, x20, #0x100", + "strb w20, [x28, #706]", + "tst x20, x20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "lock xor qword [rax], -2147483647": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": "GROUP1 0x81 /6", + "ExpectedArm64ASM": [ + "mov x20, #0xffffffff80000001", + "ldeoral x20, x20, [x4]", + "eor x20, x20, #0xffffffff80000001", + "strb w20, [x28, #706]", + "tst x20, x20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "lock xor word [rax], 1": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": "GROUP1 0x83 /6", + "ExpectedArm64ASM": [ + "mov w20, #0x1", + "ldeoralh w20, w20, [x4]", + "eor w20, w20, #0x1", + "strb w20, [x28, #706]", + "lsl w20, w20, #16", + "tst w20, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "lock xor dword [rax], 1": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": "GROUP1 0x83 /6", + "ExpectedArm64ASM": [ + "mov w20, #0x1", + "ldeoral w20, w20, [x4]", + "eor w20, w20, #0x1", + "strb w20, [x28, #706]", + "tst w20, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "lock xor qword [rax], 1": { + "ExpectedInstructionCount": 7, + "Optimal": "Yes", + "Comment": "GROUP1 0x83 /6", + "ExpectedArm64ASM": [ + "mov w20, #0x1", + "ldeoral x20, x20, [x4]", + "eor x20, x20, #0x1", + "strb w20, [x28, #706]", + "tst x20, x20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "lock dec byte [rax]": { + "ExpectedInstructionCount": 16, + "Optimal": "No", + "Comment": "GROUP3 0xfe /1", + "ExpectedArm64ASM": [ + "mov w20, #0x1", + "neg w1, w20", + "ldaddalb w1, w20, [x4]", + "sub w21, w20, #0x1 (1)", + "strb w20, [x28, #708]", + "strb w21, [x28, #706]", + "ldr w22, [x28, #728]", + "ubfx w22, w22, #29, #1", + "lsl w23, w21, #24", + "tst w23, w23", + "mrs x23, nzcv", + "bic w20, w20, w21", + "ubfx w20, w20, #7, #1", + "orr w20, w23, w20, lsl #28", + "orr w20, w20, w22, lsl #29", + "str w20, [x28, #728]" + ] + }, + "lock not byte [rax]": { + "ExpectedInstructionCount": 2, + "Optimal": "No", + "Comment": "GROUP2 0xf6 /2", + "ExpectedArm64ASM": [ + "mov w20, #0xff", + "steorlb w20, [x4]" + ] + }, + "lock not word [rax]": { + "ExpectedInstructionCount": 2, + "Optimal": "No", + "Comment": "GROUP2 0xf7 /2", + "ExpectedArm64ASM": [ + "mov w20, #0xffff", + "steorlh w20, [x4]" + ] + }, + "lock not dword [rax]": { + "ExpectedInstructionCount": 3, + "Optimal": "No", + "Comment": "GROUP2 0xf7 /2", + "ExpectedArm64ASM": [ + "mov w20, #0xffff", + "movk w20, #0xffff, lsl #16", + "steorl w20, [x4]" + ] + }, + "lock not qword [rax]": { + "ExpectedInstructionCount": 2, + "Optimal": "No", + "Comment": "GROUP2 0xf7 /2", + "ExpectedArm64ASM": [ + "mov x20, #0xffffffffffffffff", + "steorl x20, [x4]" + ] + }, + "lock neg byte [rax]": { + "ExpectedInstructionCount": 17, + "Optimal": "No", + "Comment": "GROUP2 0xf6 /3", + "ExpectedArm64ASM": [ + "ldaxrb w1, [x4]", + "neg w2, w1", + "stlxrb w3, w2, [x4]", + "cbnz w3, #-0xc", + "mov w20, w1", + "neg w21, w20", + "strb w20, [x28, #708]", + "strb w21, [x28, #706]", + "lsl w22, w21, #24", + "tst w22, w22", + "mrs x22, nzcv", + "ubfx w23, w21, #8, #1", + "orr w22, w22, w23, lsl #29", + "and w20, w21, w20", + "ubfx w20, w20, #7, #1", + "orr w20, w22, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "lock neg word [rax]": { + "ExpectedInstructionCount": 17, + "Optimal": "No", + "Comment": "GROUP2 0xf7 /3", + "ExpectedArm64ASM": [ + "ldaxrh w1, [x4]", + "neg w2, w1", + "stlxrh w3, w2, [x4]", + "cbnz w3, #-0xc", + "mov w20, w1", + "neg w21, w20", + "strb w20, [x28, #708]", + "strb w21, [x28, #706]", + "lsl w22, w21, #16", + "tst w22, w22", + "mrs x22, nzcv", + "ubfx w23, w21, #16, #1", + "orr w22, w22, w23, lsl #29", + "and w20, w21, w20", + "ubfx w20, w20, #15, #1", + "orr w20, w22, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "lock neg dword [rax]": { + "ExpectedInstructionCount": 12, + "Optimal": "No", + "Comment": "GROUP2 0xf7 /3", + "ExpectedArm64ASM": [ + "ldaxr w1, [x4]", + "neg w2, w1", + "stlxr w3, w2, [x4]", + "cbnz w3, #-0xc", + "mov w20, w1", + "neg w21, w20", + "strb w20, [x28, #708]", + "strb w21, [x28, #706]", + "cmp wzr, w20", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "str w20, [x28, #728]" + ] + }, + "lock neg qword [rax]": { + "ExpectedInstructionCount": 12, + "Optimal": "No", + "Comment": "GROUP2 0xf7 /3", + "ExpectedArm64ASM": [ + "ldaxr x1, [x4]", + "neg x2, x1", + "stlxr w3, x2, [x4]", + "cbnz x3, #-0xc", + "mov x20, x1", + "neg x21, x20", + "strb w20, [x28, #708]", + "strb w21, [x28, #706]", + "cmp xzr, x20", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "str w20, [x28, #728]" + ] + }, + "lock dec word [rax]": { + "ExpectedInstructionCount": 16, + "Optimal": "No", + "Comment": "GROUP4 0xfe /1", + "ExpectedArm64ASM": [ + "mov w20, #0x1", + "neg w1, w20", + "ldaddalh w1, w20, [x4]", + "sub w21, w20, #0x1 (1)", + "strb w20, [x28, #708]", + "strb w21, [x28, #706]", + "ldr w22, [x28, #728]", + "ubfx w22, w22, #29, #1", + "lsl w23, w21, #16", + "tst w23, w23", + "mrs x23, nzcv", + "bic w20, w20, w21", + "ubfx w20, w20, #15, #1", + "orr w20, w23, w20, lsl #28", + "orr w20, w20, w22, lsl #29", + "str w20, [x28, #728]" + ] + }, + "lock dec dword [rax]": { + "ExpectedInstructionCount": 12, + "Optimal": "No", + "Comment": "GROUP4 0xfe /1", + "ExpectedArm64ASM": [ + "mov w20, #0x1", + "neg w1, w20", + "ldaddal w1, w20, [x4]", + "sub w21, w20, #0x1 (1)", + "strb w20, [x28, #708]", + "strb w21, [x28, #706]", + "ldr w21, [x28, #728]", + "ubfx w21, w21, #29, #1", + "cmp w20, #0x1 (1)", + "mrs x20, nzcv", + "bfi w20, w21, #29, #1", + "str w20, [x28, #728]" + ] + }, + "lock dec qword [rax]": { + "ExpectedInstructionCount": 12, + "Optimal": "Yes", + "Comment": "GROUP4 0xfe /1", + "ExpectedArm64ASM": [ + "mov w20, #0x1", + "neg x1, x20", + "ldaddal x1, x20, [x4]", + "sub x21, x20, #0x1 (1)", + "strb w20, [x28, #708]", + "strb w21, [x28, #706]", + "ldr w21, [x28, #728]", + "ubfx w21, w21, #29, #1", + "cmp x20, #0x1 (1)", + "mrs x20, nzcv", + "bfi w20, w21, #29, #1", + "str w20, [x28, #728]" + ] + }, + "lock inc byte [rax]": { + "ExpectedInstructionCount": 15, + "Optimal": "No", + "Comment": "GROUP4 0xfe /0", + "ExpectedArm64ASM": [ + "mov w20, #0x1", + "ldaddalb w20, w20, [x4]", + "add w21, w20, #0x1 (1)", + "strb w20, [x28, #708]", + "strb w21, [x28, #706]", + "ldr w22, [x28, #728]", + "ubfx w22, w22, #29, #1", + "lsl w23, w21, #24", + "tst w23, w23", + "mrs x23, nzcv", + "bic w20, w21, w20", + "ubfx w20, w20, #7, #1", + "orr w20, w23, w20, lsl #28", + "orr w20, w20, w22, lsl #29", + "str w20, [x28, #728]" + ] + }, + "lock inc word [rax]": { + "ExpectedInstructionCount": 15, + "Optimal": "No", + "Comment": "GROUP4 0xfe /0", + "ExpectedArm64ASM": [ + "mov w20, #0x1", + "ldaddalh w20, w20, [x4]", + "add w21, w20, #0x1 (1)", + "strb w20, [x28, #708]", + "strb w21, [x28, #706]", + "ldr w22, [x28, #728]", + "ubfx w22, w22, #29, #1", + "lsl w23, w21, #16", + "tst w23, w23", + "mrs x23, nzcv", + "bic w20, w21, w20", + "ubfx w20, w20, #15, #1", + "orr w20, w23, w20, lsl #28", + "orr w20, w20, w22, lsl #29", + "str w20, [x28, #728]" + ] + }, + "lock inc dword [rax]": { + "ExpectedInstructionCount": 11, + "Optimal": "Yes", + "Comment": "GROUP4 0xfe /0", + "ExpectedArm64ASM": [ + "mov w20, #0x1", + "ldaddal w20, w20, [x4]", + "add w21, w20, #0x1 (1)", + "strb w20, [x28, #708]", + "strb w21, [x28, #706]", + "ldr w21, [x28, #728]", + "ubfx w21, w21, #29, #1", + "cmn w20, #0x1 (1)", + "mrs x20, nzcv", + "bfi w20, w21, #29, #1", + "str w20, [x28, #728]" + ] + }, + "lock inc qword [rax]": { + "ExpectedInstructionCount": 11, + "Optimal": "Yes", + "Comment": "GROUP4 0xfe /0", + "ExpectedArm64ASM": [ + "mov w20, #0x1", + "ldaddal x20, x20, [x4]", + "add x21, x20, #0x1 (1)", + "strb w20, [x28, #708]", + "strb w21, [x28, #706]", + "ldr w21, [x28, #728]", + "ubfx w21, w21, #29, #1", + "cmn x20, #0x1 (1)", + "mrs x20, nzcv", + "bfi w20, w21, #29, #1", + "str w20, [x28, #728]" + ] + } + } +} diff --git a/unittests/InstructionCountCI/FlagM/H0F38.json b/unittests/InstructionCountCI/FlagM/H0F38.json new file mode 100644 index 000000000..6a3282bb4 --- /dev/null +++ b/unittests/InstructionCountCI/FlagM/H0F38.json @@ -0,0 +1,131 @@ +{ + "Features": { + "Bitness": 64, + "EnabledHostFeatures": [ + "FLAGM", + "FLAGM2" + ], + "DisabledHostFeatures": [ + "SVE128", + "SVE256" + ] + }, + "Instructions": { + "ptest xmm0, xmm1": { + "ExpectedInstructionCount": 19, + "Optimal": "No", + "Comment": [ + "0x66 0x0f 0x38 0x17" + ], + "ExpectedArm64ASM": [ + "and v2.16b, v16.16b, v17.16b", + "bic v3.16b, v17.16b, v16.16b", + "cnt v2.16b, v2.16b", + "cnt v3.16b, v3.16b", + "addv h2, v2.8h", + "addv h3, v3.8h", + "umov w20, v2.h[0]", + "umov w21, v3.h[0]", + "mov w22, #0x0", + "mov w23, #0x1", + "cmp x20, #0x0 (0)", + "cset x20, eq", + "cmp x21, #0x0 (0)", + "cset x21, eq", + "lsl x20, x20, #30", + "orr w20, w20, w21, lsl #29", + "strb w23, [x28, #706]", + "strb w22, [x28, #708]", + "str w20, [x28, #728]" + ] + }, + "adcx eax, ebx": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0x66 0x0f 0x38 0xf6" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "ubfx w21, w20, #29, #1", + "mov w22, w7", + "mov w23, w4", + "add w24, w22, w21", + "add w4, w23, w24", + "cmp w4, w22", + "cset x23, lo", + "cmp w4, w22", + "cset x22, ls", + "cmp x21, #0x1 (1)", + "csel x21, x22, x23, eq", + "bfi w20, w21, #29, #1", + "str w20, [x28, #728]" + ] + }, + "adcx rax, rbx": { + "ExpectedInstructionCount": 12, + "Optimal": "Unknown", + "Comment": [ + "0x66 REX.W 0x0f 0x38 0xf6" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "ubfx w21, w20, #29, #1", + "add x22, x7, x21", + "add x4, x4, x22", + "cmp x4, x7", + "cset x22, lo", + "cmp x4, x7", + "cset x23, ls", + "cmp x21, #0x1 (1)", + "csel x21, x23, x22, eq", + "bfi w20, w21, #29, #1", + "str w20, [x28, #728]" + ] + }, + "adox eax, ebx": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xf3 0x0f 0x38 0xf6" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "ubfx w21, w20, #28, #1", + "mov w22, w7", + "mov w23, w4", + "add w24, w22, w21", + "add w4, w23, w24", + "cmp w4, w22", + "cset x23, lo", + "cmp w4, w22", + "cset x22, ls", + "cmp x21, #0x1 (1)", + "csel x21, x22, x23, eq", + "bfi w20, w21, #28, #1", + "str w20, [x28, #728]" + ] + }, + "adox rax, rbx": { + "ExpectedInstructionCount": 12, + "Optimal": "Unknown", + "Comment": [ + "0xf3 REX.W 0x0f 0x38 0xf6" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "ubfx w21, w20, #28, #1", + "add x22, x7, x21", + "add x4, x4, x22", + "cmp x4, x7", + "cset x22, lo", + "cmp x4, x7", + "cset x23, ls", + "cmp x21, #0x1 (1)", + "csel x21, x23, x22, eq", + "bfi w20, w21, #28, #1", + "str w20, [x28, #728]" + ] + } + } +} diff --git a/unittests/InstructionCountCI/FlagM/Primary.json b/unittests/InstructionCountCI/FlagM/Primary.json new file mode 100644 index 000000000..b60b3f9f9 --- /dev/null +++ b/unittests/InstructionCountCI/FlagM/Primary.json @@ -0,0 +1,3712 @@ +{ + "Features": { + "Bitness": 64, + "EnabledHostFeatures": [ + "FLAGM", + "FLAGM2" + ], + "DisabledHostFeatures": [ + "SVE128", + "SVE256" + ] + }, + "Instructions": { + "add bl, cl": { + "ExpectedInstructionCount": 18, + "Optimal": "No", + "Comment": "0x00", + "ExpectedArm64ASM": [ + "uxtb w20, w5", + "uxtb w21, w7", + "add w22, w21, w20", + "bfxil x7, x22, #0, #8", + "eor w23, w21, w20", + "strb w23, [x28, #708]", + "strb w22, [x28, #706]", + "lsl w23, w22, #24", + "tst w23, w23", + "mrs x23, nzcv", + "ubfx w24, w22, #8, #1", + "orr w23, w23, w24, lsl #29", + "eor w20, w21, w20", + "eor w21, w22, w21", + "bic w20, w21, w20", + "ubfx w20, w20, #7, #1", + "orr w20, w23, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "add bx, cx": { + "ExpectedInstructionCount": 18, + "Optimal": "No", + "Comment": "0x01", + "ExpectedArm64ASM": [ + "uxth w20, w5", + "uxth w21, w7", + "add w22, w21, w20", + "bfxil x7, x22, #0, #16", + "eor w23, w21, w20", + "strb w23, [x28, #708]", + "strb w22, [x28, #706]", + "lsl w23, w22, #16", + "tst w23, w23", + "mrs x23, nzcv", + "ubfx w24, w22, #16, #1", + "orr w23, w23, w24, lsl #29", + "eor w20, w21, w20", + "eor w21, w22, w21", + "bic w20, w21, w20", + "ubfx w20, w20, #15, #1", + "orr w20, w23, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "add ebx, ecx": { + "ExpectedInstructionCount": 9, + "Optimal": "No", + "Comment": "0x01", + "ExpectedArm64ASM": [ + "mov w20, w5", + "mov w21, w7", + "add w7, w21, w20", + "eor w22, w21, w20", + "strb w22, [x28, #708]", + "strb w7, [x28, #706]", + "cmn w21, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "add rbx, rcx": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": "0x01", + "ExpectedArm64ASM": [ + "mov x20, x7", + "add x7, x20, x5", + "eor x21, x20, x5", + "strb w21, [x28, #708]", + "strb w7, [x28, #706]", + "cmn x20, x5", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "db 0x02, 0xcb": { + "ExpectedInstructionCount": 18, + "Optimal": "No", + "Comment": [ + "0x02", + "add bl, cl but modrm.rm as source" + ], + "ExpectedArm64ASM": [ + "uxtb w20, w7", + "uxtb w21, w5", + "add w22, w21, w20", + "bfxil x5, x22, #0, #8", + "eor w23, w21, w20", + "strb w23, [x28, #708]", + "strb w22, [x28, #706]", + "lsl w23, w22, #24", + "tst w23, w23", + "mrs x23, nzcv", + "ubfx w24, w22, #8, #1", + "orr w23, w23, w24, lsl #29", + "eor w20, w21, w20", + "eor w21, w22, w21", + "bic w20, w21, w20", + "ubfx w20, w20, #7, #1", + "orr w20, w23, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "db 0x66, 0x03, 0xcb": { + "ExpectedInstructionCount": 18, + "Optimal": "No", + "Comment": [ + "0x03", + "add bx, cx but modrm.rm as source" + ], + "ExpectedArm64ASM": [ + "uxth w20, w7", + "uxth w21, w5", + "add w22, w21, w20", + "bfxil x5, x22, #0, #16", + "eor w23, w21, w20", + "strb w23, [x28, #708]", + "strb w22, [x28, #706]", + "lsl w23, w22, #16", + "tst w23, w23", + "mrs x23, nzcv", + "ubfx w24, w22, #16, #1", + "orr w23, w23, w24, lsl #29", + "eor w20, w21, w20", + "eor w21, w22, w21", + "bic w20, w21, w20", + "ubfx w20, w20, #15, #1", + "orr w20, w23, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "db 0x03, 0xcb": { + "ExpectedInstructionCount": 9, + "Optimal": "No", + "Comment": [ + "0x03", + "add ebx, ecx but modrm.rm as source" + ], + "ExpectedArm64ASM": [ + "mov w20, w7", + "mov w21, w5", + "add w5, w21, w20", + "eor w22, w21, w20", + "strb w22, [x28, #708]", + "strb w5, [x28, #706]", + "cmn w21, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "db 0x48, 0x03, 0xcb": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": [ + "0x03", + "add rbx, rcx but modrm.rm as source" + ], + "ExpectedArm64ASM": [ + "mov x20, x5", + "add x5, x20, x7", + "eor x21, x20, x7", + "strb w21, [x28, #708]", + "strb w5, [x28, #706]", + "cmn x20, x7", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "add al, 1": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": "0x04", + "ExpectedArm64ASM": [ + "uxtb w20, w4", + "add w21, w20, #0x1 (1)", + "bfxil x4, x21, #0, #8", + "strb w20, [x28, #708]", + "strb w21, [x28, #706]", + "lsl w22, w21, #24", + "tst w22, w22", + "mrs x22, nzcv", + "ubfx w23, w21, #8, #1", + "orr w22, w22, w23, lsl #29", + "bic w20, w21, w20", + "ubfx w20, w20, #7, #1", + "orr w20, w22, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "add ax, 1": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": "0x05", + "ExpectedArm64ASM": [ + "uxth w20, w4", + "add w21, w20, #0x1 (1)", + "bfxil x4, x21, #0, #16", + "strb w20, [x28, #708]", + "strb w21, [x28, #706]", + "lsl w22, w21, #16", + "tst w22, w22", + "mrs x22, nzcv", + "ubfx w23, w21, #16, #1", + "orr w22, w22, w23, lsl #29", + "bic w20, w21, w20", + "ubfx w20, w20, #15, #1", + "orr w20, w22, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "add eax, 1": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": "0x05", + "ExpectedArm64ASM": [ + "mov w20, w4", + "add w4, w20, #0x1 (1)", + "strb w20, [x28, #708]", + "strb w4, [x28, #706]", + "cmn w20, #0x1 (1)", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "add rax, 1": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": "0x05", + "ExpectedArm64ASM": [ + "mov x20, x4", + "add x4, x20, #0x1 (1)", + "strb w20, [x28, #708]", + "strb w4, [x28, #706]", + "cmn x20, #0x1 (1)", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "add al, -1": { + "ExpectedInstructionCount": 15, + "Optimal": "No", + "Comment": "0x04", + "ExpectedArm64ASM": [ + "uxtb w20, w4", + "add w21, w20, #0xff (255)", + "bfxil x4, x21, #0, #8", + "eor w22, w20, #0xff", + "strb w22, [x28, #708]", + "strb w21, [x28, #706]", + "lsl w22, w21, #24", + "tst w22, w22", + "mrs x22, nzcv", + "ubfx w23, w21, #8, #1", + "orr w22, w22, w23, lsl #29", + "bic w20, w20, w21", + "ubfx w20, w20, #7, #1", + "orr w20, w22, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "add ax, -1": { + "ExpectedInstructionCount": 16, + "Optimal": "No", + "Comment": "0x05", + "ExpectedArm64ASM": [ + "mov w20, #0xffff", + "uxth w21, w4", + "add w20, w21, w20", + "bfxil x4, x20, #0, #16", + "eor w22, w21, #0xffff", + "strb w22, [x28, #708]", + "strb w20, [x28, #706]", + "lsl w22, w20, #16", + "tst w22, w22", + "mrs x22, nzcv", + "ubfx w23, w20, #16, #1", + "orr w22, w22, w23, lsl #29", + "bic w20, w21, w20", + "ubfx w20, w20, #15, #1", + "orr w20, w22, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "add eax, -1": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": "0x05", + "ExpectedArm64ASM": [ + "mov w20, #0xffff", + "movk w20, #0xffff, lsl #16", + "mov w21, w4", + "add w4, w21, w20", + "eor w22, w21, w20", + "strb w22, [x28, #708]", + "strb w4, [x28, #706]", + "cmn w21, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "add rax, -1": { + "ExpectedInstructionCount": 9, + "Optimal": "No", + "Comment": "0x05", + "ExpectedArm64ASM": [ + "mov x20, #0xffffffffffffffff", + "mov x21, x4", + "sub x4, x21, #0x1 (1)", + "eor x22, x21, x20", + "strb w22, [x28, #708]", + "strb w4, [x28, #706]", + "cmn x21, x20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "or bl, bh": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": "", + "ExpectedArm64ASM": [ + "lsr w20, w7, #8", + "orr w20, w7, w20", + "bfxil x7, x20, #0, #8", + "strb w20, [x28, #706]", + "lsl w20, w20, #24", + "tst w20, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "or bl, cl": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": "0x08", + "ExpectedArm64ASM": [ + "orr w20, w7, w5", + "bfxil x7, x20, #0, #8", + "strb w20, [x28, #706]", + "lsl w20, w20, #24", + "tst w20, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "or bx, cx": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": "0x09", + "ExpectedArm64ASM": [ + "orr w20, w7, w5", + "bfxil x7, x20, #0, #16", + "strb w20, [x28, #706]", + "lsl w20, w20, #16", + "tst w20, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "or ebx, ecx": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": "0x09", + "ExpectedArm64ASM": [ + "orr w7, w7, w5", + "strb w7, [x28, #706]", + "tst w7, w7", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "or rbx, rcx": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": "0x09", + "ExpectedArm64ASM": [ + "orr x7, x7, x5", + "strb w7, [x28, #706]", + "tst x7, x7", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "db 0x0A, 0xcb": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": [ + "0x0A", + "or bl, cl but modrm.rm as source" + ], + "ExpectedArm64ASM": [ + "orr w20, w5, w7", + "bfxil x5, x20, #0, #8", + "strb w20, [x28, #706]", + "lsl w20, w20, #24", + "tst w20, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "db 0x66, 0x0B, 0xcb": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": [ + "0x0B", + "or bx, cx but modrm.rm as source" + ], + "ExpectedArm64ASM": [ + "orr w20, w5, w7", + "bfxil x5, x20, #0, #16", + "strb w20, [x28, #706]", + "lsl w20, w20, #16", + "tst w20, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "db 0x0B, 0xcb": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": [ + "0x0B", + "or ebx, ecx but modrm.rm as source" + ], + "ExpectedArm64ASM": [ + "orr w5, w5, w7", + "strb w5, [x28, #706]", + "tst w5, w5", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "db 0x48, 0x0B, 0xcb": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": [ + "0x0B", + "or rbx, rcx but modrm.rm as source" + ], + "ExpectedArm64ASM": [ + "orr x5, x5, x7", + "strb w5, [x28, #706]", + "tst x5, x5", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "or al, 1": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": "0x0C", + "ExpectedArm64ASM": [ + "orr w20, w4, #0x1", + "bfxil x4, x20, #0, #8", + "strb w20, [x28, #706]", + "lsl w20, w20, #24", + "tst w20, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "or ax, 1": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": "0x0D", + "ExpectedArm64ASM": [ + "uxth w20, w4", + "orr w20, w20, #0x1", + "bfxil x4, x20, #0, #16", + "strb w20, [x28, #706]", + "lsl w20, w20, #16", + "tst w20, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "or eax, 1": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": "0x0D", + "ExpectedArm64ASM": [ + "mov w20, w4", + "orr w4, w20, #0x1", + "strb w4, [x28, #706]", + "tst w4, w4", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "or rax, 1": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": "0x0D", + "ExpectedArm64ASM": [ + "orr x4, x4, #0x1", + "strb w4, [x28, #706]", + "tst x4, x4", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "or al, -1": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": "0x0C", + "ExpectedArm64ASM": [ + "orr w20, w4, #0xff", + "bfxil x4, x20, #0, #8", + "strb w20, [x28, #706]", + "lsl w20, w20, #24", + "tst w20, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "or ax, -1": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": "0x0D", + "ExpectedArm64ASM": [ + "uxth w20, w4", + "orr w20, w20, #0xffff", + "bfxil x4, x20, #0, #16", + "strb w20, [x28, #706]", + "lsl w20, w20, #16", + "tst w20, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "or eax, -1": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": "0x0D", + "ExpectedArm64ASM": [ + "mov w20, #0xffff", + "movk w20, #0xffff, lsl #16", + "mov w21, w4", + "orr w4, w21, w20", + "strb w4, [x28, #706]", + "tst w4, w4", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "or rax, -1": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": "0x0D", + "ExpectedArm64ASM": [ + "mov x20, #0xffffffffffffffff", + "orr x4, x4, x20", + "strb w4, [x28, #706]", + "tst x4, x4", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "adc bl, cl": { + "ExpectedInstructionCount": 27, + "Optimal": "No", + "Comment": "0x10", + "ExpectedArm64ASM": [ + "uxtb w20, w5", + "ldr w21, [x28, #728]", + "ubfx w21, w21, #29, #1", + "add w22, w20, w21", + "uxtb w23, w7", + "add w22, w23, w22", + "bfxil x7, x22, #0, #8", + "uxtb w22, w22", + "eor w24, w23, w20", + "strb w24, [x28, #708]", + "strb w22, [x28, #706]", + "lsl w24, w22, #24", + "tst w24, w24", + "mrs x24, nzcv", + "cmp w22, w20", + "cset x25, lo", + "cmp w22, w20", + "cset x26, ls", + "cmp x21, #0x1 (1)", + "csel x21, x26, x25, eq", + "orr w21, w24, w21, lsl #29", + "eor w20, w23, w20", + "eor w22, w22, w23", + "bic w20, w22, w20", + "ubfx w20, w20, #7, #1", + "orr w20, w21, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "adc bx, cx": { + "ExpectedInstructionCount": 27, + "Optimal": "No", + "Comment": "0x11", + "ExpectedArm64ASM": [ + "uxth w20, w5", + "ldr w21, [x28, #728]", + "ubfx w21, w21, #29, #1", + "add w22, w20, w21", + "uxth w23, w7", + "add w22, w23, w22", + "bfxil x7, x22, #0, #16", + "uxth w22, w22", + "eor w24, w23, w20", + "strb w24, [x28, #708]", + "strb w22, [x28, #706]", + "lsl w24, w22, #16", + "tst w24, w24", + "mrs x24, nzcv", + "cmp w22, w20", + "cset x25, lo", + "cmp w22, w20", + "cset x26, ls", + "cmp x21, #0x1 (1)", + "csel x21, x26, x25, eq", + "orr w21, w24, w21, lsl #29", + "eor w20, w23, w20", + "eor w22, w22, w23", + "bic w20, w22, w20", + "ubfx w20, w20, #15, #1", + "orr w20, w21, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "adc ebx, ecx": { + "ExpectedInstructionCount": 13, + "Optimal": "No", + "Comment": "0x11", + "ExpectedArm64ASM": [ + "mov w20, w5", + "ldr w21, [x28, #728]", + "ubfx w22, w21, #29, #1", + "add w22, w20, w22", + "mov w23, w7", + "add w7, w23, w22", + "eor w22, w23, w20", + "strb w22, [x28, #708]", + "strb w7, [x28, #706]", + "msr nzcv, x21", + "adcs wzr, w23, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "adc rbx, rcx": { + "ExpectedInstructionCount": 12, + "Optimal": "No", + "Comment": "0x11", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "ubfx w21, w20, #29, #1", + "add x21, x5, x21", + "mov x22, x7", + "add x7, x22, x21", + "eor x21, x22, x5", + "strb w21, [x28, #708]", + "strb w7, [x28, #706]", + "msr nzcv, x20", + "adcs xzr, x22, x5", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "db 0x12, 0xcb": { + "ExpectedInstructionCount": 27, + "Optimal": "No", + "Comment": [ + "0x12", + "adc bl, cl but modrm.rm as source" + ], + "ExpectedArm64ASM": [ + "uxtb w20, w7", + "ldr w21, [x28, #728]", + "ubfx w21, w21, #29, #1", + "add w22, w20, w21", + "uxtb w23, w5", + "add w22, w23, w22", + "bfxil x5, x22, #0, #8", + "uxtb w22, w22", + "eor w24, w23, w20", + "strb w24, [x28, #708]", + "strb w22, [x28, #706]", + "lsl w24, w22, #24", + "tst w24, w24", + "mrs x24, nzcv", + "cmp w22, w20", + "cset x25, lo", + "cmp w22, w20", + "cset x26, ls", + "cmp x21, #0x1 (1)", + "csel x21, x26, x25, eq", + "orr w21, w24, w21, lsl #29", + "eor w20, w23, w20", + "eor w22, w22, w23", + "bic w20, w22, w20", + "ubfx w20, w20, #7, #1", + "orr w20, w21, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "db 0x66, 0x13, 0xcb": { + "ExpectedInstructionCount": 27, + "Optimal": "No", + "Comment": [ + "0x13", + "adc bx, cx but modrm.rm as source" + ], + "ExpectedArm64ASM": [ + "uxth w20, w7", + "ldr w21, [x28, #728]", + "ubfx w21, w21, #29, #1", + "add w22, w20, w21", + "uxth w23, w5", + "add w22, w23, w22", + "bfxil x5, x22, #0, #16", + "uxth w22, w22", + "eor w24, w23, w20", + "strb w24, [x28, #708]", + "strb w22, [x28, #706]", + "lsl w24, w22, #16", + "tst w24, w24", + "mrs x24, nzcv", + "cmp w22, w20", + "cset x25, lo", + "cmp w22, w20", + "cset x26, ls", + "cmp x21, #0x1 (1)", + "csel x21, x26, x25, eq", + "orr w21, w24, w21, lsl #29", + "eor w20, w23, w20", + "eor w22, w22, w23", + "bic w20, w22, w20", + "ubfx w20, w20, #15, #1", + "orr w20, w21, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "db 0x13, 0xcb": { + "ExpectedInstructionCount": 13, + "Optimal": "No", + "Comment": [ + "0x13", + "adc ebx, ecx but modrm.rm as source" + ], + "ExpectedArm64ASM": [ + "mov w20, w7", + "ldr w21, [x28, #728]", + "ubfx w22, w21, #29, #1", + "add w22, w20, w22", + "mov w23, w5", + "add w5, w23, w22", + "eor w22, w23, w20", + "strb w22, [x28, #708]", + "strb w5, [x28, #706]", + "msr nzcv, x21", + "adcs wzr, w23, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "db 0x48, 0x13, 0xcb": { + "ExpectedInstructionCount": 12, + "Optimal": "No", + "Comment": [ + "0x13", + "adc rbx, rcx but modrm.rm as source" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "ubfx w21, w20, #29, #1", + "add x21, x7, x21", + "mov x22, x5", + "add x5, x22, x21", + "eor x21, x22, x7", + "strb w21, [x28, #708]", + "strb w5, [x28, #706]", + "msr nzcv, x20", + "adcs xzr, x22, x7", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "adc al, 1": { + "ExpectedInstructionCount": 24, + "Optimal": "No", + "Comment": "0x14", + "ExpectedArm64ASM": [ + "mov w20, #0x1", + "ldr w21, [x28, #728]", + "ubfx w21, w21, #29, #1", + "add w20, w20, w21", + "uxtb w22, w4", + "add w20, w22, w20", + "bfxil x4, x20, #0, #8", + "uxtb w20, w20", + "strb w22, [x28, #708]", + "strb w20, [x28, #706]", + "lsl w23, w20, #24", + "tst w23, w23", + "mrs x23, nzcv", + "cmp w20, #0x1 (1)", + "cset x24, lo", + "cmp w20, #0x1 (1)", + "cset x25, ls", + "cmp x21, #0x1 (1)", + "csel x21, x25, x24, eq", + "orr w21, w23, w21, lsl #29", + "bic w20, w20, w22", + "ubfx w20, w20, #7, #1", + "orr w20, w21, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "adc ax, 1": { + "ExpectedInstructionCount": 24, + "Optimal": "No", + "Comment": "0x15", + "ExpectedArm64ASM": [ + "mov w20, #0x1", + "ldr w21, [x28, #728]", + "ubfx w21, w21, #29, #1", + "add w20, w20, w21", + "uxth w22, w4", + "add w20, w22, w20", + "bfxil x4, x20, #0, #16", + "uxth w20, w20", + "strb w22, [x28, #708]", + "strb w20, [x28, #706]", + "lsl w23, w20, #16", + "tst w23, w23", + "mrs x23, nzcv", + "cmp w20, #0x1 (1)", + "cset x24, lo", + "cmp w20, #0x1 (1)", + "cset x25, ls", + "cmp x21, #0x1 (1)", + "csel x21, x25, x24, eq", + "orr w21, w23, w21, lsl #29", + "bic w20, w20, w22", + "ubfx w20, w20, #15, #1", + "orr w20, w21, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "adc eax, 1": { + "ExpectedInstructionCount": 12, + "Optimal": "No", + "Comment": "0x15", + "ExpectedArm64ASM": [ + "mov w20, #0x1", + "ldr w21, [x28, #728]", + "ubfx w22, w21, #29, #1", + "add w22, w20, w22", + "mov w23, w4", + "add w4, w23, w22", + "strb w23, [x28, #708]", + "strb w4, [x28, #706]", + "msr nzcv, x21", + "adcs wzr, w23, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "adc rax, 1": { + "ExpectedInstructionCount": 12, + "Optimal": "No", + "Comment": "0x15", + "ExpectedArm64ASM": [ + "mov w20, #0x1", + "ldr w21, [x28, #728]", + "ubfx w22, w21, #29, #1", + "add x22, x20, x22", + "mov x23, x4", + "add x4, x23, x22", + "strb w23, [x28, #708]", + "strb w4, [x28, #706]", + "msr nzcv, x21", + "adcs xzr, x23, x20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "adc al, -1": { + "ExpectedInstructionCount": 25, + "Optimal": "No", + "Comment": "0x14", + "ExpectedArm64ASM": [ + "mov w20, #0xff", + "ldr w21, [x28, #728]", + "ubfx w21, w21, #29, #1", + "add w20, w20, w21", + "uxtb w22, w4", + "add w20, w22, w20", + "bfxil x4, x20, #0, #8", + "uxtb w20, w20", + "eor w23, w22, #0xff", + "strb w23, [x28, #708]", + "strb w20, [x28, #706]", + "lsl w23, w20, #24", + "tst w23, w23", + "mrs x23, nzcv", + "cmp w20, #0xff (255)", + "cset x24, lo", + "cmp w20, #0xff (255)", + "cset x25, ls", + "cmp x21, #0x1 (1)", + "csel x21, x25, x24, eq", + "orr w21, w23, w21, lsl #29", + "bic w20, w22, w20", + "ubfx w20, w20, #7, #1", + "orr w20, w21, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "adc ax, -1": { + "ExpectedInstructionCount": 25, + "Optimal": "No", + "Comment": "0x15", + "ExpectedArm64ASM": [ + "mov w20, #0xffff", + "ldr w21, [x28, #728]", + "ubfx w21, w21, #29, #1", + "add w22, w20, w21", + "uxth w23, w4", + "add w22, w23, w22", + "bfxil x4, x22, #0, #16", + "uxth w22, w22", + "eor w24, w23, #0xffff", + "strb w24, [x28, #708]", + "strb w22, [x28, #706]", + "lsl w24, w22, #16", + "tst w24, w24", + "mrs x24, nzcv", + "cmp w22, w20", + "cset x25, lo", + "cmp w22, w20", + "cset x20, ls", + "cmp x21, #0x1 (1)", + "csel x20, x20, x25, eq", + "orr w20, w24, w20, lsl #29", + "bic w21, w23, w22", + "ubfx w21, w21, #15, #1", + "orr w20, w20, w21, lsl #28", + "str w20, [x28, #728]" + ] + }, + "adc eax, -1": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": "0x15", + "ExpectedArm64ASM": [ + "mov w20, #0xffff", + "movk w20, #0xffff, lsl #16", + "ldr w21, [x28, #728]", + "ubfx w22, w21, #29, #1", + "add w22, w20, w22", + "mov w23, w4", + "add w4, w23, w22", + "eor w22, w23, w20", + "strb w22, [x28, #708]", + "strb w4, [x28, #706]", + "msr nzcv, x21", + "adcs wzr, w23, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "adc rax, -1": { + "ExpectedInstructionCount": 13, + "Optimal": "No", + "Comment": "0x15", + "ExpectedArm64ASM": [ + "mov x20, #0xffffffffffffffff", + "ldr w21, [x28, #728]", + "ubfx w22, w21, #29, #1", + "add x22, x20, x22", + "mov x23, x4", + "add x4, x23, x22", + "eor x22, x23, x20", + "strb w22, [x28, #708]", + "strb w4, [x28, #706]", + "msr nzcv, x21", + "adcs xzr, x23, x20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "sbb bl, cl": { + "ExpectedInstructionCount": 27, + "Optimal": "No", + "Comment": "0x18", + "ExpectedArm64ASM": [ + "uxtb w20, w5", + "ldr w21, [x28, #728]", + "ubfx w21, w21, #29, #1", + "add w22, w20, w21", + "uxtb w23, w7", + "sub w22, w23, w22", + "bfxil x7, x22, #0, #8", + "uxtb w22, w22", + "eor w24, w23, w20", + "strb w24, [x28, #708]", + "strb w22, [x28, #706]", + "lsl w24, w22, #24", + "tst w24, w24", + "mrs x24, nzcv", + "cmp w22, w23", + "cset x25, hi", + "cmp w22, w23", + "cset x26, hs", + "cmp x21, #0x1 (1)", + "csel x21, x26, x25, eq", + "orr w21, w24, w21, lsl #29", + "eor w20, w23, w20", + "eor w22, w22, w23", + "and w20, w22, w20", + "ubfx w20, w20, #7, #1", + "orr w20, w21, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "sbb bx, cx": { + "ExpectedInstructionCount": 27, + "Optimal": "No", + "Comment": "0x19", + "ExpectedArm64ASM": [ + "uxth w20, w5", + "ldr w21, [x28, #728]", + "ubfx w21, w21, #29, #1", + "add w22, w20, w21", + "uxth w23, w7", + "sub w22, w23, w22", + "bfxil x7, x22, #0, #16", + "uxth w22, w22", + "eor w24, w23, w20", + "strb w24, [x28, #708]", + "strb w22, [x28, #706]", + "lsl w24, w22, #16", + "tst w24, w24", + "mrs x24, nzcv", + "cmp w22, w23", + "cset x25, hi", + "cmp w22, w23", + "cset x26, hs", + "cmp x21, #0x1 (1)", + "csel x21, x26, x25, eq", + "orr w21, w24, w21, lsl #29", + "eor w20, w23, w20", + "eor w22, w22, w23", + "and w20, w22, w20", + "ubfx w20, w20, #15, #1", + "orr w20, w21, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "sbb ebx, ecx": { + "ExpectedInstructionCount": 15, + "Optimal": "No", + "Comment": "0x19", + "ExpectedArm64ASM": [ + "mov w20, w5", + "ldr w21, [x28, #728]", + "ubfx w22, w21, #29, #1", + "add w22, w20, w22", + "mov w23, w7", + "sub w7, w23, w22", + "eor w22, w23, w20", + "strb w22, [x28, #708]", + "strb w7, [x28, #706]", + "eor w0, w21, #0x20000000", + "msr nzcv, x0", + "sbcs wzr, w23, w20", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "str w20, [x28, #728]" + ] + }, + "sbb rbx, rcx": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": "0x19", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "ubfx w21, w20, #29, #1", + "add x21, x5, x21", + "mov x22, x7", + "sub x7, x22, x21", + "eor x21, x22, x5", + "strb w21, [x28, #708]", + "strb w7, [x28, #706]", + "eor w0, w20, #0x20000000", + "msr nzcv, x0", + "sbcs xzr, x22, x5", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "str w20, [x28, #728]" + ] + }, + "db 0x1A, 0xcb": { + "ExpectedInstructionCount": 27, + "Optimal": "No", + "Comment": [ + "0x1A", + "sbb bl, cl but modrm.rm as source" + ], + "ExpectedArm64ASM": [ + "uxtb w20, w7", + "ldr w21, [x28, #728]", + "ubfx w21, w21, #29, #1", + "add w22, w20, w21", + "uxtb w23, w5", + "sub w22, w23, w22", + "bfxil x5, x22, #0, #8", + "uxtb w22, w22", + "eor w24, w23, w20", + "strb w24, [x28, #708]", + "strb w22, [x28, #706]", + "lsl w24, w22, #24", + "tst w24, w24", + "mrs x24, nzcv", + "cmp w22, w23", + "cset x25, hi", + "cmp w22, w23", + "cset x26, hs", + "cmp x21, #0x1 (1)", + "csel x21, x26, x25, eq", + "orr w21, w24, w21, lsl #29", + "eor w20, w23, w20", + "eor w22, w22, w23", + "and w20, w22, w20", + "ubfx w20, w20, #7, #1", + "orr w20, w21, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "db 0x66, 0x1B, 0xcb": { + "ExpectedInstructionCount": 27, + "Optimal": "No", + "Comment": [ + "0x1B", + "sbb bx, cx but modrm.rm as source" + ], + "ExpectedArm64ASM": [ + "uxth w20, w7", + "ldr w21, [x28, #728]", + "ubfx w21, w21, #29, #1", + "add w22, w20, w21", + "uxth w23, w5", + "sub w22, w23, w22", + "bfxil x5, x22, #0, #16", + "uxth w22, w22", + "eor w24, w23, w20", + "strb w24, [x28, #708]", + "strb w22, [x28, #706]", + "lsl w24, w22, #16", + "tst w24, w24", + "mrs x24, nzcv", + "cmp w22, w23", + "cset x25, hi", + "cmp w22, w23", + "cset x26, hs", + "cmp x21, #0x1 (1)", + "csel x21, x26, x25, eq", + "orr w21, w24, w21, lsl #29", + "eor w20, w23, w20", + "eor w22, w22, w23", + "and w20, w22, w20", + "ubfx w20, w20, #15, #1", + "orr w20, w21, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "db 0x1B, 0xcb": { + "ExpectedInstructionCount": 15, + "Optimal": "No", + "Comment": [ + "0x1B", + "sbb ebx, ecx but modrm.rm as source" + ], + "ExpectedArm64ASM": [ + "mov w20, w7", + "ldr w21, [x28, #728]", + "ubfx w22, w21, #29, #1", + "add w22, w20, w22", + "mov w23, w5", + "sub w5, w23, w22", + "eor w22, w23, w20", + "strb w22, [x28, #708]", + "strb w5, [x28, #706]", + "eor w0, w21, #0x20000000", + "msr nzcv, x0", + "sbcs wzr, w23, w20", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "str w20, [x28, #728]" + ] + }, + "db 0x48, 0x1B, 0xcb": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0x1B", + "sbb rbx, rcx but modrm.rm as source" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "ubfx w21, w20, #29, #1", + "add x21, x7, x21", + "mov x22, x5", + "sub x5, x22, x21", + "eor x21, x22, x7", + "strb w21, [x28, #708]", + "strb w5, [x28, #706]", + "eor w0, w20, #0x20000000", + "msr nzcv, x0", + "sbcs xzr, x22, x7", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "str w20, [x28, #728]" + ] + }, + "sbb al, 1": { + "ExpectedInstructionCount": 24, + "Optimal": "No", + "Comment": "0x1C", + "ExpectedArm64ASM": [ + "mov w20, #0x1", + "ldr w21, [x28, #728]", + "ubfx w21, w21, #29, #1", + "add w20, w20, w21", + "uxtb w22, w4", + "sub w20, w22, w20", + "bfxil x4, x20, #0, #8", + "uxtb w20, w20", + "strb w22, [x28, #708]", + "strb w20, [x28, #706]", + "lsl w23, w20, #24", + "tst w23, w23", + "mrs x23, nzcv", + "cmp w20, w22", + "cset x24, hi", + "cmp w20, w22", + "cset x25, hs", + "cmp x21, #0x1 (1)", + "csel x21, x25, x24, eq", + "orr w21, w23, w21, lsl #29", + "bic w20, w22, w20", + "ubfx w20, w20, #7, #1", + "orr w20, w21, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "sbb ax, 1": { + "ExpectedInstructionCount": 24, + "Optimal": "No", + "Comment": "0x1D", + "ExpectedArm64ASM": [ + "mov w20, #0x1", + "ldr w21, [x28, #728]", + "ubfx w21, w21, #29, #1", + "add w20, w20, w21", + "uxth w22, w4", + "sub w20, w22, w20", + "bfxil x4, x20, #0, #16", + "uxth w20, w20", + "strb w22, [x28, #708]", + "strb w20, [x28, #706]", + "lsl w23, w20, #16", + "tst w23, w23", + "mrs x23, nzcv", + "cmp w20, w22", + "cset x24, hi", + "cmp w20, w22", + "cset x25, hs", + "cmp x21, #0x1 (1)", + "csel x21, x25, x24, eq", + "orr w21, w23, w21, lsl #29", + "bic w20, w22, w20", + "ubfx w20, w20, #15, #1", + "orr w20, w21, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "sbb eax, 1": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": "0x1D", + "ExpectedArm64ASM": [ + "mov w20, #0x1", + "ldr w21, [x28, #728]", + "ubfx w22, w21, #29, #1", + "add w22, w20, w22", + "mov w23, w4", + "sub w4, w23, w22", + "strb w23, [x28, #708]", + "strb w4, [x28, #706]", + "eor w0, w21, #0x20000000", + "msr nzcv, x0", + "sbcs wzr, w23, w20", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "str w20, [x28, #728]" + ] + }, + "sbb rax, 1": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": "0x1D", + "ExpectedArm64ASM": [ + "mov w20, #0x1", + "ldr w21, [x28, #728]", + "ubfx w22, w21, #29, #1", + "add x22, x20, x22", + "mov x23, x4", + "sub x4, x23, x22", + "strb w23, [x28, #708]", + "strb w4, [x28, #706]", + "eor w0, w21, #0x20000000", + "msr nzcv, x0", + "sbcs xzr, x23, x20", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "str w20, [x28, #728]" + ] + }, + "sbb al, -1": { + "ExpectedInstructionCount": 25, + "Optimal": "No", + "Comment": "0x1C", + "ExpectedArm64ASM": [ + "mov w20, #0xff", + "ldr w21, [x28, #728]", + "ubfx w21, w21, #29, #1", + "add w20, w20, w21", + "uxtb w22, w4", + "sub w20, w22, w20", + "bfxil x4, x20, #0, #8", + "uxtb w20, w20", + "eor w23, w22, #0xff", + "strb w23, [x28, #708]", + "strb w20, [x28, #706]", + "lsl w23, w20, #24", + "tst w23, w23", + "mrs x23, nzcv", + "cmp w20, w22", + "cset x24, hi", + "cmp w20, w22", + "cset x25, hs", + "cmp x21, #0x1 (1)", + "csel x21, x25, x24, eq", + "orr w21, w23, w21, lsl #29", + "bic w20, w20, w22", + "ubfx w20, w20, #7, #1", + "orr w20, w21, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "sbb ax, -1": { + "ExpectedInstructionCount": 25, + "Optimal": "No", + "Comment": "0x1D", + "ExpectedArm64ASM": [ + "mov w20, #0xffff", + "ldr w21, [x28, #728]", + "ubfx w21, w21, #29, #1", + "add w20, w20, w21", + "uxth w22, w4", + "sub w20, w22, w20", + "bfxil x4, x20, #0, #16", + "uxth w20, w20", + "eor w23, w22, #0xffff", + "strb w23, [x28, #708]", + "strb w20, [x28, #706]", + "lsl w23, w20, #16", + "tst w23, w23", + "mrs x23, nzcv", + "cmp w20, w22", + "cset x24, hi", + "cmp w20, w22", + "cset x25, hs", + "cmp x21, #0x1 (1)", + "csel x21, x25, x24, eq", + "orr w21, w23, w21, lsl #29", + "bic w20, w20, w22", + "ubfx w20, w20, #15, #1", + "orr w20, w21, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "sbb eax, -1": { + "ExpectedInstructionCount": 16, + "Optimal": "No", + "Comment": "0x1D", + "ExpectedArm64ASM": [ + "mov w20, #0xffff", + "movk w20, #0xffff, lsl #16", + "ldr w21, [x28, #728]", + "ubfx w22, w21, #29, #1", + "add w22, w20, w22", + "mov w23, w4", + "sub w4, w23, w22", + "eor w22, w23, w20", + "strb w22, [x28, #708]", + "strb w4, [x28, #706]", + "eor w0, w21, #0x20000000", + "msr nzcv, x0", + "sbcs wzr, w23, w20", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "str w20, [x28, #728]" + ] + }, + "sbb rax, -1": { + "ExpectedInstructionCount": 15, + "Optimal": "No", + "Comment": "0x1D", + "ExpectedArm64ASM": [ + "mov x20, #0xffffffffffffffff", + "ldr w21, [x28, #728]", + "ubfx w22, w21, #29, #1", + "add x22, x20, x22", + "mov x23, x4", + "sub x4, x23, x22", + "eor x22, x23, x20", + "strb w22, [x28, #708]", + "strb w4, [x28, #706]", + "eor w0, w21, #0x20000000", + "msr nzcv, x0", + "sbcs xzr, x23, x20", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "str w20, [x28, #728]" + ] + }, + "and bl, cl": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": "0x20", + "ExpectedArm64ASM": [ + "and w20, w7, w5", + "bfxil x7, x20, #0, #8", + "strb w20, [x28, #706]", + "lsl w20, w20, #24", + "tst w20, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "and bx, cx": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": "0x21", + "ExpectedArm64ASM": [ + "and w20, w7, w5", + "bfxil x7, x20, #0, #16", + "strb w20, [x28, #706]", + "lsl w20, w20, #16", + "tst w20, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "and ebx, ecx": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": "0x21", + "ExpectedArm64ASM": [ + "and w7, w7, w5", + "strb w7, [x28, #706]", + "tst w7, w7", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "and rbx, rcx": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": "0x21", + "ExpectedArm64ASM": [ + "and x7, x7, x5", + "strb w7, [x28, #706]", + "tst x7, x7", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "db 0x22, 0xcb": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": [ + "0x22", + "and bl, cl but modrm.rm as source" + ], + "ExpectedArm64ASM": [ + "and w20, w5, w7", + "bfxil x5, x20, #0, #8", + "strb w20, [x28, #706]", + "lsl w20, w20, #24", + "tst w20, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "db 0x66, 0x23, 0xcb": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": [ + "0x23", + "and bx, cx but modrm.rm as source" + ], + "ExpectedArm64ASM": [ + "and w20, w5, w7", + "bfxil x5, x20, #0, #16", + "strb w20, [x28, #706]", + "lsl w20, w20, #16", + "tst w20, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "db 0x23, 0xcb": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": [ + "0x23", + "and ebx, ecx but modrm.rm as source" + ], + "ExpectedArm64ASM": [ + "and w5, w5, w7", + "strb w5, [x28, #706]", + "tst w5, w5", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "db 0x48, 0x23, 0xcb": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": [ + "0x23", + "and rbx, rcx but modrm.rm as source" + ], + "ExpectedArm64ASM": [ + "and x5, x5, x7", + "strb w5, [x28, #706]", + "tst x5, x5", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "and al, 1": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": "0x24", + "ExpectedArm64ASM": [ + "and w20, w4, #0x1", + "bfxil x4, x20, #0, #8", + "strb w20, [x28, #706]", + "lsl w20, w20, #24", + "tst w20, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "and ax, 1": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": "0x25", + "ExpectedArm64ASM": [ + "uxth w20, w4", + "and w20, w20, #0x1", + "bfxil x4, x20, #0, #16", + "strb w20, [x28, #706]", + "lsl w20, w20, #16", + "tst w20, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "and eax, 1": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": "0x25", + "ExpectedArm64ASM": [ + "mov w20, w4", + "and w4, w20, #0x1", + "strb w4, [x28, #706]", + "tst w4, w4", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "and rax, 1": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": "0x25", + "ExpectedArm64ASM": [ + "and x4, x4, #0x1", + "strb w4, [x28, #706]", + "tst x4, x4", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "and al, -1": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": "0x24", + "ExpectedArm64ASM": [ + "and w20, w4, #0xff", + "bfxil x4, x20, #0, #8", + "strb w20, [x28, #706]", + "lsl w20, w20, #24", + "tst w20, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "and ax, -1": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": "0x25", + "ExpectedArm64ASM": [ + "uxth w20, w4", + "and w20, w20, #0xffff", + "bfxil x4, x20, #0, #16", + "strb w20, [x28, #706]", + "lsl w20, w20, #16", + "tst w20, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "and eax, -1": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": "0x25", + "ExpectedArm64ASM": [ + "mov w20, #0xffff", + "movk w20, #0xffff, lsl #16", + "mov w21, w4", + "and w4, w21, w20", + "strb w4, [x28, #706]", + "tst w4, w4", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "and rax, -1": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": "0x25", + "ExpectedArm64ASM": [ + "mov x20, #0xffffffffffffffff", + "and x4, x4, x20", + "strb w4, [x28, #706]", + "tst x4, x4", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "sub bl, cl": { + "ExpectedInstructionCount": 18, + "Optimal": "No", + "Comment": "0x28", + "ExpectedArm64ASM": [ + "uxtb w20, w5", + "uxtb w21, w7", + "sub w22, w21, w20", + "bfxil x7, x22, #0, #8", + "eor w23, w21, w20", + "strb w23, [x28, #708]", + "strb w22, [x28, #706]", + "lsl w23, w22, #24", + "tst w23, w23", + "mrs x23, nzcv", + "ubfx w24, w22, #8, #1", + "orr w23, w23, w24, lsl #29", + "eor w20, w21, w20", + "eor w21, w22, w21", + "and w20, w21, w20", + "ubfx w20, w20, #7, #1", + "orr w20, w23, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "sub bx, cx": { + "ExpectedInstructionCount": 18, + "Optimal": "No", + "Comment": "0x29", + "ExpectedArm64ASM": [ + "uxth w20, w5", + "uxth w21, w7", + "sub w22, w21, w20", + "bfxil x7, x22, #0, #16", + "eor w23, w21, w20", + "strb w23, [x28, #708]", + "strb w22, [x28, #706]", + "lsl w23, w22, #16", + "tst w23, w23", + "mrs x23, nzcv", + "ubfx w24, w22, #16, #1", + "orr w23, w23, w24, lsl #29", + "eor w20, w21, w20", + "eor w21, w22, w21", + "and w20, w21, w20", + "ubfx w20, w20, #15, #1", + "orr w20, w23, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "sub ebx, ecx": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": "0x29", + "ExpectedArm64ASM": [ + "mov w20, w5", + "mov w21, w7", + "sub w7, w21, w20", + "eor w22, w21, w20", + "strb w22, [x28, #708]", + "strb w7, [x28, #706]", + "cmp w21, w20", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "str w20, [x28, #728]" + ] + }, + "sub rbx, rcx": { + "ExpectedInstructionCount": 9, + "Optimal": "No", + "Comment": "0x29", + "ExpectedArm64ASM": [ + "mov x20, x7", + "sub x7, x20, x5", + "eor x21, x20, x5", + "strb w21, [x28, #708]", + "strb w7, [x28, #706]", + "cmp x20, x5", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "str w20, [x28, #728]" + ] + }, + "db 0x2A, 0xcb": { + "ExpectedInstructionCount": 18, + "Optimal": "No", + "Comment": [ + "0x2A", + "sub bl, cl but modrm.rm as source" + ], + "ExpectedArm64ASM": [ + "uxtb w20, w7", + "uxtb w21, w5", + "sub w22, w21, w20", + "bfxil x5, x22, #0, #8", + "eor w23, w21, w20", + "strb w23, [x28, #708]", + "strb w22, [x28, #706]", + "lsl w23, w22, #24", + "tst w23, w23", + "mrs x23, nzcv", + "ubfx w24, w22, #8, #1", + "orr w23, w23, w24, lsl #29", + "eor w20, w21, w20", + "eor w21, w22, w21", + "and w20, w21, w20", + "ubfx w20, w20, #7, #1", + "orr w20, w23, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "db 0x66, 0x2B, 0xcb": { + "ExpectedInstructionCount": 18, + "Optimal": "No", + "Comment": [ + "0x2B", + "sub bx, cx but modrm.rm as source" + ], + "ExpectedArm64ASM": [ + "uxth w20, w7", + "uxth w21, w5", + "sub w22, w21, w20", + "bfxil x5, x22, #0, #16", + "eor w23, w21, w20", + "strb w23, [x28, #708]", + "strb w22, [x28, #706]", + "lsl w23, w22, #16", + "tst w23, w23", + "mrs x23, nzcv", + "ubfx w24, w22, #16, #1", + "orr w23, w23, w24, lsl #29", + "eor w20, w21, w20", + "eor w21, w22, w21", + "and w20, w21, w20", + "ubfx w20, w20, #15, #1", + "orr w20, w23, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "db 0x2B, 0xcb": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "0x2B", + "sub ebx, ecx but modrm.rm as source" + ], + "ExpectedArm64ASM": [ + "mov w20, w7", + "mov w21, w5", + "sub w5, w21, w20", + "eor w22, w21, w20", + "strb w22, [x28, #708]", + "strb w5, [x28, #706]", + "cmp w21, w20", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "str w20, [x28, #728]" + ] + }, + "db 0x48, 0x2B, 0xcb": { + "ExpectedInstructionCount": 9, + "Optimal": "No", + "Comment": [ + "0x2B", + "sub rbx, rcx but modrm.rm as source" + ], + "ExpectedArm64ASM": [ + "mov x20, x5", + "sub x5, x20, x7", + "eor x21, x20, x7", + "strb w21, [x28, #708]", + "strb w5, [x28, #706]", + "cmp x20, x7", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "str w20, [x28, #728]" + ] + }, + "sub al, 1": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": "0x2C", + "ExpectedArm64ASM": [ + "uxtb w20, w4", + "sub w21, w20, #0x1 (1)", + "bfxil x4, x21, #0, #8", + "strb w20, [x28, #708]", + "strb w21, [x28, #706]", + "lsl w22, w21, #24", + "tst w22, w22", + "mrs x22, nzcv", + "ubfx w23, w21, #8, #1", + "orr w22, w22, w23, lsl #29", + "bic w20, w20, w21", + "ubfx w20, w20, #7, #1", + "orr w20, w22, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "sub ax, 1": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": "0x2D", + "ExpectedArm64ASM": [ + "uxth w20, w4", + "sub w21, w20, #0x1 (1)", + "bfxil x4, x21, #0, #16", + "strb w20, [x28, #708]", + "strb w21, [x28, #706]", + "lsl w22, w21, #16", + "tst w22, w22", + "mrs x22, nzcv", + "ubfx w23, w21, #16, #1", + "orr w22, w22, w23, lsl #29", + "bic w20, w20, w21", + "ubfx w20, w20, #15, #1", + "orr w20, w22, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "sub eax, 1": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": "0x2D", + "ExpectedArm64ASM": [ + "mov w20, w4", + "sub w4, w20, #0x1 (1)", + "strb w20, [x28, #708]", + "strb w4, [x28, #706]", + "cmp w20, #0x1 (1)", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "str w20, [x28, #728]" + ] + }, + "sub rax, 1": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": "0x2D", + "ExpectedArm64ASM": [ + "mov x20, x4", + "sub x4, x20, #0x1 (1)", + "strb w20, [x28, #708]", + "strb w4, [x28, #706]", + "cmp x20, #0x1 (1)", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "str w20, [x28, #728]" + ] + }, + "sub al, -1": { + "ExpectedInstructionCount": 15, + "Optimal": "No", + "Comment": "0x2C", + "ExpectedArm64ASM": [ + "uxtb w20, w4", + "sub w21, w20, #0xff (255)", + "bfxil x4, x21, #0, #8", + "eor w22, w20, #0xff", + "strb w22, [x28, #708]", + "strb w21, [x28, #706]", + "lsl w22, w21, #24", + "tst w22, w22", + "mrs x22, nzcv", + "ubfx w23, w21, #8, #1", + "orr w22, w22, w23, lsl #29", + "bic w20, w21, w20", + "ubfx w20, w20, #7, #1", + "orr w20, w22, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "sub ax, -1": { + "ExpectedInstructionCount": 16, + "Optimal": "No", + "Comment": "0x2D", + "ExpectedArm64ASM": [ + "mov w20, #0xffff", + "uxth w21, w4", + "sub w20, w21, w20", + "bfxil x4, x20, #0, #16", + "eor w22, w21, #0xffff", + "strb w22, [x28, #708]", + "strb w20, [x28, #706]", + "lsl w22, w20, #16", + "tst w22, w22", + "mrs x22, nzcv", + "ubfx w23, w20, #16, #1", + "orr w22, w22, w23, lsl #29", + "bic w20, w20, w21", + "ubfx w20, w20, #15, #1", + "orr w20, w22, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "sub eax, -1": { + "ExpectedInstructionCount": 11, + "Optimal": "No", + "Comment": "0x2D", + "ExpectedArm64ASM": [ + "mov w20, #0xffff", + "movk w20, #0xffff, lsl #16", + "mov w21, w4", + "sub w4, w21, w20", + "eor w22, w21, w20", + "strb w22, [x28, #708]", + "strb w4, [x28, #706]", + "cmp w21, w20", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "str w20, [x28, #728]" + ] + }, + "sub rax, -1": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": "0x2D", + "ExpectedArm64ASM": [ + "mov x20, #0xffffffffffffffff", + "mov x21, x4", + "sub x4, x21, x20", + "eor x22, x21, x20", + "strb w22, [x28, #708]", + "strb w4, [x28, #706]", + "cmp x21, x20", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "str w20, [x28, #728]" + ] + }, + "xor bl, cl": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": "0x30", + "ExpectedArm64ASM": [ + "eor w20, w7, w5", + "bfxil x7, x20, #0, #8", + "strb w20, [x28, #706]", + "lsl w20, w20, #24", + "tst w20, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "xor bx, cx": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": "0x31", + "ExpectedArm64ASM": [ + "eor w20, w7, w5", + "bfxil x7, x20, #0, #16", + "strb w20, [x28, #706]", + "lsl w20, w20, #16", + "tst w20, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "xor ebx, ecx": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": "0x31", + "ExpectedArm64ASM": [ + "eor w7, w7, w5", + "strb w7, [x28, #706]", + "tst w7, w7", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "xor rbx, rcx": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": "0x31", + "ExpectedArm64ASM": [ + "eor x7, x7, x5", + "strb w7, [x28, #706]", + "tst x7, x7", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "db 0x32, 0xcb": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": [ + "0x32", + "xor bl, cl but modrm.rm as source" + ], + "ExpectedArm64ASM": [ + "eor w20, w5, w7", + "bfxil x5, x20, #0, #8", + "strb w20, [x28, #706]", + "lsl w20, w20, #24", + "tst w20, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "db 0x66, 0x33, 0xcb": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": [ + "0x33", + "xor bx, cx but modrm.rm as source" + ], + "ExpectedArm64ASM": [ + "eor w20, w5, w7", + "bfxil x5, x20, #0, #16", + "strb w20, [x28, #706]", + "lsl w20, w20, #16", + "tst w20, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "db 0x33, 0xcb": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": [ + "0x33", + "xor ebx, ecx but modrm.rm as source" + ], + "ExpectedArm64ASM": [ + "eor w5, w5, w7", + "strb w5, [x28, #706]", + "tst w5, w5", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "db 0x48, 0x33, 0xcb": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": [ + "0x33", + "xor rbx, rcx but modrm.rm as source" + ], + "ExpectedArm64ASM": [ + "eor x5, x5, x7", + "strb w5, [x28, #706]", + "tst x5, x5", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "xor al, 1": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": "0x34", + "ExpectedArm64ASM": [ + "eor w20, w4, #0x1", + "bfxil x4, x20, #0, #8", + "strb w20, [x28, #706]", + "lsl w20, w20, #24", + "tst w20, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "xor ax, 1": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": "0x35", + "ExpectedArm64ASM": [ + "uxth w20, w4", + "eor w20, w20, #0x1", + "bfxil x4, x20, #0, #16", + "strb w20, [x28, #706]", + "lsl w20, w20, #16", + "tst w20, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "xor eax, 1": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": "0x35", + "ExpectedArm64ASM": [ + "mov w20, w4", + "eor w4, w20, #0x1", + "strb w4, [x28, #706]", + "tst w4, w4", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "xor rax, 1": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": "0x35", + "ExpectedArm64ASM": [ + "eor x4, x4, #0x1", + "strb w4, [x28, #706]", + "tst x4, x4", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "cmp bl, cl": { + "ExpectedInstructionCount": 17, + "Optimal": "No", + "Comment": "0x38", + "ExpectedArm64ASM": [ + "uxtb w20, w5", + "uxtb w21, w7", + "sub w22, w21, w20", + "eor w23, w21, w20", + "strb w23, [x28, #708]", + "strb w22, [x28, #706]", + "lsl w23, w22, #24", + "tst w23, w23", + "mrs x23, nzcv", + "ubfx w24, w22, #8, #1", + "orr w23, w23, w24, lsl #29", + "eor w20, w21, w20", + "eor w21, w22, w21", + "and w20, w21, w20", + "ubfx w20, w20, #7, #1", + "orr w20, w23, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "xor al, -1": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": "0x34", + "ExpectedArm64ASM": [ + "eor w20, w4, #0xff", + "bfxil x4, x20, #0, #8", + "strb w20, [x28, #706]", + "lsl w20, w20, #24", + "tst w20, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "xor ax, -1": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": "0x35", + "ExpectedArm64ASM": [ + "uxth w20, w4", + "eor w20, w20, #0xffff", + "bfxil x4, x20, #0, #16", + "strb w20, [x28, #706]", + "lsl w20, w20, #16", + "tst w20, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "xor eax, -1": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": "0x35", + "ExpectedArm64ASM": [ + "mov w20, #0xffff", + "movk w20, #0xffff, lsl #16", + "mov w21, w4", + "eor w4, w21, w20", + "strb w4, [x28, #706]", + "tst w4, w4", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "xor rax, -1": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": "0x35", + "ExpectedArm64ASM": [ + "mov x20, #0xffffffffffffffff", + "eor x4, x4, x20", + "strb w4, [x28, #706]", + "tst x4, x4", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "cmp bx, cx": { + "ExpectedInstructionCount": 17, + "Optimal": "No", + "Comment": "0x39", + "ExpectedArm64ASM": [ + "uxth w20, w5", + "uxth w21, w7", + "sub w22, w21, w20", + "eor w23, w21, w20", + "strb w23, [x28, #708]", + "strb w22, [x28, #706]", + "lsl w23, w22, #16", + "tst w23, w23", + "mrs x23, nzcv", + "ubfx w24, w22, #16, #1", + "orr w23, w23, w24, lsl #29", + "eor w20, w21, w20", + "eor w21, w22, w21", + "and w20, w21, w20", + "ubfx w20, w20, #15, #1", + "orr w20, w23, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "cmp ebx, ecx": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": "0x39", + "ExpectedArm64ASM": [ + "mov w20, w5", + "mov w21, w7", + "sub w22, w21, w20", + "eor w23, w21, w20", + "strb w23, [x28, #708]", + "strb w22, [x28, #706]", + "cmp w21, w20", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "str w20, [x28, #728]" + ] + }, + "cmp rbx, rcx": { + "ExpectedInstructionCount": 8, + "Optimal": "Yes", + "Comment": "0x39", + "ExpectedArm64ASM": [ + "sub x20, x7, x5", + "eor x21, x7, x5", + "strb w21, [x28, #708]", + "strb w20, [x28, #706]", + "cmp x7, x5", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "str w20, [x28, #728]" + ] + }, + "db 0x3A, 0xcb": { + "ExpectedInstructionCount": 17, + "Optimal": "No", + "Comment": [ + "0x3A", + "cmp bl, cl but modrm.rm as source" + ], + "ExpectedArm64ASM": [ + "uxtb w20, w7", + "uxtb w21, w5", + "sub w22, w21, w20", + "eor w23, w21, w20", + "strb w23, [x28, #708]", + "strb w22, [x28, #706]", + "lsl w23, w22, #24", + "tst w23, w23", + "mrs x23, nzcv", + "ubfx w24, w22, #8, #1", + "orr w23, w23, w24, lsl #29", + "eor w20, w21, w20", + "eor w21, w22, w21", + "and w20, w21, w20", + "ubfx w20, w20, #7, #1", + "orr w20, w23, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "db 0x66, 0x3B, 0xcb": { + "ExpectedInstructionCount": 17, + "Optimal": "No", + "Comment": [ + "0x3B", + "cmp bx, cx but modrm.rm as source" + ], + "ExpectedArm64ASM": [ + "uxth w20, w7", + "uxth w21, w5", + "sub w22, w21, w20", + "eor w23, w21, w20", + "strb w23, [x28, #708]", + "strb w22, [x28, #706]", + "lsl w23, w22, #16", + "tst w23, w23", + "mrs x23, nzcv", + "ubfx w24, w22, #16, #1", + "orr w23, w23, w24, lsl #29", + "eor w20, w21, w20", + "eor w21, w22, w21", + "and w20, w21, w20", + "ubfx w20, w20, #15, #1", + "orr w20, w23, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "db 0x3B, 0xcb": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "0x3B", + "cmp ebx, ecx but modrm.rm as source" + ], + "ExpectedArm64ASM": [ + "mov w20, w7", + "mov w21, w5", + "sub w22, w21, w20", + "eor w23, w21, w20", + "strb w23, [x28, #708]", + "strb w22, [x28, #706]", + "cmp w21, w20", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "str w20, [x28, #728]" + ] + }, + "db 0x48, 0x3B, 0xcb": { + "ExpectedInstructionCount": 8, + "Optimal": "Yes", + "Comment": [ + "0x3B", + "cmp rbx, rcx but modrm.rm as source" + ], + "ExpectedArm64ASM": [ + "sub x20, x5, x7", + "eor x21, x5, x7", + "strb w21, [x28, #708]", + "strb w20, [x28, #706]", + "cmp x5, x7", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "str w20, [x28, #728]" + ] + }, + "cmp al, 1": { + "ExpectedInstructionCount": 13, + "Optimal": "No", + "Comment": "0x3C", + "ExpectedArm64ASM": [ + "uxtb w20, w4", + "sub w21, w20, #0x1 (1)", + "strb w20, [x28, #708]", + "strb w21, [x28, #706]", + "lsl w22, w21, #24", + "tst w22, w22", + "mrs x22, nzcv", + "ubfx w23, w21, #8, #1", + "orr w22, w22, w23, lsl #29", + "bic w20, w20, w21", + "ubfx w20, w20, #7, #1", + "orr w20, w22, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "cmp ax, 1": { + "ExpectedInstructionCount": 13, + "Optimal": "No", + "Comment": "0x3D", + "ExpectedArm64ASM": [ + "uxth w20, w4", + "sub w21, w20, #0x1 (1)", + "strb w20, [x28, #708]", + "strb w21, [x28, #706]", + "lsl w22, w21, #16", + "tst w22, w22", + "mrs x22, nzcv", + "ubfx w23, w21, #16, #1", + "orr w22, w22, w23, lsl #29", + "bic w20, w20, w21", + "ubfx w20, w20, #15, #1", + "orr w20, w22, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "cmp eax, 1": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": "0x3D", + "ExpectedArm64ASM": [ + "mov w20, w4", + "sub w21, w20, #0x1 (1)", + "strb w20, [x28, #708]", + "strb w21, [x28, #706]", + "cmp w20, #0x1 (1)", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "str w20, [x28, #728]" + ] + }, + "cmp rax, 1": { + "ExpectedInstructionCount": 7, + "Optimal": "Yes", + "Comment": "0x3D", + "ExpectedArm64ASM": [ + "sub x20, x4, #0x1 (1)", + "strb w4, [x28, #708]", + "strb w20, [x28, #706]", + "cmp x4, #0x1 (1)", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "str w20, [x28, #728]" + ] + }, + "cmp al, -1": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": "0x3C", + "ExpectedArm64ASM": [ + "uxtb w20, w4", + "sub w21, w20, #0xff (255)", + "eor w22, w20, #0xff", + "strb w22, [x28, #708]", + "strb w21, [x28, #706]", + "lsl w22, w21, #24", + "tst w22, w22", + "mrs x22, nzcv", + "ubfx w23, w21, #8, #1", + "orr w22, w22, w23, lsl #29", + "bic w20, w21, w20", + "ubfx w20, w20, #7, #1", + "orr w20, w22, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "cmp ax, -1": { + "ExpectedInstructionCount": 15, + "Optimal": "No", + "Comment": "0x3D", + "ExpectedArm64ASM": [ + "mov w20, #0xffff", + "uxth w21, w4", + "sub w20, w21, w20", + "eor w22, w21, #0xffff", + "strb w22, [x28, #708]", + "strb w20, [x28, #706]", + "lsl w22, w20, #16", + "tst w22, w22", + "mrs x22, nzcv", + "ubfx w23, w20, #16, #1", + "orr w22, w22, w23, lsl #29", + "bic w20, w20, w21", + "ubfx w20, w20, #15, #1", + "orr w20, w22, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "cmp eax, -1": { + "ExpectedInstructionCount": 11, + "Optimal": "No", + "Comment": "0x3D", + "ExpectedArm64ASM": [ + "mov w20, #0xffff", + "movk w20, #0xffff, lsl #16", + "mov w21, w4", + "sub w22, w21, w20", + "eor w23, w21, w20", + "strb w23, [x28, #708]", + "strb w22, [x28, #706]", + "cmp w21, w20", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "str w20, [x28, #728]" + ] + }, + "cmp rax, -1": { + "ExpectedInstructionCount": 9, + "Optimal": "Yes", + "Comment": "0x3D", + "ExpectedArm64ASM": [ + "mov x20, #0xffffffffffffffff", + "sub x21, x4, x20", + "eor x22, x4, x20", + "strb w22, [x28, #708]", + "strb w21, [x28, #706]", + "cmp x4, x20", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "str w20, [x28, #728]" + ] + }, + "imul ax, bx, 257": { + "ExpectedInstructionCount": 12, + "Optimal": "No", + "Comment": "0x69", + "ExpectedArm64ASM": [ + "uxth w20, w7", + "sxth x20, w20", + "mov w21, #0x101", + "mul x20, x20, x21", + "sbfx x21, x20, #16, #16", + "bfxil x4, x20, #0, #16", + "mov w22, #0x0", + "sbfx x20, x20, #15, #1", + "mov w23, #0x30000000", + "cmp x21, x20", + "csel x20, x22, x23, eq", + "str w20, [x28, #728]" + ] + }, + "imul eax, ebx, 257": { + "ExpectedInstructionCount": 12, + "Optimal": "No", + "Comment": "0x69", + "ExpectedArm64ASM": [ + "mov w20, w7", + "sxtw x20, w20", + "mov w21, #0x101", + "mul x20, x20, x21", + "asr x21, x20, #32", + "mov w4, w20", + "mov w22, #0x0", + "sbfx x20, x20, #31, #1", + "mov w23, #0x30000000", + "cmp x21, x20", + "csel x20, x22, x23, eq", + "str w20, [x28, #728]" + ] + }, + "imul rax, rbx, 257": { + "ExpectedInstructionCount": 9, + "Optimal": "No", + "Comment": "0x69", + "ExpectedArm64ASM": [ + "mov w20, #0x101", + "mul x4, x7, x20", + "smulh x20, x7, x20", + "mov w21, #0x0", + "asr x22, x4, #63", + "mov w23, #0x30000000", + "cmp x20, x22", + "csel x20, x21, x23, eq", + "str w20, [x28, #728]" + ] + }, + "imul ax, bx, 3": { + "ExpectedInstructionCount": 12, + "Optimal": "No", + "Comment": "0x6b", + "ExpectedArm64ASM": [ + "uxth w20, w7", + "sxth x20, w20", + "mov w21, #0x3", + "mul x20, x20, x21", + "sbfx x21, x20, #16, #16", + "bfxil x4, x20, #0, #16", + "mov w22, #0x0", + "sbfx x20, x20, #15, #1", + "mov w23, #0x30000000", + "cmp x21, x20", + "csel x20, x22, x23, eq", + "str w20, [x28, #728]" + ] + }, + "imul eax, ebx, 3": { + "ExpectedInstructionCount": 12, + "Optimal": "No", + "Comment": "0x6b", + "ExpectedArm64ASM": [ + "mov w20, w7", + "sxtw x20, w20", + "mov w21, #0x3", + "mul x20, x20, x21", + "asr x21, x20, #32", + "mov w4, w20", + "mov w22, #0x0", + "sbfx x20, x20, #31, #1", + "mov w23, #0x30000000", + "cmp x21, x20", + "csel x20, x22, x23, eq", + "str w20, [x28, #728]" + ] + }, + "imul rax, rbx, 3": { + "ExpectedInstructionCount": 9, + "Optimal": "No", + "Comment": "0x6b", + "ExpectedArm64ASM": [ + "mov w20, #0x3", + "mul x4, x7, x20", + "smulh x20, x7, x20", + "mov w21, #0x0", + "asr x22, x4, #63", + "mov w23, #0x30000000", + "cmp x20, x22", + "csel x20, x21, x23, eq", + "str w20, [x28, #728]" + ] + }, + "test al, bl": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": "0x84", + "ExpectedArm64ASM": [ + "and w20, w4, w7", + "strb w20, [x28, #706]", + "lsl w20, w20, #24", + "tst w20, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "test ax, bx": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": "0x84", + "ExpectedArm64ASM": [ + "and w20, w4, w7", + "strb w20, [x28, #706]", + "lsl w20, w20, #16", + "tst w20, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "test eax, ebx": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": "0x84", + "ExpectedArm64ASM": [ + "and w20, w4, w7", + "strb w20, [x28, #706]", + "tst w20, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "test rax, rbx": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": "0x84", + "ExpectedArm64ASM": [ + "and x20, x4, x7", + "strb w20, [x28, #706]", + "tst x20, x20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "pushf": { + "ExpectedInstructionCount": 41, + "Optimal": "No", + "Comment": "0x9c", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "ubfx w21, w20, #29, #1", + "ldrb w22, [x28, #708]", + "ldrb w23, [x28, #706]", + "eor w22, w22, w23", + "ubfx w22, w22, #4, #1", + "orr x21, x21, x22, lsl #4", + "ldrb w22, [x28, #712]", + "orr x21, x21, x22, lsl #8", + "ldrb w22, [x28, #713]", + "orr x21, x21, x22, lsl #9", + "ldrb w22, [x28, #714]", + "orr x21, x21, x22, lsl #10", + "ubfx w22, w20, #28, #1", + "orr x21, x21, x22, lsl #11", + "ldrb w22, [x28, #716]", + "orr x21, x21, x22, lsl #12", + "ldrb w22, [x28, #718]", + "orr x21, x21, x22, lsl #14", + "ldrb w22, [x28, #720]", + "orr x21, x21, x22, lsl #16", + "ldrb w22, [x28, #721]", + "orr x21, x21, x22, lsl #17", + "ldrb w22, [x28, #722]", + "orr x21, x21, x22, lsl #18", + "ldrb w22, [x28, #723]", + "orr x21, x21, x22, lsl #19", + "ldrb w22, [x28, #724]", + "orr x21, x21, x22, lsl #20", + "ldrb w22, [x28, #725]", + "orr x21, x21, x22, lsl #21", + "ldrb w22, [x28, #706]", + "fmov s2, w22", + "cnt v2.16b, v2.16b", + "umov w22, v2.b[0]", + "orr x22, x22, #0xfffffffffffffffe", + "orn x21, x21, x22, ror #62", + "and x20, x20, #0xc0000000", + "orr x20, x21, x20, lsr #24", + "orr x20, x20, #0x2", + "str x20, [x8, #-8]!" + ] + }, + "pushfq": { + "ExpectedInstructionCount": 41, + "Optimal": "No", + "Comment": "0x9c", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "ubfx w21, w20, #29, #1", + "ldrb w22, [x28, #708]", + "ldrb w23, [x28, #706]", + "eor w22, w22, w23", + "ubfx w22, w22, #4, #1", + "orr x21, x21, x22, lsl #4", + "ldrb w22, [x28, #712]", + "orr x21, x21, x22, lsl #8", + "ldrb w22, [x28, #713]", + "orr x21, x21, x22, lsl #9", + "ldrb w22, [x28, #714]", + "orr x21, x21, x22, lsl #10", + "ubfx w22, w20, #28, #1", + "orr x21, x21, x22, lsl #11", + "ldrb w22, [x28, #716]", + "orr x21, x21, x22, lsl #12", + "ldrb w22, [x28, #718]", + "orr x21, x21, x22, lsl #14", + "ldrb w22, [x28, #720]", + "orr x21, x21, x22, lsl #16", + "ldrb w22, [x28, #721]", + "orr x21, x21, x22, lsl #17", + "ldrb w22, [x28, #722]", + "orr x21, x21, x22, lsl #18", + "ldrb w22, [x28, #723]", + "orr x21, x21, x22, lsl #19", + "ldrb w22, [x28, #724]", + "orr x21, x21, x22, lsl #20", + "ldrb w22, [x28, #725]", + "orr x21, x21, x22, lsl #21", + "ldrb w22, [x28, #706]", + "fmov s2, w22", + "cnt v2.16b, v2.16b", + "umov w22, v2.b[0]", + "orr x22, x22, #0xfffffffffffffffe", + "orn x21, x21, x22, ror #62", + "and x20, x20, #0xc0000000", + "orr x20, x21, x20, lsr #24", + "orr x20, x20, #0x2", + "str x20, [x8, #-8]!" + ] + }, + "popf": { + "ExpectedInstructionCount": 39, + "Optimal": "No", + "Comment": "0x9d", + "ExpectedArm64ASM": [ + "ldr x20, [x8]", + "add x8, x8, #0x8 (8)", + "mov w21, #0x202", + "orr x20, x20, x21", + "ubfx w21, w20, #0, #1", + "lsl x21, x21, #29", + "ubfx w22, w20, #2, #1", + "eor w22, w22, #0x1", + "strb w22, [x28, #706]", + "strb w20, [x28, #708]", + "ubfx w22, w20, #6, #1", + "orr w21, w21, w22, lsl #30", + "ubfx w22, w20, #7, #1", + "orr w21, w21, w22, lsl #31", + "ubfx w22, w20, #8, #1", + "strb w22, [x28, #712]", + "ubfx w22, w20, #9, #1", + "strb w22, [x28, #713]", + "ubfx w22, w20, #10, #1", + "strb w22, [x28, #714]", + "ubfx w22, w20, #11, #1", + "orr w21, w21, w22, lsl #28", + "ubfx w22, w20, #12, #1", + "strb w22, [x28, #716]", + "ubfx w22, w20, #14, #1", + "strb w22, [x28, #718]", + "ubfx w22, w20, #16, #1", + "strb w22, [x28, #720]", + "ubfx w22, w20, #17, #1", + "strb w22, [x28, #721]", + "ubfx w22, w20, #18, #1", + "strb w22, [x28, #722]", + "ubfx w22, w20, #19, #1", + "strb w22, [x28, #723]", + "ubfx w22, w20, #20, #1", + "strb w22, [x28, #724]", + "ubfx w20, w20, #21, #1", + "strb w20, [x28, #725]", + "str w21, [x28, #728]" + ] + }, + "sahf": { + "ExpectedInstructionCount": 20, + "Optimal": "No", + "Comment": "0x9e", + "ExpectedArm64ASM": [ + "ubfx w20, w4, #8, #8", + "mov w21, #0x28", + "bic x20, x20, x21", + "orr x20, x20, #0x2", + "ubfx w21, w20, #0, #1", + "ldr w22, [x28, #728]", + "mov w0, w22", + "bfi w0, w21, #29, #1", + "mov w21, w0", + "ubfx w22, w20, #2, #1", + "eor w22, w22, #0x1", + "strb w22, [x28, #706]", + "strb w20, [x28, #708]", + "ubfx w22, w20, #6, #1", + "bfi w21, w22, #30, #1", + "ubfx w20, w20, #7, #1", + "mov w0, w21", + "bfi w0, w20, #31, #1", + "mov w20, w0", + "str w20, [x28, #728]" + ] + }, + "lahf": { + "ExpectedInstructionCount": 17, + "Optimal": "Yes", + "Comment": "0x9f", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "ubfx w21, w20, #29, #1", + "ldrb w22, [x28, #708]", + "ldrb w23, [x28, #706]", + "eor w22, w22, w23", + "ubfx w22, w22, #4, #1", + "orr x21, x21, x22, lsl #4", + "ldrb w22, [x28, #706]", + "fmov s2, w22", + "cnt v2.16b, v2.16b", + "umov w22, v2.b[0]", + "orr x22, x22, #0xfffffffffffffffe", + "orn x21, x21, x22, ror #62", + "and x20, x20, #0xc0000000", + "orr x20, x21, x20, lsr #24", + "orr x20, x20, #0x2", + "bfi x4, x20, #8, #8" + ] + }, + "cmpsb": { + "ExpectedInstructionCount": 22, + "Optimal": "No", + "Comment": [ + "0xa6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x11]", + "ldrb w21, [x10]", + "sub w22, w21, w20", + "ldrb w23, [x28, #714]", + "mov w24, #0x1", + "sub x23, x24, x23, lsl #1", + "add x11, x11, x23", + "add x10, x10, x23", + "eor w23, w21, w20", + "strb w23, [x28, #708]", + "strb w22, [x28, #706]", + "lsl w23, w22, #24", + "tst w23, w23", + "mrs x23, nzcv", + "ubfx w24, w22, #8, #1", + "orr w23, w23, w24, lsl #29", + "eor w20, w21, w20", + "eor w21, w22, w21", + "and w20, w21, w20", + "ubfx w20, w20, #7, #1", + "orr w20, w23, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "cmpsw": { + "ExpectedInstructionCount": 22, + "Optimal": "No", + "Comment": [ + "0xa7" + ], + "ExpectedArm64ASM": [ + "ldrh w20, [x11]", + "ldrh w21, [x10]", + "sub w22, w21, w20", + "ldrb w23, [x28, #714]", + "mov w24, #0x2", + "sub x23, x24, x23, lsl #2", + "add x11, x11, x23", + "add x10, x10, x23", + "eor w23, w21, w20", + "strb w23, [x28, #708]", + "strb w22, [x28, #706]", + "lsl w23, w22, #16", + "tst w23, w23", + "mrs x23, nzcv", + "ubfx w24, w22, #16, #1", + "orr w23, w23, w24, lsl #29", + "eor w20, w21, w20", + "eor w21, w22, w21", + "and w20, w21, w20", + "ubfx w20, w20, #15, #1", + "orr w20, w23, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "cmpsd": { + "ExpectedInstructionCount": 15, + "Optimal": "No", + "Comment": [ + "0xa7" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x11]", + "ldr w21, [x10]", + "sub w22, w21, w20", + "ldrb w23, [x28, #714]", + "mov w24, #0x4", + "sub x23, x24, x23, lsl #3", + "add x11, x11, x23", + "add x10, x10, x23", + "eor w23, w21, w20", + "strb w23, [x28, #708]", + "strb w22, [x28, #706]", + "cmp w21, w20", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "str w20, [x28, #728]" + ] + }, + "cmpsq": { + "ExpectedInstructionCount": 15, + "Optimal": "No", + "Comment": [ + "0xa7" + ], + "ExpectedArm64ASM": [ + "ldr x20, [x11]", + "ldr x21, [x10]", + "sub x22, x21, x20", + "ldrb w23, [x28, #714]", + "mov w24, #0x8", + "sub x23, x24, x23, lsl #4", + "add x11, x11, x23", + "add x10, x10, x23", + "eor x23, x21, x20", + "strb w23, [x28, #708]", + "strb w22, [x28, #706]", + "cmp x21, x20", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "str w20, [x28, #728]" + ] + }, + "repz cmpsb": { + "ExpectedInstructionCount": 26, + "Optimal": "No", + "Comment": "0xa6", + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #714]", + "mov w21, #0x1", + "sub x20, x21, x20, lsl #1", + "cbz x5, #+0x5c", + "ldrb w21, [x11]", + "ldrb w22, [x10]", + "sub w23, w22, w21", + "eor w24, w22, w21", + "strb w24, [x28, #708]", + "strb w23, [x28, #706]", + "lsl w24, w23, #24", + "tst w24, w24", + "mrs x24, nzcv", + "ubfx w25, w23, #8, #1", + "orr w24, w24, w25, lsl #29", + "eor w21, w22, w21", + "eor w22, w23, w22", + "and w21, w22, w21", + "ubfx w21, w21, #7, #1", + "orr w21, w24, w21, lsl #28", + "str w21, [x28, #728]", + "sub x5, x5, #0x1 (1)", + "add x11, x11, x20", + "add x10, x10, x20", + "ubfx w21, w21, #30, #1", + "cbnz w21, #-0x58" + ] + }, + "repz cmpsw": { + "ExpectedInstructionCount": 26, + "Optimal": "No", + "Comment": "0xa7", + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #714]", + "mov w21, #0x2", + "sub x20, x21, x20, lsl #2", + "cbz x5, #+0x5c", + "ldrh w21, [x11]", + "ldrh w22, [x10]", + "sub w23, w22, w21", + "eor w24, w22, w21", + "strb w24, [x28, #708]", + "strb w23, [x28, #706]", + "lsl w24, w23, #16", + "tst w24, w24", + "mrs x24, nzcv", + "ubfx w25, w23, #16, #1", + "orr w24, w24, w25, lsl #29", + "eor w21, w22, w21", + "eor w22, w23, w22", + "and w21, w22, w21", + "ubfx w21, w21, #15, #1", + "orr w21, w24, w21, lsl #28", + "str w21, [x28, #728]", + "sub x5, x5, #0x1 (1)", + "add x11, x11, x20", + "add x10, x10, x20", + "ubfx w21, w21, #30, #1", + "cbnz w21, #-0x58" + ] + }, + "repz cmpsd": { + "ExpectedInstructionCount": 19, + "Optimal": "No", + "Comment": "0xa7", + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #714]", + "mov w21, #0x4", + "sub x20, x21, x20, lsl #3", + "cbz x5, #+0x40", + "ldr w21, [x11]", + "ldr w22, [x10]", + "sub w23, w22, w21", + "eor w24, w22, w21", + "strb w24, [x28, #708]", + "strb w23, [x28, #706]", + "cmp w22, w21", + "mrs x21, nzcv", + "eor w21, w21, #0x20000000", + "str w21, [x28, #728]", + "sub x5, x5, #0x1 (1)", + "add x11, x11, x20", + "add x10, x10, x20", + "ubfx w21, w21, #30, #1", + "cbnz w21, #-0x3c" + ] + }, + "repz cmpsq": { + "ExpectedInstructionCount": 19, + "Optimal": "No", + "Comment": "0xa7", + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #714]", + "mov w21, #0x8", + "sub x20, x21, x20, lsl #4", + "cbz x5, #+0x40", + "ldr x21, [x11]", + "ldr x22, [x10]", + "sub x23, x22, x21", + "eor x24, x22, x21", + "strb w24, [x28, #708]", + "strb w23, [x28, #706]", + "cmp x22, x21", + "mrs x21, nzcv", + "eor w21, w21, #0x20000000", + "str w21, [x28, #728]", + "sub x5, x5, #0x1 (1)", + "add x11, x11, x20", + "add x10, x10, x20", + "ubfx w21, w21, #30, #1", + "cbnz w21, #-0x3c" + ] + }, + "repnz cmpsb": { + "ExpectedInstructionCount": 26, + "Optimal": "No", + "Comment": "0xa6", + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #714]", + "mov w21, #0x1", + "sub x20, x21, x20, lsl #1", + "cbz x5, #+0x5c", + "ldrb w21, [x11]", + "ldrb w22, [x10]", + "sub w23, w22, w21", + "eor w24, w22, w21", + "strb w24, [x28, #708]", + "strb w23, [x28, #706]", + "lsl w24, w23, #24", + "tst w24, w24", + "mrs x24, nzcv", + "ubfx w25, w23, #8, #1", + "orr w24, w24, w25, lsl #29", + "eor w21, w22, w21", + "eor w22, w23, w22", + "and w21, w22, w21", + "ubfx w21, w21, #7, #1", + "orr w21, w24, w21, lsl #28", + "str w21, [x28, #728]", + "sub x5, x5, #0x1 (1)", + "add x11, x11, x20", + "add x10, x10, x20", + "ubfx w21, w21, #30, #1", + "cbz w21, #-0x58" + ] + }, + "repnz cmpsw": { + "ExpectedInstructionCount": 26, + "Optimal": "No", + "Comment": "0xa7", + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #714]", + "mov w21, #0x2", + "sub x20, x21, x20, lsl #2", + "cbz x5, #+0x5c", + "ldrh w21, [x11]", + "ldrh w22, [x10]", + "sub w23, w22, w21", + "eor w24, w22, w21", + "strb w24, [x28, #708]", + "strb w23, [x28, #706]", + "lsl w24, w23, #16", + "tst w24, w24", + "mrs x24, nzcv", + "ubfx w25, w23, #16, #1", + "orr w24, w24, w25, lsl #29", + "eor w21, w22, w21", + "eor w22, w23, w22", + "and w21, w22, w21", + "ubfx w21, w21, #15, #1", + "orr w21, w24, w21, lsl #28", + "str w21, [x28, #728]", + "sub x5, x5, #0x1 (1)", + "add x11, x11, x20", + "add x10, x10, x20", + "ubfx w21, w21, #30, #1", + "cbz w21, #-0x58" + ] + }, + "repnz cmpsd": { + "ExpectedInstructionCount": 19, + "Optimal": "No", + "Comment": "0xa7", + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #714]", + "mov w21, #0x4", + "sub x20, x21, x20, lsl #3", + "cbz x5, #+0x40", + "ldr w21, [x11]", + "ldr w22, [x10]", + "sub w23, w22, w21", + "eor w24, w22, w21", + "strb w24, [x28, #708]", + "strb w23, [x28, #706]", + "cmp w22, w21", + "mrs x21, nzcv", + "eor w21, w21, #0x20000000", + "str w21, [x28, #728]", + "sub x5, x5, #0x1 (1)", + "add x11, x11, x20", + "add x10, x10, x20", + "ubfx w21, w21, #30, #1", + "cbz w21, #-0x3c" + ] + }, + "repnz cmpsq": { + "ExpectedInstructionCount": 19, + "Optimal": "No", + "Comment": "0xa7", + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #714]", + "mov w21, #0x8", + "sub x20, x21, x20, lsl #4", + "cbz x5, #+0x40", + "ldr x21, [x11]", + "ldr x22, [x10]", + "sub x23, x22, x21", + "eor x24, x22, x21", + "strb w24, [x28, #708]", + "strb w23, [x28, #706]", + "cmp x22, x21", + "mrs x21, nzcv", + "eor w21, w21, #0x20000000", + "str w21, [x28, #728]", + "sub x5, x5, #0x1 (1)", + "add x11, x11, x20", + "add x10, x10, x20", + "ubfx w21, w21, #30, #1", + "cbz w21, #-0x3c" + ] + }, + "test al, 1": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": "0xa8", + "ExpectedArm64ASM": [ + "and w20, w4, #0x1", + "strb w20, [x28, #706]", + "lsl w20, w20, #24", + "tst w20, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "test ax, 1": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": "0xa9", + "ExpectedArm64ASM": [ + "and w20, w4, #0x1", + "strb w20, [x28, #706]", + "lsl w20, w20, #16", + "tst w20, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "test eax, 1": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": "0xa9", + "ExpectedArm64ASM": [ + "and w20, w4, #0x1", + "strb w20, [x28, #706]", + "tst w20, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "test rax, 1": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": "0xa9", + "ExpectedArm64ASM": [ + "and x20, x4, #0x1", + "strb w20, [x28, #706]", + "tst x20, x20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "test al, -1": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": "0xa8", + "ExpectedArm64ASM": [ + "and w20, w4, #0xff", + "strb w20, [x28, #706]", + "lsl w20, w20, #24", + "tst w20, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "test ax, -1": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": "0xa9", + "ExpectedArm64ASM": [ + "and w20, w4, #0xffff", + "strb w20, [x28, #706]", + "lsl w20, w20, #16", + "tst w20, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "test eax, -1": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": "0xa9", + "ExpectedArm64ASM": [ + "mov w20, #0xffff", + "movk w20, #0xffff, lsl #16", + "and w20, w4, w20", + "strb w20, [x28, #706]", + "tst w20, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "test rax, -1": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": "0xa9", + "ExpectedArm64ASM": [ + "mov x20, #0xffffffffffffffff", + "and x20, x4, x20", + "strb w20, [x28, #706]", + "tst x20, x20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "scasb": { + "ExpectedInstructionCount": 21, + "Optimal": "No", + "Comment": "0xae", + "ExpectedArm64ASM": [ + "uxtb w20, w4", + "ldrb w21, [x11]", + "sub w22, w20, w21", + "ldrb w23, [x28, #714]", + "mov w24, #0x1", + "sub x23, x24, x23, lsl #1", + "add x11, x11, x23", + "eor w23, w20, w21", + "strb w23, [x28, #708]", + "strb w22, [x28, #706]", + "lsl w23, w22, #24", + "tst w23, w23", + "mrs x23, nzcv", + "ubfx w24, w22, #8, #1", + "orr w23, w23, w24, lsl #29", + "eor w21, w20, w21", + "eor w20, w22, w20", + "and w20, w20, w21", + "ubfx w20, w20, #7, #1", + "orr w20, w23, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "scasw": { + "ExpectedInstructionCount": 21, + "Optimal": "No", + "Comment": "0xaf", + "ExpectedArm64ASM": [ + "uxth w20, w4", + "ldrh w21, [x11]", + "sub w22, w20, w21", + "ldrb w23, [x28, #714]", + "mov w24, #0x2", + "sub x23, x24, x23, lsl #2", + "add x11, x11, x23", + "eor w23, w20, w21", + "strb w23, [x28, #708]", + "strb w22, [x28, #706]", + "lsl w23, w22, #16", + "tst w23, w23", + "mrs x23, nzcv", + "ubfx w24, w22, #16, #1", + "orr w23, w23, w24, lsl #29", + "eor w21, w20, w21", + "eor w20, w22, w20", + "and w20, w20, w21", + "ubfx w20, w20, #15, #1", + "orr w20, w23, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "scasd": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": "0xaf", + "ExpectedArm64ASM": [ + "mov w20, w4", + "ldr w21, [x11]", + "sub w22, w20, w21", + "ldrb w23, [x28, #714]", + "mov w24, #0x4", + "sub x23, x24, x23, lsl #3", + "add x11, x11, x23", + "eor w23, w20, w21", + "strb w23, [x28, #708]", + "strb w22, [x28, #706]", + "cmp w20, w21", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "str w20, [x28, #728]" + ] + }, + "scasq": { + "ExpectedInstructionCount": 13, + "Optimal": "No", + "Comment": "0xaf", + "ExpectedArm64ASM": [ + "ldr x20, [x11]", + "sub x21, x4, x20", + "ldrb w22, [x28, #714]", + "mov w23, #0x8", + "sub x22, x23, x22, lsl #4", + "add x11, x11, x22", + "eor x22, x4, x20", + "strb w22, [x28, #708]", + "strb w21, [x28, #706]", + "cmp x4, x20", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "str w20, [x28, #728]" + ] + }, + "repz scasb": { + "ExpectedInstructionCount": 25, + "Optimal": "No", + "Comment": "0xae", + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #714]", + "mov w21, #0x1", + "sub x20, x21, x20, lsl #1", + "cbz x5, #+0x58", + "uxtb w21, w4", + "ldrb w22, [x11]", + "sub w23, w21, w22", + "eor w24, w21, w22", + "strb w24, [x28, #708]", + "strb w23, [x28, #706]", + "lsl w24, w23, #24", + "tst w24, w24", + "mrs x24, nzcv", + "ubfx w25, w23, #8, #1", + "orr w24, w24, w25, lsl #29", + "eor w22, w21, w22", + "eor w21, w23, w21", + "and w21, w21, w22", + "ubfx w21, w21, #7, #1", + "orr w21, w24, w21, lsl #28", + "str w21, [x28, #728]", + "sub x5, x5, #0x1 (1)", + "add x11, x11, x20", + "ubfx w21, w21, #30, #1", + "cbnz w21, #-0x54" + ] + }, + "repz scasw": { + "ExpectedInstructionCount": 25, + "Optimal": "No", + "Comment": "0xaf", + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #714]", + "mov w21, #0x2", + "sub x20, x21, x20, lsl #2", + "cbz x5, #+0x58", + "uxth w21, w4", + "ldrh w22, [x11]", + "sub w23, w21, w22", + "eor w24, w21, w22", + "strb w24, [x28, #708]", + "strb w23, [x28, #706]", + "lsl w24, w23, #16", + "tst w24, w24", + "mrs x24, nzcv", + "ubfx w25, w23, #16, #1", + "orr w24, w24, w25, lsl #29", + "eor w22, w21, w22", + "eor w21, w23, w21", + "and w21, w21, w22", + "ubfx w21, w21, #15, #1", + "orr w21, w24, w21, lsl #28", + "str w21, [x28, #728]", + "sub x5, x5, #0x1 (1)", + "add x11, x11, x20", + "ubfx w21, w21, #30, #1", + "cbnz w21, #-0x54" + ] + }, + "repz scasd": { + "ExpectedInstructionCount": 18, + "Optimal": "No", + "Comment": "0xaf", + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #714]", + "mov w21, #0x4", + "sub x20, x21, x20, lsl #3", + "cbz x5, #+0x3c", + "mov w21, w4", + "ldr w22, [x11]", + "sub w23, w21, w22", + "eor w24, w21, w22", + "strb w24, [x28, #708]", + "strb w23, [x28, #706]", + "cmp w21, w22", + "mrs x21, nzcv", + "eor w21, w21, #0x20000000", + "str w21, [x28, #728]", + "sub x5, x5, #0x1 (1)", + "add x11, x11, x20", + "ubfx w21, w21, #30, #1", + "cbnz w21, #-0x38" + ] + }, + "repz scasq": { + "ExpectedInstructionCount": 17, + "Optimal": "No", + "Comment": "0xaf", + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #714]", + "mov w21, #0x8", + "sub x20, x21, x20, lsl #4", + "cbz x5, #+0x38", + "ldr x21, [x11]", + "sub x22, x4, x21", + "eor x23, x4, x21", + "strb w23, [x28, #708]", + "strb w22, [x28, #706]", + "cmp x4, x21", + "mrs x21, nzcv", + "eor w21, w21, #0x20000000", + "str w21, [x28, #728]", + "sub x5, x5, #0x1 (1)", + "add x11, x11, x20", + "ubfx w21, w21, #30, #1", + "cbnz w21, #-0x34" + ] + }, + "repnz scasb": { + "ExpectedInstructionCount": 25, + "Optimal": "No", + "Comment": "0xae", + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #714]", + "mov w21, #0x1", + "sub x20, x21, x20, lsl #1", + "cbz x5, #+0x58", + "uxtb w21, w4", + "ldrb w22, [x11]", + "sub w23, w21, w22", + "eor w24, w21, w22", + "strb w24, [x28, #708]", + "strb w23, [x28, #706]", + "lsl w24, w23, #24", + "tst w24, w24", + "mrs x24, nzcv", + "ubfx w25, w23, #8, #1", + "orr w24, w24, w25, lsl #29", + "eor w22, w21, w22", + "eor w21, w23, w21", + "and w21, w21, w22", + "ubfx w21, w21, #7, #1", + "orr w21, w24, w21, lsl #28", + "str w21, [x28, #728]", + "sub x5, x5, #0x1 (1)", + "add x11, x11, x20", + "ubfx w21, w21, #30, #1", + "cbz w21, #-0x54" + ] + }, + "repnz scasw": { + "ExpectedInstructionCount": 25, + "Optimal": "No", + "Comment": "0xaf", + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #714]", + "mov w21, #0x2", + "sub x20, x21, x20, lsl #2", + "cbz x5, #+0x58", + "uxth w21, w4", + "ldrh w22, [x11]", + "sub w23, w21, w22", + "eor w24, w21, w22", + "strb w24, [x28, #708]", + "strb w23, [x28, #706]", + "lsl w24, w23, #16", + "tst w24, w24", + "mrs x24, nzcv", + "ubfx w25, w23, #16, #1", + "orr w24, w24, w25, lsl #29", + "eor w22, w21, w22", + "eor w21, w23, w21", + "and w21, w21, w22", + "ubfx w21, w21, #15, #1", + "orr w21, w24, w21, lsl #28", + "str w21, [x28, #728]", + "sub x5, x5, #0x1 (1)", + "add x11, x11, x20", + "ubfx w21, w21, #30, #1", + "cbz w21, #-0x54" + ] + }, + "repnz scasd": { + "ExpectedInstructionCount": 18, + "Optimal": "No", + "Comment": "0xaf", + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #714]", + "mov w21, #0x4", + "sub x20, x21, x20, lsl #3", + "cbz x5, #+0x3c", + "mov w21, w4", + "ldr w22, [x11]", + "sub w23, w21, w22", + "eor w24, w21, w22", + "strb w24, [x28, #708]", + "strb w23, [x28, #706]", + "cmp w21, w22", + "mrs x21, nzcv", + "eor w21, w21, #0x20000000", + "str w21, [x28, #728]", + "sub x5, x5, #0x1 (1)", + "add x11, x11, x20", + "ubfx w21, w21, #30, #1", + "cbz w21, #-0x38" + ] + }, + "repnz scasq": { + "ExpectedInstructionCount": 17, + "Optimal": "No", + "Comment": "0xaf", + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #714]", + "mov w21, #0x8", + "sub x20, x21, x20, lsl #4", + "cbz x5, #+0x38", + "ldr x21, [x11]", + "sub x22, x4, x21", + "eor x23, x4, x21", + "strb w23, [x28, #708]", + "strb w22, [x28, #706]", + "cmp x4, x21", + "mrs x21, nzcv", + "eor w21, w21, #0x20000000", + "str w21, [x28, #728]", + "sub x5, x5, #0x1 (1)", + "add x11, x11, x20", + "ubfx w21, w21, #30, #1", + "cbz w21, #-0x34" + ] + }, + "cmc": { + "ExpectedInstructionCount": 3, + "Optimal": "No", + "Comment": "0xf5", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "eor w20, w20, #0x20000000", + "str w20, [x28, #728]" + ] + }, + "clc": { + "ExpectedInstructionCount": 3, + "Optimal": "No", + "Comment": "0xf8", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "and w20, w20, #0xdfffffff", + "str w20, [x28, #728]" + ] + }, + "stc": { + "ExpectedInstructionCount": 3, + "Optimal": "No", + "Comment": "0xf9", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "orr w20, w20, #0x20000000", + "str w20, [x28, #728]" + ] + } + } +} diff --git a/unittests/InstructionCountCI/FlagM/PrimaryGroup.json b/unittests/InstructionCountCI/FlagM/PrimaryGroup.json new file mode 100644 index 000000000..532eda25d --- /dev/null +++ b/unittests/InstructionCountCI/FlagM/PrimaryGroup.json @@ -0,0 +1,3896 @@ +{ + "Features": { + "Bitness": 64, + "EnabledHostFeatures": [ + "FLAGM", + "FLAGM2" + ], + "DisabledHostFeatures": [ + "SVE128", + "SVE256" + ] + }, + "Instructions": { + "add al, 1": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": "GROUP1 0x80 /0", + "ExpectedArm64ASM": [ + "uxtb w20, w4", + "add w21, w20, #0x1 (1)", + "bfxil x4, x21, #0, #8", + "strb w20, [x28, #708]", + "strb w21, [x28, #706]", + "lsl w22, w21, #24", + "tst w22, w22", + "mrs x22, nzcv", + "ubfx w23, w21, #8, #1", + "orr w22, w22, w23, lsl #29", + "bic w20, w21, w20", + "ubfx w20, w20, #7, #1", + "orr w20, w22, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "or al, 1": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": "GROUP1 0x80 /1", + "ExpectedArm64ASM": [ + "orr w20, w4, #0x1", + "bfxil x4, x20, #0, #8", + "strb w20, [x28, #706]", + "lsl w20, w20, #24", + "tst w20, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "adc al, 1": { + "ExpectedInstructionCount": 24, + "Optimal": "No", + "Comment": "GROUP1 0x80 /2", + "ExpectedArm64ASM": [ + "mov w20, #0x1", + "ldr w21, [x28, #728]", + "ubfx w21, w21, #29, #1", + "add w20, w20, w21", + "uxtb w22, w4", + "add w20, w22, w20", + "bfxil x4, x20, #0, #8", + "uxtb w20, w20", + "strb w22, [x28, #708]", + "strb w20, [x28, #706]", + "lsl w23, w20, #24", + "tst w23, w23", + "mrs x23, nzcv", + "cmp w20, #0x1 (1)", + "cset x24, lo", + "cmp w20, #0x1 (1)", + "cset x25, ls", + "cmp x21, #0x1 (1)", + "csel x21, x25, x24, eq", + "orr w21, w23, w21, lsl #29", + "bic w20, w20, w22", + "ubfx w20, w20, #7, #1", + "orr w20, w21, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "sbb al, 1": { + "ExpectedInstructionCount": 24, + "Optimal": "No", + "Comment": "GROUP1 0x80 /3", + "ExpectedArm64ASM": [ + "mov w20, #0x1", + "ldr w21, [x28, #728]", + "ubfx w21, w21, #29, #1", + "add w20, w20, w21", + "uxtb w22, w4", + "sub w20, w22, w20", + "bfxil x4, x20, #0, #8", + "uxtb w20, w20", + "strb w22, [x28, #708]", + "strb w20, [x28, #706]", + "lsl w23, w20, #24", + "tst w23, w23", + "mrs x23, nzcv", + "cmp w20, w22", + "cset x24, hi", + "cmp w20, w22", + "cset x25, hs", + "cmp x21, #0x1 (1)", + "csel x21, x25, x24, eq", + "orr w21, w23, w21, lsl #29", + "bic w20, w22, w20", + "ubfx w20, w20, #7, #1", + "orr w20, w21, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "and al, 1": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": "GROUP1 0x80 /4", + "ExpectedArm64ASM": [ + "and w20, w4, #0x1", + "bfxil x4, x20, #0, #8", + "strb w20, [x28, #706]", + "lsl w20, w20, #24", + "tst w20, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "sub al, 1": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": "GROUP1 0x80 /5", + "ExpectedArm64ASM": [ + "uxtb w20, w4", + "sub w21, w20, #0x1 (1)", + "bfxil x4, x21, #0, #8", + "strb w20, [x28, #708]", + "strb w21, [x28, #706]", + "lsl w22, w21, #24", + "tst w22, w22", + "mrs x22, nzcv", + "ubfx w23, w21, #8, #1", + "orr w22, w22, w23, lsl #29", + "bic w20, w20, w21", + "ubfx w20, w20, #7, #1", + "orr w20, w22, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "xor al, 1": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": "GROUP1 0x80 /6", + "ExpectedArm64ASM": [ + "eor w20, w4, #0x1", + "bfxil x4, x20, #0, #8", + "strb w20, [x28, #706]", + "lsl w20, w20, #24", + "tst w20, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "cmp al, 1": { + "ExpectedInstructionCount": 13, + "Optimal": "No", + "Comment": "GROUP1 0x80 /7", + "ExpectedArm64ASM": [ + "uxtb w20, w4", + "sub w21, w20, #0x1 (1)", + "strb w20, [x28, #708]", + "strb w21, [x28, #706]", + "lsl w22, w21, #24", + "tst w22, w22", + "mrs x22, nzcv", + "ubfx w23, w21, #8, #1", + "orr w22, w22, w23, lsl #29", + "bic w20, w20, w21", + "ubfx w20, w20, #7, #1", + "orr w20, w22, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "add al, -1": { + "ExpectedInstructionCount": 15, + "Optimal": "No", + "Comment": "GROUP1 0x80 /0", + "ExpectedArm64ASM": [ + "uxtb w20, w4", + "add w21, w20, #0xff (255)", + "bfxil x4, x21, #0, #8", + "eor w22, w20, #0xff", + "strb w22, [x28, #708]", + "strb w21, [x28, #706]", + "lsl w22, w21, #24", + "tst w22, w22", + "mrs x22, nzcv", + "ubfx w23, w21, #8, #1", + "orr w22, w22, w23, lsl #29", + "bic w20, w20, w21", + "ubfx w20, w20, #7, #1", + "orr w20, w22, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "or al, -1": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": "GROUP1 0x80 /1", + "ExpectedArm64ASM": [ + "orr w20, w4, #0xff", + "bfxil x4, x20, #0, #8", + "strb w20, [x28, #706]", + "lsl w20, w20, #24", + "tst w20, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "adc al, -1": { + "ExpectedInstructionCount": 25, + "Optimal": "No", + "Comment": "GROUP1 0x80 /2", + "ExpectedArm64ASM": [ + "mov w20, #0xff", + "ldr w21, [x28, #728]", + "ubfx w21, w21, #29, #1", + "add w20, w20, w21", + "uxtb w22, w4", + "add w20, w22, w20", + "bfxil x4, x20, #0, #8", + "uxtb w20, w20", + "eor w23, w22, #0xff", + "strb w23, [x28, #708]", + "strb w20, [x28, #706]", + "lsl w23, w20, #24", + "tst w23, w23", + "mrs x23, nzcv", + "cmp w20, #0xff (255)", + "cset x24, lo", + "cmp w20, #0xff (255)", + "cset x25, ls", + "cmp x21, #0x1 (1)", + "csel x21, x25, x24, eq", + "orr w21, w23, w21, lsl #29", + "bic w20, w22, w20", + "ubfx w20, w20, #7, #1", + "orr w20, w21, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "sbb al, -1": { + "ExpectedInstructionCount": 25, + "Optimal": "No", + "Comment": "GROUP1 0x80 /3", + "ExpectedArm64ASM": [ + "mov w20, #0xff", + "ldr w21, [x28, #728]", + "ubfx w21, w21, #29, #1", + "add w20, w20, w21", + "uxtb w22, w4", + "sub w20, w22, w20", + "bfxil x4, x20, #0, #8", + "uxtb w20, w20", + "eor w23, w22, #0xff", + "strb w23, [x28, #708]", + "strb w20, [x28, #706]", + "lsl w23, w20, #24", + "tst w23, w23", + "mrs x23, nzcv", + "cmp w20, w22", + "cset x24, hi", + "cmp w20, w22", + "cset x25, hs", + "cmp x21, #0x1 (1)", + "csel x21, x25, x24, eq", + "orr w21, w23, w21, lsl #29", + "bic w20, w20, w22", + "ubfx w20, w20, #7, #1", + "orr w20, w21, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "and al, -1": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": "GROUP1 0x80 /4", + "ExpectedArm64ASM": [ + "and w20, w4, #0xff", + "bfxil x4, x20, #0, #8", + "strb w20, [x28, #706]", + "lsl w20, w20, #24", + "tst w20, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "sub al, -1": { + "ExpectedInstructionCount": 15, + "Optimal": "No", + "Comment": "GROUP1 0x80 /5", + "ExpectedArm64ASM": [ + "uxtb w20, w4", + "sub w21, w20, #0xff (255)", + "bfxil x4, x21, #0, #8", + "eor w22, w20, #0xff", + "strb w22, [x28, #708]", + "strb w21, [x28, #706]", + "lsl w22, w21, #24", + "tst w22, w22", + "mrs x22, nzcv", + "ubfx w23, w21, #8, #1", + "orr w22, w22, w23, lsl #29", + "bic w20, w21, w20", + "ubfx w20, w20, #7, #1", + "orr w20, w22, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "xor al, -1": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": "GROUP1 0x80 /6", + "ExpectedArm64ASM": [ + "eor w20, w4, #0xff", + "bfxil x4, x20, #0, #8", + "strb w20, [x28, #706]", + "lsl w20, w20, #24", + "tst w20, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "cmp al, -1": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": "GROUP1 0x80 /7", + "ExpectedArm64ASM": [ + "uxtb w20, w4", + "sub w21, w20, #0xff (255)", + "eor w22, w20, #0xff", + "strb w22, [x28, #708]", + "strb w21, [x28, #706]", + "lsl w22, w21, #24", + "tst w22, w22", + "mrs x22, nzcv", + "ubfx w23, w21, #8, #1", + "orr w22, w22, w23, lsl #29", + "bic w20, w21, w20", + "ubfx w20, w20, #7, #1", + "orr w20, w22, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "add ax, 256": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": "GROUP1 0x81 /0", + "ExpectedArm64ASM": [ + "uxth w20, w4", + "add w21, w20, #0x100 (256)", + "bfxil x4, x21, #0, #16", + "strb w20, [x28, #708]", + "strb w21, [x28, #706]", + "lsl w22, w21, #16", + "tst w22, w22", + "mrs x22, nzcv", + "ubfx w23, w21, #16, #1", + "orr w22, w22, w23, lsl #29", + "bic w20, w21, w20", + "ubfx w20, w20, #15, #1", + "orr w20, w22, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "add eax, 256": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": "GROUP1 0x81 /0", + "ExpectedArm64ASM": [ + "mov w20, w4", + "add w4, w20, #0x100 (256)", + "strb w20, [x28, #708]", + "strb w4, [x28, #706]", + "cmn w20, #0x100 (256)", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "add rax, 256": { + "ExpectedInstructionCount": 7, + "Optimal": "Yes", + "Comment": "GROUP1 0x81 /0", + "ExpectedArm64ASM": [ + "mov x20, x4", + "add x4, x20, #0x100 (256)", + "strb w20, [x28, #708]", + "strb w4, [x28, #706]", + "cmn x20, #0x100 (256)", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "or eax, 256": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": "GROUP1 0x81 /1", + "ExpectedArm64ASM": [ + "orr w4, w4, #0x100", + "strb w4, [x28, #706]", + "tst w4, w4", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "or rax, 256": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": "GROUP1 0x81 /1", + "ExpectedArm64ASM": [ + "orr x4, x4, #0x100", + "strb w4, [x28, #706]", + "tst x4, x4", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "adc eax, 256": { + "ExpectedInstructionCount": 12, + "Optimal": "No", + "Comment": "GROUP1 0x81 /2", + "ExpectedArm64ASM": [ + "mov w20, #0x100", + "ldr w21, [x28, #728]", + "ubfx w22, w21, #29, #1", + "add w22, w20, w22", + "mov w23, w4", + "add w4, w23, w22", + "strb w23, [x28, #708]", + "strb w4, [x28, #706]", + "msr nzcv, x21", + "adcs wzr, w23, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "adc rax, 256": { + "ExpectedInstructionCount": 12, + "Optimal": "No", + "Comment": "GROUP1 0x81 /2", + "ExpectedArm64ASM": [ + "mov w20, #0x100", + "ldr w21, [x28, #728]", + "ubfx w22, w21, #29, #1", + "add x22, x20, x22", + "mov x23, x4", + "add x4, x23, x22", + "strb w23, [x28, #708]", + "strb w4, [x28, #706]", + "msr nzcv, x21", + "adcs xzr, x23, x20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "sbb eax, 256": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": "GROUP1 0x81 /3", + "ExpectedArm64ASM": [ + "mov w20, #0x100", + "ldr w21, [x28, #728]", + "ubfx w22, w21, #29, #1", + "add w22, w20, w22", + "mov w23, w4", + "sub w4, w23, w22", + "strb w23, [x28, #708]", + "strb w4, [x28, #706]", + "eor w0, w21, #0x20000000", + "msr nzcv, x0", + "sbcs wzr, w23, w20", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "str w20, [x28, #728]" + ] + }, + "sbb rax, 256": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": "GROUP1 0x81 /3", + "ExpectedArm64ASM": [ + "mov w20, #0x100", + "ldr w21, [x28, #728]", + "ubfx w22, w21, #29, #1", + "add x22, x20, x22", + "mov x23, x4", + "sub x4, x23, x22", + "strb w23, [x28, #708]", + "strb w4, [x28, #706]", + "eor w0, w21, #0x20000000", + "msr nzcv, x0", + "sbcs xzr, x23, x20", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "str w20, [x28, #728]" + ] + }, + "and eax, 256": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": "GROUP1 0x81 /4", + "ExpectedArm64ASM": [ + "and w4, w4, #0x100", + "strb w4, [x28, #706]", + "tst w4, w4", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "and rax, 256": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": "GROUP1 0x81 /4", + "ExpectedArm64ASM": [ + "and x4, x4, #0x100", + "strb w4, [x28, #706]", + "tst x4, x4", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "sub eax, 256": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": "GROUP1 0x81 /5", + "ExpectedArm64ASM": [ + "mov w20, w4", + "sub w4, w20, #0x100 (256)", + "strb w20, [x28, #708]", + "strb w4, [x28, #706]", + "cmp w20, #0x100 (256)", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "str w20, [x28, #728]" + ] + }, + "sub rax, 256": { + "ExpectedInstructionCount": 8, + "Optimal": "Yes", + "Comment": "GROUP1 0x81 /5", + "ExpectedArm64ASM": [ + "mov x20, x4", + "sub x4, x20, #0x100 (256)", + "strb w20, [x28, #708]", + "strb w4, [x28, #706]", + "cmp x20, #0x100 (256)", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "str w20, [x28, #728]" + ] + }, + "xor eax, 256": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": "GROUP1 0x81 /6", + "ExpectedArm64ASM": [ + "eor w4, w4, #0x100", + "strb w4, [x28, #706]", + "tst w4, w4", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "xor rax, 256": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": "GROUP1 0x81 /6", + "ExpectedArm64ASM": [ + "eor x4, x4, #0x100", + "strb w4, [x28, #706]", + "tst x4, x4", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "cmp eax, 256": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": "GROUP1 0x81 /7", + "ExpectedArm64ASM": [ + "mov w20, w4", + "sub w21, w20, #0x100 (256)", + "strb w20, [x28, #708]", + "strb w21, [x28, #706]", + "cmp w20, #0x100 (256)", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "str w20, [x28, #728]" + ] + }, + "cmp rax, 256": { + "ExpectedInstructionCount": 7, + "Optimal": "Yes", + "Comment": "GROUP1 0x81 /7", + "ExpectedArm64ASM": [ + "sub x20, x4, #0x100 (256)", + "strb w4, [x28, #708]", + "strb w20, [x28, #706]", + "cmp x4, #0x100 (256)", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "str w20, [x28, #728]" + ] + }, + "add ax, -256": { + "ExpectedInstructionCount": 15, + "Optimal": "No", + "Comment": "GROUP1 0x81 /0", + "ExpectedArm64ASM": [ + "mov w20, #0xff00", + "uxth w21, w4", + "add w20, w21, w20", + "bfxil x4, x20, #0, #16", + "strb w21, [x28, #708]", + "strb w20, [x28, #706]", + "lsl w22, w20, #16", + "tst w22, w22", + "mrs x22, nzcv", + "ubfx w23, w20, #16, #1", + "orr w22, w22, w23, lsl #29", + "bic w20, w21, w20", + "ubfx w20, w20, #15, #1", + "orr w20, w22, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "add eax, -256": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": "GROUP1 0x81 /0", + "ExpectedArm64ASM": [ + "orr w20, wzr, #0xffffff00", + "mov w21, w4", + "add w4, w21, w20", + "strb w21, [x28, #708]", + "strb w4, [x28, #706]", + "cmn w21, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "add rax, -256": { + "ExpectedInstructionCount": 8, + "Optimal": "Yes", + "Comment": "GROUP1 0x81 /0", + "ExpectedArm64ASM": [ + "mov x20, #0xffffffffffffff00", + "mov x21, x4", + "sub x4, x21, #0x100 (256)", + "strb w21, [x28, #708]", + "strb w4, [x28, #706]", + "cmn x21, x20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "or eax, -256": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": "GROUP1 0x81 /1", + "ExpectedArm64ASM": [ + "orr w4, w4, #0xffffff00", + "strb w4, [x28, #706]", + "tst w4, w4", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "or rax, -256": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": "GROUP1 0x81 /1", + "ExpectedArm64ASM": [ + "orr x4, x4, #0xffffffffffffff00", + "strb w4, [x28, #706]", + "tst x4, x4", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "adc eax, -256": { + "ExpectedInstructionCount": 12, + "Optimal": "No", + "Comment": "GROUP1 0x81 /2", + "ExpectedArm64ASM": [ + "orr w20, wzr, #0xffffff00", + "ldr w21, [x28, #728]", + "ubfx w22, w21, #29, #1", + "add w22, w20, w22", + "mov w23, w4", + "add w4, w23, w22", + "strb w23, [x28, #708]", + "strb w4, [x28, #706]", + "msr nzcv, x21", + "adcs wzr, w23, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "adc rax, -256": { + "ExpectedInstructionCount": 12, + "Optimal": "No", + "Comment": "GROUP1 0x81 /2", + "ExpectedArm64ASM": [ + "mov x20, #0xffffffffffffff00", + "ldr w21, [x28, #728]", + "ubfx w22, w21, #29, #1", + "add x22, x20, x22", + "mov x23, x4", + "add x4, x23, x22", + "strb w23, [x28, #708]", + "strb w4, [x28, #706]", + "msr nzcv, x21", + "adcs xzr, x23, x20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "sbb eax, -256": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": "GROUP1 0x81 /3", + "ExpectedArm64ASM": [ + "orr w20, wzr, #0xffffff00", + "ldr w21, [x28, #728]", + "ubfx w22, w21, #29, #1", + "add w22, w20, w22", + "mov w23, w4", + "sub w4, w23, w22", + "strb w23, [x28, #708]", + "strb w4, [x28, #706]", + "eor w0, w21, #0x20000000", + "msr nzcv, x0", + "sbcs wzr, w23, w20", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "str w20, [x28, #728]" + ] + }, + "sbb rax, -256": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": "GROUP1 0x81 /3", + "ExpectedArm64ASM": [ + "mov x20, #0xffffffffffffff00", + "ldr w21, [x28, #728]", + "ubfx w22, w21, #29, #1", + "add x22, x20, x22", + "mov x23, x4", + "sub x4, x23, x22", + "strb w23, [x28, #708]", + "strb w4, [x28, #706]", + "eor w0, w21, #0x20000000", + "msr nzcv, x0", + "sbcs xzr, x23, x20", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "str w20, [x28, #728]" + ] + }, + "and eax, -256": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": "GROUP1 0x81 /4", + "ExpectedArm64ASM": [ + "and w4, w4, #0xffffff00", + "strb w4, [x28, #706]", + "tst w4, w4", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "and rax, -256": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": "GROUP1 0x81 /4", + "ExpectedArm64ASM": [ + "and x4, x4, #0xffffffffffffff00", + "strb w4, [x28, #706]", + "tst x4, x4", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "sub eax, -256": { + "ExpectedInstructionCount": 9, + "Optimal": "No", + "Comment": "GROUP1 0x81 /5", + "ExpectedArm64ASM": [ + "orr w20, wzr, #0xffffff00", + "mov w21, w4", + "sub w4, w21, w20", + "strb w21, [x28, #708]", + "strb w4, [x28, #706]", + "cmp w21, w20", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "str w20, [x28, #728]" + ] + }, + "sub rax, -256": { + "ExpectedInstructionCount": 9, + "Optimal": "Yes", + "Comment": "GROUP1 0x81 /5", + "ExpectedArm64ASM": [ + "mov x20, #0xffffffffffffff00", + "mov x21, x4", + "sub x4, x21, x20", + "strb w21, [x28, #708]", + "strb w4, [x28, #706]", + "cmp x21, x20", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "str w20, [x28, #728]" + ] + }, + "xor eax, -256": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": "GROUP1 0x81 /6", + "ExpectedArm64ASM": [ + "eor w4, w4, #0xffffff00", + "strb w4, [x28, #706]", + "tst w4, w4", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "xor rax, -256": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": "GROUP1 0x81 /6", + "ExpectedArm64ASM": [ + "eor x4, x4, #0xffffffffffffff00", + "strb w4, [x28, #706]", + "tst x4, x4", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "cmp eax, -256": { + "ExpectedInstructionCount": 9, + "Optimal": "No", + "Comment": "GROUP1 0x81 /7", + "ExpectedArm64ASM": [ + "orr w20, wzr, #0xffffff00", + "mov w21, w4", + "sub w22, w21, w20", + "strb w21, [x28, #708]", + "strb w22, [x28, #706]", + "cmp w21, w20", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "str w20, [x28, #728]" + ] + }, + "cmp rax, -256": { + "ExpectedInstructionCount": 8, + "Optimal": "Yes", + "Comment": "GROUP1 0x81 /7", + "ExpectedArm64ASM": [ + "mov x20, #0xffffffffffffff00", + "sub x21, x4, x20", + "strb w4, [x28, #708]", + "strb w21, [x28, #706]", + "cmp x4, x20", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "str w20, [x28, #728]" + ] + }, + "add ax, 1": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": "GROUP1 0x83 /0", + "ExpectedArm64ASM": [ + "uxth w20, w4", + "add w21, w20, #0x1 (1)", + "bfxil x4, x21, #0, #16", + "strb w20, [x28, #708]", + "strb w21, [x28, #706]", + "lsl w22, w21, #16", + "tst w22, w22", + "mrs x22, nzcv", + "ubfx w23, w21, #16, #1", + "orr w22, w22, w23, lsl #29", + "bic w20, w21, w20", + "ubfx w20, w20, #15, #1", + "orr w20, w22, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "add eax, 1": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": "GROUP1 0x83 /0", + "ExpectedArm64ASM": [ + "mov w20, w4", + "add w4, w20, #0x1 (1)", + "strb w20, [x28, #708]", + "strb w4, [x28, #706]", + "cmn w20, #0x1 (1)", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "add rax, 1": { + "ExpectedInstructionCount": 7, + "Optimal": "Yes", + "Comment": "GROUP1 0x83 /0", + "ExpectedArm64ASM": [ + "mov x20, x4", + "add x4, x20, #0x1 (1)", + "strb w20, [x28, #708]", + "strb w4, [x28, #706]", + "cmn x20, #0x1 (1)", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "or eax, 1": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": "GROUP1 0x83 /1", + "ExpectedArm64ASM": [ + "mov w20, w4", + "orr w4, w20, #0x1", + "strb w4, [x28, #706]", + "tst w4, w4", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "or rax, 1": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": "GROUP1 0x83 /1", + "ExpectedArm64ASM": [ + "orr x4, x4, #0x1", + "strb w4, [x28, #706]", + "tst x4, x4", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "adc eax, 1": { + "ExpectedInstructionCount": 12, + "Optimal": "No", + "Comment": "GROUP1 0x83 /2", + "ExpectedArm64ASM": [ + "mov w20, #0x1", + "ldr w21, [x28, #728]", + "ubfx w22, w21, #29, #1", + "add w22, w20, w22", + "mov w23, w4", + "add w4, w23, w22", + "strb w23, [x28, #708]", + "strb w4, [x28, #706]", + "msr nzcv, x21", + "adcs wzr, w23, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "adc rax, 1": { + "ExpectedInstructionCount": 12, + "Optimal": "No", + "Comment": "GROUP1 0x83 /2", + "ExpectedArm64ASM": [ + "mov w20, #0x1", + "ldr w21, [x28, #728]", + "ubfx w22, w21, #29, #1", + "add x22, x20, x22", + "mov x23, x4", + "add x4, x23, x22", + "strb w23, [x28, #708]", + "strb w4, [x28, #706]", + "msr nzcv, x21", + "adcs xzr, x23, x20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "sbb eax, 1": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": "GROUP1 0x83 /3", + "ExpectedArm64ASM": [ + "mov w20, #0x1", + "ldr w21, [x28, #728]", + "ubfx w22, w21, #29, #1", + "add w22, w20, w22", + "mov w23, w4", + "sub w4, w23, w22", + "strb w23, [x28, #708]", + "strb w4, [x28, #706]", + "eor w0, w21, #0x20000000", + "msr nzcv, x0", + "sbcs wzr, w23, w20", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "str w20, [x28, #728]" + ] + }, + "sbb rax, 1": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": "GROUP1 0x83 /3", + "ExpectedArm64ASM": [ + "mov w20, #0x1", + "ldr w21, [x28, #728]", + "ubfx w22, w21, #29, #1", + "add x22, x20, x22", + "mov x23, x4", + "sub x4, x23, x22", + "strb w23, [x28, #708]", + "strb w4, [x28, #706]", + "eor w0, w21, #0x20000000", + "msr nzcv, x0", + "sbcs xzr, x23, x20", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "str w20, [x28, #728]" + ] + }, + "and eax, 1": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": "GROUP1 0x83 /4", + "ExpectedArm64ASM": [ + "mov w20, w4", + "and w4, w20, #0x1", + "strb w4, [x28, #706]", + "tst w4, w4", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "and rax, 1": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": "GROUP1 0x83 /4", + "ExpectedArm64ASM": [ + "and x4, x4, #0x1", + "strb w4, [x28, #706]", + "tst x4, x4", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "sub eax, 1": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": "GROUP1 0x83 /5", + "ExpectedArm64ASM": [ + "mov w20, w4", + "sub w4, w20, #0x1 (1)", + "strb w20, [x28, #708]", + "strb w4, [x28, #706]", + "cmp w20, #0x1 (1)", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "str w20, [x28, #728]" + ] + }, + "sub rax, 1": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": "GROUP1 0x83 /5", + "ExpectedArm64ASM": [ + "mov x20, x4", + "sub x4, x20, #0x1 (1)", + "strb w20, [x28, #708]", + "strb w4, [x28, #706]", + "cmp x20, #0x1 (1)", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "str w20, [x28, #728]" + ] + }, + "xor eax, 1": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": "GROUP1 0x83 /6", + "ExpectedArm64ASM": [ + "mov w20, w4", + "eor w4, w20, #0x1", + "strb w4, [x28, #706]", + "tst w4, w4", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "xor rax, 1": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": "GROUP1 0x83 /6", + "ExpectedArm64ASM": [ + "eor x4, x4, #0x1", + "strb w4, [x28, #706]", + "tst x4, x4", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "cmp eax, 1": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": "GROUP1 0x83 /7", + "ExpectedArm64ASM": [ + "mov w20, w4", + "sub w21, w20, #0x1 (1)", + "strb w20, [x28, #708]", + "strb w21, [x28, #706]", + "cmp w20, #0x1 (1)", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "str w20, [x28, #728]" + ] + }, + "cmp rax, 1": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": "GROUP1 0x83 /7", + "ExpectedArm64ASM": [ + "sub x20, x4, #0x1 (1)", + "strb w4, [x28, #708]", + "strb w20, [x28, #706]", + "cmp x4, #0x1 (1)", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "str w20, [x28, #728]" + ] + }, + "add ax, -1": { + "ExpectedInstructionCount": 16, + "Optimal": "No", + "Comment": "GROUP1 0x83 /0", + "ExpectedArm64ASM": [ + "mov w20, #0xffff", + "uxth w21, w4", + "add w20, w21, w20", + "bfxil x4, x20, #0, #16", + "eor w22, w21, #0xffff", + "strb w22, [x28, #708]", + "strb w20, [x28, #706]", + "lsl w22, w20, #16", + "tst w22, w22", + "mrs x22, nzcv", + "ubfx w23, w20, #16, #1", + "orr w22, w22, w23, lsl #29", + "bic w20, w21, w20", + "ubfx w20, w20, #15, #1", + "orr w20, w22, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "add eax, -1": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": "GROUP1 0x83 /0", + "ExpectedArm64ASM": [ + "mov w20, #0xffff", + "movk w20, #0xffff, lsl #16", + "mov w21, w4", + "add w4, w21, w20", + "eor w22, w21, w20", + "strb w22, [x28, #708]", + "strb w4, [x28, #706]", + "cmn w21, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "add rax, -1": { + "ExpectedInstructionCount": 9, + "Optimal": "Yes", + "Comment": "GROUP1 0x83 /0", + "ExpectedArm64ASM": [ + "mov x20, #0xffffffffffffffff", + "mov x21, x4", + "sub x4, x21, #0x1 (1)", + "eor x22, x21, x20", + "strb w22, [x28, #708]", + "strb w4, [x28, #706]", + "cmn x21, x20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "or eax, -1": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": "GROUP1 0x83 /-1", + "ExpectedArm64ASM": [ + "mov w20, #0xffff", + "movk w20, #0xffff, lsl #16", + "mov w21, w4", + "orr w4, w21, w20", + "strb w4, [x28, #706]", + "tst w4, w4", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "or rax, -1": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": "GROUP1 0x83 /-1", + "ExpectedArm64ASM": [ + "mov x20, #0xffffffffffffffff", + "orr x4, x4, x20", + "strb w4, [x28, #706]", + "tst x4, x4", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "adc eax, -1": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": "GROUP1 0x83 /2", + "ExpectedArm64ASM": [ + "mov w20, #0xffff", + "movk w20, #0xffff, lsl #16", + "ldr w21, [x28, #728]", + "ubfx w22, w21, #29, #1", + "add w22, w20, w22", + "mov w23, w4", + "add w4, w23, w22", + "eor w22, w23, w20", + "strb w22, [x28, #708]", + "strb w4, [x28, #706]", + "msr nzcv, x21", + "adcs wzr, w23, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "adc rax, -1": { + "ExpectedInstructionCount": 13, + "Optimal": "No", + "Comment": "GROUP1 0x83 /2", + "ExpectedArm64ASM": [ + "mov x20, #0xffffffffffffffff", + "ldr w21, [x28, #728]", + "ubfx w22, w21, #29, #1", + "add x22, x20, x22", + "mov x23, x4", + "add x4, x23, x22", + "eor x22, x23, x20", + "strb w22, [x28, #708]", + "strb w4, [x28, #706]", + "msr nzcv, x21", + "adcs xzr, x23, x20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "sbb eax, -1": { + "ExpectedInstructionCount": 16, + "Optimal": "No", + "Comment": "GROUP1 0x83 /3", + "ExpectedArm64ASM": [ + "mov w20, #0xffff", + "movk w20, #0xffff, lsl #16", + "ldr w21, [x28, #728]", + "ubfx w22, w21, #29, #1", + "add w22, w20, w22", + "mov w23, w4", + "sub w4, w23, w22", + "eor w22, w23, w20", + "strb w22, [x28, #708]", + "strb w4, [x28, #706]", + "eor w0, w21, #0x20000000", + "msr nzcv, x0", + "sbcs wzr, w23, w20", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "str w20, [x28, #728]" + ] + }, + "sbb rax, -1": { + "ExpectedInstructionCount": 15, + "Optimal": "No", + "Comment": "GROUP1 0x83 /3", + "ExpectedArm64ASM": [ + "mov x20, #0xffffffffffffffff", + "ldr w21, [x28, #728]", + "ubfx w22, w21, #29, #1", + "add x22, x20, x22", + "mov x23, x4", + "sub x4, x23, x22", + "eor x22, x23, x20", + "strb w22, [x28, #708]", + "strb w4, [x28, #706]", + "eor w0, w21, #0x20000000", + "msr nzcv, x0", + "sbcs xzr, x23, x20", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "str w20, [x28, #728]" + ] + }, + "and eax, -1": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": "GROUP1 0x83 /4", + "ExpectedArm64ASM": [ + "mov w20, #0xffff", + "movk w20, #0xffff, lsl #16", + "mov w21, w4", + "and w4, w21, w20", + "strb w4, [x28, #706]", + "tst w4, w4", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "and rax, -1": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": "GROUP1 0x83 /4", + "ExpectedArm64ASM": [ + "mov x20, #0xffffffffffffffff", + "and x4, x4, x20", + "strb w4, [x28, #706]", + "tst x4, x4", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "sub eax, -1": { + "ExpectedInstructionCount": 11, + "Optimal": "No", + "Comment": "GROUP1 0x83 /5", + "ExpectedArm64ASM": [ + "mov w20, #0xffff", + "movk w20, #0xffff, lsl #16", + "mov w21, w4", + "sub w4, w21, w20", + "eor w22, w21, w20", + "strb w22, [x28, #708]", + "strb w4, [x28, #706]", + "cmp w21, w20", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "str w20, [x28, #728]" + ] + }, + "sub rax, -1": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": "GROUP1 0x83 /5", + "ExpectedArm64ASM": [ + "mov x20, #0xffffffffffffffff", + "mov x21, x4", + "sub x4, x21, x20", + "eor x22, x21, x20", + "strb w22, [x28, #708]", + "strb w4, [x28, #706]", + "cmp x21, x20", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "str w20, [x28, #728]" + ] + }, + "xor eax, -1": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": "GROUP1 0x83 /6", + "ExpectedArm64ASM": [ + "mov w20, #0xffff", + "movk w20, #0xffff, lsl #16", + "mov w21, w4", + "eor w4, w21, w20", + "strb w4, [x28, #706]", + "tst w4, w4", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "xor rax, -1": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": "GROUP1 0x83 /6", + "ExpectedArm64ASM": [ + "mov x20, #0xffffffffffffffff", + "eor x4, x4, x20", + "strb w4, [x28, #706]", + "tst x4, x4", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "cmp eax, -1": { + "ExpectedInstructionCount": 11, + "Optimal": "No", + "Comment": "GROUP1 0x83 /7", + "ExpectedArm64ASM": [ + "mov w20, #0xffff", + "movk w20, #0xffff, lsl #16", + "mov w21, w4", + "sub w22, w21, w20", + "eor w23, w21, w20", + "strb w23, [x28, #708]", + "strb w22, [x28, #706]", + "cmp w21, w20", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "str w20, [x28, #728]" + ] + }, + "cmp rax, -1": { + "ExpectedInstructionCount": 9, + "Optimal": "No", + "Comment": "GROUP1 0x83 /7", + "ExpectedArm64ASM": [ + "mov x20, #0xffffffffffffffff", + "sub x21, x4, x20", + "eor x22, x4, x20", + "strb w22, [x28, #708]", + "strb w21, [x28, #706]", + "cmp x4, x20", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "str w20, [x28, #728]" + ] + }, + "rol al, 2": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": "GROUP2 0xC0 /0", + "ExpectedArm64ASM": [ + "uxtb w20, w4", + "bfi w20, w20, #8, #8", + "bfi w20, w20, #16, #16", + "ror w20, w20, #30", + "bfxil x4, x20, #0, #8", + "ubfx w20, w20, #0, #1", + "ldr w21, [x28, #728]", + "and w21, w21, #0xc0000000", + "orr w20, w21, w20, lsl #29", + "str w20, [x28, #728]" + ] + }, + "ror al, 2": { + "ExpectedInstructionCount": 9, + "Optimal": "No", + "Comment": "GROUP2 0xC0 /1", + "ExpectedArm64ASM": [ + "uxtb w20, w4", + "bfi w20, w20, #8, #8", + "ror w20, w20, #2", + "bfxil x4, x20, #0, #8", + "ubfx w20, w20, #7, #1", + "ldr w21, [x28, #728]", + "and w21, w21, #0xc0000000", + "orr w20, w21, w20, lsl #29", + "str w20, [x28, #728]" + ] + }, + "rcl al, 2": { + "ExpectedInstructionCount": 31, + "Optimal": "No", + "Comment": "GROUP2 0xC0 /2", + "ExpectedArm64ASM": [ + "uxtb w20, w4", + "ldr w21, [x28, #728]", + "ubfx w22, w21, #29, #1", + "mov w23, #0x2", + "mov w24, #0x0", + "bfi x24, x20, #55, #8", + "bfi x24, x22, #63, #1", + "bfi x24, x20, #46, #8", + "bfi x24, x22, #54, #1", + "bfi x24, x20, #37, #8", + "bfi x24, x22, #45, #1", + "bfi x24, x20, #28, #8", + "bfi x24, x22, #36, #1", + "bfi x24, x20, #19, #8", + "bfi x24, x22, #27, #1", + "mov x0, x24", + "bfxil x0, x20, #0, #8", + "mov x20, x0", + "ror x24, x20, #62", + "bfxil x4, x24, #0, #8", + "ror x20, x20, #61", + "ubfx x20, x20, #0, #1", + "cmp x23, #0x1 (1)", + "csel x22, x20, x22, hs", + "bfi w21, w22, #29, #1", + "ubfx x22, x24, #7, #1", + "eor x20, x22, x20", + "mov w0, w21", + "bfi w0, w20, #28, #1", + "mov w20, w0", + "str w20, [x28, #728]" + ] + }, + "rcr al, 2": { + "ExpectedInstructionCount": 22, + "Optimal": "No", + "Comment": "GROUP2 0xC0 /3", + "ExpectedArm64ASM": [ + "uxtb w20, w4", + "ldr w21, [x28, #728]", + "ubfx w22, w21, #29, #1", + "mov w23, #0x2", + "bfi x20, x22, #8, #1", + "bfi x20, x20, #9, #9", + "bfi x20, x20, #18, #18", + "bfi x20, x20, #36, #9", + "lsr x24, x20, #2", + "bfxil x4, x24, #0, #8", + "lsr x20, x20, #1", + "ubfx x20, x20, #0, #1", + "cmp w23, #0x1 (1)", + "csel x20, x20, x22, hs", + "mov w0, w21", + "bfi w0, w20, #29, #1", + "mov w20, w0", + "ubfx x21, x24, #7, #1", + "ubfx x22, x24, #6, #1", + "eor x21, x21, x22", + "bfi w20, w21, #28, #1", + "str w20, [x28, #728]" + ] + }, + "shl al, 2": { + "ExpectedInstructionCount": 11, + "Optimal": "No", + "Comment": "GROUP2 0xC0 /4", + "ExpectedArm64ASM": [ + "uxtb w20, w4", + "lsl w21, w20, #2", + "bfxil x4, x21, #0, #8", + "uxtb w21, w21", + "lsl w22, w21, #24", + "tst w22, w22", + "mrs x22, nzcv", + "ubfx w20, w20, #6, #1", + "orr w20, w22, w20, lsl #29", + "strb w21, [x28, #706]", + "str w20, [x28, #728]" + ] + }, + "shr al, 2": { + "ExpectedInstructionCount": 13, + "Optimal": "No", + "Comment": "GROUP2 0xC0 /5", + "ExpectedArm64ASM": [ + "uxtb w20, w4", + "lsr w21, w20, #2", + "bfxil x4, x21, #0, #8", + "ldr w22, [x28, #728]", + "ubfx w22, w22, #28, #1", + "lsl w23, w21, #24", + "tst w23, w23", + "mrs x23, nzcv", + "ubfx w20, w20, #1, #1", + "orr w20, w23, w20, lsl #29", + "strb w21, [x28, #706]", + "orr w20, w20, w22, lsl #28", + "str w20, [x28, #728]" + ] + }, + "sar al, 2": { + "ExpectedInstructionCount": 11, + "Optimal": "No", + "Comment": "GROUP2 0xC0 /7", + "ExpectedArm64ASM": [ + "uxtb w20, w4", + "sxtb x20, w20", + "asr x21, x20, #2", + "bfxil x4, x21, #0, #8", + "lsl w22, w21, #24", + "tst w22, w22", + "mrs x22, nzcv", + "ubfx x20, x20, #1, #1", + "orr w20, w22, w20, lsl #29", + "strb w21, [x28, #706]", + "str w20, [x28, #728]" + ] + }, + "rol ax, 2": { + "ExpectedInstructionCount": 9, + "Optimal": "No", + "Comment": "GROUP2 0xC1 /0", + "ExpectedArm64ASM": [ + "uxth w20, w4", + "bfi w20, w20, #16, #16", + "ror w20, w20, #30", + "bfxil x4, x20, #0, #16", + "ubfx w20, w20, #0, #1", + "ldr w21, [x28, #728]", + "and w21, w21, #0xc0000000", + "orr w20, w21, w20, lsl #29", + "str w20, [x28, #728]" + ] + }, + "rol eax, 2": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": "GROUP2 0xC1 /0", + "ExpectedArm64ASM": [ + "mov w20, w4", + "ror w4, w20, #30", + "ubfx w20, w4, #0, #1", + "ldr w21, [x28, #728]", + "and w21, w21, #0xc0000000", + "orr w20, w21, w20, lsl #29", + "str w20, [x28, #728]" + ] + }, + "rol rax, 2": { + "ExpectedInstructionCount": 6, + "Optimal": "Yes", + "Comment": "GROUP2 0xC1 /0", + "ExpectedArm64ASM": [ + "ror x4, x4, #62", + "ubfx x20, x4, #0, #1", + "ldr w21, [x28, #728]", + "and w21, w21, #0xc0000000", + "orr w20, w21, w20, lsl #29", + "str w20, [x28, #728]" + ] + }, + "ror ax, 2": { + "ExpectedInstructionCount": 9, + "Optimal": "No", + "Comment": "GROUP2 0xC1 /1", + "ExpectedArm64ASM": [ + "uxth w20, w4", + "bfi w20, w20, #16, #16", + "ror w20, w20, #2", + "bfxil x4, x20, #0, #16", + "ubfx w20, w20, #15, #1", + "ldr w21, [x28, #728]", + "and w21, w21, #0xc0000000", + "orr w20, w21, w20, lsl #29", + "str w20, [x28, #728]" + ] + }, + "ror eax, 2": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": "GROUP2 0xC1 /1", + "ExpectedArm64ASM": [ + "mov w20, w4", + "ror w4, w20, #2", + "lsr w20, w4, #31", + "ldr w21, [x28, #728]", + "and w21, w21, #0xc0000000", + "orr w20, w21, w20, lsl #29", + "str w20, [x28, #728]" + ] + }, + "ror rax, 2": { + "ExpectedInstructionCount": 6, + "Optimal": "Yes", + "Comment": "GROUP2 0xC1 /1", + "ExpectedArm64ASM": [ + "ror x4, x4, #2", + "lsr x20, x4, #63", + "ldr w21, [x28, #728]", + "and w21, w21, #0xc0000000", + "orr w20, w21, w20, lsl #29", + "str w20, [x28, #728]" + ] + }, + "rcl ax, 2": { + "ExpectedInstructionCount": 27, + "Optimal": "No", + "Comment": "GROUP2 0xC1 /2", + "ExpectedArm64ASM": [ + "uxth w20, w4", + "ldr w21, [x28, #728]", + "ubfx w22, w21, #29, #1", + "mov w23, #0x2", + "mov w24, #0x0", + "bfi x24, x20, #47, #16", + "bfi x24, x22, #63, #1", + "bfi x24, x20, #30, #16", + "bfi x24, x22, #46, #1", + "bfi x24, x20, #13, #16", + "bfi x24, x22, #29, #1", + "mov x0, x24", + "bfxil x0, x20, #0, #16", + "mov x20, x0", + "ror x24, x20, #62", + "bfxil x4, x24, #0, #16", + "ror x20, x20, #61", + "ubfx x20, x20, #0, #1", + "cmp x23, #0x1 (1)", + "csel x22, x20, x22, hs", + "bfi w21, w22, #29, #1", + "ubfx x22, x24, #15, #1", + "eor x20, x22, x20", + "mov w0, w21", + "bfi w0, w20, #28, #1", + "mov w20, w0", + "str w20, [x28, #728]" + ] + }, + "rcl eax, 2": { + "ExpectedInstructionCount": 25, + "Optimal": "No", + "Comment": "GROUP2 0xC1 /2", + "ExpectedArm64ASM": [ + "mov w20, #0x2", + "mov w21, w4", + "ldr w22, [x28, #728]", + "ubfx w23, w22, #29, #1", + "lsl w24, w21, #2", + "lsr w25, w21, #31", + "mov w26, #0x0", + "cmp w20, #0x1 (1)", + "csel w25, w25, w26, hi", + "orr w24, w24, w25", + "lsl x25, x23, #1", + "cmp w20, #0x1 (1)", + "csel x25, x25, x26, hs", + "orr w4, w24, w25", + "lsr w21, w21, #30", + "ubfx w21, w21, #0, #1", + "cmp w20, #0x1 (1)", + "csel w20, w21, w23, hs", + "mov w0, w22", + "bfi w0, w20, #29, #1", + "mov w20, w0", + "lsr w22, w4, #31", + "eor w21, w22, w21", + "bfi w20, w21, #28, #1", + "str w20, [x28, #728]" + ] + }, + "rcl rax, 2": { + "ExpectedInstructionCount": 25, + "Optimal": "No", + "Comment": "GROUP2 0xC1 /2", + "ExpectedArm64ASM": [ + "mov w20, #0x2", + "mov x21, x4", + "ldr w22, [x28, #728]", + "ubfx w23, w22, #29, #1", + "lsl x24, x21, #2", + "lsr x25, x21, #63", + "mov w26, #0x0", + "cmp x20, #0x1 (1)", + "csel x25, x25, x26, hi", + "orr x24, x24, x25", + "lsl x25, x23, #1", + "cmp x20, #0x1 (1)", + "csel x25, x25, x26, hs", + "orr x4, x24, x25", + "lsr x21, x21, #62", + "ubfx x21, x21, #0, #1", + "cmp x20, #0x1 (1)", + "csel x20, x21, x23, hs", + "mov w0, w22", + "bfi w0, w20, #29, #1", + "mov w20, w0", + "lsr x22, x4, #63", + "eor x21, x22, x21", + "bfi w20, w21, #28, #1", + "str w20, [x28, #728]" + ] + }, + "rcr ax, 2": { + "ExpectedInstructionCount": 21, + "Optimal": "No", + "Comment": "GROUP2 0xC1 /3", + "ExpectedArm64ASM": [ + "uxth w20, w4", + "ldr w21, [x28, #728]", + "ubfx w22, w21, #29, #1", + "mov w23, #0x2", + "bfi x20, x22, #16, #1", + "bfi x20, x20, #17, #17", + "bfi x20, x20, #34, #17", + "lsr x24, x20, #2", + "bfxil x4, x24, #0, #16", + "lsr x20, x20, #1", + "ubfx x20, x20, #0, #1", + "cmp w23, #0x1 (1)", + "csel x20, x20, x22, hs", + "mov w0, w21", + "bfi w0, w20, #29, #1", + "mov w20, w0", + "ubfx x21, x24, #15, #1", + "ubfx x22, x24, #14, #1", + "eor x21, x21, x22", + "bfi w20, w21, #28, #1", + "str w20, [x28, #728]" + ] + }, + "rcr eax, 2": { + "ExpectedInstructionCount": 26, + "Optimal": "No", + "Comment": "GROUP2 0xC1 /3", + "ExpectedArm64ASM": [ + "mov w20, #0x2", + "mov w21, w4", + "ldr w22, [x28, #728]", + "ubfx w23, w22, #29, #1", + "lsr w24, w21, #2", + "lsl w25, w21, #31", + "mov w26, #0x0", + "cmp w20, #0x1 (1)", + "csel w25, w25, w26, hi", + "orr w24, w24, w25", + "lsl x25, x23, #30", + "cmp w20, #0x1 (1)", + "csel x25, x25, x26, hs", + "orr w4, w24, w25", + "lsr w21, w21, #1", + "ubfx w21, w21, #0, #1", + "cmp w20, #0x1 (1)", + "csel w20, w21, w23, hs", + "mov w0, w22", + "bfi w0, w20, #29, #1", + "mov w20, w0", + "lsr w21, w4, #31", + "ubfx w22, w4, #30, #1", + "eor w21, w21, w22", + "bfi w20, w21, #28, #1", + "str w20, [x28, #728]" + ] + }, + "rcr rax, 2": { + "ExpectedInstructionCount": 26, + "Optimal": "No", + "Comment": "GROUP2 0xC1 /3", + "ExpectedArm64ASM": [ + "mov w20, #0x2", + "mov x21, x4", + "ldr w22, [x28, #728]", + "ubfx w23, w22, #29, #1", + "lsr x24, x21, #2", + "lsl x25, x21, #63", + "mov w26, #0x0", + "cmp x20, #0x1 (1)", + "csel x25, x25, x26, hi", + "orr x24, x24, x25", + "lsl x25, x23, #62", + "cmp x20, #0x1 (1)", + "csel x25, x25, x26, hs", + "orr x4, x24, x25", + "lsr x21, x21, #1", + "ubfx x21, x21, #0, #1", + "cmp x20, #0x1 (1)", + "csel x20, x21, x23, hs", + "mov w0, w22", + "bfi w0, w20, #29, #1", + "mov w20, w0", + "lsr x21, x4, #63", + "ubfx x22, x4, #62, #1", + "eor x21, x21, x22", + "bfi w20, w21, #28, #1", + "str w20, [x28, #728]" + ] + }, + "shl ax, 2": { + "ExpectedInstructionCount": 11, + "Optimal": "No", + "Comment": "GROUP2 0xC1 /4", + "ExpectedArm64ASM": [ + "uxth w20, w4", + "lsl w21, w20, #2", + "bfxil x4, x21, #0, #16", + "uxth w21, w21", + "lsl w22, w21, #16", + "tst w22, w22", + "mrs x22, nzcv", + "ubfx w20, w20, #14, #1", + "orr w20, w22, w20, lsl #29", + "strb w21, [x28, #706]", + "str w20, [x28, #728]" + ] + }, + "shl eax, 2": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": "GROUP2 0xC1 /4", + "ExpectedArm64ASM": [ + "mov w20, w4", + "lsl w4, w20, #2", + "tst w4, w4", + "mrs x21, nzcv", + "ubfx w20, w20, #30, #1", + "orr w20, w21, w20, lsl #29", + "strb w4, [x28, #706]", + "str w20, [x28, #728]" + ] + }, + "shl rax, 2": { + "ExpectedInstructionCount": 8, + "Optimal": "Yes", + "Comment": "GROUP2 0xC1 /4", + "ExpectedArm64ASM": [ + "mov x20, x4", + "lsl x4, x20, #2", + "tst x4, x4", + "mrs x21, nzcv", + "ubfx x20, x20, #62, #1", + "orr w20, w21, w20, lsl #29", + "strb w4, [x28, #706]", + "str w20, [x28, #728]" + ] + }, + "shr ax, 2": { + "ExpectedInstructionCount": 13, + "Optimal": "No", + "Comment": "GROUP2 0xC1 /5", + "ExpectedArm64ASM": [ + "uxth w20, w4", + "lsr w21, w20, #2", + "bfxil x4, x21, #0, #16", + "ldr w22, [x28, #728]", + "ubfx w22, w22, #28, #1", + "lsl w23, w21, #16", + "tst w23, w23", + "mrs x23, nzcv", + "ubfx w20, w20, #1, #1", + "orr w20, w23, w20, lsl #29", + "strb w21, [x28, #706]", + "orr w20, w20, w22, lsl #28", + "str w20, [x28, #728]" + ] + }, + "shr eax, 2": { + "ExpectedInstructionCount": 11, + "Optimal": "No", + "Comment": "GROUP2 0xC1 /5", + "ExpectedArm64ASM": [ + "mov w20, w4", + "lsr w4, w20, #2", + "ldr w21, [x28, #728]", + "ubfx w21, w21, #28, #1", + "tst w4, w4", + "mrs x22, nzcv", + "ubfx w20, w20, #1, #1", + "orr w20, w22, w20, lsl #29", + "strb w4, [x28, #706]", + "orr w20, w20, w21, lsl #28", + "str w20, [x28, #728]" + ] + }, + "shr rax, 2": { + "ExpectedInstructionCount": 11, + "Optimal": "Yes", + "Comment": "GROUP2 0xC1 /5", + "ExpectedArm64ASM": [ + "mov x20, x4", + "lsr x4, x20, #2", + "ldr w21, [x28, #728]", + "ubfx w21, w21, #28, #1", + "tst x4, x4", + "mrs x22, nzcv", + "ubfx x20, x20, #1, #1", + "orr w20, w22, w20, lsl #29", + "strb w4, [x28, #706]", + "orr w20, w20, w21, lsl #28", + "str w20, [x28, #728]" + ] + }, + "sar ax, 2": { + "ExpectedInstructionCount": 11, + "Optimal": "No", + "Comment": "GROUP2 0xC1 /7", + "ExpectedArm64ASM": [ + "uxth w20, w4", + "sxth x20, w20", + "asr x21, x20, #2", + "bfxil x4, x21, #0, #16", + "lsl w22, w21, #16", + "tst w22, w22", + "mrs x22, nzcv", + "ubfx x20, x20, #1, #1", + "orr w20, w22, w20, lsl #29", + "strb w21, [x28, #706]", + "str w20, [x28, #728]" + ] + }, + "sar eax, 2": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": "GROUP2 0xC1 /7", + "ExpectedArm64ASM": [ + "mov w20, w4", + "asr w4, w20, #2", + "tst w4, w4", + "mrs x21, nzcv", + "ubfx w20, w20, #1, #1", + "orr w20, w21, w20, lsl #29", + "strb w4, [x28, #706]", + "str w20, [x28, #728]" + ] + }, + "sar rax, 2": { + "ExpectedInstructionCount": 8, + "Optimal": "Yes", + "Comment": "GROUP2 0xC1 /7", + "ExpectedArm64ASM": [ + "mov x20, x4", + "asr x4, x20, #2", + "tst x4, x4", + "mrs x21, nzcv", + "ubfx x20, x20, #1, #1", + "orr w20, w21, w20, lsl #29", + "strb w4, [x28, #706]", + "str w20, [x28, #728]" + ] + }, + "rol al, 1": { + "ExpectedInstructionCount": 13, + "Optimal": "No", + "Comment": "GROUP2 0xd0 /0", + "ExpectedArm64ASM": [ + "uxtb w20, w4", + "bfi w20, w20, #8, #8", + "bfi w20, w20, #16, #16", + "ror w20, w20, #31", + "bfxil x4, x20, #0, #8", + "ubfx w21, w20, #0, #1", + "ldr w22, [x28, #728]", + "and w22, w22, #0xc0000000", + "orr w22, w22, w21, lsl #29", + "ubfx w20, w20, #7, #1", + "eor w20, w20, w21", + "orr w20, w22, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "ror al, 1": { + "ExpectedInstructionCount": 12, + "Optimal": "No", + "Comment": "GROUP2 0xd0 /1", + "ExpectedArm64ASM": [ + "uxtb w20, w4", + "bfi w20, w20, #8, #8", + "ror w20, w20, #1", + "bfxil x4, x20, #0, #8", + "ubfx w21, w20, #7, #1", + "ldr w22, [x28, #728]", + "and w22, w22, #0xc0000000", + "orr w22, w22, w21, lsl #29", + "ubfx w20, w20, #6, #1", + "eor w20, w20, w21", + "orr w20, w22, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "rcl al, 1": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": "GROUP2 0xd0 /2", + "ExpectedArm64ASM": [ + "uxtb w20, w4", + "ldr w21, [x28, #728]", + "ubfx w22, w21, #29, #1", + "ubfx w23, w20, #7, #1", + "lsl w20, w20, #1", + "orr w20, w20, w22", + "bfxil x4, x20, #0, #8", + "bfi w21, w23, #29, #1", + "ubfx w20, w20, #7, #1", + "eor w20, w20, w23", + "mov w0, w21", + "bfi w0, w20, #28, #1", + "mov w20, w0", + "str w20, [x28, #728]" + ] + }, + "rcr al, 1": { + "ExpectedInstructionCount": 15, + "Optimal": "No", + "Comment": "GROUP2 0xd0 /3", + "ExpectedArm64ASM": [ + "uxtb w20, w4", + "ldr w21, [x28, #728]", + "ubfx w22, w21, #29, #1", + "ubfx w23, w20, #0, #1", + "ubfx w20, w20, #1, #7", + "bfi w20, w22, #7, #1", + "bfxil x4, x20, #0, #8", + "bfi w21, w23, #29, #1", + "ubfx w22, w20, #7, #1", + "ubfx w20, w20, #6, #1", + "eor w20, w22, w20", + "mov w0, w21", + "bfi w0, w20, #28, #1", + "mov w20, w0", + "str w20, [x28, #728]" + ] + }, + "shl al, 1": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": "GROUP2 0xd0 /4", + "ExpectedArm64ASM": [ + "uxtb w20, w4", + "lsl w21, w20, #1", + "bfxil x4, x21, #0, #8", + "uxtb w21, w21", + "lsl w22, w21, #24", + "tst w22, w22", + "mrs x22, nzcv", + "ubfx w23, w20, #7, #1", + "orr w22, w22, w23, lsl #29", + "strb w21, [x28, #706]", + "eor w20, w21, w20", + "ubfx w20, w20, #7, #1", + "orr w20, w22, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "shr al, 1": { + "ExpectedInstructionCount": 12, + "Optimal": "No", + "Comment": "GROUP2 0xd0 /5", + "ExpectedArm64ASM": [ + "uxtb w20, w4", + "lsr w21, w20, #1", + "bfxil x4, x21, #0, #8", + "lsl w22, w21, #24", + "tst w22, w22", + "mrs x22, nzcv", + "ubfx w23, w20, #0, #1", + "orr w22, w22, w23, lsl #29", + "strb w21, [x28, #706]", + "ubfx w20, w20, #7, #1", + "orr w20, w22, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "sar al, 1": { + "ExpectedInstructionCount": 11, + "Optimal": "No", + "Comment": "GROUP2 0xd0 /7", + "ExpectedArm64ASM": [ + "uxtb w20, w4", + "sxtb x20, w20", + "asr w21, w20, #1", + "bfxil x4, x21, #0, #8", + "lsl w22, w21, #24", + "tst w22, w22", + "mrs x22, nzcv", + "ubfx x20, x20, #0, #1", + "orr w20, w22, w20, lsl #29", + "strb w21, [x28, #706]", + "str w20, [x28, #728]" + ] + }, + "rol ax, 1": { + "ExpectedInstructionCount": 12, + "Optimal": "No", + "Comment": "GROUP2 0xd1 /0", + "ExpectedArm64ASM": [ + "uxth w20, w4", + "bfi w20, w20, #16, #16", + "ror w20, w20, #31", + "bfxil x4, x20, #0, #16", + "ubfx w21, w20, #0, #1", + "ldr w22, [x28, #728]", + "and w22, w22, #0xc0000000", + "orr w22, w22, w21, lsl #29", + "ubfx w20, w20, #15, #1", + "eor w20, w20, w21", + "orr w20, w22, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "rol eax, 1": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": "GROUP2 0xd1 /0", + "ExpectedArm64ASM": [ + "mov w20, w4", + "ror w4, w20, #31", + "ubfx w20, w4, #0, #1", + "ldr w21, [x28, #728]", + "and w21, w21, #0xc0000000", + "orr w21, w21, w20, lsl #29", + "lsr w22, w4, #31", + "eor w20, w22, w20", + "orr w20, w21, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "rol rax, 1": { + "ExpectedInstructionCount": 9, + "Optimal": "Yes", + "Comment": "GROUP2 0xd1 /0", + "ExpectedArm64ASM": [ + "ror x4, x4, #63", + "ubfx x20, x4, #0, #1", + "ldr w21, [x28, #728]", + "and w21, w21, #0xc0000000", + "orr w21, w21, w20, lsl #29", + "lsr x22, x4, #63", + "eor x20, x22, x20", + "orr w20, w21, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "ror ax, 1": { + "ExpectedInstructionCount": 12, + "Optimal": "No", + "Comment": "GROUP2 0xd1 /1", + "ExpectedArm64ASM": [ + "uxth w20, w4", + "bfi w20, w20, #16, #16", + "ror w20, w20, #1", + "bfxil x4, x20, #0, #16", + "ubfx w21, w20, #15, #1", + "ldr w22, [x28, #728]", + "and w22, w22, #0xc0000000", + "orr w22, w22, w21, lsl #29", + "ubfx w20, w20, #14, #1", + "eor w20, w20, w21", + "orr w20, w22, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "ror eax, 1": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": "GROUP2 0xd1 /1", + "ExpectedArm64ASM": [ + "mov w20, w4", + "ror w4, w20, #1", + "lsr w20, w4, #31", + "ldr w21, [x28, #728]", + "and w21, w21, #0xc0000000", + "orr w21, w21, w20, lsl #29", + "ubfx w22, w4, #30, #1", + "eor w20, w22, w20", + "orr w20, w21, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "ror rax, 1": { + "ExpectedInstructionCount": 9, + "Optimal": "Yes", + "Comment": "GROUP2 0xd1 /1", + "ExpectedArm64ASM": [ + "ror x4, x4, #1", + "lsr x20, x4, #63", + "ldr w21, [x28, #728]", + "and w21, w21, #0xc0000000", + "orr w21, w21, w20, lsl #29", + "ubfx x22, x4, #62, #1", + "eor x20, x22, x20", + "orr w20, w21, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "rcl ax, 1": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": "GROUP2 0xd1 /2", + "ExpectedArm64ASM": [ + "uxth w20, w4", + "ldr w21, [x28, #728]", + "ubfx w22, w21, #29, #1", + "ubfx w23, w20, #15, #1", + "lsl w20, w20, #1", + "orr w20, w20, w22", + "bfxil x4, x20, #0, #16", + "bfi w21, w23, #29, #1", + "ubfx w20, w20, #15, #1", + "eor w20, w20, w23", + "mov w0, w21", + "bfi w0, w20, #28, #1", + "mov w20, w0", + "str w20, [x28, #728]" + ] + }, + "rcl eax, 1": { + "ExpectedInstructionCount": 13, + "Optimal": "No", + "Comment": "GROUP2 0xd1 /2", + "ExpectedArm64ASM": [ + "mov w20, w4", + "ldr w21, [x28, #728]", + "ubfx w22, w21, #29, #1", + "lsr w23, w20, #31", + "lsl w20, w20, #1", + "orr w4, w20, w22", + "mov w0, w21", + "bfi w0, w23, #29, #1", + "mov w20, w0", + "lsr w21, w4, #31", + "eor w21, w21, w23", + "bfi w20, w21, #28, #1", + "str w20, [x28, #728]" + ] + }, + "rcl rax, 1": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": "GROUP2 0xd1 /2", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "ubfx w21, w20, #29, #1", + "lsr x22, x4, #63", + "lsl x23, x4, #1", + "orr x4, x23, x21", + "bfi w20, w22, #29, #1", + "lsr x21, x4, #63", + "eor w21, w21, w22", + "bfi w20, w21, #28, #1", + "str w20, [x28, #728]" + ] + }, + "rcr ax, 1": { + "ExpectedInstructionCount": 16, + "Optimal": "No", + "Comment": "GROUP2 0xd1 /3", + "ExpectedArm64ASM": [ + "uxth w20, w4", + "ldr w21, [x28, #728]", + "ubfx w22, w21, #29, #1", + "ubfx w23, w20, #1, #15", + "lsl w22, w22, #15", + "orr w22, w23, w22", + "bfxil x4, x22, #0, #16", + "ubfx w20, w20, #0, #1", + "mov w0, w21", + "bfi w0, w20, #29, #1", + "mov w20, w0", + "ubfx w21, w22, #15, #1", + "ubfx w22, w22, #14, #1", + "eor w21, w21, w22", + "bfi w20, w21, #28, #1", + "str w20, [x28, #728]" + ] + }, + "rcr eax, 1": { + "ExpectedInstructionCount": 13, + "Optimal": "No", + "Comment": "GROUP2 0xd1 /3", + "ExpectedArm64ASM": [ + "mov w20, w4", + "ldr w21, [x28, #728]", + "ubfx w22, w21, #29, #1", + "extr w4, w22, w20, #1", + "ubfx w20, w20, #0, #1", + "mov w0, w21", + "bfi w0, w20, #29, #1", + "mov w20, w0", + "lsr w21, w4, #31", + "ubfx w22, w4, #30, #1", + "eor w21, w21, w22", + "bfi w20, w21, #28, #1", + "str w20, [x28, #728]" + ] + }, + "rcr rax, 1": { + "ExpectedInstructionCount": 13, + "Optimal": "No", + "Comment": "GROUP2 0xd1 /3", + "ExpectedArm64ASM": [ + "mov x20, x4", + "ldr w21, [x28, #728]", + "ubfx w22, w21, #29, #1", + "extr x4, x22, x20, #1", + "ubfx x20, x20, #0, #1", + "mov w0, w21", + "bfi w0, w20, #29, #1", + "mov w20, w0", + "lsr x21, x4, #63", + "ubfx x22, x4, #62, #1", + "eor x21, x21, x22", + "bfi w20, w21, #28, #1", + "str w20, [x28, #728]" + ] + }, + "shl ax, 1": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": "GROUP2 0xd1 /4", + "ExpectedArm64ASM": [ + "uxth w20, w4", + "lsl w21, w20, #1", + "bfxil x4, x21, #0, #16", + "uxth w21, w21", + "lsl w22, w21, #16", + "tst w22, w22", + "mrs x22, nzcv", + "ubfx w23, w20, #15, #1", + "orr w22, w22, w23, lsl #29", + "strb w21, [x28, #706]", + "eor w20, w21, w20", + "ubfx w20, w20, #15, #1", + "orr w20, w22, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "shl eax, 1": { + "ExpectedInstructionCount": 11, + "Optimal": "No", + "Comment": "GROUP2 0xd1 /4", + "ExpectedArm64ASM": [ + "mov w20, w4", + "lsl w4, w20, #1", + "tst w4, w4", + "mrs x21, nzcv", + "lsr w22, w20, #31", + "orr w21, w21, w22, lsl #29", + "strb w4, [x28, #706]", + "eor w20, w4, w20", + "lsr w20, w20, #31", + "orr w20, w21, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "shl rax, 1": { + "ExpectedInstructionCount": 11, + "Optimal": "Yes", + "Comment": "GROUP2 0xd1 /4", + "ExpectedArm64ASM": [ + "mov x20, x4", + "lsl x4, x20, #1", + "tst x4, x4", + "mrs x21, nzcv", + "lsr x22, x20, #63", + "orr w21, w21, w22, lsl #29", + "strb w4, [x28, #706]", + "eor x20, x4, x20", + "lsr x20, x20, #63", + "orr w20, w21, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "shr ax, 1": { + "ExpectedInstructionCount": 12, + "Optimal": "No", + "Comment": "GROUP2 0xd1 /5", + "ExpectedArm64ASM": [ + "uxth w20, w4", + "lsr w21, w20, #1", + "bfxil x4, x21, #0, #16", + "lsl w22, w21, #16", + "tst w22, w22", + "mrs x22, nzcv", + "ubfx w23, w20, #0, #1", + "orr w22, w22, w23, lsl #29", + "strb w21, [x28, #706]", + "ubfx w20, w20, #15, #1", + "orr w20, w22, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "shr eax, 1": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": "GROUP2 0xd1 /5", + "ExpectedArm64ASM": [ + "mov w20, w4", + "lsr w4, w20, #1", + "tst w4, w4", + "mrs x21, nzcv", + "ubfx w22, w20, #0, #1", + "orr w21, w21, w22, lsl #29", + "strb w4, [x28, #706]", + "lsr w20, w20, #31", + "orr w20, w21, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "shr rax, 1": { + "ExpectedInstructionCount": 10, + "Optimal": "Yes", + "Comment": "GROUP2 0xd1 /5", + "ExpectedArm64ASM": [ + "mov x20, x4", + "lsr x4, x20, #1", + "tst x4, x4", + "mrs x21, nzcv", + "ubfx x22, x20, #0, #1", + "orr w21, w21, w22, lsl #29", + "strb w4, [x28, #706]", + "lsr x20, x20, #63", + "orr w20, w21, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "sar ax, 1": { + "ExpectedInstructionCount": 11, + "Optimal": "No", + "Comment": "GROUP2 0xd1 /7", + "ExpectedArm64ASM": [ + "uxth w20, w4", + "sxth x20, w20", + "asr w21, w20, #1", + "bfxil x4, x21, #0, #16", + "lsl w22, w21, #16", + "tst w22, w22", + "mrs x22, nzcv", + "ubfx x20, x20, #0, #1", + "orr w20, w22, w20, lsl #29", + "strb w21, [x28, #706]", + "str w20, [x28, #728]" + ] + }, + "sar eax, 1": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": "GROUP2 0xd1 /7", + "ExpectedArm64ASM": [ + "mov w20, w4", + "asr w4, w20, #1", + "tst w4, w4", + "mrs x21, nzcv", + "ubfx w20, w20, #0, #1", + "orr w20, w21, w20, lsl #29", + "strb w4, [x28, #706]", + "str w20, [x28, #728]" + ] + }, + "sar rax, 1": { + "ExpectedInstructionCount": 8, + "Optimal": "Yes", + "Comment": "GROUP2 0xd1 /7", + "ExpectedArm64ASM": [ + "mov x20, x4", + "asr x4, x20, #1", + "tst x4, x4", + "mrs x21, nzcv", + "ubfx x20, x20, #0, #1", + "orr w20, w21, w20, lsl #29", + "strb w4, [x28, #706]", + "str w20, [x28, #728]" + ] + }, + "rol al, cl": { + "ExpectedInstructionCount": 19, + "Optimal": "No", + "Comment": "GROUP2 0xd2 /0", + "ExpectedArm64ASM": [ + "uxtb w20, w4", + "uxtb w21, w5", + "and w21, w21, #0x1f", + "bfi w20, w20, #8, #8", + "bfi w20, w20, #16, #16", + "mov w22, #0x20", + "sub w22, w22, w21", + "ror w20, w20, w22", + "bfxil x4, x20, #0, #8", + "ldr w22, [x28, #728]", + "and w23, w22, #0xc0000000", + "ubfx w24, w20, #0, #1", + "orr w23, w23, w24, lsl #29", + "ubfx w20, w20, #7, #1", + "eor w20, w20, w24", + "orr w20, w23, w20, lsl #28", + "cmp x21, #0x0 (0)", + "csel w20, w22, w20, eq", + "str w20, [x28, #728]" + ] + }, + "ror al, cl": { + "ExpectedInstructionCount": 17, + "Optimal": "No", + "Comment": "GROUP2 0xd2 /1", + "ExpectedArm64ASM": [ + "uxtb w20, w4", + "uxtb w21, w5", + "and w21, w21, #0x1f", + "bfi w20, w20, #8, #8", + "bfi w20, w20, #16, #16", + "ror w20, w20, w21", + "bfxil x4, x20, #0, #8", + "ldr w22, [x28, #728]", + "and w23, w22, #0xc0000000", + "ubfx w24, w20, #7, #1", + "orr w23, w23, w24, lsl #29", + "ubfx w20, w20, #6, #1", + "eor w20, w20, w24", + "orr w20, w23, w20, lsl #28", + "cmp x21, #0x0 (0)", + "csel w20, w22, w20, eq", + "str w20, [x28, #728]" + ] + }, + "rcl al, cl": { + "ExpectedInstructionCount": 39, + "Optimal": "No", + "Comment": "GROUP2 0xd2 /2", + "ExpectedArm64ASM": [ + "uxtb w20, w5", + "uxtb w21, w4", + "ldr w22, [x28, #728]", + "ubfx w23, w22, #29, #1", + "and w20, w20, #0x1f", + "mov w24, #0x0", + "bfi x24, x21, #55, #8", + "bfi x24, x23, #63, #1", + "bfi x24, x21, #46, #8", + "bfi x24, x23, #54, #1", + "bfi x24, x21, #37, #8", + "bfi x24, x23, #45, #1", + "bfi x24, x21, #28, #8", + "bfi x24, x23, #36, #1", + "bfi x24, x21, #19, #8", + "bfi x24, x23, #27, #1", + "mov x0, x24", + "bfxil x0, x21, #0, #8", + "mov x21, x0", + "mov w24, #0x40", + "sub w24, w24, w20", + "ror x24, x21, x24", + "bfxil x4, x24, #0, #8", + "mov w25, #0x3f", + "sub x25, x25, x20", + "ror x21, x21, x25", + "ubfx x21, x21, #0, #1", + "cmp x20, #0x1 (1)", + "csel x23, x21, x23, hs", + "bfi w22, w23, #29, #1", + "ubfx w23, w22, #28, #1", + "ubfx x24, x24, #7, #1", + "eor x21, x24, x21", + "cmp x20, #0x0 (0)", + "csel x20, x23, x21, eq", + "mov w0, w22", + "bfi w0, w20, #28, #1", + "mov w20, w0", + "str w20, [x28, #728]" + ] + }, + "rcr al, cl": { + "ExpectedInstructionCount": 24, + "Optimal": "No", + "Comment": "GROUP2 0xd2 /3", + "ExpectedArm64ASM": [ + "uxtb w20, w5", + "uxtb w21, w4", + "ldr w22, [x28, #728]", + "ubfx w23, w22, #29, #1", + "and w20, w20, #0x1f", + "bfi x21, x23, #8, #1", + "bfi x21, x21, #9, #9", + "bfi x21, x21, #18, #18", + "bfi x21, x21, #36, #9", + "lsr x24, x21, x20", + "bfxil x4, x24, #0, #8", + "sub w25, w20, #0x1 (1)", + "lsr x21, x21, x25", + "ubfx x21, x21, #0, #1", + "cmp w20, #0x1 (1)", + "csel x20, x21, x23, hs", + "mov w0, w22", + "bfi w0, w20, #29, #1", + "mov w20, w0", + "ubfx x21, x24, #7, #1", + "ubfx x22, x24, #6, #1", + "eor x21, x21, x22", + "bfi w20, w21, #28, #1", + "str w20, [x28, #728]" + ] + }, + "shl al, cl": { + "ExpectedInstructionCount": 24, + "Optimal": "No", + "Comment": "GROUP2 0xd2 /4", + "ExpectedArm64ASM": [ + "uxtb w20, w4", + "uxtb w21, w5", + "lsl w22, w20, w21", + "bfxil x4, x22, #0, #8", + "uxtb w22, w22", + "ldr w23, [x28, #728]", + "lsl w24, w22, #24", + "tst w24, w24", + "mrs x24, nzcv", + "mov w25, #0x8", + "sub w25, w25, w21", + "lsr w25, w20, w25", + "ubfx w25, w25, #0, #1", + "orr w24, w24, w25, lsl #29", + "ldrb w25, [x28, #706]", + "cmp x21, #0x0 (0)", + "csel w25, w25, w22, eq", + "strb w25, [x28, #706]", + "eor w20, w20, w22", + "ubfx w20, w20, #7, #1", + "orr w20, w24, w20, lsl #28", + "cmp x21, #0x0 (0)", + "csel w20, w23, w20, eq", + "str w20, [x28, #728]" + ] + }, + "shr al, cl": { + "ExpectedInstructionCount": 22, + "Optimal": "No", + "Comment": "GROUP2 0xd2 /5", + "ExpectedArm64ASM": [ + "uxtb w20, w4", + "uxtb w21, w5", + "lsr w22, w20, w21", + "bfxil x4, x22, #0, #8", + "ldr w23, [x28, #728]", + "lsl w24, w22, #24", + "tst w24, w24", + "mrs x24, nzcv", + "sub x25, x21, #0x1 (1)", + "lsr w25, w20, w25", + "ubfx w25, w25, #0, #1", + "orr w24, w24, w25, lsl #29", + "ldrb w25, [x28, #706]", + "cmp x21, #0x0 (0)", + "csel w25, w25, w22, eq", + "strb w25, [x28, #706]", + "eor w20, w20, w22", + "ubfx w20, w20, #7, #1", + "orr w20, w24, w20, lsl #28", + "cmp x21, #0x0 (0)", + "csel w20, w23, w20, eq", + "str w20, [x28, #728]" + ] + }, + "sar al, cl": { + "ExpectedInstructionCount": 20, + "Optimal": "No", + "Comment": "GROUP2 0xd2 /7", + "ExpectedArm64ASM": [ + "uxtb w20, w4", + "uxtb w21, w5", + "sxtb x20, w20", + "asr w22, w20, w21", + "bfxil x4, x22, #0, #8", + "ldr w23, [x28, #728]", + "lsl w24, w22, #24", + "tst w24, w24", + "mrs x24, nzcv", + "sub x25, x21, #0x1 (1)", + "lsr x20, x20, x25", + "ubfx x20, x20, #0, #1", + "orr w20, w24, w20, lsl #29", + "ldrb w24, [x28, #706]", + "cmp x21, #0x0 (0)", + "csel w22, w24, w22, eq", + "strb w22, [x28, #706]", + "cmp x21, #0x0 (0)", + "csel w20, w23, w20, eq", + "str w20, [x28, #728]" + ] + }, + "rol ax, cl": { + "ExpectedInstructionCount": 18, + "Optimal": "No", + "Comment": "GROUP2 0xd3 /0", + "ExpectedArm64ASM": [ + "uxth w20, w4", + "uxth w21, w5", + "and w21, w21, #0x1f", + "bfi w20, w20, #16, #16", + "mov w22, #0x20", + "sub w22, w22, w21", + "ror w20, w20, w22", + "bfxil x4, x20, #0, #16", + "ldr w22, [x28, #728]", + "and w23, w22, #0xc0000000", + "ubfx w24, w20, #0, #1", + "orr w23, w23, w24, lsl #29", + "ubfx w20, w20, #15, #1", + "eor w20, w20, w24", + "orr w20, w23, w20, lsl #28", + "cmp x21, #0x0 (0)", + "csel w20, w22, w20, eq", + "str w20, [x28, #728]" + ] + }, + "rol eax, cl": { + "ExpectedInstructionCount": 16, + "Optimal": "No", + "Comment": "GROUP2 0xd3 /0", + "ExpectedArm64ASM": [ + "mov w20, w4", + "mov w21, w5", + "and w21, w21, #0x1f", + "mov w22, #0x20", + "sub w22, w22, w21", + "ror w4, w20, w22", + "ldr w20, [x28, #728]", + "and w22, w20, #0xc0000000", + "ubfx w23, w4, #0, #1", + "orr w22, w22, w23, lsl #29", + "lsr w24, w4, #31", + "eor w23, w24, w23", + "orr w22, w22, w23, lsl #28", + "cmp x21, #0x0 (0)", + "csel w20, w20, w22, eq", + "str w20, [x28, #728]" + ] + }, + "rol rax, cl": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": "GROUP2 0xd3 /0", + "ExpectedArm64ASM": [ + "and x20, x5, #0x3f", + "mov w21, #0x40", + "sub x21, x21, x20", + "ror x4, x4, x21", + "ldr w21, [x28, #728]", + "and w22, w21, #0xc0000000", + "ubfx x23, x4, #0, #1", + "orr w22, w22, w23, lsl #29", + "lsr x24, x4, #63", + "eor x23, x24, x23", + "orr w22, w22, w23, lsl #28", + "cmp x20, #0x0 (0)", + "csel w20, w21, w22, eq", + "str w20, [x28, #728]" + ] + }, + "ror ax, cl": { + "ExpectedInstructionCount": 16, + "Optimal": "No", + "Comment": "GROUP2 0xd3 /1", + "ExpectedArm64ASM": [ + "uxth w20, w4", + "uxth w21, w5", + "and w21, w21, #0x1f", + "bfi w20, w20, #16, #16", + "ror w20, w20, w21", + "bfxil x4, x20, #0, #16", + "ldr w22, [x28, #728]", + "and w23, w22, #0xc0000000", + "ubfx w24, w20, #15, #1", + "orr w23, w23, w24, lsl #29", + "ubfx w20, w20, #14, #1", + "eor w20, w20, w24", + "orr w20, w23, w20, lsl #28", + "cmp x21, #0x0 (0)", + "csel w20, w22, w20, eq", + "str w20, [x28, #728]" + ] + }, + "ror eax, cl": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": "GROUP2 0xd3 /1", + "ExpectedArm64ASM": [ + "mov w20, w4", + "mov w21, w5", + "and w21, w21, #0x1f", + "ror w4, w20, w21", + "ldr w20, [x28, #728]", + "and w22, w20, #0xc0000000", + "lsr w23, w4, #31", + "orr w22, w22, w23, lsl #29", + "ubfx w24, w4, #30, #1", + "eor w23, w24, w23", + "orr w22, w22, w23, lsl #28", + "cmp x21, #0x0 (0)", + "csel w20, w20, w22, eq", + "str w20, [x28, #728]" + ] + }, + "ror rax, cl": { + "ExpectedInstructionCount": 12, + "Optimal": "No", + "Comment": "GROUP2 0xd3 /1", + "ExpectedArm64ASM": [ + "and x20, x5, #0x3f", + "ror x4, x4, x20", + "ldr w21, [x28, #728]", + "and w22, w21, #0xc0000000", + "lsr x23, x4, #63", + "orr w22, w22, w23, lsl #29", + "ubfx x24, x4, #62, #1", + "eor x23, x24, x23", + "orr w22, w22, w23, lsl #28", + "cmp x20, #0x0 (0)", + "csel w20, w21, w22, eq", + "str w20, [x28, #728]" + ] + }, + "rcl ax, cl": { + "ExpectedInstructionCount": 35, + "Optimal": "No", + "Comment": "GROUP2 0xd3 /2", + "ExpectedArm64ASM": [ + "uxth w20, w5", + "uxth w21, w4", + "ldr w22, [x28, #728]", + "ubfx w23, w22, #29, #1", + "and w20, w20, #0x1f", + "mov w24, #0x0", + "bfi x24, x21, #47, #16", + "bfi x24, x23, #63, #1", + "bfi x24, x21, #30, #16", + "bfi x24, x23, #46, #1", + "bfi x24, x21, #13, #16", + "bfi x24, x23, #29, #1", + "mov x0, x24", + "bfxil x0, x21, #0, #16", + "mov x21, x0", + "mov w24, #0x40", + "sub w24, w24, w20", + "ror x24, x21, x24", + "bfxil x4, x24, #0, #16", + "mov w25, #0x3f", + "sub x25, x25, x20", + "ror x21, x21, x25", + "ubfx x21, x21, #0, #1", + "cmp x20, #0x1 (1)", + "csel x23, x21, x23, hs", + "bfi w22, w23, #29, #1", + "ubfx w23, w22, #28, #1", + "ubfx x24, x24, #15, #1", + "eor x21, x24, x21", + "cmp x20, #0x0 (0)", + "csel x20, x23, x21, eq", + "mov w0, w22", + "bfi w0, w20, #28, #1", + "mov w20, w0", + "str w20, [x28, #728]" + ] + }, + "rcl eax, cl": { + "ExpectedInstructionCount": 33, + "Optimal": "No", + "Comment": "GROUP2 0xd3 /2", + "ExpectedArm64ASM": [ + "mov w20, w5", + "mov w21, w4", + "ldr w22, [x28, #728]", + "ubfx w23, w22, #29, #1", + "lsl w24, w21, w20", + "mov w25, #0x21", + "sub w25, w25, w20", + "lsr w25, w21, w25", + "mov w26, #0x0", + "cmp w20, #0x1 (1)", + "csel w25, w25, w26, hi", + "orr w24, w24, w25", + "sub w25, w20, #0x1 (1)", + "lsl x25, x23, x25", + "cmp w20, #0x1 (1)", + "csel x25, x25, x26, hs", + "orr w4, w24, w25", + "mov w24, #0x20", + "sub w24, w24, w20", + "lsr w21, w21, w24", + "ubfx w21, w21, #0, #1", + "cmp w20, #0x1 (1)", + "csel w23, w21, w23, hs", + "bfi w22, w23, #29, #1", + "ubfx w23, w22, #28, #1", + "lsr w24, w4, #31", + "eor w21, w24, w21", + "cmp x20, #0x0 (0)", + "csel w20, w23, w21, eq", + "mov w0, w22", + "bfi w0, w20, #28, #1", + "mov w20, w0", + "str w20, [x28, #728]" + ] + }, + "rcl rax, cl": { + "ExpectedInstructionCount": 32, + "Optimal": "No", + "Comment": "GROUP2 0xd3 /2", + "ExpectedArm64ASM": [ + "mov x20, x4", + "ldr w21, [x28, #728]", + "ubfx w22, w21, #29, #1", + "lsl x23, x20, x5", + "mov w24, #0x41", + "sub x24, x24, x5", + "lsr x24, x20, x24", + "mov w25, #0x0", + "cmp x5, #0x1 (1)", + "csel x24, x24, x25, hi", + "orr x23, x23, x24", + "sub x24, x5, #0x1 (1)", + "lsl x24, x22, x24", + "cmp x5, #0x1 (1)", + "csel x24, x24, x25, hs", + "orr x4, x23, x24", + "mov w23, #0x40", + "sub x23, x23, x5", + "lsr x20, x20, x23", + "ubfx x20, x20, #0, #1", + "cmp x5, #0x1 (1)", + "csel x22, x20, x22, hs", + "bfi w21, w22, #29, #1", + "ubfx w22, w21, #28, #1", + "lsr x23, x4, #63", + "eor x20, x23, x20", + "cmp x5, #0x0 (0)", + "csel x20, x22, x20, eq", + "mov w0, w21", + "bfi w0, w20, #28, #1", + "mov w20, w0", + "str w20, [x28, #728]" + ] + }, + "rcr ax, cl": { + "ExpectedInstructionCount": 23, + "Optimal": "No", + "Comment": "GROUP2 0xd3 /3", + "ExpectedArm64ASM": [ + "uxth w20, w5", + "uxth w21, w4", + "ldr w22, [x28, #728]", + "ubfx w23, w22, #29, #1", + "and w20, w20, #0x1f", + "bfi x21, x23, #16, #1", + "bfi x21, x21, #17, #17", + "bfi x21, x21, #34, #17", + "lsr x24, x21, x20", + "bfxil x4, x24, #0, #16", + "sub w25, w20, #0x1 (1)", + "lsr x21, x21, x25", + "ubfx x21, x21, #0, #1", + "cmp w20, #0x1 (1)", + "csel x20, x21, x23, hs", + "mov w0, w22", + "bfi w0, w20, #29, #1", + "mov w20, w0", + "ubfx x21, x24, #15, #1", + "ubfx x22, x24, #14, #1", + "eor x21, x21, x22", + "bfi w20, w21, #28, #1", + "str w20, [x28, #728]" + ] + }, + "rcr eax, cl": { + "ExpectedInstructionCount": 36, + "Optimal": "No", + "Comment": "GROUP2 0xd3 /3", + "ExpectedArm64ASM": [ + "mov w20, w5", + "mov w21, w4", + "ldr w22, [x28, #728]", + "ubfx w23, w22, #29, #1", + "lsr w24, w21, w20", + "mov w25, #0x21", + "sub w25, w25, w20", + "lsl w25, w21, w25", + "mov w26, #0x0", + "cmp w20, #0x1 (1)", + "csel w25, w25, w26, hi", + "orr w24, w24, w25", + "mov w25, #0x20", + "sub w25, w25, w20", + "lsl x25, x23, x25", + "cmp w20, #0x1 (1)", + "csel x25, x25, x26, hs", + "orr w4, w24, w25", + "sub w24, w20, #0x1 (1)", + "lsr w21, w21, w24", + "ubfx w21, w21, #0, #1", + "cmp w20, #0x1 (1)", + "csel w21, w21, w23, hs", + "mov w0, w22", + "bfi w0, w21, #29, #1", + "mov w21, w0", + "ubfx w22, w21, #28, #1", + "lsr w23, w4, #31", + "ubfx w24, w4, #30, #1", + "eor w23, w23, w24", + "cmp x20, #0x0 (0)", + "csel w20, w22, w23, eq", + "mov w0, w21", + "bfi w0, w20, #28, #1", + "mov w20, w0", + "str w20, [x28, #728]" + ] + }, + "rcr rax, cl": { + "ExpectedInstructionCount": 33, + "Optimal": "No", + "Comment": "GROUP2 0xd3 /3", + "ExpectedArm64ASM": [ + "mov x20, x4", + "ldr w21, [x28, #728]", + "ubfx w22, w21, #29, #1", + "lsr x23, x20, x5", + "mov w24, #0x41", + "sub x24, x24, x5", + "lsl x24, x20, x24", + "mov w25, #0x0", + "cmp x5, #0x1 (1)", + "csel x24, x24, x25, hi", + "orr x23, x23, x24", + "mov w24, #0x40", + "sub x24, x24, x5", + "lsl x24, x22, x24", + "cmp x5, #0x1 (1)", + "csel x24, x24, x25, hs", + "orr x4, x23, x24", + "sub x23, x5, #0x1 (1)", + "lsr x20, x20, x23", + "ubfx x20, x20, #0, #1", + "cmp x5, #0x1 (1)", + "csel x20, x20, x22, hs", + "mov w0, w21", + "bfi w0, w20, #29, #1", + "mov w20, w0", + "ubfx w21, w20, #28, #1", + "lsr x22, x4, #63", + "ubfx x23, x4, #62, #1", + "eor x22, x22, x23", + "cmp x5, #0x0 (0)", + "csel x21, x21, x22, eq", + "bfi w20, w21, #28, #1", + "str w20, [x28, #728]" + ] + }, + "shl ax, cl": { + "ExpectedInstructionCount": 24, + "Optimal": "No", + "Comment": "GROUP2 0xd3 /4", + "ExpectedArm64ASM": [ + "uxth w20, w4", + "uxth w21, w5", + "lsl w22, w20, w21", + "bfxil x4, x22, #0, #16", + "uxth w22, w22", + "ldr w23, [x28, #728]", + "lsl w24, w22, #16", + "tst w24, w24", + "mrs x24, nzcv", + "mov w25, #0x10", + "sub w25, w25, w21", + "lsr w25, w20, w25", + "ubfx w25, w25, #0, #1", + "orr w24, w24, w25, lsl #29", + "ldrb w25, [x28, #706]", + "cmp x21, #0x0 (0)", + "csel w25, w25, w22, eq", + "strb w25, [x28, #706]", + "eor w20, w20, w22", + "ubfx w20, w20, #15, #1", + "orr w20, w24, w20, lsl #28", + "cmp x21, #0x0 (0)", + "csel w20, w23, w20, eq", + "str w20, [x28, #728]" + ] + }, + "shl eax, cl": { + "ExpectedInstructionCount": 21, + "Optimal": "No", + "Comment": "GROUP2 0xd3 /4", + "ExpectedArm64ASM": [ + "mov w20, w4", + "mov w21, w5", + "lsl w4, w20, w21", + "ldr w22, [x28, #728]", + "tst w4, w4", + "mrs x23, nzcv", + "mov w24, #0x20", + "sub w24, w24, w21", + "lsr w24, w20, w24", + "ubfx w24, w24, #0, #1", + "orr w23, w23, w24, lsl #29", + "ldrb w24, [x28, #706]", + "cmp x21, #0x0 (0)", + "csel w24, w24, w4, eq", + "strb w24, [x28, #706]", + "eor w20, w20, w4", + "lsr w20, w20, #31", + "orr w20, w23, w20, lsl #28", + "cmp x21, #0x0 (0)", + "csel w20, w22, w20, eq", + "str w20, [x28, #728]" + ] + }, + "shl rax, cl": { + "ExpectedInstructionCount": 20, + "Optimal": "Yes", + "Comment": "GROUP2 0xd3 /4", + "ExpectedArm64ASM": [ + "mov x20, x4", + "lsl x4, x20, x5", + "ldr w21, [x28, #728]", + "tst x4, x4", + "mrs x22, nzcv", + "mov w23, #0x40", + "sub x23, x23, x5", + "lsr x23, x20, x23", + "ubfx x23, x23, #0, #1", + "orr w22, w22, w23, lsl #29", + "ldrb w23, [x28, #706]", + "cmp x5, #0x0 (0)", + "csel x23, x23, x4, eq", + "strb w23, [x28, #706]", + "eor x20, x20, x4", + "lsr x20, x20, #63", + "orr w20, w22, w20, lsl #28", + "cmp x5, #0x0 (0)", + "csel w20, w21, w20, eq", + "str w20, [x28, #728]" + ] + }, + "shr ax, cl": { + "ExpectedInstructionCount": 22, + "Optimal": "No", + "Comment": "GROUP2 0xd3 /5", + "ExpectedArm64ASM": [ + "uxth w20, w4", + "uxth w21, w5", + "lsr w22, w20, w21", + "bfxil x4, x22, #0, #16", + "ldr w23, [x28, #728]", + "lsl w24, w22, #16", + "tst w24, w24", + "mrs x24, nzcv", + "sub x25, x21, #0x1 (1)", + "lsr w25, w20, w25", + "ubfx w25, w25, #0, #1", + "orr w24, w24, w25, lsl #29", + "ldrb w25, [x28, #706]", + "cmp x21, #0x0 (0)", + "csel w25, w25, w22, eq", + "strb w25, [x28, #706]", + "eor w20, w20, w22", + "ubfx w20, w20, #15, #1", + "orr w20, w24, w20, lsl #28", + "cmp x21, #0x0 (0)", + "csel w20, w23, w20, eq", + "str w20, [x28, #728]" + ] + }, + "shr eax, cl": { + "ExpectedInstructionCount": 20, + "Optimal": "No", + "Comment": "GROUP2 0xd3 /5", + "ExpectedArm64ASM": [ + "mov w20, w4", + "mov w21, w5", + "lsr w4, w20, w21", + "ldr w22, [x28, #728]", + "tst w4, w4", + "mrs x23, nzcv", + "sub x24, x21, #0x1 (1)", + "lsr w24, w20, w24", + "ubfx w24, w24, #0, #1", + "orr w23, w23, w24, lsl #29", + "ldrb w24, [x28, #706]", + "cmp x21, #0x0 (0)", + "csel w24, w24, w4, eq", + "strb w24, [x28, #706]", + "eor w20, w20, w4", + "lsr w20, w20, #31", + "orr w20, w23, w20, lsl #28", + "cmp x21, #0x0 (0)", + "csel w20, w22, w20, eq", + "str w20, [x28, #728]" + ] + }, + "shr rax, cl": { + "ExpectedInstructionCount": 19, + "Optimal": "Yes", + "Comment": "GROUP2 0xd3 /5", + "ExpectedArm64ASM": [ + "mov x20, x4", + "lsr x4, x20, x5", + "ldr w21, [x28, #728]", + "tst x4, x4", + "mrs x22, nzcv", + "sub x23, x5, #0x1 (1)", + "lsr x23, x20, x23", + "ubfx x23, x23, #0, #1", + "orr w22, w22, w23, lsl #29", + "ldrb w23, [x28, #706]", + "cmp x5, #0x0 (0)", + "csel x23, x23, x4, eq", + "strb w23, [x28, #706]", + "eor x20, x20, x4", + "lsr x20, x20, #63", + "orr w20, w22, w20, lsl #28", + "cmp x5, #0x0 (0)", + "csel w20, w21, w20, eq", + "str w20, [x28, #728]" + ] + }, + "sar ax, cl": { + "ExpectedInstructionCount": 20, + "Optimal": "No", + "Comment": "GROUP2 0xd3 /7", + "ExpectedArm64ASM": [ + "uxth w20, w4", + "uxth w21, w5", + "sxth x20, w20", + "asr w22, w20, w21", + "bfxil x4, x22, #0, #16", + "ldr w23, [x28, #728]", + "lsl w24, w22, #16", + "tst w24, w24", + "mrs x24, nzcv", + "sub x25, x21, #0x1 (1)", + "lsr x20, x20, x25", + "ubfx x20, x20, #0, #1", + "orr w20, w24, w20, lsl #29", + "ldrb w24, [x28, #706]", + "cmp x21, #0x0 (0)", + "csel w22, w24, w22, eq", + "strb w22, [x28, #706]", + "cmp x21, #0x0 (0)", + "csel w20, w23, w20, eq", + "str w20, [x28, #728]" + ] + }, + "sar eax, cl": { + "ExpectedInstructionCount": 17, + "Optimal": "No", + "Comment": "GROUP2 0xd3 /7", + "ExpectedArm64ASM": [ + "mov w20, w4", + "mov w21, w5", + "asr w4, w20, w21", + "ldr w22, [x28, #728]", + "tst w4, w4", + "mrs x23, nzcv", + "sub x24, x21, #0x1 (1)", + "lsr w20, w20, w24", + "ubfx w20, w20, #0, #1", + "orr w20, w23, w20, lsl #29", + "ldrb w23, [x28, #706]", + "cmp x21, #0x0 (0)", + "csel w23, w23, w4, eq", + "strb w23, [x28, #706]", + "cmp x21, #0x0 (0)", + "csel w20, w22, w20, eq", + "str w20, [x28, #728]" + ] + }, + "sar rax, cl": { + "ExpectedInstructionCount": 16, + "Optimal": "Yes", + "Comment": "GROUP2 0xd3 /7", + "ExpectedArm64ASM": [ + "mov x20, x4", + "asr x4, x20, x5", + "ldr w21, [x28, #728]", + "tst x4, x4", + "mrs x22, nzcv", + "sub x23, x5, #0x1 (1)", + "lsr x20, x20, x23", + "ubfx x20, x20, #0, #1", + "orr w20, w22, w20, lsl #29", + "ldrb w22, [x28, #706]", + "cmp x5, #0x0 (0)", + "csel x22, x22, x4, eq", + "strb w22, [x28, #706]", + "cmp x5, #0x0 (0)", + "csel w20, w21, w20, eq", + "str w20, [x28, #728]" + ] + }, + "test bl, 1": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": "GROUP2 0xf6 /0", + "ExpectedArm64ASM": [ + "and w20, w7, #0x1", + "strb w20, [x28, #706]", + "lsl w20, w20, #24", + "tst w20, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "not bl": { + "ExpectedInstructionCount": 3, + "Optimal": "No", + "Comment": "GROUP2 0xf6 /2", + "ExpectedArm64ASM": [ + "uxtb w20, w7", + "eor x20, x20, #0xff", + "bfxil x7, x20, #0, #8" + ] + }, + "neg bl": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": "GROUP2 0xf6 /3", + "ExpectedArm64ASM": [ + "uxtb w20, w7", + "neg w21, w20", + "bfxil x7, x21, #0, #8", + "strb w20, [x28, #708]", + "strb w21, [x28, #706]", + "lsl w22, w21, #24", + "tst w22, w22", + "mrs x22, nzcv", + "ubfx w23, w21, #8, #1", + "orr w22, w22, w23, lsl #29", + "and w20, w21, w20", + "ubfx w20, w20, #7, #1", + "orr w20, w22, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "mul bl": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": "GROUP2 0xf6 /4", + "ExpectedArm64ASM": [ + "uxtb w20, w7", + "uxtb x21, w4", + "mul x20, x20, x21", + "bfxil x4, x20, #0, #16", + "ubfx x20, x20, #8, #8", + "mov w21, #0x0", + "mov w22, #0x30000000", + "cmp x20, #0x0 (0)", + "csel x20, x21, x22, eq", + "str w20, [x28, #728]" + ] + }, + "imul bl": { + "ExpectedInstructionCount": 12, + "Optimal": "No", + "Comment": "GROUP2 0xf6 /5", + "ExpectedArm64ASM": [ + "uxtb w20, w7", + "sxtb x20, w20", + "sxtb x21, w4", + "mul x20, x20, x21", + "bfxil x4, x20, #0, #16", + "sbfx x21, x20, #8, #8", + "mov w22, #0x0", + "sbfx x20, x20, #7, #1", + "mov w23, #0x30000000", + "cmp x21, x20", + "csel x20, x22, x23, eq", + "str w20, [x28, #728]" + ] + }, + "div bl": { + "ExpectedInstructionCount": 13, + "Optimal": "No", + "Comment": "GROUP2 0xf6 /6", + "ExpectedArm64ASM": [ + "uxtb w20, w7", + "uxth w21, w4", + "uxth w0, w21", + "uxth w1, w20", + "udiv w22, w0, w1", + "uxth w0, w21", + "uxth w1, w20", + "udiv w2, w0, w1", + "msub w20, w2, w1, w0", + "mov x0, x22", + "bfi x0, x20, #8, #8", + "mov x20, x0", + "bfxil x4, x20, #0, #16" + ] + }, + "idiv bl": { + "ExpectedInstructionCount": 11, + "Optimal": "No", + "Comment": "GROUP2 0xf6 /7", + "ExpectedArm64ASM": [ + "uxtb w20, w7", + "uxth w21, w4", + "sxth x21, w21", + "sxtb x20, w20", + "sdiv x22, x21, x20", + "sdiv x0, x21, x20", + "msub x20, x0, x20, x21", + "mov x0, x22", + "bfi x0, x20, #8, #8", + "mov x20, x0", + "bfxil x4, x20, #0, #16" + ] + }, + "test bx, 1": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": "GROUP2 0xf7 /0", + "ExpectedArm64ASM": [ + "and w20, w7, #0x1", + "strb w20, [x28, #706]", + "lsl w20, w20, #16", + "tst w20, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "test ebx, 1": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": "GROUP2 0xf7 /0", + "ExpectedArm64ASM": [ + "and w20, w7, #0x1", + "strb w20, [x28, #706]", + "tst w20, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "test rbx, 1": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": "GROUP2 0xf7 /0", + "ExpectedArm64ASM": [ + "and x20, x7, #0x1", + "strb w20, [x28, #706]", + "tst x20, x20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "test bx, -1": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": "GROUP2 0xf7 /0", + "ExpectedArm64ASM": [ + "and w20, w7, #0xffff", + "strb w20, [x28, #706]", + "lsl w20, w20, #16", + "tst w20, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "test ebx, -1": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": "GROUP2 0xf7 /0", + "ExpectedArm64ASM": [ + "mov w20, #0xffff", + "movk w20, #0xffff, lsl #16", + "and w20, w7, w20", + "strb w20, [x28, #706]", + "tst w20, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "test rbx, -1": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": "GROUP2 0xf7 /0", + "ExpectedArm64ASM": [ + "mov x20, #0xffffffffffffffff", + "and x20, x7, x20", + "strb w20, [x28, #706]", + "tst x20, x20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "neg bx": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": "GROUP2 0xf7 /2", + "ExpectedArm64ASM": [ + "uxth w20, w7", + "neg w21, w20", + "bfxil x7, x21, #0, #16", + "strb w20, [x28, #708]", + "strb w21, [x28, #706]", + "lsl w22, w21, #16", + "tst w22, w22", + "mrs x22, nzcv", + "ubfx w23, w21, #16, #1", + "orr w22, w22, w23, lsl #29", + "and w20, w21, w20", + "ubfx w20, w20, #15, #1", + "orr w20, w22, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "neg ebx": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": "GROUP2 0xf7 /2", + "ExpectedArm64ASM": [ + "mov w20, w7", + "neg w7, w20", + "strb w20, [x28, #708]", + "strb w7, [x28, #706]", + "cmp wzr, w20", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "str w20, [x28, #728]" + ] + }, + "neg rbx": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": "GROUP2 0xf7 /2", + "ExpectedArm64ASM": [ + "mov x20, x7", + "neg x7, x20", + "strb w20, [x28, #708]", + "strb w7, [x28, #706]", + "cmp xzr, x20", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "str w20, [x28, #728]" + ] + }, + "mul bx": { + "ExpectedInstructionCount": 11, + "Optimal": "No", + "Comment": "GROUP2 0xf7 /3", + "ExpectedArm64ASM": [ + "uxth w20, w7", + "uxth x21, w4", + "mul x20, x20, x21", + "bfxil x4, x20, #0, #16", + "ubfx x20, x20, #16, #16", + "bfxil x6, x20, #0, #16", + "mov w21, #0x0", + "mov w22, #0x30000000", + "cmp x20, #0x0 (0)", + "csel x20, x21, x22, eq", + "str w20, [x28, #728]" + ] + }, + "mul ebx": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": "GROUP2 0xf7 /3", + "ExpectedArm64ASM": [ + "mov w20, w7", + "mov w21, w4", + "mul x20, x20, x21", + "mov w4, w20", + "lsr x6, x20, #32", + "mov w20, #0x0", + "mov w21, #0x30000000", + "cmp x6, #0x0 (0)", + "csel x20, x20, x21, eq", + "str w20, [x28, #728]" + ] + }, + "mul rbx": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": "GROUP2 0xf7 /3", + "ExpectedArm64ASM": [ + "mov x20, x4", + "mul x4, x7, x20", + "umulh x6, x7, x20", + "mov w20, #0x0", + "mov w21, #0x30000000", + "cmp x6, #0x0 (0)", + "csel x20, x20, x21, eq", + "str w20, [x28, #728]" + ] + }, + "imul bx": { + "ExpectedInstructionCount": 13, + "Optimal": "No", + "Comment": "GROUP2 0xf7 /5", + "ExpectedArm64ASM": [ + "uxth w20, w7", + "sxth x20, w20", + "sxth x21, w4", + "mul x20, x20, x21", + "bfxil x4, x20, #0, #16", + "sbfx x21, x20, #16, #16", + "bfxil x6, x21, #0, #16", + "mov w22, #0x0", + "sbfx x20, x20, #15, #1", + "mov w23, #0x30000000", + "cmp x21, x20", + "csel x20, x22, x23, eq", + "str w20, [x28, #728]" + ] + }, + "imul ebx": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": "GROUP2 0xf7 /5", + "ExpectedArm64ASM": [ + "mov w20, w7", + "sxtw x20, w20", + "sxtw x21, w4", + "mul x20, x20, x21", + "mov w4, w20", + "lsr x6, x20, #32", + "asr x21, x20, #32", + "sxtw x20, w20", + "mov w22, #0x0", + "sbfx x20, x20, #31, #1", + "mov w23, #0x30000000", + "cmp x21, x20", + "csel x20, x22, x23, eq", + "str w20, [x28, #728]" + ] + }, + "imul rbx": { + "ExpectedInstructionCount": 9, + "Optimal": "No", + "Comment": "GROUP2 0xf7 /5", + "ExpectedArm64ASM": [ + "mov x20, x4", + "mul x4, x7, x20", + "smulh x6, x7, x20", + "mov w20, #0x0", + "asr x21, x4, #63", + "mov w22, #0x30000000", + "cmp x6, x21", + "csel x20, x20, x22, eq", + "str w20, [x28, #728]" + ] + }, + "div bx": { + "ExpectedInstructionCount": 12, + "Optimal": "No", + "Comment": "GROUP2 0xf7 /6", + "ExpectedArm64ASM": [ + "uxth w20, w7", + "uxth w21, w4", + "uxth w22, w6", + "uxth w0, w21", + "bfi w0, w22, #16, #16", + "udiv w23, w0, w20", + "uxth w0, w21", + "bfi w0, w22, #16, #16", + "udiv w1, w0, w20", + "msub w20, w1, w20, w0", + "bfxil x4, x23, #0, #16", + "bfxil x6, x20, #0, #16" + ] + }, + "inc al": { + "ExpectedInstructionCount": 15, + "Optimal": "No", + "Comment": "GROUP3 0xfe /0", + "ExpectedArm64ASM": [ + "uxtb w20, w4", + "add w21, w20, #0x1 (1)", + "bfxil x4, x21, #0, #8", + "strb w20, [x28, #708]", + "strb w21, [x28, #706]", + "ldr w22, [x28, #728]", + "ubfx w22, w22, #29, #1", + "lsl w23, w21, #24", + "tst w23, w23", + "mrs x23, nzcv", + "bic w20, w21, w20", + "ubfx w20, w20, #7, #1", + "orr w20, w23, w20, lsl #28", + "orr w20, w20, w22, lsl #29", + "str w20, [x28, #728]" + ] + }, + "dec al": { + "ExpectedInstructionCount": 15, + "Optimal": "No", + "Comment": "GROUP3 0xfe /1", + "ExpectedArm64ASM": [ + "uxtb w20, w4", + "sub w21, w20, #0x1 (1)", + "bfxil x4, x21, #0, #8", + "strb w20, [x28, #708]", + "strb w21, [x28, #706]", + "ldr w22, [x28, #728]", + "ubfx w22, w22, #29, #1", + "lsl w23, w21, #24", + "tst w23, w23", + "mrs x23, nzcv", + "bic w20, w20, w21", + "ubfx w20, w20, #7, #1", + "orr w20, w23, w20, lsl #28", + "orr w20, w20, w22, lsl #29", + "str w20, [x28, #728]" + ] + }, + "inc ax": { + "ExpectedInstructionCount": 15, + "Optimal": "No", + "Comment": "GROUP4 0xfe /0", + "ExpectedArm64ASM": [ + "uxth w20, w4", + "add w21, w20, #0x1 (1)", + "bfxil x4, x21, #0, #16", + "strb w20, [x28, #708]", + "strb w21, [x28, #706]", + "ldr w22, [x28, #728]", + "ubfx w22, w22, #29, #1", + "lsl w23, w21, #16", + "tst w23, w23", + "mrs x23, nzcv", + "bic w20, w21, w20", + "ubfx w20, w20, #15, #1", + "orr w20, w23, w20, lsl #28", + "orr w20, w20, w22, lsl #29", + "str w20, [x28, #728]" + ] + }, + "inc eax": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": "GROUP4 0xfe /0", + "ExpectedArm64ASM": [ + "mov w20, w4", + "add w4, w20, #0x1 (1)", + "strb w20, [x28, #708]", + "strb w4, [x28, #706]", + "ldr w21, [x28, #728]", + "ubfx w21, w21, #29, #1", + "cmn w20, #0x1 (1)", + "mrs x20, nzcv", + "bfi w20, w21, #29, #1", + "str w20, [x28, #728]" + ] + }, + "inc rax": { + "ExpectedInstructionCount": 10, + "Optimal": "Yes", + "Comment": "GROUP4 0xfe /0", + "ExpectedArm64ASM": [ + "mov x20, x4", + "add x4, x20, #0x1 (1)", + "strb w20, [x28, #708]", + "strb w4, [x28, #706]", + "ldr w21, [x28, #728]", + "ubfx w21, w21, #29, #1", + "cmn x20, #0x1 (1)", + "mrs x20, nzcv", + "bfi w20, w21, #29, #1", + "str w20, [x28, #728]" + ] + }, + "dec ax": { + "ExpectedInstructionCount": 15, + "Optimal": "No", + "Comment": "GROUP4 0xfe /1", + "ExpectedArm64ASM": [ + "uxth w20, w4", + "sub w21, w20, #0x1 (1)", + "bfxil x4, x21, #0, #16", + "strb w20, [x28, #708]", + "strb w21, [x28, #706]", + "ldr w22, [x28, #728]", + "ubfx w22, w22, #29, #1", + "lsl w23, w21, #16", + "tst w23, w23", + "mrs x23, nzcv", + "bic w20, w20, w21", + "ubfx w20, w20, #15, #1", + "orr w20, w23, w20, lsl #28", + "orr w20, w20, w22, lsl #29", + "str w20, [x28, #728]" + ] + }, + "dec eax": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": "GROUP4 0xfe /1", + "ExpectedArm64ASM": [ + "mov w20, w4", + "sub w4, w20, #0x1 (1)", + "strb w20, [x28, #708]", + "strb w4, [x28, #706]", + "ldr w21, [x28, #728]", + "ubfx w21, w21, #29, #1", + "cmp w20, #0x1 (1)", + "mrs x20, nzcv", + "bfi w20, w21, #29, #1", + "str w20, [x28, #728]" + ] + }, + "dec rax": { + "ExpectedInstructionCount": 10, + "Optimal": "Yes", + "Comment": "GROUP4 0xfe /1", + "ExpectedArm64ASM": [ + "mov x20, x4", + "sub x4, x20, #0x1 (1)", + "strb w20, [x28, #708]", + "strb w4, [x28, #706]", + "ldr w21, [x28, #728]", + "ubfx w21, w21, #29, #1", + "cmp x20, #0x1 (1)", + "mrs x20, nzcv", + "bfi w20, w21, #29, #1", + "str w20, [x28, #728]" + ] + } + } +} diff --git a/unittests/InstructionCountCI/FlagM/Secondary.json b/unittests/InstructionCountCI/FlagM/Secondary.json new file mode 100644 index 000000000..88c862deb --- /dev/null +++ b/unittests/InstructionCountCI/FlagM/Secondary.json @@ -0,0 +1,2291 @@ +{ + "Features": { + "Bitness": 64, + "EnabledHostFeatures": [ + "FLAGM", + "FLAGM2" + ], + "DisabledHostFeatures": [ + "SVE128", + "SVE256", + "RPRES", + "AFP" + ] + }, + "Instructions": { + "ucomiss xmm0, xmm1": { + "ExpectedInstructionCount": 19, + "Optimal": "No", + "Comment": "0x0f 0x2e", + "ExpectedArm64ASM": [ + "fcmp s16, s17", + "cset x20, eq", + "csinc x20, x20, xzr, vc", + "cset x1, lt", + "bfi x20, x1, #1, #1", + "cset x1, vs", + "bfi x20, x1, #2, #1", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "lsl x21, x21, #29", + "orr w21, w21, w22, lsl #30", + "eor w20, w20, #0x1", + "strb w20, [x28, #706]", + "mov w20, #0x0", + "mov w22, #0x90000000", + "bic x21, x21, x22", + "strb w20, [x28, #708]", + "str w21, [x28, #728]" + ] + }, + "comiss xmm0, xmm1": { + "ExpectedInstructionCount": 22, + "Optimal": "No", + "Comment": "0x0f 0x2f", + "ExpectedArm64ASM": [ + "fcmp s16, s17", + "cset x20, eq", + "csinc x20, x20, xzr, vc", + "cset x1, lt", + "bfi x20, x1, #1, #1", + "cset x1, vs", + "bfi x20, x1, #2, #1", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "ldr w23, [x28, #728]", + "mov w0, w23", + "bfi w0, w21, #29, #1", + "mov w21, w0", + "bfi w21, w22, #30, #1", + "eor w20, w20, #0x1", + "strb w20, [x28, #706]", + "mov w20, #0x0", + "mov w22, #0x90000000", + "bic x21, x21, x22", + "strb w20, [x28, #708]", + "str w21, [x28, #728]" + ] + }, + "cmovo ax, bx": { + "ExpectedInstructionCount": 4, + "Optimal": "No", + "Comment": "0x0f 0x40", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x10000000", + "csel w20, w7, w4, ne", + "bfxil x4, x20, #0, #16" + ] + }, + "cmovo eax, ebx": { + "ExpectedInstructionCount": 3, + "Optimal": "No", + "Comment": "0x0f 0x40", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x10000000", + "csel w4, w7, w4, ne" + ] + }, + "cmovo rax, rbx": { + "ExpectedInstructionCount": 3, + "Optimal": "Yes", + "Comment": "0x0f 0x40", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x10000000", + "csel x4, x7, x4, ne" + ] + }, + "cmovno ax, bx": { + "ExpectedInstructionCount": 4, + "Optimal": "No", + "Comment": "0x0f 0x41", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x10000000", + "csel w20, w7, w4, eq", + "bfxil x4, x20, #0, #16" + ] + }, + "cmovno eax, ebx": { + "ExpectedInstructionCount": 3, + "Optimal": "No", + "Comment": "0x0f 0x41", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x10000000", + "csel w4, w7, w4, eq" + ] + }, + "cmovno rax, rbx": { + "ExpectedInstructionCount": 3, + "Optimal": "Yes", + "Comment": "0x0f 0x41", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x10000000", + "csel x4, x7, x4, eq" + ] + }, + "cmovb ax, bx": { + "ExpectedInstructionCount": 4, + "Optimal": "No", + "Comment": "0x0f 0x42", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x20000000", + "csel w20, w7, w4, ne", + "bfxil x4, x20, #0, #16" + ] + }, + "cmovb eax, ebx": { + "ExpectedInstructionCount": 3, + "Optimal": "No", + "Comment": "0x0f 0x42", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x20000000", + "csel w4, w7, w4, ne" + ] + }, + "cmovb rax, rbx": { + "ExpectedInstructionCount": 3, + "Optimal": "No", + "Comment": "0x0f 0x42", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x20000000", + "csel x4, x7, x4, ne" + ] + }, + "cmovnb ax, bx": { + "ExpectedInstructionCount": 4, + "Optimal": "No", + "Comment": "0x0f 0x43", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x20000000", + "csel w20, w7, w4, eq", + "bfxil x4, x20, #0, #16" + ] + }, + "cmovnb eax, ebx": { + "ExpectedInstructionCount": 3, + "Optimal": "No", + "Comment": "0x0f 0x43", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x20000000", + "csel w4, w7, w4, eq" + ] + }, + "cmovnb rax, rbx": { + "ExpectedInstructionCount": 3, + "Optimal": "Yes", + "Comment": "0x0f 0x43", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x20000000", + "csel x4, x7, x4, eq" + ] + }, + "cmovz ax, bx": { + "ExpectedInstructionCount": 4, + "Optimal": "No", + "Comment": "0x0f 0x44", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x40000000", + "csel w20, w7, w4, ne", + "bfxil x4, x20, #0, #16" + ] + }, + "cmovz eax, ebx": { + "ExpectedInstructionCount": 3, + "Optimal": "No", + "Comment": "0x0f 0x44", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x40000000", + "csel w4, w7, w4, ne" + ] + }, + "cmovz rax, rbx": { + "ExpectedInstructionCount": 3, + "Optimal": "Yes", + "Comment": "0x0f 0x44", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x40000000", + "csel x4, x7, x4, ne" + ] + }, + "cmovnz ax, bx": { + "ExpectedInstructionCount": 4, + "Optimal": "No", + "Comment": "0x0f 0x45", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x40000000", + "csel w20, w7, w4, eq", + "bfxil x4, x20, #0, #16" + ] + }, + "cmovnz eax, ebx": { + "ExpectedInstructionCount": 3, + "Optimal": "No", + "Comment": "0x0f 0x45", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x40000000", + "csel w4, w7, w4, eq" + ] + }, + "cmovnz rax, rbx": { + "ExpectedInstructionCount": 3, + "Optimal": "Yes", + "Comment": "0x0f 0x45", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x40000000", + "csel x4, x7, x4, eq" + ] + }, + "cmovbe ax, bx": { + "ExpectedInstructionCount": 4, + "Optimal": "No", + "Comment": "0x0f 0x46", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x60000000", + "csel w20, w7, w4, ne", + "bfxil x4, x20, #0, #16" + ] + }, + "cmovbe eax, ebx": { + "ExpectedInstructionCount": 3, + "Optimal": "No", + "Comment": "0x0f 0x46", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x60000000", + "csel w4, w7, w4, ne" + ] + }, + "cmovbe rax, rbx": { + "ExpectedInstructionCount": 3, + "Optimal": "No", + "Comment": "0x0f 0x46", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x60000000", + "csel x4, x7, x4, ne" + ] + }, + "cmovnbe ax, bx": { + "ExpectedInstructionCount": 4, + "Optimal": "No", + "Comment": "0x0f 0x47", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x60000000", + "csel w20, w7, w4, eq", + "bfxil x4, x20, #0, #16" + ] + }, + "cmovnbe eax, ebx": { + "ExpectedInstructionCount": 3, + "Optimal": "No", + "Comment": "0x0f 0x47", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x60000000", + "csel w4, w7, w4, eq" + ] + }, + "cmovnbe rax, rbx": { + "ExpectedInstructionCount": 3, + "Optimal": "No", + "Comment": "0x0f 0x47", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x60000000", + "csel x4, x7, x4, eq" + ] + }, + "cmovs ax, bx": { + "ExpectedInstructionCount": 4, + "Optimal": "No", + "Comment": "0x0f 0x48", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x80000000", + "csel w20, w7, w4, ne", + "bfxil x4, x20, #0, #16" + ] + }, + "cmovs eax, ebx": { + "ExpectedInstructionCount": 3, + "Optimal": "No", + "Comment": "0x0f 0x48", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x80000000", + "csel w4, w7, w4, ne" + ] + }, + "cmovs rax, rbx": { + "ExpectedInstructionCount": 3, + "Optimal": "Yes", + "Comment": "0x0f 0x48", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x80000000", + "csel x4, x7, x4, ne" + ] + }, + "cmovns ax, bx": { + "ExpectedInstructionCount": 4, + "Optimal": "No", + "Comment": "0x0f 0x49", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x80000000", + "csel w20, w7, w4, eq", + "bfxil x4, x20, #0, #16" + ] + }, + "cmovns eax, ebx": { + "ExpectedInstructionCount": 3, + "Optimal": "No", + "Comment": "0x0f 0x49", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x80000000", + "csel w4, w7, w4, eq" + ] + }, + "cmovns rax, rbx": { + "ExpectedInstructionCount": 3, + "Optimal": "Yes", + "Comment": "0x0f 0x49", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x80000000", + "csel x4, x7, x4, eq" + ] + }, + "cmovpe ax, bx": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": "0x0f 0x4a", + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #706]", + "fmov s2, w20", + "cnt v2.16b, v2.16b", + "umov w20, v2.b[0]", + "tst w20, #0x1", + "csel w20, w7, w4, eq", + "bfxil x4, x20, #0, #16" + ] + }, + "cmovpe eax, ebx": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": "0x0f 0x4a", + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #706]", + "fmov s2, w20", + "cnt v2.16b, v2.16b", + "umov w20, v2.b[0]", + "tst w20, #0x1", + "csel w4, w7, w4, eq" + ] + }, + "cmovpe rax, rbx": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": "0x0f 0x4a", + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #706]", + "fmov s2, w20", + "cnt v2.16b, v2.16b", + "umov w20, v2.b[0]", + "tst w20, #0x1", + "csel x4, x7, x4, eq" + ] + }, + "cmovnp ax, bx": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": "0x0f 0x4b", + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #706]", + "fmov s2, w20", + "cnt v2.16b, v2.16b", + "umov w20, v2.b[0]", + "tst w20, #0x1", + "csel w20, w7, w4, ne", + "bfxil x4, x20, #0, #16" + ] + }, + "cmovnp eax, ebx": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": "0x0f 0x4b", + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #706]", + "fmov s2, w20", + "cnt v2.16b, v2.16b", + "umov w20, v2.b[0]", + "tst w20, #0x1", + "csel w4, w7, w4, ne" + ] + }, + "cmovnp rax, rbx": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": "0x0f 0x4b", + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #706]", + "fmov s2, w20", + "cnt v2.16b, v2.16b", + "umov w20, v2.b[0]", + "tst w20, #0x1", + "csel x4, x7, x4, ne" + ] + }, + "cmovl ax, bx": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": "0x0f 0x4c", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "lsr w21, w20, #31", + "ubfx w20, w20, #28, #1", + "cmp w21, w20", + "csel w20, w7, w4, ne", + "bfxil x4, x20, #0, #16" + ] + }, + "cmovl eax, ebx": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": "0x0f 0x4c", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "lsr w21, w20, #31", + "ubfx w20, w20, #28, #1", + "cmp w21, w20", + "csel w4, w7, w4, ne" + ] + }, + "cmovl rax, rbx": { + "ExpectedInstructionCount": 5, + "Optimal": "Yes", + "Comment": "0x0f 0x4c", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "lsr w21, w20, #31", + "ubfx w20, w20, #28, #1", + "cmp w21, w20", + "csel x4, x7, x4, ne" + ] + }, + "cmovnl ax, bx": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": "0x0f 0x4d", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "lsr w21, w20, #31", + "ubfx w20, w20, #28, #1", + "cmp w21, w20", + "csel w20, w7, w4, eq", + "bfxil x4, x20, #0, #16" + ] + }, + "cmovnl eax, ebx": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": "0x0f 0x4d", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "lsr w21, w20, #31", + "ubfx w20, w20, #28, #1", + "cmp w21, w20", + "csel w4, w7, w4, eq" + ] + }, + "cmovnl rax, rbx": { + "ExpectedInstructionCount": 5, + "Optimal": "Yes", + "Comment": "0x0f 0x4d", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "lsr w21, w20, #31", + "ubfx w20, w20, #28, #1", + "cmp w21, w20", + "csel x4, x7, x4, eq" + ] + }, + "cmovle ax, bx": { + "ExpectedInstructionCount": 11, + "Optimal": "No", + "Comment": "0x0f 0x4e", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x40000000", + "cset w21, ne", + "lsr w22, w20, #31", + "ubfx w20, w20, #28, #1", + "cmp w22, w20", + "cset w20, ne", + "orr w20, w21, w20", + "cmp w20, #0x1 (1)", + "csel w20, w7, w4, eq", + "bfxil x4, x20, #0, #16" + ] + }, + "cmovle eax, ebx": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": "0x0f 0x4e", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x40000000", + "cset w21, ne", + "lsr w22, w20, #31", + "ubfx w20, w20, #28, #1", + "cmp w22, w20", + "cset w20, ne", + "orr w20, w21, w20", + "cmp w20, #0x1 (1)", + "csel w4, w7, w4, eq" + ] + }, + "cmovle rax, rbx": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": "0x0f 0x4e", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x40000000", + "cset w21, ne", + "lsr w22, w20, #31", + "ubfx w20, w20, #28, #1", + "cmp w22, w20", + "cset w20, ne", + "orr w20, w21, w20", + "cmp w20, #0x1 (1)", + "csel x4, x7, x4, eq" + ] + }, + "cmovnle ax, bx": { + "ExpectedInstructionCount": 11, + "Optimal": "No", + "Comment": "0x0f 0x4f", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x40000000", + "cset w21, eq", + "lsr w22, w20, #31", + "ubfx w20, w20, #28, #1", + "cmp w22, w20", + "cset w20, eq", + "and w20, w21, w20", + "cmp w20, #0x1 (1)", + "csel w20, w7, w4, eq", + "bfxil x4, x20, #0, #16" + ] + }, + "cmovnle eax, ebx": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": "0x0f 0x4f", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x40000000", + "cset w21, eq", + "lsr w22, w20, #31", + "ubfx w20, w20, #28, #1", + "cmp w22, w20", + "cset w20, eq", + "and w20, w21, w20", + "cmp w20, #0x1 (1)", + "csel w4, w7, w4, eq" + ] + }, + "cmovnle rax, rbx": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": "0x0f 0x4f", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x40000000", + "cset w21, eq", + "lsr w22, w20, #31", + "ubfx w20, w20, #28, #1", + "cmp w22, w20", + "cset w20, eq", + "and w20, w21, w20", + "cmp w20, #0x1 (1)", + "csel x4, x7, x4, eq" + ] + }, + "seto al": { + "ExpectedInstructionCount": 4, + "Optimal": "Yes", + "Comment": "0x0f 0x90", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x10000000", + "cset x20, ne", + "bfxil x4, x20, #0, #8" + ] + }, + "setno al": { + "ExpectedInstructionCount": 4, + "Optimal": "Yes", + "Comment": "0x0f 0x91", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x10000000", + "cset x20, eq", + "bfxil x4, x20, #0, #8" + ] + }, + "setb al": { + "ExpectedInstructionCount": 4, + "Optimal": "Yes", + "Comment": "0x0f 0x92", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x20000000", + "cset x20, ne", + "bfxil x4, x20, #0, #8" + ] + }, + "setnb al": { + "ExpectedInstructionCount": 4, + "Optimal": "Yes", + "Comment": "0x0f 0x93", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x20000000", + "cset x20, eq", + "bfxil x4, x20, #0, #8" + ] + }, + "setz al": { + "ExpectedInstructionCount": 4, + "Optimal": "Yes", + "Comment": "0x0f 0x94", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x40000000", + "cset x20, ne", + "bfxil x4, x20, #0, #8" + ] + }, + "setnz al": { + "ExpectedInstructionCount": 4, + "Optimal": "Yes", + "Comment": "0x0f 0x95", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x40000000", + "cset x20, eq", + "bfxil x4, x20, #0, #8" + ] + }, + "setbe al": { + "ExpectedInstructionCount": 4, + "Optimal": "No", + "Comment": "0x0f 0x96", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x60000000", + "cset x20, ne", + "bfxil x4, x20, #0, #8" + ] + }, + "setnbe al": { + "ExpectedInstructionCount": 4, + "Optimal": "No", + "Comment": "0x0f 0x97", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x60000000", + "cset x20, eq", + "bfxil x4, x20, #0, #8" + ] + }, + "sets al": { + "ExpectedInstructionCount": 4, + "Optimal": "Yes", + "Comment": "0x0f 0x98", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x80000000", + "cset x20, ne", + "bfxil x4, x20, #0, #8" + ] + }, + "setns al": { + "ExpectedInstructionCount": 4, + "Optimal": "Yes", + "Comment": "0x0f 0x99", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x80000000", + "cset x20, eq", + "bfxil x4, x20, #0, #8" + ] + }, + "setpe al": { + "ExpectedInstructionCount": 7, + "Optimal": "Yes", + "Comment": "0x0f 0x9a", + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #706]", + "fmov s2, w20", + "cnt v2.16b, v2.16b", + "umov w20, v2.b[0]", + "tst w20, #0x1", + "cset x20, eq", + "bfxil x4, x20, #0, #8" + ] + }, + "setnp al": { + "ExpectedInstructionCount": 7, + "Optimal": "Yes", + "Comment": "0x0f 0x9b", + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #706]", + "fmov s2, w20", + "cnt v2.16b, v2.16b", + "umov w20, v2.b[0]", + "tst w20, #0x1", + "cset x20, ne", + "bfxil x4, x20, #0, #8" + ] + }, + "setl al": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": "0x0f 0x9c", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "lsr w21, w20, #31", + "ubfx w20, w20, #28, #1", + "cmp w21, w20", + "cset x20, ne", + "bfxil x4, x20, #0, #8" + ] + }, + "setnl al": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": "0x0f 0x9d", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "lsr w21, w20, #31", + "ubfx w20, w20, #28, #1", + "cmp w21, w20", + "cset x20, eq", + "bfxil x4, x20, #0, #8" + ] + }, + "setle al": { + "ExpectedInstructionCount": 11, + "Optimal": "No", + "Comment": "0x0f 0x9e", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x40000000", + "cset w21, ne", + "lsr w22, w20, #31", + "ubfx w20, w20, #28, #1", + "cmp w22, w20", + "cset w20, ne", + "orr w20, w21, w20", + "cmp w20, #0x1 (1)", + "cset x20, eq", + "bfxil x4, x20, #0, #8" + ] + }, + "setnle al": { + "ExpectedInstructionCount": 11, + "Optimal": "No", + "Comment": "0x0f 0x9f", + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x40000000", + "cset w21, eq", + "lsr w22, w20, #31", + "ubfx w20, w20, #28, #1", + "cmp w22, w20", + "cset w20, eq", + "and w20, w21, w20", + "cmp w20, #0x1 (1)", + "cset x20, eq", + "bfxil x4, x20, #0, #8" + ] + }, + "bt ax, bx": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": "0x0f 0xa3", + "ExpectedArm64ASM": [ + "uxth w20, w7", + "and x20, x20, #0xf", + "lsr x20, x4, x20", + "ubfx x20, x20, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "bt [rax], bx": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": "0x0f 0xa3", + "ExpectedArm64ASM": [ + "uxth w20, w7", + "ubfx w21, w20, #0, #3", + "sbfx x20, x20, #3, #13", + "ldrb w20, [x4, x20, sxtx]", + "lsr w20, w20, w21", + "ubfx w20, w20, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "bt eax, ebx": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": "0x0f 0xa3", + "ExpectedArm64ASM": [ + "mov w20, w7", + "and x20, x20, #0x1f", + "lsr x20, x4, x20", + "ubfx x20, x20, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "bt [rax], ebx": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": "0x0f 0xa3", + "ExpectedArm64ASM": [ + "mov w20, w7", + "ubfx w21, w20, #0, #3", + "sbfx x20, x20, #3, #29", + "ldrb w20, [x4, x20, sxtx]", + "lsr w20, w20, w21", + "ubfx w20, w20, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "bt rax, rbx": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": "0x0f 0xa3", + "ExpectedArm64ASM": [ + "and x20, x7, #0x3f", + "lsr x20, x4, x20", + "ubfx x20, x20, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "bt [rax], rbx": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": "0x0f 0xa3", + "ExpectedArm64ASM": [ + "ubfx x20, x7, #0, #3", + "asr x21, x7, #3", + "ldrb w21, [x4, x21, sxtx]", + "lsr w20, w21, w20", + "ubfx w20, w20, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "shld ax, bx, 1": { + "ExpectedInstructionCount": 16, + "Optimal": "No", + "Comment": "0x0f 0xac", + "ExpectedArm64ASM": [ + "uxth w20, w7", + "uxth w21, w4", + "lsl x22, x21, #1", + "lsr w20, w20, #15", + "orr x20, x22, x20", + "bfxil x4, x20, #0, #16", + "lsl w22, w20, #16", + "tst w22, w22", + "mrs x22, nzcv", + "ubfx w23, w21, #15, #1", + "orr w22, w22, w23, lsl #29", + "strb w20, [x28, #706]", + "eor w20, w20, w21", + "ubfx w20, w20, #15, #1", + "orr w20, w22, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "shld ax, bx, 15": { + "ExpectedInstructionCount": 13, + "Optimal": "No", + "Comment": "0x0f 0xac", + "ExpectedArm64ASM": [ + "uxth w20, w7", + "uxth w21, w4", + "lsl x22, x21, #15", + "lsr w20, w20, #1", + "orr x20, x22, x20", + "bfxil x4, x20, #0, #16", + "lsl w22, w20, #16", + "tst w22, w22", + "mrs x22, nzcv", + "ubfx w21, w21, #1, #1", + "orr w21, w22, w21, lsl #29", + "strb w20, [x28, #706]", + "str w21, [x28, #728]" + ] + }, + "shld ax, bx, 16": { + "ExpectedInstructionCount": 12, + "Optimal": "No", + "Comment": "0x0f 0xac", + "ExpectedArm64ASM": [ + "uxth w20, w7", + "uxth w21, w4", + "lsl x22, x21, #16", + "orr x20, x22, x20", + "bfxil x4, x20, #0, #16", + "lsl w22, w20, #16", + "tst w22, w22", + "mrs x22, nzcv", + "ubfx w21, w21, #0, #1", + "orr w21, w22, w21, lsl #29", + "strb w20, [x28, #706]", + "str w21, [x28, #728]" + ] + }, + "shld ax, bx, 31": { + "ExpectedInstructionCount": 13, + "Optimal": "No", + "Comment": "0x0f 0xac", + "ExpectedArm64ASM": [ + "uxth w20, w7", + "uxth w21, w4", + "lsl x22, x21, #31", + "lsr w20, w20, #17", + "orr x20, x22, x20", + "bfxil x4, x20, #0, #16", + "lsl w22, w20, #16", + "tst w22, w22", + "mrs x22, nzcv", + "ubfx w21, w21, #1, #1", + "orr w21, w22, w21, lsl #29", + "strb w20, [x28, #706]", + "str w21, [x28, #728]" + ] + }, + "shld eax, ebx, 1": { + "ExpectedInstructionCount": 12, + "Optimal": "No", + "Comment": "0x0f 0xac", + "ExpectedArm64ASM": [ + "mov w20, w7", + "mov w21, w4", + "extr w4, w21, w20, #31", + "tst w4, w4", + "mrs x20, nzcv", + "lsr w22, w21, #31", + "orr w20, w20, w22, lsl #29", + "strb w4, [x28, #706]", + "eor w21, w4, w21", + "lsr w21, w21, #31", + "orr w20, w20, w21, lsl #28", + "str w20, [x28, #728]" + ] + }, + "shld eax, ebx, 15": { + "ExpectedInstructionCount": 9, + "Optimal": "No", + "Comment": "0x0f 0xac", + "ExpectedArm64ASM": [ + "mov w20, w7", + "mov w21, w4", + "extr w4, w21, w20, #17", + "tst w4, w4", + "mrs x20, nzcv", + "ubfx w21, w21, #17, #1", + "orr w20, w20, w21, lsl #29", + "strb w4, [x28, #706]", + "str w20, [x28, #728]" + ] + }, + "shld eax, ebx, 16": { + "ExpectedInstructionCount": 9, + "Optimal": "No", + "Comment": "0x0f 0xac", + "ExpectedArm64ASM": [ + "mov w20, w7", + "mov w21, w4", + "extr w4, w21, w20, #16", + "tst w4, w4", + "mrs x20, nzcv", + "ubfx w21, w21, #16, #1", + "orr w20, w20, w21, lsl #29", + "strb w4, [x28, #706]", + "str w20, [x28, #728]" + ] + }, + "shld eax, ebx, 31": { + "ExpectedInstructionCount": 9, + "Optimal": "No", + "Comment": "0x0f 0xac", + "ExpectedArm64ASM": [ + "mov w20, w7", + "mov w21, w4", + "extr w4, w21, w20, #1", + "tst w4, w4", + "mrs x20, nzcv", + "ubfx w21, w21, #1, #1", + "orr w20, w20, w21, lsl #29", + "strb w4, [x28, #706]", + "str w20, [x28, #728]" + ] + }, + "shld rax, rbx, 1": { + "ExpectedInstructionCount": 11, + "Optimal": "No", + "Comment": "0x0f 0xac", + "ExpectedArm64ASM": [ + "mov x20, x4", + "extr x4, x20, x7, #63", + "tst x4, x4", + "mrs x21, nzcv", + "lsr x22, x20, #63", + "orr w21, w21, w22, lsl #29", + "strb w4, [x28, #706]", + "eor x20, x4, x20", + "lsr x20, x20, #63", + "orr w20, w21, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "shld rax, rbx, 15": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": "0x0f 0xac", + "ExpectedArm64ASM": [ + "mov x20, x4", + "extr x4, x20, x7, #49", + "tst x4, x4", + "mrs x21, nzcv", + "ubfx x20, x20, #49, #1", + "orr w20, w21, w20, lsl #29", + "strb w4, [x28, #706]", + "str w20, [x28, #728]" + ] + }, + "shld rax, rbx, 32": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": "0x0f 0xac", + "ExpectedArm64ASM": [ + "mov x20, x4", + "extr x4, x20, x7, #32", + "tst x4, x4", + "mrs x21, nzcv", + "ubfx x20, x20, #32, #1", + "orr w20, w21, w20, lsl #29", + "strb w4, [x28, #706]", + "str w20, [x28, #728]" + ] + }, + "shld rax, rbx, 63": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": "0x0f 0xac", + "ExpectedArm64ASM": [ + "mov x20, x4", + "extr x4, x20, x7, #1", + "tst x4, x4", + "mrs x21, nzcv", + "ubfx x20, x20, #1, #1", + "orr w20, w21, w20, lsl #29", + "strb w4, [x28, #706]", + "str w20, [x28, #728]" + ] + }, + "shld ax, bx, cl": { + "ExpectedInstructionCount": 31, + "Optimal": "No", + "Comment": "0x0f 0xad", + "ExpectedArm64ASM": [ + "uxth w20, w7", + "uxth w21, w4", + "uxtb w22, w5", + "and x22, x22, #0x1f", + "mov w23, #0x10", + "sub x24, x23, x22", + "lsl x25, x21, x22", + "lsr w20, w20, w24", + "orr x20, x25, x20", + "cmp x22, #0x0 (0)", + "csel x20, x21, x20, eq", + "bfxil x4, x20, #0, #16", + "uxth x20, w20", + "ldr w24, [x28, #728]", + "lsl w25, w20, #16", + "tst w25, w25", + "mrs x25, nzcv", + "sub w23, w23, w22", + "lsr w23, w21, w23", + "ubfx w23, w23, #0, #1", + "orr w23, w25, w23, lsl #29", + "ldrb w25, [x28, #706]", + "cmp x22, #0x0 (0)", + "csel x25, x25, x20, eq", + "strb w25, [x28, #706]", + "eor w20, w21, w20", + "ubfx w20, w20, #15, #1", + "orr w20, w23, w20, lsl #28", + "cmp x22, #0x0 (0)", + "csel w20, w24, w20, eq", + "str w20, [x28, #728]" + ] + }, + "shld eax, ebx, cl": { + "ExpectedInstructionCount": 30, + "Optimal": "No", + "Comment": "0x0f 0xad", + "ExpectedArm64ASM": [ + "mov w20, w7", + "mov w21, w4", + "uxtb w22, w5", + "and x22, x22, #0x1f", + "mov w23, #0x20", + "sub x24, x23, x22", + "lsl x25, x21, x22", + "lsr w20, w20, w24", + "orr x20, x25, x20", + "cmp x22, #0x0 (0)", + "csel x20, x21, x20, eq", + "mov w4, w20", + "mov w20, w20", + "ldr w24, [x28, #728]", + "tst w20, w20", + "mrs x25, nzcv", + "sub w23, w23, w22", + "lsr w23, w21, w23", + "ubfx w23, w23, #0, #1", + "orr w23, w25, w23, lsl #29", + "ldrb w25, [x28, #706]", + "cmp x22, #0x0 (0)", + "csel x25, x25, x20, eq", + "strb w25, [x28, #706]", + "eor w20, w21, w20", + "lsr w20, w20, #31", + "orr w20, w23, w20, lsl #28", + "cmp x22, #0x0 (0)", + "csel w20, w24, w20, eq", + "str w20, [x28, #728]" + ] + }, + "shld rax, rbx, cl": { + "ExpectedInstructionCount": 27, + "Optimal": "No", + "Comment": "0x0f 0xad", + "ExpectedArm64ASM": [ + "mov x20, x4", + "uxtb w21, w5", + "and x21, x21, #0x3f", + "mov w22, #0x40", + "sub x23, x22, x21", + "lsl x24, x20, x21", + "lsr x23, x7, x23", + "orr x23, x24, x23", + "cmp x21, #0x0 (0)", + "csel x4, x20, x23, eq", + "ldr w23, [x28, #728]", + "tst x4, x4", + "mrs x24, nzcv", + "sub x22, x22, x21", + "lsr x22, x20, x22", + "ubfx x22, x22, #0, #1", + "orr w22, w24, w22, lsl #29", + "ldrb w24, [x28, #706]", + "cmp x21, #0x0 (0)", + "csel x24, x24, x4, eq", + "strb w24, [x28, #706]", + "eor x20, x20, x4", + "lsr x20, x20, #63", + "orr w20, w22, w20, lsl #28", + "cmp x21, #0x0 (0)", + "csel w20, w23, w20, eq", + "str w20, [x28, #728]" + ] + }, + "bts ax, bx": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": "0x0f 0xab", + "ExpectedArm64ASM": [ + "uxth w20, w7", + "and x20, x20, #0xf", + "lsr x21, x4, x20", + "mov w22, #0x1", + "lsl x20, x22, x20", + "orr x20, x4, x20", + "bfxil x4, x20, #0, #16", + "ubfx x20, x21, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "bts [rax], bx": { + "ExpectedInstructionCount": 12, + "Optimal": "No", + "Comment": "0x0f 0xab", + "ExpectedArm64ASM": [ + "uxth w20, w7", + "ubfx w21, w20, #0, #3", + "sbfx x20, x20, #3, #13", + "mov w22, #0x1", + "lsl x22, x22, x21", + "ldrb w23, [x4, x20, sxtx]", + "lsr w21, w23, w21", + "orr x22, x23, x22", + "strb w22, [x4, x20, sxtx]", + "ubfx w20, w21, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "bts eax, ebx": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": "0x0f 0xab", + "ExpectedArm64ASM": [ + "mov w20, w7", + "and x20, x20, #0x1f", + "lsr x21, x4, x20", + "mov w22, #0x1", + "lsl x20, x22, x20", + "orr x20, x4, x20", + "mov w4, w20", + "ubfx x20, x21, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "bts [rax], ebx": { + "ExpectedInstructionCount": 12, + "Optimal": "No", + "Comment": "0x0f 0xab", + "ExpectedArm64ASM": [ + "mov w20, w7", + "ubfx w21, w20, #0, #3", + "sbfx x20, x20, #3, #29", + "mov w22, #0x1", + "lsl x22, x22, x21", + "ldrb w23, [x4, x20, sxtx]", + "lsr w21, w23, w21", + "orr x22, x23, x22", + "strb w22, [x4, x20, sxtx]", + "ubfx w20, w21, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "bts rax, rbx": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": "0x0f 0xab", + "ExpectedArm64ASM": [ + "and x20, x7, #0x3f", + "lsr x21, x4, x20", + "mov w22, #0x1", + "lsl x20, x22, x20", + "orr x4, x4, x20", + "ubfx x20, x21, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "bts [rax], rbx": { + "ExpectedInstructionCount": 11, + "Optimal": "No", + "Comment": "0x0f 0xab", + "ExpectedArm64ASM": [ + "ubfx x20, x7, #0, #3", + "asr x21, x7, #3", + "mov w22, #0x1", + "lsl x22, x22, x20", + "ldrb w23, [x4, x21, sxtx]", + "lsr w20, w23, w20", + "orr x22, x23, x22", + "strb w22, [x4, x21, sxtx]", + "ubfx w20, w20, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "lock bts [rax], bx": { + "ExpectedInstructionCount": 11, + "Optimal": "No", + "Comment": "0x0f 0xb3", + "ExpectedArm64ASM": [ + "uxth w20, w7", + "ubfx w21, w20, #0, #3", + "sbfx x20, x20, #3, #13", + "add x20, x4, x20", + "mov w22, #0x1", + "lsl x22, x22, x21", + "ldsetalb w22, w20, [x20]", + "lsr w20, w20, w21", + "ubfx w20, w20, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "lock bts [rax], ebx": { + "ExpectedInstructionCount": 11, + "Optimal": "No", + "Comment": "0x0f 0xb3", + "ExpectedArm64ASM": [ + "mov w20, w7", + "ubfx w21, w20, #0, #3", + "sbfx x20, x20, #3, #29", + "add x20, x4, x20", + "mov w22, #0x1", + "lsl x22, x22, x21", + "ldsetalb w22, w20, [x20]", + "lsr w20, w20, w21", + "ubfx w20, w20, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "lock bts [rax], rbx": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": "0x0f 0xb3", + "ExpectedArm64ASM": [ + "ubfx x20, x7, #0, #3", + "asr x21, x7, #3", + "add x21, x4, x21", + "mov w22, #0x1", + "lsl x22, x22, x20", + "ldsetalb w22, w21, [x21]", + "lsr w20, w21, w20", + "ubfx w20, w20, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "imul ax, bx": { + "ExpectedInstructionCount": 13, + "Optimal": "No", + "Comment": "0x0f 0xaf", + "ExpectedArm64ASM": [ + "uxth w20, w4", + "uxth w21, w7", + "sxth x20, w20", + "sxth x21, w21", + "mul x20, x20, x21", + "sbfx x21, x20, #16, #16", + "bfxil x4, x20, #0, #16", + "mov w22, #0x0", + "sbfx x20, x20, #15, #1", + "mov w23, #0x30000000", + "cmp x21, x20", + "csel x20, x22, x23, eq", + "str w20, [x28, #728]" + ] + }, + "imul eax, ebx": { + "ExpectedInstructionCount": 13, + "Optimal": "No", + "Comment": "0x0f 0xaf", + "ExpectedArm64ASM": [ + "mov w20, w4", + "mov w21, w7", + "sxtw x20, w20", + "sxtw x21, w21", + "mul x20, x20, x21", + "asr x21, x20, #32", + "mov w4, w20", + "mov w22, #0x0", + "sbfx x20, x20, #31, #1", + "mov w23, #0x30000000", + "cmp x21, x20", + "csel x20, x22, x23, eq", + "str w20, [x28, #728]" + ] + }, + "imul rax, rbx": { + "ExpectedInstructionCount": 9, + "Optimal": "No", + "Comment": "0x0f 0xaf", + "ExpectedArm64ASM": [ + "mov x20, x4", + "mul x4, x20, x7", + "smulh x20, x20, x7", + "mov w21, #0x0", + "asr x22, x4, #63", + "mov w23, #0x30000000", + "cmp x20, x22", + "csel x20, x21, x23, eq", + "str w20, [x28, #728]" + ] + }, + "cmpxchg al, bl": { + "ExpectedInstructionCount": 24, + "Optimal": "No", + "Comment": "0x0f 0xb0", + "ExpectedArm64ASM": [ + "uxtb w20, w7", + "uxtb w21, w4", + "uxtb x22, w4", + "cmp x21, x22", + "csel x23, x22, x21, eq", + "cmp x21, x22", + "csel w20, w20, w21, eq", + "bfxil x4, x23, #0, #8", + "bfxil x4, x20, #0, #8", + "sub x20, x22, x23", + "eor w21, w22, w23", + "strb w21, [x28, #708]", + "strb w20, [x28, #706]", + "lsl w21, w20, #24", + "tst w21, w21", + "mrs x21, nzcv", + "ubfx w24, w20, #8, #1", + "orr w21, w21, w24, lsl #29", + "eor w23, w22, w23", + "eor w20, w20, w22", + "and w20, w20, w23", + "ubfx w20, w20, #7, #1", + "orr w20, w21, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "cmpxchg [rax], bl": { + "ExpectedInstructionCount": 21, + "Optimal": "No", + "Comment": "0x0f 0xb0", + "ExpectedArm64ASM": [ + "uxtb w20, w7", + "uxtb w21, w4", + "mov w1, w21", + "casalb w1, w20, [x4]", + "mov w20, w1", + "bfxil x4, x20, #0, #8", + "sub w22, w21, w20", + "eor w23, w21, w20", + "strb w23, [x28, #708]", + "strb w22, [x28, #706]", + "lsl w23, w22, #24", + "tst w23, w23", + "mrs x23, nzcv", + "ubfx w24, w22, #8, #1", + "orr w23, w23, w24, lsl #29", + "eor w20, w21, w20", + "eor w21, w22, w21", + "and w20, w21, w20", + "ubfx w20, w20, #7, #1", + "orr w20, w23, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "cmpxchg ax, bx": { + "ExpectedInstructionCount": 24, + "Optimal": "No", + "Comment": "0x0f 0xb1", + "ExpectedArm64ASM": [ + "uxth w20, w7", + "uxth w21, w4", + "uxth x22, w4", + "cmp x21, x22", + "csel x23, x22, x21, eq", + "cmp x21, x22", + "csel w20, w20, w21, eq", + "bfxil x4, x23, #0, #16", + "bfxil x4, x20, #0, #16", + "sub x20, x22, x23", + "eor w21, w22, w23", + "strb w21, [x28, #708]", + "strb w20, [x28, #706]", + "lsl w21, w20, #16", + "tst w21, w21", + "mrs x21, nzcv", + "ubfx w24, w20, #16, #1", + "orr w21, w21, w24, lsl #29", + "eor w23, w22, w23", + "eor w20, w20, w22", + "and w20, w20, w23", + "ubfx w20, w20, #15, #1", + "orr w20, w21, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "cmpxchg [rax], bx": { + "ExpectedInstructionCount": 21, + "Optimal": "No", + "Comment": "0x0f 0xb1", + "ExpectedArm64ASM": [ + "uxth w20, w7", + "uxth w21, w4", + "mov w1, w21", + "casalh w1, w20, [x4]", + "mov w20, w1", + "bfxil x4, x20, #0, #16", + "sub w22, w21, w20", + "eor w23, w21, w20", + "strb w23, [x28, #708]", + "strb w22, [x28, #706]", + "lsl w23, w22, #16", + "tst w23, w23", + "mrs x23, nzcv", + "ubfx w24, w22, #16, #1", + "orr w23, w23, w24, lsl #29", + "eor w20, w21, w20", + "eor w21, w22, w21", + "and w20, w21, w20", + "ubfx w20, w20, #15, #1", + "orr w20, w23, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "cmpxchg eax, ebx": { + "ExpectedInstructionCount": 19, + "Optimal": "No", + "Comment": "0x0f 0xb1", + "ExpectedArm64ASM": [ + "mov w20, w7", + "mov x21, x4", + "mov w22, w21", + "mov w23, w21", + "cmp x22, x23", + "csel x24, x23, x22, eq", + "cmp x22, x23", + "csel x20, x20, x21, eq", + "cmp x24, x23", + "csel x4, x21, x22, eq", + "mov x4, x20", + "sub x20, x23, x24", + "eor w21, w23, w24", + "strb w21, [x28, #708]", + "strb w20, [x28, #706]", + "cmp w23, w24", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "str w20, [x28, #728]" + ] + }, + "cmpxchg [rax], ebx": { + "ExpectedInstructionCount": 15, + "Optimal": "No", + "Comment": "0x0f 0xb1", + "ExpectedArm64ASM": [ + "mov w20, w7", + "mov w21, w4", + "mov w1, w21", + "casal w1, w20, [x4]", + "mov w20, w1", + "cmp w20, w21", + "csel x4, x4, x20, eq", + "sub w22, w21, w20", + "eor w23, w21, w20", + "strb w23, [x28, #708]", + "strb w22, [x28, #706]", + "cmp w21, w20", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "str w20, [x28, #728]" + ] + }, + "cmpxchg rax, rbx": { + "ExpectedInstructionCount": 15, + "Optimal": "No", + "Comment": "0x0f 0xb1", + "ExpectedArm64ASM": [ + "mov x20, x4", + "cmp x20, x20", + "csel x21, x20, x20, eq", + "cmp x20, x20", + "csel x22, x7, x20, eq", + "mov x4, x21", + "mov x4, x22", + "sub x22, x20, x21", + "eor x23, x20, x21", + "strb w23, [x28, #708]", + "strb w22, [x28, #706]", + "cmp x20, x21", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "str w20, [x28, #728]" + ] + }, + "cmpxchg [rax], rbx": { + "ExpectedInstructionCount": 12, + "Optimal": "No", + "Comment": "0x0f 0xb1", + "ExpectedArm64ASM": [ + "mov x20, x4", + "mov x1, x20", + "casal x1, x7, [x20]", + "mov x4, x1", + "sub x21, x20, x4", + "eor x22, x20, x4", + "strb w22, [x28, #708]", + "strb w21, [x28, #706]", + "cmp x20, x4", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "str w20, [x28, #728]" + ] + }, + "btr ax, bx": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": "0x0f 0xb3", + "ExpectedArm64ASM": [ + "uxth w20, w7", + "and x20, x20, #0xf", + "lsr x21, x4, x20", + "mov w22, #0x1", + "lsl x20, x22, x20", + "bic x20, x4, x20", + "bfxil x4, x20, #0, #16", + "ubfx x20, x21, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "btr [rax], bx": { + "ExpectedInstructionCount": 12, + "Optimal": "No", + "Comment": "0x0f 0xb3", + "ExpectedArm64ASM": [ + "uxth w20, w7", + "ubfx w21, w20, #0, #3", + "sbfx x20, x20, #3, #13", + "mov w22, #0x1", + "lsl x22, x22, x21", + "ldrb w23, [x4, x20, sxtx]", + "lsr w21, w23, w21", + "bic x22, x23, x22", + "strb w22, [x4, x20, sxtx]", + "ubfx w20, w21, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "btr eax, ebx": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": "0x0f 0xb3", + "ExpectedArm64ASM": [ + "mov w20, w7", + "and x20, x20, #0x1f", + "lsr x21, x4, x20", + "mov w22, #0x1", + "lsl x20, x22, x20", + "bic x20, x4, x20", + "mov w4, w20", + "ubfx x20, x21, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "btr [rax], ebx": { + "ExpectedInstructionCount": 12, + "Optimal": "No", + "Comment": "0x0f 0xb3", + "ExpectedArm64ASM": [ + "mov w20, w7", + "ubfx w21, w20, #0, #3", + "sbfx x20, x20, #3, #29", + "mov w22, #0x1", + "lsl x22, x22, x21", + "ldrb w23, [x4, x20, sxtx]", + "lsr w21, w23, w21", + "bic x22, x23, x22", + "strb w22, [x4, x20, sxtx]", + "ubfx w20, w21, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "btr rax, rbx": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": "0x0f 0xb3", + "ExpectedArm64ASM": [ + "and x20, x7, #0x3f", + "lsr x21, x4, x20", + "mov w22, #0x1", + "lsl x20, x22, x20", + "bic x4, x4, x20", + "ubfx x20, x21, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "btr [rax], rbx": { + "ExpectedInstructionCount": 11, + "Optimal": "No", + "Comment": "0x0f 0xb3", + "ExpectedArm64ASM": [ + "ubfx x20, x7, #0, #3", + "asr x21, x7, #3", + "mov w22, #0x1", + "lsl x22, x22, x20", + "ldrb w23, [x4, x21, sxtx]", + "lsr w20, w23, w20", + "bic x22, x23, x22", + "strb w22, [x4, x21, sxtx]", + "ubfx w20, w20, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "lock btr [rax], bx": { + "ExpectedInstructionCount": 11, + "Optimal": "No", + "Comment": "0x0f 0xb3", + "ExpectedArm64ASM": [ + "uxth w20, w7", + "ubfx w21, w20, #0, #3", + "sbfx x20, x20, #3, #13", + "add x20, x4, x20", + "mov w22, #0x1", + "lsl x22, x22, x21", + "ldclralb w22, w20, [x20]", + "lsr w20, w20, w21", + "ubfx w20, w20, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "lock btr [rax], ebx": { + "ExpectedInstructionCount": 11, + "Optimal": "No", + "Comment": "0x0f 0xb3", + "ExpectedArm64ASM": [ + "mov w20, w7", + "ubfx w21, w20, #0, #3", + "sbfx x20, x20, #3, #29", + "add x20, x4, x20", + "mov w22, #0x1", + "lsl x22, x22, x21", + "ldclralb w22, w20, [x20]", + "lsr w20, w20, w21", + "ubfx w20, w20, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "lock btr [rax], rbx": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": "0x0f 0xb3", + "ExpectedArm64ASM": [ + "ubfx x20, x7, #0, #3", + "asr x21, x7, #3", + "add x21, x4, x21", + "mov w22, #0x1", + "lsl x22, x22, x20", + "ldclralb w22, w21, [x21]", + "lsr w20, w21, w20", + "ubfx w20, w20, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "btc ax, bx": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": "0x0f 0xbb", + "ExpectedArm64ASM": [ + "uxth w20, w7", + "and x20, x20, #0xf", + "lsr x21, x4, x20", + "mov w22, #0x1", + "lsl x20, x22, x20", + "eor x20, x4, x20", + "bfxil x4, x20, #0, #16", + "ubfx x20, x21, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "btc [rax], bx": { + "ExpectedInstructionCount": 12, + "Optimal": "No", + "Comment": "0x0f 0xbb", + "ExpectedArm64ASM": [ + "uxth w20, w7", + "ubfx w21, w20, #0, #3", + "sbfx x20, x20, #3, #13", + "mov w22, #0x1", + "lsl x22, x22, x21", + "ldrb w23, [x4, x20, sxtx]", + "lsr w21, w23, w21", + "eor x22, x23, x22", + "strb w22, [x4, x20, sxtx]", + "ubfx w20, w21, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "btc eax, ebx": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": "0x0f 0xbb", + "ExpectedArm64ASM": [ + "mov w20, w7", + "and x20, x20, #0x1f", + "lsr x21, x4, x20", + "mov w22, #0x1", + "lsl x20, x22, x20", + "eor x20, x4, x20", + "mov w4, w20", + "ubfx x20, x21, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "btc [rax], ebx": { + "ExpectedInstructionCount": 12, + "Optimal": "No", + "Comment": "0x0f 0xbb", + "ExpectedArm64ASM": [ + "mov w20, w7", + "ubfx w21, w20, #0, #3", + "sbfx x20, x20, #3, #29", + "mov w22, #0x1", + "lsl x22, x22, x21", + "ldrb w23, [x4, x20, sxtx]", + "lsr w21, w23, w21", + "eor x22, x23, x22", + "strb w22, [x4, x20, sxtx]", + "ubfx w20, w21, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "btc rax, rbx": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": "0x0f 0xbb", + "ExpectedArm64ASM": [ + "and x20, x7, #0x3f", + "lsr x21, x4, x20", + "mov w22, #0x1", + "lsl x20, x22, x20", + "eor x4, x4, x20", + "ubfx x20, x21, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "btc [rax], rbx": { + "ExpectedInstructionCount": 11, + "Optimal": "No", + "Comment": "0x0f 0xbb", + "ExpectedArm64ASM": [ + "ubfx x20, x7, #0, #3", + "asr x21, x7, #3", + "mov w22, #0x1", + "lsl x22, x22, x20", + "ldrb w23, [x4, x21, sxtx]", + "lsr w20, w23, w20", + "eor x22, x23, x22", + "strb w22, [x4, x21, sxtx]", + "ubfx w20, w20, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "lock btc [rax], bx": { + "ExpectedInstructionCount": 11, + "Optimal": "No", + "Comment": "0x0f 0xb3", + "ExpectedArm64ASM": [ + "uxth w20, w7", + "ubfx w21, w20, #0, #3", + "sbfx x20, x20, #3, #13", + "add x20, x4, x20", + "mov w22, #0x1", + "lsl x22, x22, x21", + "ldeoralb w22, w20, [x20]", + "lsr w20, w20, w21", + "ubfx w20, w20, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "lock btc [rax], ebx": { + "ExpectedInstructionCount": 11, + "Optimal": "No", + "Comment": "0x0f 0xb3", + "ExpectedArm64ASM": [ + "mov w20, w7", + "ubfx w21, w20, #0, #3", + "sbfx x20, x20, #3, #29", + "add x20, x4, x20", + "mov w22, #0x1", + "lsl x22, x22, x21", + "ldeoralb w22, w20, [x20]", + "lsr w20, w20, w21", + "ubfx w20, w20, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "lock btc [rax], rbx": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": "0x0f 0xb3", + "ExpectedArm64ASM": [ + "ubfx x20, x7, #0, #3", + "asr x21, x7, #3", + "add x21, x4, x21", + "mov w22, #0x1", + "lsl x22, x22, x20", + "ldeoralb w22, w21, [x21]", + "lsr w20, w21, w20", + "ubfx w20, w20, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "bsf ax, bx": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": "0x0f 0xbc", + "ExpectedArm64ASM": [ + "uxth w20, w4", + "uxth w21, w7", + "uxth w0, w21", + "cmp w0, #0x0 (0)", + "rbit w0, w0", + "clz w22, w0", + "csinv w22, w22, wzr, ne", + "cmp x21, #0x0 (0)", + "csel w20, w20, w22, eq", + "bfxil x4, x20, #0, #16", + "cmp x21, #0x0 (0)", + "cset x20, eq", + "lsl x20, x20, #30", + "str w20, [x28, #728]" + ] + }, + "bsf eax, ebx": { + "ExpectedInstructionCount": 12, + "Optimal": "No", + "Comment": "0x0f 0xbc", + "ExpectedArm64ASM": [ + "mov w20, w7", + "lsr w0, w20, #0", + "cmp w0, #0x0 (0)", + "rbit w0, w0", + "clz w21, w0", + "csinv w21, w21, wzr, ne", + "cmp x20, #0x0 (0)", + "csel x4, x4, x21, eq", + "cmp x20, #0x0 (0)", + "cset x20, eq", + "lsl x20, x20, #30", + "str w20, [x28, #728]" + ] + }, + "bsf rax, rbx": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": "0x0f 0xbc", + "ExpectedArm64ASM": [ + "rbit x0, x7", + "cmp x7, #0x0 (0)", + "clz x20, x0", + "csinv x20, x20, xzr, ne", + "cmp x7, #0x0 (0)", + "csel x4, x4, x20, eq", + "cmp x7, #0x0 (0)", + "cset x20, eq", + "lsl x20, x20, #30", + "str w20, [x28, #728]" + ] + }, + "bsr ax, bx": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": "0x0f 0xbd", + "ExpectedArm64ASM": [ + "uxth w20, w4", + "uxth w21, w7", + "mov x0, #0xf", + "lsl w22, w21, #16", + "orr w22, w22, #0x8000", + "clz w22, w22", + "sub x22, x0, x22", + "cmp x21, #0x0 (0)", + "csel w20, w20, w22, eq", + "bfxil x4, x20, #0, #16", + "cmp x21, #0x0 (0)", + "cset x20, eq", + "lsl x20, x20, #30", + "str w20, [x28, #728]" + ] + }, + "bsr eax, ebx": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": "0x0f 0xbd", + "ExpectedArm64ASM": [ + "mov w20, w7", + "mov x0, #0x1f", + "clz w21, w20", + "sub x21, x0, x21", + "cmp x20, #0x0 (0)", + "csel x4, x4, x21, eq", + "cmp x20, #0x0 (0)", + "cset x20, eq", + "lsl x20, x20, #30", + "str w20, [x28, #728]" + ] + }, + "bsr rax, rbx": { + "ExpectedInstructionCount": 9, + "Optimal": "No", + "Comment": "0x0f 0xbd", + "ExpectedArm64ASM": [ + "mov x0, #0x3f", + "clz x20, x7", + "sub x20, x0, x20", + "cmp x7, #0x0 (0)", + "csel x4, x4, x20, eq", + "cmp x7, #0x0 (0)", + "cset x20, eq", + "lsl x20, x20, #30", + "str w20, [x28, #728]" + ] + }, + "xadd al, bl": { + "ExpectedInstructionCount": 19, + "Optimal": "No", + "Comment": "0x0f 0xc0", + "ExpectedArm64ASM": [ + "uxtb w20, w4", + "uxtb w21, w7", + "add w22, w20, w21", + "bfxil x7, x20, #0, #8", + "bfxil x4, x22, #0, #8", + "eor w23, w20, w21", + "strb w23, [x28, #708]", + "strb w22, [x28, #706]", + "lsl w23, w22, #24", + "tst w23, w23", + "mrs x23, nzcv", + "ubfx w24, w22, #8, #1", + "orr w23, w23, w24, lsl #29", + "eor w21, w20, w21", + "eor w20, w22, w20", + "bic w20, w20, w21", + "ubfx w20, w20, #7, #1", + "orr w20, w23, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "xadd [rax], bl": { + "ExpectedInstructionCount": 18, + "Optimal": "No", + "Comment": "0x0f 0xc0", + "ExpectedArm64ASM": [ + "uxtb w20, w7", + "ldaddalb w20, w21, [x4]", + "bfxil x7, x21, #0, #8", + "add w22, w21, w20", + "eor w23, w21, w20", + "strb w23, [x28, #708]", + "strb w22, [x28, #706]", + "lsl w23, w22, #24", + "tst w23, w23", + "mrs x23, nzcv", + "ubfx w24, w22, #8, #1", + "orr w23, w23, w24, lsl #29", + "eor w20, w21, w20", + "eor w21, w22, w21", + "bic w20, w21, w20", + "ubfx w20, w20, #7, #1", + "orr w20, w23, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "xadd ax, bx": { + "ExpectedInstructionCount": 19, + "Optimal": "No", + "Comment": "0x0f 0xc1", + "ExpectedArm64ASM": [ + "uxth w20, w4", + "uxth w21, w7", + "add w22, w20, w21", + "bfxil x7, x20, #0, #16", + "bfxil x4, x22, #0, #16", + "eor w23, w20, w21", + "strb w23, [x28, #708]", + "strb w22, [x28, #706]", + "lsl w23, w22, #16", + "tst w23, w23", + "mrs x23, nzcv", + "ubfx w24, w22, #16, #1", + "orr w23, w23, w24, lsl #29", + "eor w21, w20, w21", + "eor w20, w22, w20", + "bic w20, w20, w21", + "ubfx w20, w20, #15, #1", + "orr w20, w23, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "xadd [rax], bx": { + "ExpectedInstructionCount": 18, + "Optimal": "No", + "Comment": "0x0f 0xc1", + "ExpectedArm64ASM": [ + "uxth w20, w7", + "ldaddalh w20, w21, [x4]", + "bfxil x7, x21, #0, #16", + "add w22, w21, w20", + "eor w23, w21, w20", + "strb w23, [x28, #708]", + "strb w22, [x28, #706]", + "lsl w23, w22, #16", + "tst w23, w23", + "mrs x23, nzcv", + "ubfx w24, w22, #16, #1", + "orr w23, w23, w24, lsl #29", + "eor w20, w21, w20", + "eor w21, w22, w21", + "bic w20, w21, w20", + "ubfx w20, w20, #15, #1", + "orr w20, w23, w20, lsl #28", + "str w20, [x28, #728]" + ] + }, + "xadd eax, ebx": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": "0x0f 0xc1", + "ExpectedArm64ASM": [ + "mov w20, w4", + "mov w21, w7", + "add w4, w20, w21", + "mov x7, x20", + "eor w22, w20, w21", + "strb w22, [x28, #708]", + "strb w4, [x28, #706]", + "cmn w20, w21", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "xadd [rax], ebx": { + "ExpectedInstructionCount": 9, + "Optimal": "Yes", + "Comment": "0x0f 0xc1", + "ExpectedArm64ASM": [ + "mov w20, w7", + "ldaddal w20, w7, [x4]", + "add w21, w7, w20", + "eor w22, w7, w20", + "strb w22, [x28, #708]", + "strb w21, [x28, #706]", + "cmn w7, w20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "xadd rax, rbx": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": "0x0f 0xc1", + "ExpectedArm64ASM": [ + "mov x20, x4", + "mov x21, x7", + "add x4, x20, x21", + "mov x7, x20", + "eor x22, x20, x21", + "strb w22, [x28, #708]", + "strb w4, [x28, #706]", + "cmn x20, x21", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "xadd [rax], rbx": { + "ExpectedInstructionCount": 9, + "Optimal": "Yes", + "Comment": "0x0f 0xc1", + "ExpectedArm64ASM": [ + "mov x20, x7", + "ldaddal x20, x7, [x4]", + "add x21, x7, x20", + "eor x22, x7, x20", + "strb w22, [x28, #708]", + "strb w21, [x28, #706]", + "cmn x7, x20", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "pmovmskb eax, mm0": { + "ExpectedInstructionCount": 12, + "Optimal": "Yes", + "Comment": "0x0f 0xd7", + "ExpectedArm64ASM": [ + "ldr d2, [x28, #752]", + "mov x20, #0x201", + "movk x20, #0x804, lsl #16", + "movk x20, #0x2010, lsl #32", + "movk x20, #0x8040, lsl #48", + "dup v3.2d, x20", + "cmlt v2.16b, v2.16b, #0", + "and v2.16b, v2.16b, v3.16b", + "addp v2.16b, v2.16b, v2.16b", + "addp v2.8b, v2.8b, v2.8b", + "addp v2.8b, v2.8b, v2.8b", + "umov w4, v2.h[0]" + ] + }, + "maskmovq mm0, mm1": { + "ExpectedInstructionCount": 6, + "Optimal": "Yes", + "Comment": "0x0f 0xf7", + "ExpectedArm64ASM": [ + "ldr d2, [x28, #768]", + "cmlt v2.16b, v2.16b, #0", + "ldr d3, [x28, #752]", + "ldr d4, [x11]", + "bsl v2.8b, v3.8b, v4.8b", + "str d2, [x11]" + ] + } + } +} diff --git a/unittests/InstructionCountCI/FlagM/SecondaryGroup.json b/unittests/InstructionCountCI/FlagM/SecondaryGroup.json new file mode 100644 index 000000000..a57d4382a --- /dev/null +++ b/unittests/InstructionCountCI/FlagM/SecondaryGroup.json @@ -0,0 +1,2039 @@ +{ + "Features": { + "Bitness": 64, + "EnabledHostFeatures": [ + "FLAGM", + "FLAGM2", + "RNG" + ], + "DisabledHostFeatures": [ + "SVE128", + "SVE256" + ] + }, + "Instructions": { + "sgdt [rax]": { + "ExpectedInstructionCount": 4, + "Optimal": "No", + "Comment": "GROUP7 0x0F 0x1 /0", + "ExpectedArm64ASM": [ + "mov w20, #0x0", + "strh w20, [x4]", + "mov x20, #0xfffffffffffe0000", + "stur x20, [x4, #2]" + ] + }, + "bt ax, 0": { + "ExpectedInstructionCount": 3, + "Optimal": "No", + "Comment": "GROUP8 0x0F 0xBA /4", + "ExpectedArm64ASM": [ + "ubfx x20, x4, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "bt eax, 0": { + "ExpectedInstructionCount": 3, + "Optimal": "No", + "Comment": "GROUP8 0x0F 0xBA /4", + "ExpectedArm64ASM": [ + "ubfx x20, x4, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "bt rax, 0": { + "ExpectedInstructionCount": 3, + "Optimal": "No", + "Comment": "GROUP8 0x0F 0xBA /4", + "ExpectedArm64ASM": [ + "ubfx x20, x4, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "bt ax, 15": { + "ExpectedInstructionCount": 4, + "Optimal": "No", + "Comment": "GROUP8 0x0F 0xBA /4", + "ExpectedArm64ASM": [ + "lsr x20, x4, #15", + "ubfx x20, x20, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "bt eax, 31": { + "ExpectedInstructionCount": 4, + "Optimal": "No", + "Comment": "GROUP8 0x0F 0xBA /4", + "ExpectedArm64ASM": [ + "lsr x20, x4, #31", + "ubfx x20, x20, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "bt rax, 63": { + "ExpectedInstructionCount": 4, + "Optimal": "No", + "Comment": "GROUP8 0x0F 0xBA /4", + "ExpectedArm64ASM": [ + "lsr x20, x4, #63", + "ubfx x20, x20, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "bt word [rax], 0": { + "ExpectedInstructionCount": 4, + "Optimal": "No", + "Comment": "GROUP8 0x0F 0xBA /6", + "ExpectedArm64ASM": [ + "ldrb w20, [x4]", + "ubfx w20, w20, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "bt dword [rax], 0": { + "ExpectedInstructionCount": 4, + "Optimal": "No", + "Comment": "GROUP8 0x0F 0xBA /6", + "ExpectedArm64ASM": [ + "ldrb w20, [x4]", + "ubfx w20, w20, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "bt qword [rax], 0": { + "ExpectedInstructionCount": 4, + "Optimal": "No", + "Comment": "GROUP8 0x0F 0xBA /6", + "ExpectedArm64ASM": [ + "ldrb w20, [x4]", + "ubfx w20, w20, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "bt word [rax], 15": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": "GROUP8 0x0F 0xBA /6", + "ExpectedArm64ASM": [ + "ldrb w20, [x4, #1]", + "lsr w20, w20, #7", + "ubfx w20, w20, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "bt dword [rax], 31": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": "GROUP8 0x0F 0xBA /6", + "ExpectedArm64ASM": [ + "ldrb w20, [x4, #3]", + "lsr w20, w20, #7", + "ubfx w20, w20, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "bt qword [rax], 63": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": "GROUP8 0x0F 0xBA /6", + "ExpectedArm64ASM": [ + "ldrb w20, [x4, #7]", + "lsr w20, w20, #7", + "ubfx w20, w20, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "bts ax, 0": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": "GROUP8 0x0F 0xBA /5", + "ExpectedArm64ASM": [ + "mov x20, x4", + "orr x21, x20, #0x1", + "mov x0, x20", + "bfxil x0, x21, #0, #16", + "mov x4, x0", + "ubfx x20, x20, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "bts eax, 0": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": "GROUP8 0x0F 0xBA /5", + "ExpectedArm64ASM": [ + "mov x20, x4", + "orr x21, x20, #0x1", + "mov w4, w21", + "ubfx x20, x20, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "bts rax, 0": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": "GROUP8 0x0F 0xBA /5", + "ExpectedArm64ASM": [ + "mov x20, x4", + "orr x4, x20, #0x1", + "ubfx x20, x20, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "bts ax, 15": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": "GROUP8 0x0F 0xBA /5", + "ExpectedArm64ASM": [ + "lsr x20, x4, #15", + "orr x21, x4, #0x8000", + "bfxil x4, x21, #0, #16", + "ubfx x20, x20, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "bts eax, 31": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": "GROUP8 0x0F 0xBA /5", + "ExpectedArm64ASM": [ + "lsr x20, x4, #31", + "orr x21, x4, #0x80000000", + "mov w4, w21", + "ubfx x20, x20, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "bts rax, 63": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": "GROUP8 0x0F 0xBA /5", + "ExpectedArm64ASM": [ + "lsr x20, x4, #63", + "orr x4, x4, #0x8000000000000000", + "ubfx x20, x20, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "bts word [rax], 0": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": "GROUP8 0x0F 0xBA /6", + "ExpectedArm64ASM": [ + "ldrb w20, [x4]", + "orr x21, x20, #0x1", + "strb w21, [x4]", + "ubfx w20, w20, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "bts dword [rax], 0": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": "GROUP8 0x0F 0xBA /6", + "ExpectedArm64ASM": [ + "ldrb w20, [x4]", + "orr x21, x20, #0x1", + "strb w21, [x4]", + "ubfx w20, w20, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "bts qword [rax], 0": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": "GROUP8 0x0F 0xBA /6", + "ExpectedArm64ASM": [ + "ldrb w20, [x4]", + "orr x21, x20, #0x1", + "strb w21, [x4]", + "ubfx w20, w20, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "bts word [rax], 15": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": "GROUP8 0x0F 0xBA /6", + "ExpectedArm64ASM": [ + "ldrb w20, [x4, #1]", + "lsr w21, w20, #7", + "orr x20, x20, #0x80", + "strb w20, [x4, #1]", + "ubfx w20, w21, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "bts dword [rax], 31": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": "GROUP8 0x0F 0xBA /6", + "ExpectedArm64ASM": [ + "ldrb w20, [x4, #3]", + "lsr w21, w20, #7", + "orr x20, x20, #0x80", + "strb w20, [x4, #3]", + "ubfx w20, w21, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "bts qword [rax], 63": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": "GROUP8 0x0F 0xBA /6", + "ExpectedArm64ASM": [ + "ldrb w20, [x4, #7]", + "lsr w21, w20, #7", + "orr x20, x20, #0x80", + "strb w20, [x4, #7]", + "ubfx w20, w21, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "lock bts word [rax], 0": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": "GROUP8 0x0F 0xBA /6", + "ExpectedArm64ASM": [ + "add x20, x4, #0x0 (0)", + "mov w21, #0x1", + "ldsetalb w21, w20, [x20]", + "ubfx w20, w20, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "lock bts dword [rax], 0": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": "GROUP8 0x0F 0xBA /6", + "ExpectedArm64ASM": [ + "add x20, x4, #0x0 (0)", + "mov w21, #0x1", + "ldsetalb w21, w20, [x20]", + "ubfx w20, w20, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "lock bts qword [rax], 0": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": "GROUP8 0x0F 0xBA /6", + "ExpectedArm64ASM": [ + "add x20, x4, #0x0 (0)", + "mov w21, #0x1", + "ldsetalb w21, w20, [x20]", + "ubfx w20, w20, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "lock bts word [rax], 15": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": "GROUP8 0x0F 0xBA /6", + "ExpectedArm64ASM": [ + "add x20, x4, #0x1 (1)", + "mov w21, #0x80", + "ldsetalb w21, w20, [x20]", + "lsr w20, w20, #7", + "ubfx w20, w20, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "lock bts dword [rax], 31": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": "GROUP8 0x0F 0xBA /6", + "ExpectedArm64ASM": [ + "add x20, x4, #0x3 (3)", + "mov w21, #0x80", + "ldsetalb w21, w20, [x20]", + "lsr w20, w20, #7", + "ubfx w20, w20, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "lock bts qword [rax], 63": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": "GROUP8 0x0F 0xBA /6", + "ExpectedArm64ASM": [ + "add x20, x4, #0x7 (7)", + "mov w21, #0x80", + "ldsetalb w21, w20, [x20]", + "lsr w20, w20, #7", + "ubfx w20, w20, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "btr ax, 0": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": "GROUP8 0x0F 0xBA /6", + "ExpectedArm64ASM": [ + "mov x20, x4", + "and x21, x20, #0xfffffffffffffffe", + "mov x0, x20", + "bfxil x0, x21, #0, #16", + "mov x4, x0", + "ubfx x20, x20, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "btr eax, 0": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": "GROUP8 0x0F 0xBA /6", + "ExpectedArm64ASM": [ + "mov x20, x4", + "and x21, x20, #0xfffffffffffffffe", + "mov w4, w21", + "ubfx x20, x20, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "btr rax, 0": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": "GROUP8 0x0F 0xBA /6", + "ExpectedArm64ASM": [ + "mov x20, x4", + "and x4, x20, #0xfffffffffffffffe", + "ubfx x20, x20, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "btr ax, 15": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": "GROUP8 0x0F 0xBA /6", + "ExpectedArm64ASM": [ + "lsr x20, x4, #15", + "and x21, x4, #0xffffffffffff7fff", + "bfxil x4, x21, #0, #16", + "ubfx x20, x20, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "btr eax, 31": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": "GROUP8 0x0F 0xBA /6", + "ExpectedArm64ASM": [ + "lsr x20, x4, #31", + "and x21, x4, #0xffffffff7fffffff", + "mov w4, w21", + "ubfx x20, x20, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "btr rax, 63": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": "GROUP8 0x0F 0xBA /6", + "ExpectedArm64ASM": [ + "lsr x20, x4, #63", + "and x4, x4, #0x7fffffffffffffff", + "ubfx x20, x20, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "btr word [rax], 0": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": "GROUP8 0x0F 0xBA /6", + "ExpectedArm64ASM": [ + "ldrb w20, [x4]", + "and x21, x20, #0xfffffffffffffffe", + "strb w21, [x4]", + "ubfx w20, w20, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "btr dword [rax], 0": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": "GROUP8 0x0F 0xBA /6", + "ExpectedArm64ASM": [ + "ldrb w20, [x4]", + "and x21, x20, #0xfffffffffffffffe", + "strb w21, [x4]", + "ubfx w20, w20, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "btr qword [rax], 0": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": "GROUP8 0x0F 0xBA /6", + "ExpectedArm64ASM": [ + "ldrb w20, [x4]", + "and x21, x20, #0xfffffffffffffffe", + "strb w21, [x4]", + "ubfx w20, w20, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "btr word [rax], 15": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": "GROUP8 0x0F 0xBA /6", + "ExpectedArm64ASM": [ + "ldrb w20, [x4, #1]", + "lsr w21, w20, #7", + "and x20, x20, #0xffffffffffffff7f", + "strb w20, [x4, #1]", + "ubfx w20, w21, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "btr dword [rax], 31": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": "GROUP8 0x0F 0xBA /6", + "ExpectedArm64ASM": [ + "ldrb w20, [x4, #3]", + "lsr w21, w20, #7", + "and x20, x20, #0xffffffffffffff7f", + "strb w20, [x4, #3]", + "ubfx w20, w21, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "btr qword [rax], 63": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": "GROUP8 0x0F 0xBA /6", + "ExpectedArm64ASM": [ + "ldrb w20, [x4, #7]", + "lsr w21, w20, #7", + "and x20, x20, #0xffffffffffffff7f", + "strb w20, [x4, #7]", + "ubfx w20, w21, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "lock btr word [rax], 0": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": "GROUP8 0x0F 0xBA /6", + "ExpectedArm64ASM": [ + "add x20, x4, #0x0 (0)", + "mov w21, #0x1", + "ldclralb w21, w20, [x20]", + "ubfx w20, w20, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "lock btr dword [rax], 0": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": "GROUP8 0x0F 0xBA /6", + "ExpectedArm64ASM": [ + "add x20, x4, #0x0 (0)", + "mov w21, #0x1", + "ldclralb w21, w20, [x20]", + "ubfx w20, w20, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "lock btr qword [rax], 0": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": "GROUP8 0x0F 0xBA /6", + "ExpectedArm64ASM": [ + "add x20, x4, #0x0 (0)", + "mov w21, #0x1", + "ldclralb w21, w20, [x20]", + "ubfx w20, w20, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "lock btr word [rax], 15": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": "GROUP8 0x0F 0xBA /6", + "ExpectedArm64ASM": [ + "add x20, x4, #0x1 (1)", + "mov w21, #0x80", + "ldclralb w21, w20, [x20]", + "lsr w20, w20, #7", + "ubfx w20, w20, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "lock btr dword [rax], 31": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": "GROUP8 0x0F 0xBA /6", + "ExpectedArm64ASM": [ + "add x20, x4, #0x3 (3)", + "mov w21, #0x80", + "ldclralb w21, w20, [x20]", + "lsr w20, w20, #7", + "ubfx w20, w20, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "lock btr qword [rax], 63": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": "GROUP8 0x0F 0xBA /6", + "ExpectedArm64ASM": [ + "add x20, x4, #0x7 (7)", + "mov w21, #0x80", + "ldclralb w21, w20, [x20]", + "lsr w20, w20, #7", + "ubfx w20, w20, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "btc ax, 0": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": "GROUP8 0x0F 0xBA /7", + "ExpectedArm64ASM": [ + "mov x20, x4", + "eor x21, x20, #0x1", + "mov x0, x20", + "bfxil x0, x21, #0, #16", + "mov x4, x0", + "ubfx x20, x20, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "btc eax, 0": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": "GROUP8 0x0F 0xBA /7", + "ExpectedArm64ASM": [ + "mov x20, x4", + "eor x21, x20, #0x1", + "mov w4, w21", + "ubfx x20, x20, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "btc rax, 0": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": "GROUP8 0x0F 0xBA /7", + "ExpectedArm64ASM": [ + "mov x20, x4", + "eor x4, x20, #0x1", + "ubfx x20, x20, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "btc ax, 15": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": "GROUP8 0x0F 0xBA /7", + "ExpectedArm64ASM": [ + "lsr x20, x4, #15", + "eor x21, x4, #0x8000", + "bfxil x4, x21, #0, #16", + "ubfx x20, x20, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "btc eax, 31": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": "GROUP8 0x0F 0xBA /7", + "ExpectedArm64ASM": [ + "lsr x20, x4, #31", + "eor x21, x4, #0x80000000", + "mov w4, w21", + "ubfx x20, x20, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "btc rax, 63": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": "GROUP8 0x0F 0xBA /7", + "ExpectedArm64ASM": [ + "lsr x20, x4, #63", + "eor x4, x4, #0x8000000000000000", + "ubfx x20, x20, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "btc word [rax], 0": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": "GROUP8 0x0F 0xBA /6", + "ExpectedArm64ASM": [ + "ldrb w20, [x4]", + "eor x21, x20, #0x1", + "strb w21, [x4]", + "ubfx w20, w20, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "btc dword [rax], 0": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": "GROUP8 0x0F 0xBA /6", + "ExpectedArm64ASM": [ + "ldrb w20, [x4]", + "eor x21, x20, #0x1", + "strb w21, [x4]", + "ubfx w20, w20, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "btc qword [rax], 0": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": "GROUP8 0x0F 0xBA /6", + "ExpectedArm64ASM": [ + "ldrb w20, [x4]", + "eor x21, x20, #0x1", + "strb w21, [x4]", + "ubfx w20, w20, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "btc word [rax], 15": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": "GROUP8 0x0F 0xBA /6", + "ExpectedArm64ASM": [ + "ldrb w20, [x4, #1]", + "lsr w21, w20, #7", + "eor x20, x20, #0x80", + "strb w20, [x4, #1]", + "ubfx w20, w21, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "btc dword [rax], 31": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": "GROUP8 0x0F 0xBA /6", + "ExpectedArm64ASM": [ + "ldrb w20, [x4, #3]", + "lsr w21, w20, #7", + "eor x20, x20, #0x80", + "strb w20, [x4, #3]", + "ubfx w20, w21, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "btc qword [rax], 63": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": "GROUP8 0x0F 0xBA /6", + "ExpectedArm64ASM": [ + "ldrb w20, [x4, #7]", + "lsr w21, w20, #7", + "eor x20, x20, #0x80", + "strb w20, [x4, #7]", + "ubfx w20, w21, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "lock btc word [rax], 0": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": "GROUP8 0x0F 0xBA /6", + "ExpectedArm64ASM": [ + "add x20, x4, #0x0 (0)", + "mov w21, #0x1", + "ldeoralb w21, w20, [x20]", + "ubfx w20, w20, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "lock btc dword [rax], 0": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": "GROUP8 0x0F 0xBA /6", + "ExpectedArm64ASM": [ + "add x20, x4, #0x0 (0)", + "mov w21, #0x1", + "ldeoralb w21, w20, [x20]", + "ubfx w20, w20, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "lock btc qword [rax], 0": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": "GROUP8 0x0F 0xBA /6", + "ExpectedArm64ASM": [ + "add x20, x4, #0x0 (0)", + "mov w21, #0x1", + "ldeoralb w21, w20, [x20]", + "ubfx w20, w20, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "lock btc word [rax], 15": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": "GROUP8 0x0F 0xBA /6", + "ExpectedArm64ASM": [ + "add x20, x4, #0x1 (1)", + "mov w21, #0x80", + "ldeoralb w21, w20, [x20]", + "lsr w20, w20, #7", + "ubfx w20, w20, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "lock btc dword [rax], 31": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": "GROUP8 0x0F 0xBA /6", + "ExpectedArm64ASM": [ + "add x20, x4, #0x3 (3)", + "mov w21, #0x80", + "ldeoralb w21, w20, [x20]", + "lsr w20, w20, #7", + "ubfx w20, w20, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "lock btc qword [rax], 63": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": "GROUP8 0x0F 0xBA /6", + "ExpectedArm64ASM": [ + "add x20, x4, #0x7 (7)", + "mov w21, #0x80", + "ldeoralb w21, w20, [x20]", + "lsr w20, w20, #7", + "ubfx w20, w20, #0, #1", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "cmpxchg8b [rbp]": { + "ExpectedInstructionCount": 25, + "Optimal": "No", + "Comment": "GROUP9 0x0F 0xC7 /1", + "ExpectedArm64ASM": [ + "add x20, x9, #0x0 (0)", + "mov w21, w4", + "mov w22, w6", + "mov w23, w22", + "mov w22, w21", + "mov w21, w7", + "mov w24, w5", + "mov w25, w24", + "mov w24, w21", + "mov w2, w22", + "mov w3, w23", + "caspal w2, w3, w24, w25, [x20]", + "mov w20, w2", + "mov w21, w3", + "mov w24, w20", + "mov w25, w21", + "cmp x20, x22", + "ccmp x21, x23, #nzcv, eq", + "cset x20, eq", + "ldr w21, [x28, #728]", + "bfi w21, w20, #30, #1", + "str w21, [x28, #728]", + "cbnz x20, #+0xc", + "mov x4, x24", + "mov x6, x25" + ] + }, + "cmpxchg16b [rbp]": { + "ExpectedInstructionCount": 21, + "Optimal": "No", + "Comment": "GROUP9 0x0F 0xC7 /1", + "ExpectedArm64ASM": [ + "add x20, x9, #0x0 (0)", + "mov x22, x4", + "mov x23, x6", + "mov x24, x7", + "mov x25, x5", + "mov x2, x22", + "mov x3, x23", + "caspal x2, x3, x24, x25, [x20]", + "mov x20, x2", + "mov x21, x3", + "mov x24, x20", + "mov x25, x21", + "cmp x20, x22", + "ccmp x21, x23, #nzcv, eq", + "cset x20, eq", + "ldr w21, [x28, #728]", + "bfi w21, w20, #30, #1", + "str w21, [x28, #728]", + "cbnz x20, #+0xc", + "mov x4, x24", + "mov x6, x25" + ] + }, + "rdrand ax": { + "ExpectedInstructionCount": 11, + "Optimal": "No", + "Comment": "GROUP9 0x0F 0xC7 /6", + "ExpectedArm64ASM": [ + "mrs x20, rndr", + "cset x21, ne", + "mov x22, x20", + "mov x20, x21", + "bfxil x4, x22, #0, #16", + "mov w21, #0x0", + "mov w22, #0x1", + "strb w22, [x28, #706]", + "strb w21, [x28, #708]", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "rdrand eax": { + "ExpectedInstructionCount": 11, + "Optimal": "No", + "Comment": "GROUP9 0x0F 0xC7 /6", + "ExpectedArm64ASM": [ + "mrs x20, rndr", + "cset x21, ne", + "mov x22, x20", + "mov x20, x21", + "mov w4, w22", + "mov w21, #0x0", + "mov w22, #0x1", + "strb w22, [x28, #706]", + "strb w21, [x28, #708]", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "rdrand rax": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": "GROUP9 0x0F 0xC7 /6", + "ExpectedArm64ASM": [ + "mrs x20, rndr", + "cset x21, ne", + "mov x4, x20", + "mov x20, x21", + "mov w21, #0x0", + "mov w22, #0x1", + "strb w22, [x28, #706]", + "strb w21, [x28, #708]", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "rdseed ax": { + "ExpectedInstructionCount": 11, + "Optimal": "No", + "Comment": "GROUP9 0x0F 0xC7 /7", + "ExpectedArm64ASM": [ + "mrs x20, rndrrs", + "cset x21, ne", + "mov x22, x20", + "mov x20, x21", + "bfxil x4, x22, #0, #16", + "mov w21, #0x0", + "mov w22, #0x1", + "strb w22, [x28, #706]", + "strb w21, [x28, #708]", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "rdseed eax": { + "ExpectedInstructionCount": 11, + "Optimal": "No", + "Comment": "GROUP9 0x0F 0xC7 /7", + "ExpectedArm64ASM": [ + "mrs x20, rndrrs", + "cset x21, ne", + "mov x22, x20", + "mov x20, x21", + "mov w4, w22", + "mov w21, #0x0", + "mov w22, #0x1", + "strb w22, [x28, #706]", + "strb w21, [x28, #708]", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "rdseed rax": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": "GROUP9 0x0F 0xC7 /7", + "ExpectedArm64ASM": [ + "mrs x20, rndrrs", + "cset x21, ne", + "mov x4, x20", + "mov x20, x21", + "mov w21, #0x0", + "mov w22, #0x1", + "strb w22, [x28, #706]", + "strb w21, [x28, #708]", + "lsl x20, x20, #29", + "str w20, [x28, #728]" + ] + }, + "psrlw mm0, 0": { + "ExpectedInstructionCount": 0, + "Type": "MMX", + "Optimal": "Yes", + "Comment": "GROUP12 0x0F 0xC7 /2", + "ExpectedArm64ASM": [] + }, + "psrlw mm0, 15": { + "ExpectedInstructionCount": 3, + "Type": "MMX", + "Optimal": "Yes", + "Comment": "GROUP12 0x0F 0xC7 /2", + "ExpectedArm64ASM": [ + "ldr d2, [x28, #752]", + "ushr v2.8h, v2.8h, #15", + "str d2, [x28, #752]" + ] + }, + "psrlw mm0, 16": { + "ExpectedInstructionCount": 3, + "Type": "MMX", + "Optimal": "No", + "Comment": "GROUP12 0x0F 0xC7 /2", + "ExpectedArm64ASM": [ + "ldr d2, [x28, #752]", + "movi v2.2d, #0x0", + "str d2, [x28, #752]" + ] + }, + "psrlw xmm0, 0": { + "ExpectedInstructionCount": 0, + "Type": "SSE", + "Optimal": "Yes", + "Comment": "GROUP12 0x0F 0xC7 /2", + "ExpectedArm64ASM": [] + }, + "psrlw xmm0, 15": { + "ExpectedInstructionCount": 1, + "Type": "SSE", + "Optimal": "Yes", + "Comment": "GROUP12 0x0F 0xC7 /2", + "ExpectedArm64ASM": [ + "ushr v16.8h, v16.8h, #15" + ] + }, + "psrlw xmm0, 16": { + "ExpectedInstructionCount": 1, + "Type": "SSE", + "Optimal": "No", + "Comment": "GROUP12 0x0F 0xC7 /2", + "ExpectedArm64ASM": [ + "movi v16.2d, #0x0" + ] + }, + "psraw mm0, 0": { + "ExpectedInstructionCount": 0, + "Type": "MMX", + "Optimal": "Yes", + "Comment": "GROUP12 0x0F 0xC7 /3", + "ExpectedArm64ASM": [] + }, + "psraw mm0, 15": { + "ExpectedInstructionCount": 3, + "Type": "MMX", + "Optimal": "Yes", + "Comment": "GROUP12 0x0F 0xC7 /3", + "ExpectedArm64ASM": [ + "ldr d2, [x28, #752]", + "sshr v2.8h, v2.8h, #15", + "str d2, [x28, #752]" + ] + }, + "psraw mm0, 16": { + "ExpectedInstructionCount": 3, + "Type": "MMX", + "Optimal": "Yes", + "Comment": "GROUP12 0x0F 0xC7 /3", + "ExpectedArm64ASM": [ + "ldr d2, [x28, #752]", + "sshr v2.8h, v2.8h, #15", + "str d2, [x28, #752]" + ] + }, + "psraw xmm0, 0": { + "ExpectedInstructionCount": 0, + "Type": "SSE", + "Optimal": "Yes", + "Comment": "GROUP12 0x0F 0xC7 /3", + "ExpectedArm64ASM": [] + }, + "psraw xmm0, 15": { + "ExpectedInstructionCount": 1, + "Type": "SSE", + "Optimal": "Yes", + "Comment": "GROUP12 0x0F 0xC7 /3", + "ExpectedArm64ASM": [ + "sshr v16.8h, v16.8h, #15" + ] + }, + "psraw xmm0, 16": { + "ExpectedInstructionCount": 1, + "Type": "SSE", + "Optimal": "Yes", + "Comment": "GROUP12 0x0F 0xC7 /3", + "ExpectedArm64ASM": [ + "sshr v16.8h, v16.8h, #15" + ] + }, + "psllw mm0, 0": { + "ExpectedInstructionCount": 0, + "Type": "MMX", + "Optimal": "Yes", + "Comment": "GROUP12 0x0F 0xC7 /6", + "ExpectedArm64ASM": [] + }, + "psllw mm0, 15": { + "ExpectedInstructionCount": 3, + "Type": "MMX", + "Optimal": "Yes", + "Comment": "GROUP12 0x0F 0xC7 /6", + "ExpectedArm64ASM": [ + "ldr d2, [x28, #752]", + "shl v2.8h, v2.8h, #15", + "str d2, [x28, #752]" + ] + }, + "psllw mm0, 16": { + "ExpectedInstructionCount": 3, + "Type": "MMX", + "Optimal": "No", + "Comment": "GROUP12 0x0F 0xC7 /6", + "ExpectedArm64ASM": [ + "ldr d2, [x28, #752]", + "movi v2.2d, #0x0", + "str d2, [x28, #752]" + ] + }, + "psllw xmm0, 0": { + "ExpectedInstructionCount": 0, + "Type": "SSE", + "Optimal": "Yes", + "Comment": "GROUP12 0x0F 0xC7 /6", + "ExpectedArm64ASM": [] + }, + "psllw xmm0, 15": { + "ExpectedInstructionCount": 1, + "Type": "SSE", + "Optimal": "Yes", + "Comment": "GROUP12 0x0F 0xC7 /6", + "ExpectedArm64ASM": [ + "shl v16.8h, v16.8h, #15" + ] + }, + "psllw xmm0, 16": { + "ExpectedInstructionCount": 1, + "Type": "SSE", + "Optimal": "No", + "Comment": "GROUP12 0x0F 0xC7 /6", + "ExpectedArm64ASM": [ + "movi v16.2d, #0x0" + ] + }, + "psrld mm0, 0": { + "ExpectedInstructionCount": 0, + "Type": "MMX", + "Optimal": "Yes", + "Comment": "GROUP13 0x0F 0xC7 /2", + "ExpectedArm64ASM": [] + }, + "psrld mm0, 31": { + "ExpectedInstructionCount": 3, + "Type": "MMX", + "Optimal": "Yes", + "Comment": "GROUP13 0x0F 0xC7 /2", + "ExpectedArm64ASM": [ + "ldr d2, [x28, #752]", + "ushr v2.4s, v2.4s, #31", + "str d2, [x28, #752]" + ] + }, + "psrld mm0, 32": { + "ExpectedInstructionCount": 3, + "Type": "MMX", + "Optimal": "No", + "Comment": "GROUP13 0x0F 0xC7 /2", + "ExpectedArm64ASM": [ + "ldr d2, [x28, #752]", + "movi v2.2d, #0x0", + "str d2, [x28, #752]" + ] + }, + "psrld xmm0, 0": { + "ExpectedInstructionCount": 0, + "Type": "SSE", + "Optimal": "Yes", + "Comment": "GROUP13 0x0F 0xC7 /2", + "ExpectedArm64ASM": [] + }, + "psrld xmm0, 31": { + "ExpectedInstructionCount": 1, + "Type": "SSE", + "Optimal": "Yes", + "Comment": "GROUP13 0x0F 0xC7 /2", + "ExpectedArm64ASM": [ + "ushr v16.4s, v16.4s, #31" + ] + }, + "psrld xmm0, 32": { + "ExpectedInstructionCount": 1, + "Type": "SSE", + "Optimal": "No", + "Comment": "GROUP13 0x0F 0xC7 /2", + "ExpectedArm64ASM": [ + "movi v16.2d, #0x0" + ] + }, + "psrad mm0, 0": { + "ExpectedInstructionCount": 0, + "Type": "MMX", + "Optimal": "Yes", + "Comment": "GROUP13 0x0F 0xC7 /3", + "ExpectedArm64ASM": [] + }, + "psrad mm0, 31": { + "ExpectedInstructionCount": 3, + "Type": "MMX", + "Optimal": "Yes", + "Comment": "GROUP13 0x0F 0xC7 /3", + "ExpectedArm64ASM": [ + "ldr d2, [x28, #752]", + "sshr v2.4s, v2.4s, #31", + "str d2, [x28, #752]" + ] + }, + "psrad mm0, 32": { + "ExpectedInstructionCount": 3, + "Type": "MMX", + "Optimal": "Yes", + "Comment": "GROUP13 0x0F 0xC7 /3", + "ExpectedArm64ASM": [ + "ldr d2, [x28, #752]", + "sshr v2.4s, v2.4s, #31", + "str d2, [x28, #752]" + ] + }, + "psrad xmm0, 0": { + "ExpectedInstructionCount": 0, + "Type": "SSE", + "Optimal": "Yes", + "Comment": "GROUP13 0x0F 0xC7 /3", + "ExpectedArm64ASM": [] + }, + "psrad xmm0, 31": { + "ExpectedInstructionCount": 1, + "Type": "SSE", + "Optimal": "Yes", + "Comment": "GROUP13 0x0F 0xC7 /3", + "ExpectedArm64ASM": [ + "sshr v16.4s, v16.4s, #31" + ] + }, + "psrad xmm0, 32": { + "ExpectedInstructionCount": 1, + "Type": "SSE", + "Optimal": "Yes", + "Comment": "GROUP13 0x0F 0xC7 /3", + "ExpectedArm64ASM": [ + "sshr v16.4s, v16.4s, #31" + ] + }, + "pslld mm0, 0": { + "ExpectedInstructionCount": 0, + "Type": "MMX", + "Optimal": "Yes", + "Comment": "GROUP13 0x0F 0xC7 /6", + "ExpectedArm64ASM": [] + }, + "pslld mm0, 31": { + "ExpectedInstructionCount": 3, + "Type": "MMX", + "Optimal": "Yes", + "Comment": "GROUP13 0x0F 0xC7 /6", + "ExpectedArm64ASM": [ + "ldr d2, [x28, #752]", + "shl v2.4s, v2.4s, #31", + "str d2, [x28, #752]" + ] + }, + "pslld mm0, 32": { + "ExpectedInstructionCount": 3, + "Type": "MMX", + "Optimal": "No", + "Comment": "GROUP13 0x0F 0xC7 /6", + "ExpectedArm64ASM": [ + "ldr d2, [x28, #752]", + "movi v2.2d, #0x0", + "str d2, [x28, #752]" + ] + }, + "pslld xmm0, 0": { + "ExpectedInstructionCount": 0, + "Type": "SSE", + "Optimal": "Yes", + "Comment": "GROUP13 0x0F 0xC7 /6", + "ExpectedArm64ASM": [] + }, + "pslld xmm0, 31": { + "ExpectedInstructionCount": 1, + "Type": "SSE", + "Optimal": "Yes", + "Comment": "GROUP13 0x0F 0xC7 /6", + "ExpectedArm64ASM": [ + "shl v16.4s, v16.4s, #31" + ] + }, + "pslld xmm0, 32": { + "ExpectedInstructionCount": 1, + "Type": "SSE", + "Optimal": "No", + "Comment": "GROUP13 0x0F 0xC7 /6", + "ExpectedArm64ASM": [ + "movi v16.2d, #0x0" + ] + }, + "psrlq mm0, 0": { + "ExpectedInstructionCount": 0, + "Type": "MMX", + "Optimal": "Yes", + "Comment": "GROUP14 0x0F 0xC7 /2", + "ExpectedArm64ASM": [] + }, + "psrlq mm0, 63": { + "ExpectedInstructionCount": 3, + "Type": "MMX", + "Optimal": "No", + "Comment": "GROUP14 0x0F 0xC7 /2", + "ExpectedArm64ASM": [ + "ldr d2, [x28, #752]", + "ushr v2.2d, v2.2d, #63", + "str d2, [x28, #752]" + ] + }, + "psrlq mm0, 64": { + "ExpectedInstructionCount": 3, + "Type": "MMX", + "Optimal": "No", + "Comment": "GROUP14 0x0F 0xC7 /2", + "ExpectedArm64ASM": [ + "ldr d2, [x28, #752]", + "movi v2.2d, #0x0", + "str d2, [x28, #752]" + ] + }, + "psrlq xmm0, 0": { + "ExpectedInstructionCount": 0, + "Type": "SSE", + "Optimal": "Yes", + "Comment": "GROUP14 0x0F 0xC7 /2", + "ExpectedArm64ASM": [] + }, + "psrlq xmm0, 63": { + "ExpectedInstructionCount": 1, + "Type": "SSE", + "Optimal": "Yes", + "Comment": "GROUP14 0x0F 0xC7 /2", + "ExpectedArm64ASM": [ + "ushr v16.2d, v16.2d, #63" + ] + }, + "psrlq xmm0, 64": { + "ExpectedInstructionCount": 1, + "Type": "SSE", + "Optimal": "No", + "Comment": "GROUP14 0x0F 0xC7 /2", + "ExpectedArm64ASM": [ + "movi v16.2d, #0x0" + ] + }, + "psrldq xmm0, 0": { + "ExpectedInstructionCount": 0, + "Type": "SSE", + "Optimal": "No", + "Comment": "GROUP14 0x0F 0xC7 /3", + "ExpectedArm64ASM": [] + }, + "psrldq xmm0, 15": { + "ExpectedInstructionCount": 2, + "Type": "SSE", + "Optimal": "No", + "Comment": "GROUP14 0x0F 0xC7 /3", + "ExpectedArm64ASM": [ + "movi v2.2d, #0x0", + "ext v16.16b, v16.16b, v2.16b, #15" + ] + }, + "psrldq xmm0, 16": { + "ExpectedInstructionCount": 1, + "Type": "SSE", + "Optimal": "No", + "Comment": "GROUP14 0x0F 0xC7 /3", + "ExpectedArm64ASM": [ + "movi v16.2d, #0x0" + ] + }, + "psllq mm0, 0": { + "ExpectedInstructionCount": 0, + "Type": "MMX", + "Optimal": "Yes", + "Comment": "GROUP14 0x0F 0xC7 /6", + "ExpectedArm64ASM": [] + }, + "psllq mm0, 63": { + "ExpectedInstructionCount": 3, + "Type": "MMX", + "Optimal": "Yes", + "Comment": "GROUP14 0x0F 0xC7 /6", + "ExpectedArm64ASM": [ + "ldr d2, [x28, #752]", + "shl v2.2d, v2.2d, #63", + "str d2, [x28, #752]" + ] + }, + "psllq mm0, 64": { + "ExpectedInstructionCount": 3, + "Type": "MMX", + "Optimal": "No", + "Comment": "GROUP14 0x0F 0xC7 /6", + "ExpectedArm64ASM": [ + "ldr d2, [x28, #752]", + "movi v2.2d, #0x0", + "str d2, [x28, #752]" + ] + }, + "psllq xmm0, 0": { + "ExpectedInstructionCount": 0, + "Type": "SSE", + "Optimal": "Yes", + "Comment": "GROUP14 0x0F 0xC7 /6", + "ExpectedArm64ASM": [] + }, + "psllq xmm0, 63": { + "ExpectedInstructionCount": 1, + "Type": "SSE", + "Optimal": "Yes", + "Comment": "GROUP14 0x0F 0xC7 /6", + "ExpectedArm64ASM": [ + "shl v16.2d, v16.2d, #63" + ] + }, + "psllq xmm0, 64": { + "ExpectedInstructionCount": 1, + "Type": "SSE", + "Optimal": "No", + "Comment": "GROUP14 0x0F 0xC7 /6", + "ExpectedArm64ASM": [ + "movi v16.2d, #0x0" + ] + }, + "fxsave [rax]": { + "ExpectedInstructionCount": 58, + "Optimal": "No", + "Comment": "GROUP15 0x0F 0xAE /0", + "ExpectedArm64ASM": [ + "ldrh w20, [x28, #1008]", + "strh w20, [x4]", + "mov w20, #0x0", + "ldrb w21, [x28, #747]", + "bfi x20, x21, #11, #3", + "ldrb w21, [x28, #744]", + "ldrb w22, [x28, #745]", + "ldrb w23, [x28, #746]", + "ldrb w24, [x28, #750]", + "orr x20, x20, x21, lsl #8", + "orr x20, x20, x22, lsl #9", + "orr x20, x20, x23, lsl #10", + "orr x20, x20, x24, lsl #14", + "strh w20, [x4, #2]", + "ldrb w20, [x28, #1010]", + "strb w20, [x4, #4]", + "ldr q2, [x28, #752]", + "str q2, [x4, #32]", + "ldr q2, [x28, #768]", + "str q2, [x4, #48]", + "ldr q2, [x28, #784]", + "str q2, [x4, #64]", + "ldr q2, [x28, #800]", + "str q2, [x4, #80]", + "ldr q2, [x28, #816]", + "str q2, [x4, #96]", + "ldr q2, [x28, #832]", + "str q2, [x4, #112]", + "ldr q2, [x28, #848]", + "str q2, [x4, #128]", + "ldr q2, [x28, #864]", + "str q2, [x4, #144]", + "str q16, [x4, #160]", + "str q17, [x4, #176]", + "str q18, [x4, #192]", + "str q19, [x4, #208]", + "str q20, [x4, #224]", + "str q21, [x4, #240]", + "str q22, [x4, #256]", + "str q23, [x4, #272]", + "str q24, [x4, #288]", + "str q25, [x4, #304]", + "str q26, [x4, #320]", + "str q27, [x4, #336]", + "str q28, [x4, #352]", + "str q29, [x4, #368]", + "str q30, [x4, #384]", + "str q31, [x4, #400]", + "mov w20, #0x1f80", + "mrs x21, fpcr", + "ubfx x21, x21, #22, #3", + "rbit w0, w21", + "bfi x21, x0, #30, #2", + "bfi w20, w21, #13, #3", + "add x21, x4, #0x18 (24)", + "str w20, [x4, #24]", + "mov w20, #0xffff", + "str w20, [x21, #4]" + ] + }, + "rdfsbase eax": { + "ExpectedInstructionCount": 1, + "Optimal": "Yes", + "Comment": "GROUP15 0x0F 0xAE /0", + "ExpectedArm64ASM": [ + "ldr w4, [x28, #176]" + ] + }, + "rdfsbase rax": { + "ExpectedInstructionCount": 1, + "Optimal": "Yes", + "Comment": "GROUP15 0x0F 0xAE /0", + "ExpectedArm64ASM": [ + "ldr x4, [x28, #176]" + ] + }, + "fxrstor [rax]": { + "ExpectedInstructionCount": 56, + "Optimal": "No", + "Comment": "GROUP15 0x0F 0xAE /1", + "ExpectedArm64ASM": [ + "ldrh w20, [x4]", + "strh w20, [x28, #1008]", + "ldrh w20, [x4, #2]", + "ubfx w21, w20, #11, #3", + "strb w21, [x28, #747]", + "ubfx w21, w20, #8, #1", + "ubfx w22, w20, #9, #1", + "ubfx w23, w20, #10, #1", + "ubfx w20, w20, #14, #1", + "strb w21, [x28, #744]", + "strb w22, [x28, #745]", + "strb w23, [x28, #746]", + "strb w20, [x28, #750]", + "ldrb w20, [x4, #4]", + "strb w20, [x28, #1010]", + "ldr q2, [x4, #32]", + "str q2, [x28, #752]", + "ldr q2, [x4, #48]", + "str q2, [x28, #768]", + "ldr q2, [x4, #64]", + "str q2, [x28, #784]", + "ldr q2, [x4, #80]", + "str q2, [x28, #800]", + "ldr q2, [x4, #96]", + "str q2, [x28, #816]", + "ldr q2, [x4, #112]", + "str q2, [x28, #832]", + "ldr q2, [x4, #128]", + "str q2, [x28, #848]", + "ldr q2, [x4, #144]", + "str q2, [x28, #864]", + "ldr q16, [x4, #160]", + "ldr q17, [x4, #176]", + "ldr q18, [x4, #192]", + "ldr q19, [x4, #208]", + "ldr q20, [x4, #224]", + "ldr q21, [x4, #240]", + "ldr q22, [x4, #256]", + "ldr q23, [x4, #272]", + "ldr q24, [x4, #288]", + "ldr q25, [x4, #304]", + "ldr q26, [x4, #320]", + "ldr q27, [x4, #336]", + "ldr q28, [x4, #352]", + "ldr q29, [x4, #368]", + "ldr q30, [x4, #384]", + "ldr q31, [x4, #400]", + "ldr w20, [x4, #24]", + "ubfx w20, w20, #13, #3", + "rbit w1, w20", + "lsr w1, w1, #30", + "mrs x0, fpcr", + "bfi x0, x1, #22, #2", + "lsr x1, x20, #2", + "bfi x0, x1, #24, #1", + "msr fpcr, x0" + ] + }, + "rdgsbase eax": { + "ExpectedInstructionCount": 1, + "Optimal": "Yes", + "Comment": "GROUP15 0x0F 0xAE /1", + "ExpectedArm64ASM": [ + "ldr w4, [x28, #168]" + ] + }, + "rdgsbase rax": { + "ExpectedInstructionCount": 1, + "Optimal": "Yes", + "Comment": "GROUP15 0x0F 0xAE /1", + "ExpectedArm64ASM": [ + "ldr x4, [x28, #168]" + ] + }, + "ldmxcsr [rax]": { + "ExpectedInstructionCount": 9, + "Optimal": "No", + "Comment": "GROUP15 0x0F 0xAE /2", + "ExpectedArm64ASM": [ + "ldr w20, [x4]", + "ubfx w20, w20, #13, #3", + "rbit w1, w20", + "lsr w1, w1, #30", + "mrs x0, fpcr", + "bfi x0, x1, #22, #2", + "lsr x1, x20, #2", + "bfi x0, x1, #24, #1", + "msr fpcr, x0" + ] + }, + "wrfsbase eax": { + "ExpectedInstructionCount": 2, + "Optimal": "Yes", + "Comment": "GROUP15 0x0F 0xAE /2", + "ExpectedArm64ASM": [ + "mov w20, w4", + "str x20, [x28, #176]" + ] + }, + "wrfsbase rax": { + "ExpectedInstructionCount": 1, + "Optimal": "Yes", + "Comment": "GROUP15 0x0F 0xAE /2", + "ExpectedArm64ASM": [ + "str x4, [x28, #176]" + ] + }, + "stmxcsr [rax]": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": "GROUP15 0x0F 0xAE /3", + "ExpectedArm64ASM": [ + "mov w20, #0x1f80", + "mrs x21, fpcr", + "ubfx x21, x21, #22, #3", + "rbit w0, w21", + "bfi x21, x0, #30, #2", + "bfi w20, w21, #13, #3", + "str w20, [x4]" + ] + }, + "wrgsbase eax": { + "ExpectedInstructionCount": 2, + "Optimal": "Yes", + "Comment": "GROUP15 0x0F 0xAE /3", + "ExpectedArm64ASM": [ + "mov w20, w4", + "str x20, [x28, #168]" + ] + }, + "wrgsbase rax": { + "ExpectedInstructionCount": 1, + "Optimal": "Yes", + "Comment": "GROUP15 0x0F 0xAE /3", + "ExpectedArm64ASM": [ + "str x4, [x28, #168]" + ] + }, + "xsave [rax]": { + "ExpectedInstructionCount": 71, + "Optimal": "No", + "Comment": "GROUP15 0x0F 0xAE /4", + "ExpectedArm64ASM": [ + "mov x20, x4", + "mov x21, x4", + "ubfx x22, x20, #0, #1", + "cbnz x22, #+0x8", + "b #+0x84", + "ldrh w22, [x28, #1008]", + "strh w22, [x21]", + "mov w22, #0x0", + "ldrb w23, [x28, #747]", + "bfi x22, x23, #11, #3", + "ldrb w23, [x28, #744]", + "ldrb w24, [x28, #745]", + "ldrb w25, [x28, #746]", + "ldrb w26, [x28, #750]", + "orr x22, x22, x23, lsl #8", + "orr x22, x22, x24, lsl #9", + "orr x22, x22, x25, lsl #10", + "orr x22, x22, x26, lsl #14", + "strh w22, [x21, #2]", + "ldrb w22, [x28, #1010]", + "strb w22, [x21, #4]", + "ldr q2, [x28, #752]", + "str q2, [x21, #32]", + "ldr q2, [x28, #768]", + "str q2, [x21, #48]", + "ldr q2, [x28, #784]", + "str q2, [x21, #64]", + "ldr q2, [x28, #800]", + "str q2, [x21, #80]", + "ldr q2, [x28, #816]", + "str q2, [x21, #96]", + "ldr q2, [x28, #832]", + "str q2, [x21, #112]", + "ldr q2, [x28, #848]", + "str q2, [x21, #128]", + "ldr q2, [x28, #864]", + "str q2, [x21, #144]", + "ubfx x22, x20, #1, #1", + "cbnz x22, #+0x8", + "b #+0x44", + "str q16, [x21, #160]", + "str q17, [x21, #176]", + "str q18, [x21, #192]", + "str q19, [x21, #208]", + "str q20, [x21, #224]", + "str q21, [x21, #240]", + "str q22, [x21, #256]", + "str q23, [x21, #272]", + "str q24, [x21, #288]", + "str q25, [x21, #304]", + "str q26, [x21, #320]", + "str q27, [x21, #336]", + "str q28, [x21, #352]", + "str q29, [x21, #368]", + "str q30, [x21, #384]", + "str q31, [x21, #400]", + "ubfx x22, x20, #1, #2", + "cbnz x22, #+0x8", + "b #+0x2c", + "mov w22, #0x1f80", + "mrs x23, fpcr", + "ubfx x23, x23, #22, #3", + "rbit w0, w23", + "bfi x23, x0, #30, #2", + "bfi w22, w23, #13, #3", + "add x23, x21, #0x18 (24)", + "str w22, [x21, #24]", + "mov w22, #0xffff", + "str w22, [x23, #4]", + "ubfx x20, x20, #0, #3", + "str x20, [x21, #512]" + ] + }, + "lfence": { + "ExpectedInstructionCount": 1, + "Optimal": "Yes", + "Comment": "GROUP15 0x0F 0xAE /5", + "ExpectedArm64ASM": [ + "dmb ld" + ] + }, + "xrstor [rax]": { + "ExpectedInstructionCount": 104, + "Optimal": "No", + "Comment": "GROUP15 0x0F 0xAE /5", + "ExpectedArm64ASM": [ + "mov x20, x4", + "ldr x21, [x20, #512]", + "ubfx x22, x21, #0, #1", + "cbnz x22, #+0x8", + "b #+0x84", + "ldrh w22, [x20]", + "strh w22, [x28, #1008]", + "ldrh w22, [x20, #2]", + "ubfx w23, w22, #11, #3", + "strb w23, [x28, #747]", + "ubfx w23, w22, #8, #1", + "ubfx w24, w22, #9, #1", + "ubfx w25, w22, #10, #1", + "ubfx w22, w22, #14, #1", + "strb w23, [x28, #744]", + "strb w24, [x28, #745]", + "strb w25, [x28, #746]", + "strb w22, [x28, #750]", + "ldrb w22, [x20, #4]", + "strb w22, [x28, #1010]", + "ldr q2, [x20, #32]", + "str q2, [x28, #752]", + "ldr q2, [x20, #48]", + "str q2, [x28, #768]", + "ldr q2, [x20, #64]", + "str q2, [x28, #784]", + "ldr q2, [x20, #80]", + "str q2, [x28, #800]", + "ldr q2, [x20, #96]", + "str q2, [x28, #816]", + "ldr q2, [x20, #112]", + "str q2, [x28, #832]", + "ldr q2, [x20, #128]", + "str q2, [x28, #848]", + "ldr q2, [x20, #144]", + "str q2, [x28, #864]", + "b #+0x4c", + "mov w22, #0x0", + "mov w23, #0x37f", + "strh w23, [x28, #1008]", + "strb w22, [x28, #747]", + "strb w22, [x28, #744]", + "strb w22, [x28, #745]", + "strb w22, [x28, #746]", + "strb w22, [x28, #750]", + "strb w22, [x28, #1010]", + "movi v2.2d, #0x0", + "str q2, [x28, #752]", + "str q2, [x28, #768]", + "str q2, [x28, #784]", + "str q2, [x28, #800]", + "str q2, [x28, #816]", + "str q2, [x28, #832]", + "str q2, [x28, #848]", + "str q2, [x28, #864]", + "ubfx x22, x21, #1, #1", + "cbnz x22, #+0x8", + "b #+0x48", + "ldr q16, [x20, #160]", + "ldr q17, [x20, #176]", + "ldr q18, [x20, #192]", + "ldr q19, [x20, #208]", + "ldr q20, [x20, #224]", + "ldr q21, [x20, #240]", + "ldr q22, [x20, #256]", + "ldr q23, [x20, #272]", + "ldr q24, [x20, #288]", + "ldr q25, [x20, #304]", + "ldr q26, [x20, #320]", + "ldr q27, [x20, #336]", + "ldr q28, [x20, #352]", + "ldr q29, [x20, #368]", + "ldr q30, [x20, #384]", + "ldr q31, [x20, #400]", + "b #+0x44", + "movi v16.2d, #0x0", + "mov v17.16b, v16.16b", + "mov v18.16b, v16.16b", + "mov v19.16b, v16.16b", + "mov v20.16b, v16.16b", + "mov v21.16b, v16.16b", + "mov v22.16b, v16.16b", + "mov v23.16b, v16.16b", + "mov v24.16b, v16.16b", + "mov v25.16b, v16.16b", + "mov v26.16b, v16.16b", + "mov v27.16b, v16.16b", + "mov v28.16b, v16.16b", + "mov v29.16b, v16.16b", + "mov v30.16b, v16.16b", + "mov v31.16b, v16.16b", + "ubfx x21, x21, #1, #2", + "cbnz x21, #+0x8", + "b #+0x2c", + "ldr w20, [x20, #24]", + "ubfx w20, w20, #13, #3", + "rbit w1, w20", + "lsr w1, w1, #30", + "mrs x0, fpcr", + "bfi x0, x1, #22, #2", + "lsr x1, x20, #2", + "bfi x0, x1, #24, #1", + "msr fpcr, x0", + "b #+0x4" + ] + }, + "mfence": { + "ExpectedInstructionCount": 1, + "Optimal": "Yes", + "Comment": "GROUP15 0x0F 0xAE /6", + "ExpectedArm64ASM": [ + "dmb sy" + ] + }, + "clwb [rax]": { + "ExpectedInstructionCount": 1, + "Optimal": "Yes", + "Comment": "GROUP15 0x0F 0xAE /6", + "ExpectedArm64ASM": [ + "dc cvac, x4" + ] + }, + "sfence": { + "ExpectedInstructionCount": 1, + "Optimal": "Yes", + "Comment": "GROUP15 0x0F 0xAE /7", + "ExpectedArm64ASM": [ + "dmb st" + ] + }, + "clflush [rax]": { + "ExpectedInstructionCount": 2, + "Optimal": "Yes", + "Comment": "GROUP15 0x0F 0xAE /7", + "ExpectedArm64ASM": [ + "dc civac, x4", + "dsb ish" + ] + }, + "clflushopt [rax]": { + "ExpectedInstructionCount": 1, + "Optimal": "Yes", + "Comment": "GROUP15 0x0F 0xAE /7", + "ExpectedArm64ASM": [ + "dc civac, x4" + ] + }, + "prefetchnta [rax]": { + "ExpectedInstructionCount": 0, + "Optimal": "Yes", + "Comment": [ + "GROUP16 0x0F 0x18 /0", + "NOP implementation" + ], + "ExpectedArm64ASM": [] + }, + "prefetcht0 [rax]": { + "ExpectedInstructionCount": 0, + "Optimal": "Yes", + "Comment": [ + "GROUP16 0x0F 0x18 /1", + "NOP implementation" + ], + "ExpectedArm64ASM": [] + }, + "prefetcht1 [rax]": { + "ExpectedInstructionCount": 0, + "Optimal": "Yes", + "Comment": [ + "GROUP16 0x0F 0x18 /2", + "NOP implementation" + ], + "ExpectedArm64ASM": [] + }, + "prefetcht2 [rax]": { + "ExpectedInstructionCount": 0, + "Optimal": "Yes", + "Comment": [ + "GROUP16 0x0F 0x18 /3", + "NOP implementation" + ], + "ExpectedArm64ASM": [] + }, + "db 0x0f, 0x18, 0x20;": { + "ExpectedInstructionCount": 0, + "Optimal": "Yes", + "Comment": [ + "GROUP16 0x0F 0x18 /4", + "nop dword [rax]", + "NOP implementation" + ], + "ExpectedArm64ASM": [] + }, + "db 0x0f, 0x0d, 0x00": { + "ExpectedInstructionCount": 0, + "Optimal": "Yes", + "Comment": [ + "GROUPP 0x0F 0x0D /0", + "prefetch_exclusive [rax]", + "NOP implementation" + ], + "ExpectedArm64ASM": [] + }, + "prefetchw [rax]": { + "ExpectedInstructionCount": 0, + "Optimal": "Yes", + "Comment": [ + "GROUPP 0x0F 0x0D /1", + "NOP implementation" + ], + "ExpectedArm64ASM": [] + }, + "prefetchwt1 [rax]": { + "ExpectedInstructionCount": 0, + "Optimal": "Yes", + "Comment": [ + "GROUPP 0x0F 0x0D /2", + "NOP implementation" + ], + "ExpectedArm64ASM": [] + } + } +} diff --git a/unittests/InstructionCountCI/FlagM/SecondaryModRM.json b/unittests/InstructionCountCI/FlagM/SecondaryModRM.json new file mode 100644 index 000000000..0fba723a3 --- /dev/null +++ b/unittests/InstructionCountCI/FlagM/SecondaryModRM.json @@ -0,0 +1,94 @@ +{ + "Features": { + "Bitness": 64, + "EnabledHostFeatures": [ + "CLZERO", + "FLAGM", + "FLAGM2" + ], + "DisabledHostFeatures": [ + "SVE128", + "SVE256", + "AFP" + ] + }, + "Instructions": { + "xgetbv": { + "ExpectedInstructionCount": 46, + "Optimal": "No", + "Comment": "0xF 0x01 /2 RM-0", + "ExpectedArm64ASM": [ + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "ldr x0, [x28, #1096]", + "ldr x2, [x28, #1112]", + "mov w1, w5", + "blr x2", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "mov w20, w0", + "lsr x21, x0, #32", + "mov w4, w20", + "mov w6, w21" + ] + }, + "rdtscp": { + "ExpectedInstructionCount": 17, + "Optimal": "No", + "Comment": "0xF 0x01 /7 RM-1", + "ExpectedArm64ASM": [ + "dmb ld", + "mrs x20, S3_3_c14_c0_2", + "mov w4, w20", + "lsr x6, x20, #32", + "str x8, [x28, #40]", + "mov w0, #0x100", + "str x0, [x28, #1040]", + "sub sp, sp, #0x10 (16)", + "mov w8, #0xa8", + "mov x0, sp", + "add x1, sp, #0x4 (4)", + "svc #0x0", + "ldp w0, w1, [sp]", + "sub sp, sp, #0x10 (16)", + "ldr x8, [x28, #40]", + "str xzr, [x28, #1040]", + "orr x5, x0, x1, lsl #12" + ] + } + } +} diff --git a/unittests/InstructionCountCI/FlagM/Secondary_OpSize.json b/unittests/InstructionCountCI/FlagM/Secondary_OpSize.json new file mode 100644 index 000000000..287f8e27e --- /dev/null +++ b/unittests/InstructionCountCI/FlagM/Secondary_OpSize.json @@ -0,0 +1,100 @@ +{ + "Features": { + "Bitness": 64, + "EnabledHostFeatures": [ + "FLAGM", + "FLAGM2" + ], + "DisabledHostFeatures": [ + "SVE128", + "SVE256", + "FCMA" + ] + }, + "Instructions": { + "ucomisd xmm0, xmm1": { + "ExpectedInstructionCount": 19, + "Optimal": "No", + "Comment": "0x66 0x0f 0x2e", + "ExpectedArm64ASM": [ + "fcmp d16, d17", + "cset x20, eq", + "csinc x20, x20, xzr, vc", + "cset x1, lt", + "bfi x20, x1, #1, #1", + "cset x1, vs", + "bfi x20, x1, #2, #1", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "lsl x21, x21, #29", + "orr w21, w21, w22, lsl #30", + "eor w20, w20, #0x1", + "strb w20, [x28, #706]", + "mov w20, #0x0", + "mov w22, #0x90000000", + "bic x21, x21, x22", + "strb w20, [x28, #708]", + "str w21, [x28, #728]" + ] + }, + "comisd xmm0, xmm1": { + "ExpectedInstructionCount": 22, + "Optimal": "No", + "Comment": "0x66 0x0f 0x2f", + "ExpectedArm64ASM": [ + "fcmp d16, d17", + "cset x20, eq", + "csinc x20, x20, xzr, vc", + "cset x1, lt", + "bfi x20, x1, #1, #1", + "cset x1, vs", + "bfi x20, x1, #2, #1", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "ldr w23, [x28, #728]", + "mov w0, w23", + "bfi w0, w21, #29, #1", + "mov w21, w0", + "bfi w21, w22, #30, #1", + "eor w20, w20, #0x1", + "strb w20, [x28, #706]", + "mov w20, #0x0", + "mov w22, #0x90000000", + "bic x21, x21, x22", + "strb w20, [x28, #708]", + "str w21, [x28, #728]" + ] + }, + "pmovmskb eax, xmm0": { + "ExpectedInstructionCount": 11, + "Optimal": "Yes", + "Comment": "0x66 0x0f 0xd7", + "ExpectedArm64ASM": [ + "mov x20, #0x201", + "movk x20, #0x804, lsl #16", + "movk x20, #0x2010, lsl #32", + "movk x20, #0x8040, lsl #48", + "dup v2.2d, x20", + "cmlt v3.16b, v16.16b, #0", + "and v2.16b, v3.16b, v2.16b", + "addp v2.16b, v2.16b, v2.16b", + "addp v2.8b, v2.8b, v2.8b", + "addp v2.8b, v2.8b, v2.8b", + "umov w4, v2.h[0]" + ] + }, + "maskmovdqu xmm0, xmm1": { + "ExpectedInstructionCount": 4, + "Optimal": "Yes", + "Comment": "0x66 0x0f 0xf7", + "ExpectedArm64ASM": [ + "cmlt v2.16b, v17.16b, #0", + "ldr q3, [x11]", + "bsl v2.16b, v16.16b, v3.16b", + "str q2, [x11]" + ] + } + } +} diff --git a/unittests/InstructionCountCI/FlagM/Secondary_REP.json b/unittests/InstructionCountCI/FlagM/Secondary_REP.json new file mode 100644 index 000000000..866656d2a --- /dev/null +++ b/unittests/InstructionCountCI/FlagM/Secondary_REP.json @@ -0,0 +1,173 @@ +{ + "Features": { + "Bitness": 64, + "EnabledHostFeatures": [ + "FLAGM", + "FLAGM2" + ], + "DisabledHostFeatures": [ + "SVE128", + "SVE256", + "RPRES", + "AFP" + ] + }, + "Instructions": { + "popcnt ax, bx": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": "0xf3 0x0f 0xb8", + "ExpectedArm64ASM": [ + "uxth w20, w7", + "fmov s0, w20", + "cnt v0.8b, v0.8b", + "addp v0.8b, v0.8b, v0.8b", + "umov w20, v0.b[0]", + "bfxil x4, x20, #0, #16", + "mov w21, #0x0", + "mov w22, #0x1", + "cmp x20, #0x0 (0)", + "cset x20, eq", + "strb w22, [x28, #706]", + "strb w21, [x28, #708]", + "lsl x20, x20, #30", + "str w20, [x28, #728]" + ] + }, + "popcnt eax, ebx": { + "ExpectedInstructionCount": 13, + "Optimal": "No", + "Comment": "0xf3 0x0f 0xb8", + "ExpectedArm64ASM": [ + "mov w20, w7", + "fmov s0, w20", + "cnt v0.8b, v0.8b", + "addv b0, v0.8b", + "umov w4, v0.b[0]", + "mov w20, #0x0", + "mov w21, #0x1", + "cmp x4, #0x0 (0)", + "cset x22, eq", + "strb w21, [x28, #706]", + "strb w20, [x28, #708]", + "lsl x20, x22, #30", + "str w20, [x28, #728]" + ] + }, + "popcnt rax, rbx": { + "ExpectedInstructionCount": 12, + "Optimal": "No", + "Comment": "0xf3 0x0f 0xb8", + "ExpectedArm64ASM": [ + "fmov d0, x7", + "cnt v0.8b, v0.8b", + "addv b0, v0.8b", + "umov w4, v0.b[0]", + "mov w20, #0x0", + "mov w21, #0x1", + "cmp x4, #0x0 (0)", + "cset x22, eq", + "strb w21, [x28, #706]", + "strb w20, [x28, #708]", + "lsl x20, x22, #30", + "str w20, [x28, #728]" + ] + }, + "tzcnt ax, bx": { + "ExpectedInstructionCount": 11, + "Optimal": "No", + "Comment": "0xf3 0x0f 0xbc", + "ExpectedArm64ASM": [ + "uxth w20, w7", + "rbit w20, w20", + "orr w20, w20, #0x8000", + "clz w20, w20", + "bfxil x4, x20, #0, #16", + "cmp x20, #0x0 (0)", + "cset x21, eq", + "lsl x21, x21, #29", + "ubfx w20, w20, #0, #1", + "orr w20, w21, w20, lsl #30", + "str w20, [x28, #728]" + ] + }, + "tzcnt eax, ebx": { + "ExpectedInstructionCount": 9, + "Optimal": "No", + "Comment": "0xf3 0x0f 0xbc", + "ExpectedArm64ASM": [ + "mov w20, w7", + "rbit w4, w20", + "clz w4, w4", + "cmp x4, #0x0 (0)", + "cset x20, eq", + "lsl x20, x20, #29", + "ubfx w21, w4, #0, #1", + "orr w20, w20, w21, lsl #30", + "str w20, [x28, #728]" + ] + }, + "tzcnt rax, rbx": { + "ExpectedInstructionCount": 8, + "Optimal": "Yes", + "Comment": "0xf3 0x0f 0xbc", + "ExpectedArm64ASM": [ + "rbit x4, x7", + "clz x4, x4", + "cmp x4, #0x0 (0)", + "cset x20, eq", + "lsl x20, x20, #29", + "ubfx w21, w4, #0, #1", + "orr w20, w20, w21, lsl #30", + "str w20, [x28, #728]" + ] + }, + "lzcnt ax, bx": { + "ExpectedInstructionCount": 11, + "Optimal": "No", + "Comment": "0xf3 0x0f 0xbd", + "ExpectedArm64ASM": [ + "uxth w20, w7", + "lsl w21, w20, #16", + "orr w21, w21, #0x8000", + "clz w21, w21", + "bfxil x4, x21, #0, #16", + "cmp x20, #0x0 (0)", + "cset x21, eq", + "lsl x21, x21, #29", + "ubfx w20, w20, #15, #1", + "orr w20, w21, w20, lsl #30", + "str w20, [x28, #728]" + ] + }, + "lzcnt eax, ebx": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": "0xf3 0x0f 0xbd", + "ExpectedArm64ASM": [ + "mov w20, w7", + "clz w4, w20", + "cmp x20, #0x0 (0)", + "cset x21, eq", + "lsl x21, x21, #29", + "lsr w20, w20, #31", + "orr w20, w21, w20, lsl #30", + "str w20, [x28, #728]" + ] + }, + "lzcnt rax, rbx": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": "0xf3 0x0f 0xbd", + "ExpectedArm64ASM": [ + "clz x4, x7", + "cmp x7, #0x0 (0)", + "cset x20, eq", + "lsl x20, x20, #29", + "lsr x21, x7, #63", + "orr w20, w20, w21, lsl #30", + "str w20, [x28, #728]" + ] + } + } +} diff --git a/unittests/InstructionCountCI/FlagM/VEX_map1.json b/unittests/InstructionCountCI/FlagM/VEX_map1.json new file mode 100644 index 000000000..8e34cf7ff --- /dev/null +++ b/unittests/InstructionCountCI/FlagM/VEX_map1.json @@ -0,0 +1,200 @@ +{ + "Features": { + "Bitness": 64, + "EnabledHostFeatures": [ + "SVE128", + "SVE256", + "FLAGM", + "FLAGM2" + ], + "DisabledHostFeatures": [ + "FCMA", + "RPRES", + "AFP" + ] + }, + "Instructions": { + "vucomiss xmm0, xmm1": { + "ExpectedInstructionCount": 19, + "Optimal": "No", + "Comment": [ + "Map 1 0b00 0x2e 128-bit" + ], + "ExpectedArm64ASM": [ + "fcmp s16, s17", + "cset x20, eq", + "csinc x20, x20, xzr, vc", + "cset x1, lt", + "bfi x20, x1, #1, #1", + "cset x1, vs", + "bfi x20, x1, #2, #1", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "lsl x21, x21, #29", + "orr w21, w21, w22, lsl #30", + "eor w20, w20, #0x1", + "strb w20, [x28, #706]", + "mov w20, #0x0", + "mov w22, #0x90000000", + "bic x21, x21, x22", + "strb w20, [x28, #708]", + "str w21, [x28, #728]" + ] + }, + "vucomisd xmm0, xmm1": { + "ExpectedInstructionCount": 22, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x2e 128-bit" + ], + "ExpectedArm64ASM": [ + "fcmp d16, d17", + "cset x20, eq", + "csinc x20, x20, xzr, vc", + "cset x1, lt", + "bfi x20, x1, #1, #1", + "cset x1, vs", + "bfi x20, x1, #2, #1", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "ldr w23, [x28, #728]", + "mov w0, w23", + "bfi w0, w21, #29, #1", + "mov w21, w0", + "bfi w21, w22, #30, #1", + "eor w20, w20, #0x1", + "strb w20, [x28, #706]", + "mov w20, #0x0", + "mov w22, #0x90000000", + "bic x21, x21, x22", + "strb w20, [x28, #708]", + "str w21, [x28, #728]" + ] + }, + "vcomiss xmm0, xmm1": { + "ExpectedInstructionCount": 22, + "Optimal": "No", + "Comment": [ + "Map 1 0b00 0x2f 128-bit" + ], + "ExpectedArm64ASM": [ + "fcmp s16, s17", + "cset x20, eq", + "csinc x20, x20, xzr, vc", + "cset x1, lt", + "bfi x20, x1, #1, #1", + "cset x1, vs", + "bfi x20, x1, #2, #1", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "ldr w23, [x28, #728]", + "mov w0, w23", + "bfi w0, w21, #29, #1", + "mov w21, w0", + "bfi w21, w22, #30, #1", + "eor w20, w20, #0x1", + "strb w20, [x28, #706]", + "mov w20, #0x0", + "mov w22, #0x90000000", + "bic x21, x21, x22", + "strb w20, [x28, #708]", + "str w21, [x28, #728]" + ] + }, + "vcomisd xmm0, xmm1": { + "ExpectedInstructionCount": 22, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0x2f 128-bit" + ], + "ExpectedArm64ASM": [ + "fcmp d16, d17", + "cset x20, eq", + "csinc x20, x20, xzr, vc", + "cset x1, lt", + "bfi x20, x1, #1, #1", + "cset x1, vs", + "bfi x20, x1, #2, #1", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "ldr w23, [x28, #728]", + "mov w0, w23", + "bfi w0, w21, #29, #1", + "mov w21, w0", + "bfi w21, w22, #30, #1", + "eor w20, w20, #0x1", + "strb w20, [x28, #706]", + "mov w20, #0x0", + "mov w22, #0x90000000", + "bic x21, x21, x22", + "strb w20, [x28, #708]", + "str w21, [x28, #728]" + ] + }, + "vpmovmskb rax, xmm0": { + "ExpectedInstructionCount": 11, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xd7 256-bit" + ], + "ExpectedArm64ASM": [ + "mov x20, #0x201", + "movk x20, #0x804, lsl #16", + "movk x20, #0x2010, lsl #32", + "movk x20, #0x8040, lsl #48", + "dup v2.2d, x20", + "cmlt v3.16b, v16.16b, #0", + "and v2.16b, v3.16b, v2.16b", + "addp v2.16b, v2.16b, v2.16b", + "addp v2.8b, v2.8b, v2.8b", + "addp v2.8b, v2.8b, v2.8b", + "umov w4, v2.h[0]" + ] + }, + "vpmovmskb rax, ymm0": { + "ExpectedInstructionCount": 19, + "Optimal": "No", + "Comment": [ + "Map 1 0b01 0xd7 256-bit" + ], + "ExpectedArm64ASM": [ + "mov x20, #0x201", + "movk x20, #0x804, lsl #16", + "movk x20, #0x2010, lsl #32", + "movk x20, #0x8040, lsl #48", + "mov z2.d, x20", + "mov z0.d, #0", + "cmplt p0.b, p7/z, z16.b, #0", + "not z0.b, p0/m, z16.b", + "orr z0.b, p0/m, z0.b, z16.b", + "mov z3.d, z0.d", + "and z2.d, z3.d, z2.d", + "movprfx z0, z2", + "addp z0.b, p7/m, z0.b, z2.b", + "uzp1 z2.b, z0.b, z0.b", + "uzp2 z1.b, z0.b, z0.b", + "splice z2.d, p6, z2.d, z1.d", + "addp v2.16b, v2.16b, v2.16b", + "addp v2.8b, v2.8b, v2.8b", + "mov w4, v2.s[0]" + ] + }, + "vmaskmovdqu xmm0, xmm1": { + "ExpectedInstructionCount": 4, + "Optimal": "Yes", + "Comment": [ + "Map 1 0b01 0xf7 128-bit" + ], + "ExpectedArm64ASM": [ + "cmlt v2.16b, v17.16b, #0", + "ldr q3, [x11]", + "bsl v2.16b, v16.16b, v3.16b", + "str q2, [x11]" + ] + } + } +} diff --git a/unittests/InstructionCountCI/FlagM/VEX_map2.json b/unittests/InstructionCountCI/FlagM/VEX_map2.json new file mode 100644 index 000000000..b435830ae --- /dev/null +++ b/unittests/InstructionCountCI/FlagM/VEX_map2.json @@ -0,0 +1,614 @@ +{ + "Features": { + "Bitness": 64, + "EnabledHostFeatures": [ + "SVE256", + "FLAGM", + "FLAGM2" + ], + "DisabledHostFeatures": [ + "AFP" + ] + }, + "Instructions": { + "vtestps xmm0, xmm1": { + "ExpectedInstructionCount": 25, + "Optimal": "No", + "Comment": [ + "Map 2 0b01 0x0e 128-bit" + ], + "ExpectedArm64ASM": [ + "mov w20, #0x80000000", + "dup v2.4s, w20", + "and v3.16b, v17.16b, v16.16b", + "bic v4.16b, v17.16b, v16.16b", + "and v3.16b, v3.16b, v2.16b", + "and v2.16b, v4.16b, v2.16b", + "cnt v3.16b, v3.16b", + "cnt v2.16b, v2.16b", + "addv h3, v3.8h", + "addv h2, v2.8h", + "umov w20, v3.h[0]", + "umov w21, v2.h[0]", + "mov w22, #0x0", + "mov w23, #0x1", + "cmp x20, #0x0 (0)", + "cset x20, eq", + "cmp x21, #0x0 (0)", + "cset x21, eq", + "lsl x20, x20, #30", + "orr w20, w20, w21, lsl #29", + "mov w21, #0x90000000", + "bic x20, x20, x21", + "strb w23, [x28, #706]", + "strb w22, [x28, #708]", + "str w20, [x28, #728]" + ] + }, + "vtestps ymm0, ymm1": { + "ExpectedInstructionCount": 33, + "Optimal": "No", + "Comment": [ + "Map 2 0b01 0x0e 256-bit" + ], + "ExpectedArm64ASM": [ + "mov w20, #0x80000000", + "mov z2.s, w20", + "and z3.d, z17.d, z16.d", + "bic z4.d, z17.d, z16.d", + "and z3.d, z3.d, z2.d", + "and z2.d, z4.d, z2.d", + "cnt z3.b, p7/m, z3.b", + "cnt z2.b, p7/m, z2.b", + "not p0.b, p7/z, p6.b", + "compact z0.d, p0, z3.d", + "addv h1, v3.8h", + "addv h0, v0.8h", + "add v3.8h, v0.8h, v1.8h", + "not p0.b, p7/z, p6.b", + "compact z0.d, p0, z2.d", + "addv h1, v2.8h", + "addv h0, v0.8h", + "add v2.8h, v0.8h, v1.8h", + "umov w20, v3.h[0]", + "umov w21, v2.h[0]", + "mov w22, #0x0", + "mov w23, #0x1", + "cmp x20, #0x0 (0)", + "cset x20, eq", + "cmp x21, #0x0 (0)", + "cset x21, eq", + "lsl x20, x20, #30", + "orr w20, w20, w21, lsl #29", + "mov w21, #0x90000000", + "bic x20, x20, x21", + "strb w23, [x28, #706]", + "strb w22, [x28, #708]", + "str w20, [x28, #728]" + ] + }, + "vtestpd xmm0, xmm1": { + "ExpectedInstructionCount": 25, + "Optimal": "No", + "Comment": [ + "Map 2 0b01 0x0f 128-bit" + ], + "ExpectedArm64ASM": [ + "mov x20, #0x8000000000000000", + "dup v2.2d, x20", + "and v3.16b, v17.16b, v16.16b", + "bic v4.16b, v17.16b, v16.16b", + "and v3.16b, v3.16b, v2.16b", + "and v2.16b, v4.16b, v2.16b", + "cnt v3.16b, v3.16b", + "cnt v2.16b, v2.16b", + "addv h3, v3.8h", + "addv h2, v2.8h", + "umov w20, v3.h[0]", + "umov w21, v2.h[0]", + "mov w22, #0x0", + "mov w23, #0x1", + "cmp x20, #0x0 (0)", + "cset x20, eq", + "cmp x21, #0x0 (0)", + "cset x21, eq", + "lsl x20, x20, #30", + "orr w20, w20, w21, lsl #29", + "mov w21, #0x90000000", + "bic x20, x20, x21", + "strb w23, [x28, #706]", + "strb w22, [x28, #708]", + "str w20, [x28, #728]" + ] + }, + "vtestpd ymm0, ymm1": { + "ExpectedInstructionCount": 33, + "Optimal": "No", + "Comment": [ + "Map 2 0b01 0x0f 256-bit" + ], + "ExpectedArm64ASM": [ + "mov x20, #0x8000000000000000", + "mov z2.d, x20", + "and z3.d, z17.d, z16.d", + "bic z4.d, z17.d, z16.d", + "and z3.d, z3.d, z2.d", + "and z2.d, z4.d, z2.d", + "cnt z3.b, p7/m, z3.b", + "cnt z2.b, p7/m, z2.b", + "not p0.b, p7/z, p6.b", + "compact z0.d, p0, z3.d", + "addv h1, v3.8h", + "addv h0, v0.8h", + "add v3.8h, v0.8h, v1.8h", + "not p0.b, p7/z, p6.b", + "compact z0.d, p0, z2.d", + "addv h1, v2.8h", + "addv h0, v0.8h", + "add v2.8h, v0.8h, v1.8h", + "umov w20, v3.h[0]", + "umov w21, v2.h[0]", + "mov w22, #0x0", + "mov w23, #0x1", + "cmp x20, #0x0 (0)", + "cset x20, eq", + "cmp x21, #0x0 (0)", + "cset x21, eq", + "lsl x20, x20, #30", + "orr w20, w20, w21, lsl #29", + "mov w21, #0x90000000", + "bic x20, x20, x21", + "strb w23, [x28, #706]", + "strb w22, [x28, #708]", + "str w20, [x28, #728]" + ] + }, + "vptest xmm0, xmm1": { + "ExpectedInstructionCount": 19, + "Optimal": "No", + "Comment": [ + "Map 2 0b01 0x16 128-bit" + ], + "ExpectedArm64ASM": [ + "and v2.16b, v16.16b, v17.16b", + "bic v3.16b, v17.16b, v16.16b", + "cnt v2.16b, v2.16b", + "cnt v3.16b, v3.16b", + "addv h2, v2.8h", + "addv h3, v3.8h", + "umov w20, v2.h[0]", + "umov w21, v3.h[0]", + "mov w22, #0x0", + "mov w23, #0x1", + "cmp x20, #0x0 (0)", + "cset x20, eq", + "cmp x21, #0x0 (0)", + "cset x21, eq", + "lsl x20, x20, #30", + "orr w20, w20, w21, lsl #29", + "strb w23, [x28, #706]", + "strb w22, [x28, #708]", + "str w20, [x28, #728]" + ] + }, + "vptest ymm0, ymm1": { + "ExpectedInstructionCount": 27, + "Optimal": "No", + "Comment": [ + "Map 2 0b01 0x16 256-bit" + ], + "ExpectedArm64ASM": [ + "and z2.d, z16.d, z17.d", + "bic z3.d, z17.d, z16.d", + "cnt z2.b, p7/m, z2.b", + "cnt z3.b, p7/m, z3.b", + "not p0.b, p7/z, p6.b", + "compact z0.d, p0, z2.d", + "addv h1, v2.8h", + "addv h0, v0.8h", + "add v2.8h, v0.8h, v1.8h", + "not p0.b, p7/z, p6.b", + "compact z0.d, p0, z3.d", + "addv h1, v3.8h", + "addv h0, v0.8h", + "add v3.8h, v0.8h, v1.8h", + "umov w20, v2.h[0]", + "umov w21, v3.h[0]", + "mov w22, #0x0", + "mov w23, #0x1", + "cmp x20, #0x0 (0)", + "cset x20, eq", + "cmp x21, #0x0 (0)", + "cset x21, eq", + "lsl x20, x20, #30", + "orr w20, w20, w21, lsl #29", + "strb w23, [x28, #706]", + "strb w22, [x28, #708]", + "str w20, [x28, #728]" + ] + }, + "vmaskmovps xmm0, xmm1, [rax]": { + "ExpectedInstructionCount": 3, + "Optimal": "No", + "Comment": [ + "Map 2 0b01 0x2c 128-bit" + ], + "ExpectedArm64ASM": [ + "cmplt p0.s, p6/z, z17.s, #0", + "ld1w {z2.s}, p0/z, [x4]", + "mov v16.16b, v2.16b" + ] + }, + "vmaskmovps ymm0, ymm1, [rax]": { + "ExpectedInstructionCount": 2, + "Optimal": "No", + "Comment": [ + "Map 2 0b01 0x2c 256-bit" + ], + "ExpectedArm64ASM": [ + "cmplt p0.s, p7/z, z17.s, #0", + "ld1w {z16.s}, p0/z, [x4]" + ] + }, + "vmaskmovpd xmm0, xmm1, [rax]": { + "ExpectedInstructionCount": 3, + "Optimal": "No", + "Comment": [ + "Map 2 0b01 0x2d 128-bit" + ], + "ExpectedArm64ASM": [ + "cmplt p0.d, p6/z, z17.d, #0", + "ld1d {z2.d}, p0/z, [x4]", + "mov v16.16b, v2.16b" + ] + }, + "vmaskmovpd ymm0, ymm1, [rax]": { + "ExpectedInstructionCount": 2, + "Optimal": "No", + "Comment": [ + "Map 2 0b01 0x2d 256-bit" + ], + "ExpectedArm64ASM": [ + "cmplt p0.d, p7/z, z17.d, #0", + "ld1d {z16.d}, p0/z, [x4]" + ] + }, + "vmaskmovps [rax], xmm0, xmm1": { + "ExpectedInstructionCount": 2, + "Optimal": "No", + "Comment": [ + "Map 2 0b01 0x2e 128-bit" + ], + "ExpectedArm64ASM": [ + "cmplt p0.s, p6/z, z16.s, #0", + "st1w {z17.s}, p0, [x4]" + ] + }, + "vmaskmovps [rax], ymm0, ymm1": { + "ExpectedInstructionCount": 2, + "Optimal": "No", + "Comment": [ + "Map 2 0b01 0x2e 256-bit" + ], + "ExpectedArm64ASM": [ + "cmplt p0.s, p7/z, z16.s, #0", + "st1w {z17.s}, p0, [x4]" + ] + }, + "vmaskmovpd [rax], xmm0, xmm1": { + "ExpectedInstructionCount": 2, + "Optimal": "No", + "Comment": [ + "Map 2 0b01 0x2f 128-bit" + ], + "ExpectedArm64ASM": [ + "cmplt p0.d, p6/z, z16.d, #0", + "st1d {z17.d}, p0, [x4]" + ] + }, + "vmaskmovpd [rax], ymm0, ymm1": { + "ExpectedInstructionCount": 2, + "Optimal": "No", + "Comment": [ + "Map 2 0b01 0x2f 256-bit" + ], + "ExpectedArm64ASM": [ + "cmplt p0.d, p7/z, z16.d, #0", + "st1d {z17.d}, p0, [x4]" + ] + }, + "vpmaskmovd xmm0, xmm1, [rax]": { + "ExpectedInstructionCount": 3, + "Optimal": "No", + "Comment": [ + "Map 2 0b01 0x8c 128-bit" + ], + "ExpectedArm64ASM": [ + "cmplt p0.s, p6/z, z17.s, #0", + "ld1w {z2.s}, p0/z, [x4]", + "mov v16.16b, v2.16b" + ] + }, + "vpmaskmovd ymm0, ymm1, [rax]": { + "ExpectedInstructionCount": 2, + "Optimal": "No", + "Comment": [ + "Map 2 0b01 0x8c 256-bit" + ], + "ExpectedArm64ASM": [ + "cmplt p0.s, p7/z, z17.s, #0", + "ld1w {z16.s}, p0/z, [x4]" + ] + }, + "vpmaskmovq xmm0, xmm1, [rax]": { + "ExpectedInstructionCount": 3, + "Optimal": "No", + "Comment": [ + "Map 2 0b01 0x8c 128-bit" + ], + "ExpectedArm64ASM": [ + "cmplt p0.d, p6/z, z17.d, #0", + "ld1d {z2.d}, p0/z, [x4]", + "mov v16.16b, v2.16b" + ] + }, + "vpmaskmovq ymm0, ymm1, [rax]": { + "ExpectedInstructionCount": 2, + "Optimal": "No", + "Comment": [ + "Map 2 0b01 0x8c 256-bit" + ], + "ExpectedArm64ASM": [ + "cmplt p0.d, p7/z, z17.d, #0", + "ld1d {z16.d}, p0/z, [x4]" + ] + }, + "vpmaskmovd [rax], xmm0, xmm1": { + "ExpectedInstructionCount": 2, + "Optimal": "No", + "Comment": [ + "Map 2 0b01 0x8e 128-bit" + ], + "ExpectedArm64ASM": [ + "cmplt p0.s, p6/z, z16.s, #0", + "st1w {z17.s}, p0, [x4]" + ] + }, + "vpmaskmovd [rax], ymm0, ymm1": { + "ExpectedInstructionCount": 2, + "Optimal": "No", + "Comment": [ + "Map 2 0b01 0x8e 256-bit" + ], + "ExpectedArm64ASM": [ + "cmplt p0.s, p7/z, z16.s, #0", + "st1w {z17.s}, p0, [x4]" + ] + }, + "vpmaskmovq [rax], xmm0, xmm1": { + "ExpectedInstructionCount": 2, + "Optimal": "No", + "Comment": [ + "Map 2 0b01 0x8e 128-bit" + ], + "ExpectedArm64ASM": [ + "cmplt p0.d, p6/z, z16.d, #0", + "st1d {z17.d}, p0, [x4]" + ] + }, + "vpmaskmovq [rax], ymm0, ymm1": { + "ExpectedInstructionCount": 2, + "Optimal": "No", + "Comment": [ + "Map 2 0b01 0x8e 256-bit" + ], + "ExpectedArm64ASM": [ + "cmplt p0.d, p7/z, z16.d, #0", + "st1d {z17.d}, p0, [x4]" + ] + }, + "andn eax, ebx, ecx": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": [ + "Map 2 0b00 0xf2 32-bit" + ], + "ExpectedArm64ASM": [ + "mov w20, w7", + "mov w21, w5", + "bic w4, w21, w20", + "strb w4, [x28, #706]", + "tst w4, w4", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "andn rax, rbx, rcx": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": [ + "Map 2 0b00 0xf2 64-bit" + ], + "ExpectedArm64ASM": [ + "bic x4, x5, x7", + "strb w4, [x28, #706]", + "tst x4, x4", + "mrs x20, nzcv", + "str w20, [x28, #728]" + ] + }, + "bzhi eax, ebx, ecx": { + "ExpectedInstructionCount": 18, + "Optimal": "No", + "Comment": [ + "Map 2 0b00 0xf5 32-bit" + ], + "ExpectedArm64ASM": [ + "mov w20, w7", + "mov w21, w5", + "and x21, x21, #0xff", + "mov w22, #0xffff", + "movk w22, #0xffff, lsl #16", + "lsl w22, w22, w21", + "bic w22, w20, w22", + "cmp x21, #0x1f (31)", + "csel w4, w20, w22, hi", + "ldr w20, [x28, #728]", + "and w20, w20, #0xefffffff", + "cmp x4, #0x0 (0)", + "cset x22, eq", + "bfi w20, w22, #30, #1", + "cmp x21, #0x1f (31)", + "cset x21, hi", + "bfi w20, w21, #29, #1", + "str w20, [x28, #728]" + ] + }, + "bzhi rax, rbx, rcx": { + "ExpectedInstructionCount": 17, + "Optimal": "No", + "Comment": [ + "Map 2 0b00 0xf5 64-bit" + ], + "ExpectedArm64ASM": [ + "and x20, x5, #0xff", + "mov x21, #0xffffffffffffffff", + "lsl x21, x21, x20", + "bic x21, x7, x21", + "cmp x20, #0x3f (63)", + "csel x4, x7, x21, hi", + "ldr w21, [x28, #728]", + "and w21, w21, #0xefffffff", + "cmp x4, #0x0 (0)", + "cset x22, eq", + "bfi w21, w22, #30, #1", + "cmp x20, #0x3f (63)", + "cset x20, hi", + "mov w0, w21", + "bfi w0, w20, #29, #1", + "mov w20, w0", + "str w20, [x28, #728]" + ] + }, + "pdep eax, ebx, ecx": { + "ExpectedInstructionCount": 25, + "Optimal": "No", + "Comment": [ + "Map 2 0b11 0xf5 32-bit" + ], + "ExpectedArm64ASM": [ + "mov w20, w7", + "mov w21, w5", + "cbz w21, #+0x58", + "mov w3, wzr", + "stp x4, x5, [x28, #8]", + "str x6, [x28, #24]", + "mov w4, w20", + "mov w5, w21", + "mov w6, wzr", + "rbit w0, w5", + "clz w0, w0", + "lsr w1, w4, w3", + "and w1, w1, #0x1", + "sub w2, w5, #0x1 (1)", + "add w3, w3, #0x1 (1)", + "ands w5, w5, w2", + "lsl w0, w1, w0", + "orr w6, w6, w0", + "b.ne #-0x24", + "mov w3, w6", + "ldp x4, x5, [x28, #8]", + "ldr x6, [x28, #24]", + "mov w4, w3", + "b #+0x8", + "mov w4, wzr" + ] + }, + "pdep rax, rbx, rcx": { + "ExpectedInstructionCount": 23, + "Optimal": "No", + "Comment": [ + "Map 2 0b11 0xf5 64-bit" + ], + "ExpectedArm64ASM": [ + "cbz x5, #+0x58", + "mov x3, xzr", + "stp x4, x5, [x28, #8]", + "str x6, [x28, #24]", + "mov x4, x7", + "mov x5, x5", + "mov x6, xzr", + "rbit x0, x5", + "clz x0, x0", + "lsr x1, x4, x3", + "and x1, x1, #0x1", + "sub x2, x5, #0x1 (1)", + "add x3, x3, #0x1 (1)", + "ands x5, x5, x2", + "lsl x0, x1, x0", + "orr x6, x6, x0", + "b.ne #-0x24", + "mov x3, x6", + "ldp x4, x5, [x28, #8]", + "ldr x6, [x28, #24]", + "mov x4, x3", + "b #+0x8", + "mov x4, xzr" + ] + }, + "bextr eax, ebx, ecx": { + "ExpectedInstructionCount": 19, + "Optimal": "No", + "Comment": [ + "Map 2 0b00 0xf7 32-bit" + ], + "ExpectedArm64ASM": [ + "mov w20, w7", + "mov w21, w5", + "mov w22, #0x1f", + "uxtb w23, w21", + "lsr w20, w20, w23", + "mov w24, #0x0", + "cmp w23, #0x1f (31)", + "csel w20, w20, w24, ls", + "ubfx w21, w21, #8, #8", + "cmp w21, #0x1f (31)", + "csel w21, w21, w22, ls", + "mov w22, #0x1", + "lsl w21, w22, w21", + "sub w21, w21, #0x1 (1)", + "and w4, w20, w21", + "cmp x4, #0x0 (0)", + "cset x20, eq", + "lsl x20, x20, #30", + "str w20, [x28, #728]" + ] + }, + "bextr rax, rbx, rcx": { + "ExpectedInstructionCount": 17, + "Optimal": "No", + "Comment": [ + "Map 2 0b00 0xf7 64-bit" + ], + "ExpectedArm64ASM": [ + "mov w20, #0x3f", + "uxtb x21, w5", + "lsr x22, x7, x21", + "mov w23, #0x0", + "cmp x21, #0x3f (63)", + "csel x21, x22, x23, ls", + "ubfx x22, x5, #8, #8", + "cmp x22, #0x3f (63)", + "csel x20, x22, x20, ls", + "mov w22, #0x1", + "lsl x20, x22, x20", + "sub x20, x20, #0x1 (1)", + "and x4, x21, x20", + "cmp x4, #0x0 (0)", + "cset x20, eq", + "lsl x20, x20, #30", + "str w20, [x28, #728]" + ] + } + } +} diff --git a/unittests/InstructionCountCI/FlagM/VEX_map_group.json b/unittests/InstructionCountCI/FlagM/VEX_map_group.json new file mode 100644 index 000000000..916fe6fd3 --- /dev/null +++ b/unittests/InstructionCountCI/FlagM/VEX_map_group.json @@ -0,0 +1,124 @@ +{ + "Features": { + "Bitness": 64, + "EnabledHostFeatures": [ + "SVE256", + "FLAGM", + "FLAGM2" + ], + "DisabledHostFeatures": [] + }, + "Instructions": { + "blsr eax, ebx": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "Map group 17 0b001 32-bit" + ], + "ExpectedArm64ASM": [ + "mov w20, w7", + "sub x21, x20, #0x1 (1)", + "and x21, x21, x20", + "mov w4, w21", + "tst w21, w21", + "mrs x21, nzcv", + "cmp x20, #0x0 (0)", + "cset x20, ne", + "orr w20, w21, w20, lsl #29", + "str w20, [x28, #728]" + ] + }, + "blsr rax, rbx": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": [ + "Map group 17 0b001 64-bit" + ], + "ExpectedArm64ASM": [ + "sub x20, x7, #0x1 (1)", + "and x4, x20, x7", + "tst x4, x4", + "mrs x20, nzcv", + "cmp x7, #0x0 (0)", + "cset x21, ne", + "orr w20, w20, w21, lsl #29", + "str w20, [x28, #728]" + ] + }, + "blsmsk eax, ebx": { + "ExpectedInstructionCount": 13, + "Optimal": "No", + "Comment": [ + "Map group 17 0b010 32-bit" + ], + "ExpectedArm64ASM": [ + "mov w20, w7", + "sub x21, x20, #0x1 (1)", + "eor x21, x21, x20", + "mov w4, w21", + "mov w21, #0x50000000", + "ldr w22, [x28, #728]", + "bic x21, x22, x21", + "cmp x20, #0x0 (0)", + "cset x20, ne", + "mov w0, w21", + "bfi w0, w20, #29, #1", + "mov w20, w0", + "str w20, [x28, #728]" + ] + }, + "blsmsk rax, rbx": { + "ExpectedInstructionCount": 9, + "Optimal": "No", + "Comment": [ + "Map group 17 0b010 64-bit" + ], + "ExpectedArm64ASM": [ + "sub x20, x7, #0x1 (1)", + "eor x4, x20, x7", + "mov w20, #0x50000000", + "ldr w21, [x28, #728]", + "bic x20, x21, x20", + "cmp x7, #0x0 (0)", + "cset x21, ne", + "bfi w20, w21, #29, #1", + "str w20, [x28, #728]" + ] + }, + "blsi eax, ebx": { + "ExpectedInstructionCount": 9, + "Optimal": "No", + "Comment": [ + "Map group 17 0b011 32-bit" + ], + "ExpectedArm64ASM": [ + "mov w20, w7", + "neg w21, w20", + "and w4, w20, w21", + "tst w4, w4", + "mrs x20, nzcv", + "cmp x4, #0x0 (0)", + "cset x21, ne", + "orr w20, w20, w21, lsl #29", + "str w20, [x28, #728]" + ] + }, + "blsi rax, rbx": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": [ + "Map group 17 0b011 64-bit" + ], + "ExpectedArm64ASM": [ + "neg x20, x7", + "and x4, x7, x20", + "tst x4, x4", + "mrs x20, nzcv", + "cmp x4, #0x0 (0)", + "cset x21, ne", + "orr w20, w20, w21, lsl #29", + "str w20, [x28, #728]" + ] + } + } +} diff --git a/unittests/InstructionCountCI/FlagM/x87.json b/unittests/InstructionCountCI/FlagM/x87.json new file mode 100644 index 000000000..3bee5063e --- /dev/null +++ b/unittests/InstructionCountCI/FlagM/x87.json @@ -0,0 +1,23893 @@ +{ + "Features": { + "Bitness": 64, + "EnabledHostFeatures": [ + "FLAGM", + "FLAGM2" + ], + "DisabledHostFeatures": [ + "SVE128", + "SVE256", + "CSSC", + "AFP" + ] + }, + "Instructions": { + "fadd dword [rax]": { + "ExpectedInstructionCount": 99, + "Optimal": "No", + "Comment": [ + "0xd8 !11b /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldr s2, [x4]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "fmov s0, s2", + "ldrh w0, [x28, #1008]", + "ldr x1, [x28, #1144]", + "blr x1", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1384]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fmul dword [rax]": { + "ExpectedInstructionCount": 99, + "Optimal": "No", + "Comment": [ + "0xd8 !11b /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldr s2, [x4]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "fmov s0, s2", + "ldrh w0, [x28, #1008]", + "ldr x1, [x28, #1144]", + "blr x1", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcom dword [rax]": { + "ExpectedInstructionCount": 105, + "Optimal": "No", + "Comment": [ + "0xd8 !11b /2" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldr s2, [x4]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "fmov s0, s2", + "ldrh w0, [x28, #1008]", + "ldr x1, [x28, #1144]", + "blr x1", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1280]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x20, x0", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "strb w21, [x28, #744]", + "mov w21, #0x0", + "strb w21, [x28, #745]", + "strb w20, [x28, #746]", + "strb w22, [x28, #750]" + ] + }, + "fcomp dword [rax]": { + "ExpectedInstructionCount": 113, + "Optimal": "No", + "Comment": [ + "0xd8 !11b /3" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldr s2, [x4]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "fmov s0, s2", + "ldrh w0, [x28, #1008]", + "ldr x1, [x28, #1144]", + "blr x1", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1280]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x21, x0", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "strb w22, [x28, #744]", + "mov w22, #0x0", + "strb w22, [x28, #745]", + "strb w21, [x28, #746]", + "strb w23, [x28, #750]", + "ldrb w21, [x28, #1010]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "fsub dword [rax]": { + "ExpectedInstructionCount": 99, + "Optimal": "No", + "Comment": [ + "0xd8 !11b /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldr s2, [x4]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "fmov s0, s2", + "ldrh w0, [x28, #1008]", + "ldr x1, [x28, #1144]", + "blr x1", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1392]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fsubr dword [rax]": { + "ExpectedInstructionCount": 99, + "Optimal": "No", + "Comment": [ + "0xd8 !11b /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldr s2, [x4]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "fmov s0, s2", + "ldrh w0, [x28, #1008]", + "ldr x1, [x28, #1144]", + "blr x1", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1392]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fdiv dword [rax]": { + "ExpectedInstructionCount": 99, + "Optimal": "No", + "Comment": [ + "0xd8 !11b /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldr s2, [x4]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "fmov s0, s2", + "ldrh w0, [x28, #1008]", + "ldr x1, [x28, #1144]", + "blr x1", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1408]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fdivr dword [rax]": { + "ExpectedInstructionCount": 99, + "Optimal": "No", + "Comment": [ + "0xd8 !11b /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldr s2, [x4]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "fmov s0, s2", + "ldrh w0, [x28, #1008]", + "ldr x1, [x28, #1144]", + "blr x1", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1408]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fadd st0, st0": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xc0 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x0 (0)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1384]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fadd st0, st1": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xc1 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1384]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fadd st0, st2": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xc2 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1384]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fadd st0, st3": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xc3 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1384]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fadd st0, st4": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xc4 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x4 (4)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1384]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fadd st0, st5": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xc5 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x5 (5)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1384]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fadd st0, st6": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xc6 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x6 (6)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1384]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fadd st0, st7": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xc7 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x7 (7)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1384]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fmul st0, st0": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xc8 /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x0 (0)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fmul st0, st1": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xc9 /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fmul st0, st2": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xca /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fmul st0, st3": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xcb /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fmul st0, st4": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xcc /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x4 (4)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fmul st0, st5": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xcd /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x5 (5)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fmul st0, st6": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xce /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x6 (6)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fmul st0, st7": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xcf /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x7 (7)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcom st0, st0": { + "ExpectedInstructionCount": 63, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xd0 /2" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "mov w21, #0x0", + "add w22, w20, #0x0 (0)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1280]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x20, x0", + "ubfx x22, x20, #1, #1", + "ubfx x23, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w22, w22, w20", + "orr w23, w23, w20", + "strb w22, [x28, #744]", + "strb w21, [x28, #745]", + "strb w20, [x28, #746]", + "strb w23, [x28, #750]" + ] + }, + "fcom st0, st1": { + "ExpectedInstructionCount": 63, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xd1 /2" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1280]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x20, x0", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "strb w21, [x28, #744]", + "mov w21, #0x0", + "strb w21, [x28, #745]", + "strb w20, [x28, #746]", + "strb w22, [x28, #750]" + ] + }, + "fcom st0, st2": { + "ExpectedInstructionCount": 63, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xd2 /2" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1280]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x20, x0", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "strb w21, [x28, #744]", + "mov w21, #0x0", + "strb w21, [x28, #745]", + "strb w20, [x28, #746]", + "strb w22, [x28, #750]" + ] + }, + "fcom st0, st3": { + "ExpectedInstructionCount": 63, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xd3 /2" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1280]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x20, x0", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "strb w21, [x28, #744]", + "mov w21, #0x0", + "strb w21, [x28, #745]", + "strb w20, [x28, #746]", + "strb w22, [x28, #750]" + ] + }, + "fcom st0, st4": { + "ExpectedInstructionCount": 63, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xd4 /2" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x4 (4)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1280]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x20, x0", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "strb w21, [x28, #744]", + "mov w21, #0x0", + "strb w21, [x28, #745]", + "strb w20, [x28, #746]", + "strb w22, [x28, #750]" + ] + }, + "fcom st0, st5": { + "ExpectedInstructionCount": 63, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xd5 /2" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x5 (5)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1280]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x20, x0", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "strb w21, [x28, #744]", + "mov w21, #0x0", + "strb w21, [x28, #745]", + "strb w20, [x28, #746]", + "strb w22, [x28, #750]" + ] + }, + "fcom st0, st6": { + "ExpectedInstructionCount": 63, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xd6 /2" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x6 (6)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1280]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x20, x0", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "strb w21, [x28, #744]", + "mov w21, #0x0", + "strb w21, [x28, #745]", + "strb w20, [x28, #746]", + "strb w22, [x28, #750]" + ] + }, + "fcom st0, st7": { + "ExpectedInstructionCount": 63, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xd7 /2" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x7 (7)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1280]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x20, x0", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "strb w21, [x28, #744]", + "mov w21, #0x0", + "strb w21, [x28, #745]", + "strb w20, [x28, #746]", + "strb w22, [x28, #750]" + ] + }, + "fcomp st0, st0": { + "ExpectedInstructionCount": 71, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xd8 /3" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "mov w21, #0x0", + "add w22, w20, #0x0 (0)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1280]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x22, x0", + "ubfx x23, x22, #1, #1", + "ubfx x24, x22, #0, #1", + "ubfx x22, x22, #2, #1", + "orr w23, w23, w22", + "orr w24, w24, w22", + "strb w23, [x28, #744]", + "strb w21, [x28, #745]", + "strb w22, [x28, #746]", + "strb w24, [x28, #750]", + "ldrb w21, [x28, #1010]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "fcomp st0, st1": { + "ExpectedInstructionCount": 71, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xd9 /3" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "mov w21, #0x1", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1280]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x22, x0", + "ubfx x23, x22, #1, #1", + "ubfx x24, x22, #0, #1", + "ubfx x22, x22, #2, #1", + "orr w23, w23, w22", + "orr w24, w24, w22", + "strb w23, [x28, #744]", + "mov w23, #0x0", + "strb w23, [x28, #745]", + "strb w22, [x28, #746]", + "strb w24, [x28, #750]", + "ldrb w22, [x28, #1010]", + "lsl w21, w21, w20", + "bic w21, w22, w21", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "fcomp st0, st2": { + "ExpectedInstructionCount": 71, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xda /3" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1280]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x21, x0", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "strb w22, [x28, #744]", + "mov w22, #0x0", + "strb w22, [x28, #745]", + "strb w21, [x28, #746]", + "strb w23, [x28, #750]", + "ldrb w21, [x28, #1010]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "fcomp st0, st3": { + "ExpectedInstructionCount": 71, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xdb /3" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1280]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x21, x0", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "strb w22, [x28, #744]", + "mov w22, #0x0", + "strb w22, [x28, #745]", + "strb w21, [x28, #746]", + "strb w23, [x28, #750]", + "ldrb w21, [x28, #1010]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "fcomp st0, st4": { + "ExpectedInstructionCount": 71, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xdc /3" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x4 (4)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1280]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x21, x0", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "strb w22, [x28, #744]", + "mov w22, #0x0", + "strb w22, [x28, #745]", + "strb w21, [x28, #746]", + "strb w23, [x28, #750]", + "ldrb w21, [x28, #1010]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "fcomp st0, st5": { + "ExpectedInstructionCount": 71, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xdd /3" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x5 (5)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1280]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x21, x0", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "strb w22, [x28, #744]", + "mov w22, #0x0", + "strb w22, [x28, #745]", + "strb w21, [x28, #746]", + "strb w23, [x28, #750]", + "ldrb w21, [x28, #1010]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "fcomp st0, st6": { + "ExpectedInstructionCount": 71, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xde /3" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x6 (6)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1280]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x21, x0", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "strb w22, [x28, #744]", + "mov w22, #0x0", + "strb w22, [x28, #745]", + "strb w21, [x28, #746]", + "strb w23, [x28, #750]", + "ldrb w21, [x28, #1010]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "fcomp st0, st7": { + "ExpectedInstructionCount": 71, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xdf /3" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x7 (7)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1280]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x21, x0", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "strb w22, [x28, #744]", + "mov w22, #0x0", + "strb w22, [x28, #745]", + "strb w21, [x28, #746]", + "strb w23, [x28, #750]", + "ldrb w21, [x28, #1010]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "fsub st0, st0": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xe0 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x0 (0)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1392]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fsub st0, st1": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xe1 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1392]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fsub st0, st2": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xe2 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1392]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fsub st0, st3": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xe3 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1392]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fsub st0, st4": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xe4 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x4 (4)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1392]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fsub st0, st5": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xe5 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x5 (5)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1392]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fsub st0, st6": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xe6 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x6 (6)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1392]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fsub st0, st7": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xe7 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x7 (7)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1392]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fsubr st0, st0": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xe8 /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x0 (0)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1392]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fsubr st0, st1": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xe9 /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1392]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fsubr st0, st2": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xea /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1392]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fsubr st0, st3": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xeb /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1392]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fsubr st0, st4": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xec /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x4 (4)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1392]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fsubr st0, st5": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xed /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x5 (5)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1392]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fsubr st0, st6": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xee /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x6 (6)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1392]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fsubr st0, st7": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xef /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x7 (7)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1392]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fdiv st0, st0": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xf0 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x0 (0)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1408]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fdiv st0, st1": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xf1 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1408]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fdiv st0, st2": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xf2 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1408]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fdiv st0, st3": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xf3 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1408]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fdiv st0, st4": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xf4 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x4 (4)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1408]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fdiv st0, st5": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xf5 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x5 (5)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1408]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fdiv st0, st6": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xf6 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x6 (6)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1408]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fdiv st0, st7": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xf7 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x7 (7)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1408]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fdivr st0, st0": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xf8 /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x0 (0)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1408]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fdivr st0, st1": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xf9 /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1408]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fdivr st0, st2": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xfa /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1408]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fdivr st0, st3": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xfb /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1408]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fdivr st0, st4": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xfc /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x4 (4)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1408]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fdivr st0, st5": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xfd /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x5 (5)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1408]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fdivr st0, st6": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xfe /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x6 (6)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1408]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fdivr st0, st7": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xff /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x7 (7)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1408]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fld dword [rax]": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "0xd9 !11b /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldr s2, [x4]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "fmov s0, s2", + "ldrh w0, [x28, #1008]", + "ldr x1, [x28, #1144]", + "blr x1", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov w21, #0x1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "ldrb w22, [x28, #1010]", + "lsl w21, w21, w20", + "orr w21, w22, w21", + "strb w21, [x28, #1010]", + "strb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fst dword [rax]": { + "ExpectedInstructionCount": 48, + "Optimal": "No", + "Comment": [ + "0xd9 !11b /2" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1160]", + "blr x3", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "fmov s2, s0", + "str s2, [x4]" + ] + }, + "fstp dword [rax]": { + "ExpectedInstructionCount": 56, + "Optimal": "No", + "Comment": [ + "0xd9 !11b /3" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1160]", + "blr x3", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "fmov s2, s0", + "str s2, [x4]", + "ldrb w21, [x28, #1010]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "fldenv [rax]": { + "ExpectedInstructionCount": 46, + "Optimal": "No", + "Comment": [ + "0xd9 !11b /4" + ], + "ExpectedArm64ASM": [ + "ldrh w20, [x4]", + "strh w20, [x28, #1008]", + "ldr w20, [x4, #4]", + "ubfx w21, w20, #11, #3", + "strb w21, [x28, #747]", + "ubfx w21, w20, #8, #1", + "ubfx w22, w20, #9, #1", + "ubfx w23, w20, #10, #1", + "ubfx w20, w20, #14, #1", + "strb w21, [x28, #744]", + "strb w22, [x28, #745]", + "strb w23, [x28, #746]", + "strb w20, [x28, #750]", + "ldr w20, [x4, #8]", + "ubfx w21, w20, #0, #2", + "cmp x21, #0x3 (3)", + "cset x21, ne", + "ubfx w22, w20, #2, #2", + "cmp x22, #0x3 (3)", + "cset x22, ne", + "orr w21, w21, w22, lsl #1", + "ubfx w22, w20, #4, #2", + "cmp x22, #0x3 (3)", + "cset x22, ne", + "orr w21, w21, w22, lsl #2", + "ubfx w22, w20, #6, #2", + "cmp x22, #0x3 (3)", + "cset x22, ne", + "orr w21, w21, w22, lsl #3", + "ubfx w22, w20, #8, #2", + "cmp x22, #0x3 (3)", + "cset x22, ne", + "orr w21, w21, w22, lsl #4", + "ubfx w22, w20, #10, #2", + "cmp x22, #0x3 (3)", + "cset x22, ne", + "orr w21, w21, w22, lsl #5", + "ubfx w22, w20, #12, #2", + "cmp x22, #0x3 (3)", + "cset x22, ne", + "orr w21, w21, w22, lsl #6", + "ubfx w20, w20, #14, #2", + "cmp x20, #0x3 (3)", + "cset x20, ne", + "orr w20, w21, w20, lsl #7", + "strb w20, [x28, #1010]" + ] + }, + "fldcw [rax]": { + "ExpectedInstructionCount": 2, + "Optimal": "No", + "Comment": [ + "0xd9 !11b /5" + ], + "ExpectedArm64ASM": [ + "ldrh w20, [x4]", + "strh w20, [x28, #1008]" + ] + }, + "fnstenv [rax]": { + "ExpectedInstructionCount": 62, + "Optimal": "No", + "Comment": [ + "0xd9 !11b /6" + ], + "ExpectedArm64ASM": [ + "ldrh w20, [x28, #1008]", + "str w20, [x4]", + "mov w20, #0x0", + "ldrb w21, [x28, #747]", + "mov x0, x20", + "bfi x0, x21, #11, #3", + "mov x21, x0", + "ldrb w22, [x28, #744]", + "ldrb w23, [x28, #745]", + "ldrb w24, [x28, #746]", + "ldrb w25, [x28, #750]", + "orr x21, x21, x22, lsl #8", + "orr x21, x21, x23, lsl #9", + "orr x21, x21, x24, lsl #10", + "orr x21, x21, x25, lsl #14", + "str w21, [x4, #4]", + "ldrb w21, [x28, #1010]", + "and w22, w21, #0x1", + "mov w23, #0x3", + "cmp x22, #0x0 (0)", + "csel x22, x23, x20, eq", + "orr w22, w20, w22", + "lsr w24, w21, #1", + "and w24, w24, #0x1", + "cmp x24, #0x0 (0)", + "csel x24, x23, x20, eq", + "orr w22, w22, w24, lsl #2", + "lsr w24, w21, #2", + "and w24, w24, #0x1", + "cmp x24, #0x0 (0)", + "csel x24, x23, x20, eq", + "orr w22, w22, w24, lsl #4", + "lsr w24, w21, #3", + "and w24, w24, #0x1", + "cmp x24, #0x0 (0)", + "csel x24, x23, x20, eq", + "orr w22, w22, w24, lsl #6", + "lsr w24, w21, #4", + "and w24, w24, #0x1", + "cmp x24, #0x0 (0)", + "csel x24, x23, x20, eq", + "orr w22, w22, w24, lsl #8", + "lsr w24, w21, #5", + "and w24, w24, #0x1", + "cmp x24, #0x0 (0)", + "csel x24, x23, x20, eq", + "orr w22, w22, w24, lsl #10", + "lsr w24, w21, #6", + "and w24, w24, #0x1", + "cmp x24, #0x0 (0)", + "csel x24, x23, x20, eq", + "orr w22, w22, w24, lsl #12", + "lsr w21, w21, #7", + "and w21, w21, #0x1", + "cmp x21, #0x0 (0)", + "csel x21, x23, x20, eq", + "orr w21, w22, w21, lsl #14", + "str w21, [x4, #8]", + "str w20, [x4, #12]", + "str w20, [x4, #16]", + "str w20, [x4, #20]", + "str w20, [x4, #24]" + ] + }, + "fnstcw [rax]": { + "ExpectedInstructionCount": 2, + "Optimal": "Yes", + "Comment": [ + "0xd9 !11b /7" + ], + "ExpectedArm64ASM": [ + "ldrh w20, [x28, #1008]", + "strh w20, [x4]" + ] + }, + "fld st0": { + "ExpectedInstructionCount": 15, + "Optimal": "No", + "Comment": [ + "0xd9 11b 0xc0 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x0 (0)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "mov w21, #0x1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "ldrb w22, [x28, #1010]", + "lsl w21, w21, w20", + "orr w21, w22, w21", + "strb w21, [x28, #1010]", + "strb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fld st1": { + "ExpectedInstructionCount": 15, + "Optimal": "No", + "Comment": [ + "0xd9 11b 0xc1 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "mov w21, #0x1", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q2, [x0, #752]", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "ldrb w22, [x28, #1010]", + "lsl w21, w21, w20", + "orr w21, w22, w21", + "strb w21, [x28, #1010]", + "strb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fld st2": { + "ExpectedInstructionCount": 15, + "Optimal": "No", + "Comment": [ + "0xd9 11b 0xc2 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "mov w21, #0x1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "ldrb w22, [x28, #1010]", + "lsl w21, w21, w20", + "orr w21, w22, w21", + "strb w21, [x28, #1010]", + "strb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fld st3": { + "ExpectedInstructionCount": 15, + "Optimal": "No", + "Comment": [ + "0xd9 11b 0xc3 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "mov w21, #0x1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "ldrb w22, [x28, #1010]", + "lsl w21, w21, w20", + "orr w21, w22, w21", + "strb w21, [x28, #1010]", + "strb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fld st4": { + "ExpectedInstructionCount": 15, + "Optimal": "No", + "Comment": [ + "0xd9 11b 0xc4 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x4 (4)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "mov w21, #0x1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "ldrb w22, [x28, #1010]", + "lsl w21, w21, w20", + "orr w21, w22, w21", + "strb w21, [x28, #1010]", + "strb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fld st5": { + "ExpectedInstructionCount": 15, + "Optimal": "No", + "Comment": [ + "0xd9 11b 0xc5 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x5 (5)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "mov w21, #0x1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "ldrb w22, [x28, #1010]", + "lsl w21, w21, w20", + "orr w21, w22, w21", + "strb w21, [x28, #1010]", + "strb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fld st6": { + "ExpectedInstructionCount": 15, + "Optimal": "No", + "Comment": [ + "0xd9 11b 0xc6 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x6 (6)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "mov w21, #0x1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "ldrb w22, [x28, #1010]", + "lsl w21, w21, w20", + "orr w21, w22, w21", + "strb w21, [x28, #1010]", + "strb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fld st7": { + "ExpectedInstructionCount": 15, + "Optimal": "No", + "Comment": [ + "0xd9 11b 0xc7 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x7 (7)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "mov w21, #0x1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "ldrb w22, [x28, #1010]", + "lsl w21, w21, w20", + "orr w21, w22, w21", + "strb w21, [x28, #1010]", + "strb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fxch st0, st0": { + "ExpectedInstructionCount": 11, + "Optimal": "No", + "Comment": [ + "0xd9 11b 0xc8 /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x0 (0)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x20, lsl #4", + "str q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fxch st0, st1": { + "ExpectedInstructionCount": 11, + "Optimal": "No", + "Comment": [ + "0xd9 11b 0xc9 /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x20, lsl #4", + "str q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fxch st0, st2": { + "ExpectedInstructionCount": 11, + "Optimal": "No", + "Comment": [ + "0xd9 11b 0xca /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x20, lsl #4", + "str q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fxch st0, st3": { + "ExpectedInstructionCount": 11, + "Optimal": "No", + "Comment": [ + "0xd9 11b 0xcb /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x20, lsl #4", + "str q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fxch st0, st4": { + "ExpectedInstructionCount": 11, + "Optimal": "No", + "Comment": [ + "0xd9 11b 0xcc /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x4 (4)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x20, lsl #4", + "str q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fxch st0, st5": { + "ExpectedInstructionCount": 11, + "Optimal": "No", + "Comment": [ + "0xd9 11b 0xcd /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x5 (5)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x20, lsl #4", + "str q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fxch st0, st6": { + "ExpectedInstructionCount": 11, + "Optimal": "No", + "Comment": [ + "0xd9 11b 0xce /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x6 (6)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x20, lsl #4", + "str q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fxch st0, st7": { + "ExpectedInstructionCount": 11, + "Optimal": "No", + "Comment": [ + "0xd9 11b 0xcf /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x7 (7)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x20, lsl #4", + "str q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fnop": { + "ExpectedInstructionCount": 0, + "Optimal": "Yes", + "Comment": [ + "0xd9 11b 0xd0 /2" + ], + "ExpectedArm64ASM": [] + }, + "fchs": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "0xd9 11b 0xe0 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #752]", + "mov w21, #0x0", + "mov w22, #0x8000", + "fmov d3, x21", + "mov v3.d[1], x22", + "eor v2.16b, v2.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fabs": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "0xd9 11b 0xe1 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #752]", + "mov x21, #0xffffffffffffffff", + "mov w22, #0x7fff", + "fmov d3, x21", + "mov v3.d[1], x22", + "and v2.16b, v2.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "ftst": { + "ExpectedInstructionCount": 60, + "Optimal": "No", + "Comment": [ + "0xd9 11b 0xe4 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #752]", + "mov w20, #0x0", + "fmov d3, x20", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1280]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x21, x0", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "strb w22, [x28, #744]", + "strb w20, [x28, #745]", + "strb w21, [x28, #746]", + "strb w23, [x28, #750]" + ] + }, + "fxam": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xd9 11b 0xe5 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #752]", + "mov x21, v2.d[1]", + "ubfx x21, x21, #15, #1", + "strb w21, [x28, #745]", + "ldrb w21, [x28, #1010]", + "lsr w20, w21, w20", + "and w20, w20, #0x1", + "cmp x20, #0x1 (1)", + "cset x21, ne", + "strb w21, [x28, #744]", + "strb w20, [x28, #746]", + "strb w21, [x28, #750]" + ] + }, + "fld1": { + "ExpectedInstructionCount": 15, + "Optimal": "No", + "Comment": [ + "0xd9 11b 0xe8 /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "mov w21, #0x1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "ldrb w22, [x28, #1010]", + "lsl w21, w21, w20", + "orr w21, w22, w21", + "strb w21, [x28, #1010]", + "strb w20, [x28, #747]", + "mov x21, #0x8000000000000000", + "mov w22, #0x3fff", + "fmov d2, x21", + "mov v2.d[1], x22", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fldl2t": { + "ExpectedInstructionCount": 18, + "Optimal": "No", + "Comment": [ + "0xd9 11b 0xe9 /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "mov w21, #0x1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "ldrb w22, [x28, #1010]", + "lsl w21, w21, w20", + "orr w21, w22, w21", + "strb w21, [x28, #1010]", + "strb w20, [x28, #747]", + "mov x21, #0x8afe", + "movk x21, #0xcd1b, lsl #16", + "movk x21, #0x784b, lsl #32", + "movk x21, #0xd49a, lsl #48", + "mov w22, #0x4000", + "fmov d2, x21", + "mov v2.d[1], x22", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fldl2e": { + "ExpectedInstructionCount": 18, + "Optimal": "No", + "Comment": [ + "0xd9 11b 0xea /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "mov w21, #0x1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "ldrb w22, [x28, #1010]", + "lsl w21, w21, w20", + "orr w21, w22, w21", + "strb w21, [x28, #1010]", + "strb w20, [x28, #747]", + "mov x21, #0xf0bc", + "movk x21, #0x5c17, lsl #16", + "movk x21, #0x3b29, lsl #32", + "movk x21, #0xb8aa, lsl #48", + "mov w22, #0x3fff", + "fmov d2, x21", + "mov v2.d[1], x22", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fldpi": { + "ExpectedInstructionCount": 18, + "Optimal": "No", + "Comment": [ + "0xd9 11b 0xeb /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "mov w21, #0x1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "ldrb w22, [x28, #1010]", + "lsl w21, w21, w20", + "orr w21, w22, w21", + "strb w21, [x28, #1010]", + "strb w20, [x28, #747]", + "mov x21, #0xc235", + "movk x21, #0x2168, lsl #16", + "movk x21, #0xdaa2, lsl #32", + "movk x21, #0xc90f, lsl #48", + "mov w22, #0x4000", + "fmov d2, x21", + "mov v2.d[1], x22", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fldlg2": { + "ExpectedInstructionCount": 18, + "Optimal": "No", + "Comment": [ + "0xd9 11b 0xec /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "mov w21, #0x1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "ldrb w22, [x28, #1010]", + "lsl w21, w21, w20", + "orr w21, w22, w21", + "strb w21, [x28, #1010]", + "strb w20, [x28, #747]", + "mov x21, #0xf799", + "movk x21, #0xfbcf, lsl #16", + "movk x21, #0x9a84, lsl #32", + "movk x21, #0x9a20, lsl #48", + "mov w22, #0x3ffd", + "fmov d2, x21", + "mov v2.d[1], x22", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fldln2": { + "ExpectedInstructionCount": 18, + "Optimal": "No", + "Comment": [ + "0xd9 11b 0xed /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "mov w21, #0x1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "ldrb w22, [x28, #1010]", + "lsl w21, w21, w20", + "orr w21, w22, w21", + "strb w21, [x28, #1010]", + "strb w20, [x28, #747]", + "mov x21, #0x79ac", + "movk x21, #0xd1cf, lsl #16", + "movk x21, #0x17f7, lsl #32", + "movk x21, #0xb172, lsl #48", + "mov w22, #0x3ffe", + "fmov d2, x21", + "mov v2.d[1], x22", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fldz": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xd9 11b 0xee /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "mov w21, #0x1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "ldrb w22, [x28, #1010]", + "lsl w21, w21, w20", + "orr w21, w22, w21", + "strb w21, [x28, #1010]", + "strb w20, [x28, #747]", + "mov w21, #0x0", + "fmov d2, x21", + "mov v2.d[1], x21", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "f2xm1": { + "ExpectedInstructionCount": 51, + "Optimal": "No", + "Comment": [ + "0xd9 11b 0xf0 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1312]", + "blr x3", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fyl2x": { + "ExpectedInstructionCount": 63, + "Optimal": "No", + "Comment": [ + "0xd9 11b 0xf1 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldrb w21, [x28, #1010]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1010]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "strb w21, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1416]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fptan": { + "ExpectedInstructionCount": 67, + "Optimal": "No", + "Comment": [ + "0xd9 11b 0xf2 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "mov w21, #0x1", + "sub w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "ldrb w23, [x28, #1010]", + "lsl w21, w21, w22", + "orr w21, w23, w21", + "strb w21, [x28, #1010]", + "strb w22, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1320]", + "blr x3", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov x21, #0x8000000000000000", + "mov w23, #0x3fff", + "fmov d3, x21", + "mov v3.d[1], x23", + "mov w21, #0x0", + "strb w21, [x28, #746]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]", + "add x0, x28, x22, lsl #4", + "str q3, [x0, #752]" + ] + }, + "fpatan": { + "ExpectedInstructionCount": 63, + "Optimal": "No", + "Comment": [ + "0xd9 11b 0xf3 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldrb w21, [x28, #1010]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1010]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "strb w21, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1424]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fxtract": { + "ExpectedInstructionCount": 107, + "Optimal": "No", + "Comment": [ + "0xd9 11b 0xf4 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "mov w21, #0x1", + "sub w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "ldrb w23, [x28, #1010]", + "lsl w21, w21, w22", + "orr w21, w23, w21", + "strb w21, [x28, #1010]", + "strb w22, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1352]", + "blr x3", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1360]", + "blr x3", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q3, [x0, #752]", + "add x0, x28, x22, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fprem1": { + "ExpectedInstructionCount": 59, + "Optimal": "No", + "Comment": [ + "0xd9 11b 0xf5 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1432]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov w21, #0x0", + "strb w21, [x28, #746]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fdecstp": { + "ExpectedInstructionCount": 4, + "Optimal": "Yes", + "Comment": [ + "0xd9 11b 0xf6 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "fincstp": { + "ExpectedInstructionCount": 4, + "Optimal": "Yes", + "Comment": [ + "0xd9 11b 0xf7 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "fprem": { + "ExpectedInstructionCount": 59, + "Optimal": "No", + "Comment": [ + "0xd9 11b 0xf8 /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1440]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov w21, #0x0", + "strb w21, [x28, #746]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fyl2xp1": { + "ExpectedInstructionCount": 115, + "Optimal": "No", + "Comment": [ + "0xd9 11b 0xf9 /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldrb w21, [x28, #1010]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1010]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "strb w21, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #752]", + "mov x20, #0x8000000000000000", + "mov w22, #0x3fff", + "fmov d4, x20", + "mov v4.d[1], x22", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1384]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1416]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fsqrt": { + "ExpectedInstructionCount": 51, + "Optimal": "No", + "Comment": [ + "0xd9 11b 0xfa /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1328]", + "blr x3", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fsincos": { + "ExpectedInstructionCount": 109, + "Optimal": "No", + "Comment": [ + "0xd9 11b 0xfb /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "mov w21, #0x1", + "sub w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "ldrb w23, [x28, #1010]", + "lsl w21, w21, w22", + "orr w21, w23, w21", + "strb w21, [x28, #1010]", + "strb w22, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1336]", + "blr x3", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1344]", + "blr x3", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov w21, #0x0", + "strb w21, [x28, #746]", + "add x0, x28, x20, lsl #4", + "str q3, [x0, #752]", + "add x0, x28, x22, lsl #4", + "str q2, [x0, #752]" + ] + }, + "frndint": { + "ExpectedInstructionCount": 51, + "Optimal": "No", + "Comment": [ + "0xd9 11b 0xfc /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1304]", + "blr x3", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fscale": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "0xd9 11b 0xfd /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1448]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fsin": { + "ExpectedInstructionCount": 53, + "Optimal": "No", + "Comment": [ + "0xd9 11b 0xfe /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1336]", + "blr x3", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov w21, #0x0", + "strb w21, [x28, #746]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcos": { + "ExpectedInstructionCount": 53, + "Optimal": "No", + "Comment": [ + "0xd9 11b 0xff /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1344]", + "blr x3", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov w21, #0x0", + "strb w21, [x28, #746]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fiadd dword [rax]": { + "ExpectedInstructionCount": 99, + "Optimal": "No", + "Comment": [ + "0xda !11b /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldr w21, [x4]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov w1, w21", + "ldr x2, [x28, #1296]", + "blr x2", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1384]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fimul dword [rax]": { + "ExpectedInstructionCount": 99, + "Optimal": "No", + "Comment": [ + "0xda !11b /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldr w21, [x4]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov w1, w21", + "ldr x2, [x28, #1296]", + "blr x2", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "ficom dword [rax]": { + "ExpectedInstructionCount": 105, + "Optimal": "No", + "Comment": [ + "0xda !11b /2" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldr w21, [x4]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov w1, w21", + "ldr x2, [x28, #1296]", + "blr x2", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1280]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x20, x0", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "strb w21, [x28, #744]", + "mov w21, #0x0", + "strb w21, [x28, #745]", + "strb w20, [x28, #746]", + "strb w22, [x28, #750]" + ] + }, + "ficomp dword [rax]": { + "ExpectedInstructionCount": 113, + "Optimal": "No", + "Comment": [ + "0xda !11b /3" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldr w21, [x4]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov w1, w21", + "ldr x2, [x28, #1296]", + "blr x2", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1280]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x21, x0", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "strb w22, [x28, #744]", + "mov w22, #0x0", + "strb w22, [x28, #745]", + "strb w21, [x28, #746]", + "strb w23, [x28, #750]", + "ldrb w21, [x28, #1010]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "fisub dword [rax]": { + "ExpectedInstructionCount": 99, + "Optimal": "No", + "Comment": [ + "0xda !11b /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldr w21, [x4]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov w1, w21", + "ldr x2, [x28, #1296]", + "blr x2", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1392]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fisubr dword [rax]": { + "ExpectedInstructionCount": 99, + "Optimal": "No", + "Comment": [ + "0xda !11b /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldr w21, [x4]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov w1, w21", + "ldr x2, [x28, #1296]", + "blr x2", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1392]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fidiv dword [rax]": { + "ExpectedInstructionCount": 99, + "Optimal": "No", + "Comment": [ + "0xda !11b /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldr w21, [x4]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov w1, w21", + "ldr x2, [x28, #1296]", + "blr x2", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1408]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fidivr dword [rax]": { + "ExpectedInstructionCount": 99, + "Optimal": "No", + "Comment": [ + "0xda !11b /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldr w21, [x4]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov w1, w21", + "ldr x2, [x28, #1296]", + "blr x2", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1408]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovb st0, st0": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xda 11b 0xc0 /0" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x20000000", + "csetm x20, ne", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x0 (0)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovb st0, st1": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xda 11b 0xc1 /0" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x20000000", + "csetm x20, ne", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovb st0, st2": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xda 11b 0xc2 /0" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x20000000", + "csetm x20, ne", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovb st0, st3": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xda 11b 0xc3 /0" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x20000000", + "csetm x20, ne", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovb st0, st4": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xda 11b 0xc4 /0" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x20000000", + "csetm x20, ne", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x4 (4)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovb st0, st5": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xda 11b 0xc5 /0" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x20000000", + "csetm x20, ne", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x5 (5)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovb st0, st6": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xda 11b 0xc6 /0" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x20000000", + "csetm x20, ne", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x6 (6)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovb st0, st7": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xda 11b 0xc7 /0" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x20000000", + "csetm x20, ne", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x7 (7)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmove st0, st0": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xda 11b 0xc8 /1" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x40000000", + "csetm x20, ne", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x0 (0)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmove st0, st1": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xda 11b 0xc9 /1" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x40000000", + "csetm x20, ne", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmove st0, st2": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xda 11b 0xca /1" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x40000000", + "csetm x20, ne", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmove st0, st3": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xda 11b 0xcb /1" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x40000000", + "csetm x20, ne", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmove st0, st4": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xda 11b 0xcc /1" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x40000000", + "csetm x20, ne", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x4 (4)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmove st0, st5": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xda 11b 0xcd /1" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x40000000", + "csetm x20, ne", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x5 (5)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmove st0, st6": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xda 11b 0xce /1" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x40000000", + "csetm x20, ne", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x6 (6)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmove st0, st7": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xda 11b 0xcf /1" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x40000000", + "csetm x20, ne", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x7 (7)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovbe st0, st0": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xda 11b 0xd0 /0" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x60000000", + "csetm x20, ne", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x0 (0)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovbe st0, st1": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xda 11b 0xd1 /0" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x60000000", + "csetm x20, ne", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovbe st0, st2": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xda 11b 0xd2 /0" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x60000000", + "csetm x20, ne", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovbe st0, st3": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xda 11b 0xd3 /0" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x60000000", + "csetm x20, ne", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovbe st0, st4": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xda 11b 0xd4 /0" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x60000000", + "csetm x20, ne", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x4 (4)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovbe st0, st5": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xda 11b 0xd5 /0" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x60000000", + "csetm x20, ne", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x5 (5)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovbe st0, st6": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xda 11b 0xd6 /0" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x60000000", + "csetm x20, ne", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x6 (6)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovbe st0, st7": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xda 11b 0xd7 /0" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x60000000", + "csetm x20, ne", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x7 (7)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovu st0, st0": { + "ExpectedInstructionCount": 17, + "Optimal": "No", + "Comment": [ + "0xda 11b 0xd8 /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #706]", + "fmov s2, w20", + "cnt v2.16b, v2.16b", + "umov w20, v2.b[0]", + "tst w20, #0x1", + "csetm x20, eq", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x0 (0)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovu st0, st1": { + "ExpectedInstructionCount": 17, + "Optimal": "No", + "Comment": [ + "0xda 11b 0xd9 /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #706]", + "fmov s2, w20", + "cnt v2.16b, v2.16b", + "umov w20, v2.b[0]", + "tst w20, #0x1", + "csetm x20, eq", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovu st0, st2": { + "ExpectedInstructionCount": 17, + "Optimal": "No", + "Comment": [ + "0xda 11b 0xda /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #706]", + "fmov s2, w20", + "cnt v2.16b, v2.16b", + "umov w20, v2.b[0]", + "tst w20, #0x1", + "csetm x20, eq", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovu st0, st3": { + "ExpectedInstructionCount": 17, + "Optimal": "No", + "Comment": [ + "0xda 11b 0xdb /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #706]", + "fmov s2, w20", + "cnt v2.16b, v2.16b", + "umov w20, v2.b[0]", + "tst w20, #0x1", + "csetm x20, eq", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovu st0, st4": { + "ExpectedInstructionCount": 17, + "Optimal": "No", + "Comment": [ + "0xda 11b 0xdc /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #706]", + "fmov s2, w20", + "cnt v2.16b, v2.16b", + "umov w20, v2.b[0]", + "tst w20, #0x1", + "csetm x20, eq", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x4 (4)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovu st0, st5": { + "ExpectedInstructionCount": 17, + "Optimal": "No", + "Comment": [ + "0xda 11b 0xdd /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #706]", + "fmov s2, w20", + "cnt v2.16b, v2.16b", + "umov w20, v2.b[0]", + "tst w20, #0x1", + "csetm x20, eq", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x5 (5)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovu st0, st6": { + "ExpectedInstructionCount": 17, + "Optimal": "No", + "Comment": [ + "0xda 11b 0xde /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #706]", + "fmov s2, w20", + "cnt v2.16b, v2.16b", + "umov w20, v2.b[0]", + "tst w20, #0x1", + "csetm x20, eq", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x6 (6)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovu st0, st7": { + "ExpectedInstructionCount": 17, + "Optimal": "No", + "Comment": [ + "0xda 11b 0xdf /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #706]", + "fmov s2, w20", + "cnt v2.16b, v2.16b", + "umov w20, v2.b[0]", + "tst w20, #0x1", + "csetm x20, eq", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x7 (7)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fucompp": { + "ExpectedInstructionCount": 76, + "Optimal": "No", + "Comment": [ + "0xda 11b 0xe9 /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "mov w21, #0x1", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1280]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x22, x0", + "ubfx x23, x22, #1, #1", + "ubfx x24, x22, #0, #1", + "ubfx x22, x22, #2, #1", + "orr w23, w23, w22", + "orr w24, w24, w22", + "strb w23, [x28, #744]", + "mov w23, #0x0", + "strb w23, [x28, #745]", + "strb w22, [x28, #746]", + "strb w24, [x28, #750]", + "ldrb w22, [x28, #1010]", + "lsl w23, w21, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "lsl w21, w21, w20", + "bic w21, w22, w21", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "fild dword [rax]": { + "ExpectedInstructionCount": 33, + "Optimal": "No", + "Comment": [ + "0xdf !11b /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "mov w21, #0x1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "ldrb w22, [x28, #1010]", + "lsl w21, w21, w20", + "orr w21, w22, w21", + "strb w21, [x28, #1010]", + "strb w20, [x28, #747]", + "ldr w21, [x4]", + "mov w22, #0x0", + "sxtw x21, w21", + "mov w23, #0x8000", + "cmp x21, #0x0 (0)", + "csel x23, x23, x22, lt", + "cmp x21, #0x0 (0)", + "cneg x21, x21, mi", + "mov w24, #0x3f", + "mov x0, #0x3f", + "clz x25, x21", + "sub x25, x0, x25", + "sub x24, x24, x25", + "lsl x25, x21, x24", + "mov w26, #0x403e", + "sub x24, x26, x24", + "cmp x21, #0x0 (0)", + "csel x21, x22, x24, eq", + "orr x21, x23, x21", + "fmov d2, x25", + "fmov d3, x21", + "mov v2.d[1], v3.d[0]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fisttp dword [rax]": { + "ExpectedInstructionCount": 56, + "Optimal": "No", + "Comment": [ + "0xdb !11b /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1208]", + "blr x3", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov w21, w0", + "str w21, [x4]", + "ldrb w21, [x28, #1010]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "fist dword [rax]": { + "ExpectedInstructionCount": 48, + "Optimal": "No", + "Comment": [ + "0xdb !11b /2" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1184]", + "blr x3", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov w20, w0", + "str w20, [x4]" + ] + }, + "fistp dword [rax]": { + "ExpectedInstructionCount": 56, + "Optimal": "No", + "Comment": [ + "0xdf !11b /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1184]", + "blr x3", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov w21, w0", + "str w21, [x4]", + "ldrb w21, [x28, #1010]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "fld tword [rax]": { + "ExpectedInstructionCount": 12, + "Optimal": "No", + "Comment": [ + "0xdb !11b /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldr q2, [x4]", + "mov w21, #0x1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "ldrb w22, [x28, #1010]", + "lsl w21, w21, w20", + "orr w21, w22, w21", + "strb w21, [x28, #1010]", + "strb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fstp tword [rax]": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xdb !11b /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #752]", + "str d2, [x4]", + "mov x21, v2.d[1]", + "strh w21, [x4, #8]", + "ldrb w21, [x28, #1010]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "fcmovnb st0, st0": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xc0 /0" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x20000000", + "csetm x20, eq", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x0 (0)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovnb st0, st1": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xc1 /0" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x20000000", + "csetm x20, eq", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovnb st0, st2": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xc2 /0" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x20000000", + "csetm x20, eq", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovnb st0, st3": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xc3 /0" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x20000000", + "csetm x20, eq", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovnb st0, st4": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xc4 /0" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x20000000", + "csetm x20, eq", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x4 (4)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovnb st0, st5": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xc5 /0" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x20000000", + "csetm x20, eq", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x5 (5)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovnb st0, st6": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xc6 /0" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x20000000", + "csetm x20, eq", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x6 (6)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovnb st0, st7": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xc7 /0" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x20000000", + "csetm x20, eq", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x7 (7)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovne st0, st0": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xc8 /1" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x40000000", + "csetm x20, eq", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x0 (0)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovne st0, st1": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xc9 /1" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x40000000", + "csetm x20, eq", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovne st0, st2": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xca /1" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x40000000", + "csetm x20, eq", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovne st0, st3": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xcb /1" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x40000000", + "csetm x20, eq", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovne st0, st4": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xcc /1" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x40000000", + "csetm x20, eq", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x4 (4)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovne st0, st5": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xcd /1" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x40000000", + "csetm x20, eq", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x5 (5)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovne st0, st6": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xce /1" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x40000000", + "csetm x20, eq", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x6 (6)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovne st0, st7": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xcf /1" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x40000000", + "csetm x20, eq", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x7 (7)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovnbe st0, st0": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xd0 /2" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x60000000", + "csetm x20, eq", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x0 (0)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovnbe st0, st1": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xd1 /2" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x60000000", + "csetm x20, eq", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovnbe st0, st2": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xd2 /2" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x60000000", + "csetm x20, eq", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovnbe st0, st3": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xd3 /2" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x60000000", + "csetm x20, eq", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovnbe st0, st4": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xd4 /2" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x60000000", + "csetm x20, eq", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x4 (4)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovnbe st0, st5": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xd5 /2" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x60000000", + "csetm x20, eq", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x5 (5)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovnbe st0, st6": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xd6 /2" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x60000000", + "csetm x20, eq", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x6 (6)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovnbe st0, st7": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xd7 /2" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x60000000", + "csetm x20, eq", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x7 (7)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovnu st0, st0": { + "ExpectedInstructionCount": 17, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xd8 /3" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #706]", + "fmov s2, w20", + "cnt v2.16b, v2.16b", + "umov w20, v2.b[0]", + "tst w20, #0x1", + "csetm x20, ne", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x0 (0)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovnu st0, st1": { + "ExpectedInstructionCount": 17, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xd9 /3" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #706]", + "fmov s2, w20", + "cnt v2.16b, v2.16b", + "umov w20, v2.b[0]", + "tst w20, #0x1", + "csetm x20, ne", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovnu st0, st2": { + "ExpectedInstructionCount": 17, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xda /3" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #706]", + "fmov s2, w20", + "cnt v2.16b, v2.16b", + "umov w20, v2.b[0]", + "tst w20, #0x1", + "csetm x20, ne", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovnu st0, st3": { + "ExpectedInstructionCount": 17, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xdb /3" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #706]", + "fmov s2, w20", + "cnt v2.16b, v2.16b", + "umov w20, v2.b[0]", + "tst w20, #0x1", + "csetm x20, ne", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovnu st0, st4": { + "ExpectedInstructionCount": 17, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xdc /3" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #706]", + "fmov s2, w20", + "cnt v2.16b, v2.16b", + "umov w20, v2.b[0]", + "tst w20, #0x1", + "csetm x20, ne", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x4 (4)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovnu st0, st5": { + "ExpectedInstructionCount": 17, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xdd /3" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #706]", + "fmov s2, w20", + "cnt v2.16b, v2.16b", + "umov w20, v2.b[0]", + "tst w20, #0x1", + "csetm x20, ne", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x5 (5)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovnu st0, st6": { + "ExpectedInstructionCount": 17, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xde /3" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #706]", + "fmov s2, w20", + "cnt v2.16b, v2.16b", + "umov w20, v2.b[0]", + "tst w20, #0x1", + "csetm x20, ne", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x6 (6)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovnu st0, st7": { + "ExpectedInstructionCount": 17, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xdf /3" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #706]", + "fmov s2, w20", + "cnt v2.16b, v2.16b", + "umov w20, v2.b[0]", + "tst w20, #0x1", + "csetm x20, ne", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x7 (7)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fnclex": { + "ExpectedInstructionCount": 0, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xe2 /4" + ], + "ExpectedArm64ASM": [] + }, + "fninit": { + "ExpectedInstructionCount": 9, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xe3 /4" + ], + "ExpectedArm64ASM": [ + "mov w20, #0x0", + "mov w21, #0x37f", + "strh w21, [x28, #1008]", + "strb w20, [x28, #747]", + "strb w20, [x28, #744]", + "strb w20, [x28, #745]", + "strb w20, [x28, #746]", + "strb w20, [x28, #750]", + "strb w20, [x28, #1010]" + ] + }, + "fucomi st0, st0": { + "ExpectedInstructionCount": 63, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xe8 /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x0 (0)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1280]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x20, x0", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "lsl x21, x21, #29", + "orr w21, w21, w22, lsl #30", + "eor w20, w20, #0x1", + "strb w20, [x28, #706]", + "str w21, [x28, #728]" + ] + }, + "fucomi st0, st1": { + "ExpectedInstructionCount": 63, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xe9 /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1280]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x20, x0", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "lsl x21, x21, #29", + "orr w21, w21, w22, lsl #30", + "eor w20, w20, #0x1", + "strb w20, [x28, #706]", + "str w21, [x28, #728]" + ] + }, + "fucomi st0, st2": { + "ExpectedInstructionCount": 63, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xea /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1280]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x20, x0", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "lsl x21, x21, #29", + "orr w21, w21, w22, lsl #30", + "eor w20, w20, #0x1", + "strb w20, [x28, #706]", + "str w21, [x28, #728]" + ] + }, + "fucomi st0, st3": { + "ExpectedInstructionCount": 63, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xeb /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1280]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x20, x0", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "lsl x21, x21, #29", + "orr w21, w21, w22, lsl #30", + "eor w20, w20, #0x1", + "strb w20, [x28, #706]", + "str w21, [x28, #728]" + ] + }, + "fucomi st0, st4": { + "ExpectedInstructionCount": 63, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xec /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x4 (4)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1280]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x20, x0", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "lsl x21, x21, #29", + "orr w21, w21, w22, lsl #30", + "eor w20, w20, #0x1", + "strb w20, [x28, #706]", + "str w21, [x28, #728]" + ] + }, + "fucomi st0, st5": { + "ExpectedInstructionCount": 63, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xed /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x5 (5)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1280]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x20, x0", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "lsl x21, x21, #29", + "orr w21, w21, w22, lsl #30", + "eor w20, w20, #0x1", + "strb w20, [x28, #706]", + "str w21, [x28, #728]" + ] + }, + "fucomi st0, st6": { + "ExpectedInstructionCount": 63, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xee /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x6 (6)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1280]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x20, x0", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "lsl x21, x21, #29", + "orr w21, w21, w22, lsl #30", + "eor w20, w20, #0x1", + "strb w20, [x28, #706]", + "str w21, [x28, #728]" + ] + }, + "fucomi st0, st7": { + "ExpectedInstructionCount": 63, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xef /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x7 (7)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1280]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x20, x0", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "lsl x21, x21, #29", + "orr w21, w21, w22, lsl #30", + "eor w20, w20, #0x1", + "strb w20, [x28, #706]", + "str w21, [x28, #728]" + ] + }, + "fcomi st0, st0": { + "ExpectedInstructionCount": 63, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xf0 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x0 (0)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1280]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x20, x0", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "lsl x21, x21, #29", + "orr w21, w21, w22, lsl #30", + "eor w20, w20, #0x1", + "strb w20, [x28, #706]", + "str w21, [x28, #728]" + ] + }, + "fcomi st0, st1": { + "ExpectedInstructionCount": 63, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xf1 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1280]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x20, x0", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "lsl x21, x21, #29", + "orr w21, w21, w22, lsl #30", + "eor w20, w20, #0x1", + "strb w20, [x28, #706]", + "str w21, [x28, #728]" + ] + }, + "fcomi st0, st2": { + "ExpectedInstructionCount": 63, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xf2 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1280]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x20, x0", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "lsl x21, x21, #29", + "orr w21, w21, w22, lsl #30", + "eor w20, w20, #0x1", + "strb w20, [x28, #706]", + "str w21, [x28, #728]" + ] + }, + "fcomi st0, st3": { + "ExpectedInstructionCount": 63, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xf3 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1280]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x20, x0", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "lsl x21, x21, #29", + "orr w21, w21, w22, lsl #30", + "eor w20, w20, #0x1", + "strb w20, [x28, #706]", + "str w21, [x28, #728]" + ] + }, + "fcomi st0, st4": { + "ExpectedInstructionCount": 63, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xf4 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x4 (4)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1280]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x20, x0", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "lsl x21, x21, #29", + "orr w21, w21, w22, lsl #30", + "eor w20, w20, #0x1", + "strb w20, [x28, #706]", + "str w21, [x28, #728]" + ] + }, + "fcomi st0, st5": { + "ExpectedInstructionCount": 63, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xf5 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x5 (5)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1280]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x20, x0", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "lsl x21, x21, #29", + "orr w21, w21, w22, lsl #30", + "eor w20, w20, #0x1", + "strb w20, [x28, #706]", + "str w21, [x28, #728]" + ] + }, + "fcomi st0, st6": { + "ExpectedInstructionCount": 63, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xf6 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x6 (6)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1280]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x20, x0", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "lsl x21, x21, #29", + "orr w21, w21, w22, lsl #30", + "eor w20, w20, #0x1", + "strb w20, [x28, #706]", + "str w21, [x28, #728]" + ] + }, + "fcomi st0, st7": { + "ExpectedInstructionCount": 63, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xf7 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x7 (7)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1280]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x20, x0", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "lsl x21, x21, #29", + "orr w21, w21, w22, lsl #30", + "eor w20, w20, #0x1", + "strb w20, [x28, #706]", + "str w21, [x28, #728]" + ] + }, + "fadd qword [rax]": { + "ExpectedInstructionCount": 99, + "Optimal": "No", + "Comment": [ + "0xdc !11b /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldr d2, [x4]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov v0.8b, v2.8b", + "ldrh w0, [x28, #1008]", + "ldr x1, [x28, #1152]", + "blr x1", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1384]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fmul qword [rax]": { + "ExpectedInstructionCount": 99, + "Optimal": "No", + "Comment": [ + "0xdc !11b /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldr d2, [x4]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov v0.8b, v2.8b", + "ldrh w0, [x28, #1008]", + "ldr x1, [x28, #1152]", + "blr x1", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcom qword [rax]": { + "ExpectedInstructionCount": 105, + "Optimal": "No", + "Comment": [ + "0xdc !11b /2" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldr d2, [x4]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov v0.8b, v2.8b", + "ldrh w0, [x28, #1008]", + "ldr x1, [x28, #1152]", + "blr x1", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1280]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x20, x0", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "strb w21, [x28, #744]", + "mov w21, #0x0", + "strb w21, [x28, #745]", + "strb w20, [x28, #746]", + "strb w22, [x28, #750]" + ] + }, + "fcomp qword [rax]": { + "ExpectedInstructionCount": 113, + "Optimal": "No", + "Comment": [ + "0xdc !11b /3" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldr d2, [x4]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov v0.8b, v2.8b", + "ldrh w0, [x28, #1008]", + "ldr x1, [x28, #1152]", + "blr x1", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1280]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x21, x0", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "strb w22, [x28, #744]", + "mov w22, #0x0", + "strb w22, [x28, #745]", + "strb w21, [x28, #746]", + "strb w23, [x28, #750]", + "ldrb w21, [x28, #1010]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "fsub qword [rax]": { + "ExpectedInstructionCount": 99, + "Optimal": "No", + "Comment": [ + "0xdc !11b /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldr d2, [x4]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov v0.8b, v2.8b", + "ldrh w0, [x28, #1008]", + "ldr x1, [x28, #1152]", + "blr x1", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1392]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fsubr qword [rax]": { + "ExpectedInstructionCount": 99, + "Optimal": "No", + "Comment": [ + "0xdc !11b /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldr d2, [x4]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov v0.8b, v2.8b", + "ldrh w0, [x28, #1008]", + "ldr x1, [x28, #1152]", + "blr x1", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1392]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fdiv qword [rax]": { + "ExpectedInstructionCount": 99, + "Optimal": "No", + "Comment": [ + "0xdc !11b /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldr d2, [x4]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov v0.8b, v2.8b", + "ldrh w0, [x28, #1008]", + "ldr x1, [x28, #1152]", + "blr x1", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1408]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fdivr qword [rax]": { + "ExpectedInstructionCount": 99, + "Optimal": "No", + "Comment": [ + "0xdc !11b /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldr d2, [x4]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov v0.8b, v2.8b", + "ldrh w0, [x28, #1008]", + "ldr x1, [x28, #1152]", + "blr x1", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1408]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "db 0xdc, 0xc0": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "fadd st0, st0", + "Needs manual encoding since otherwise nasm will emit the 0xd8 variant.", + "0xdc 11b 0xc0 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x0 (0)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1384]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fadd st1, st0": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "0xdc 11b 0xc1 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1384]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fadd st2, st0": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "0xdc 11b 0xc2 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1384]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fadd st3, st0": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "0xdc 11b 0xc3 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1384]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fadd st4, st0": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "0xdc 11b 0xc4 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x4 (4)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1384]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fadd st5, st0": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "0xdc 11b 0xc5 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x5 (5)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1384]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fadd st6, st0": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "0xdc 11b 0xc6 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x6 (6)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1384]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fadd st7, st0": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "0xdc 11b 0xc7 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x7 (7)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1384]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "db 0xdc, 0xc8": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "fmul st0, st0", + "Needs manual encoding since otherwise nasm will emit the 0xd8 variant.", + "0xdc 11b 0xc8 /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x0 (0)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fmul st1, st0": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "0xdc 11b 0xc9 /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fmul st2, st0": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "0xdc 11b 0xca /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fmul st3, st0": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "0xdc 11b 0xcb /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fmul st4, st0": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "0xdc 11b 0xcc /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x4 (4)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fmul st5, st0": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "0xdc 11b 0xcd /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x5 (5)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fmul st6, st0": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "0xdc 11b 0xce /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x6 (6)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fmul st7, st0": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "0xdc 11b 0xcf /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x7 (7)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "db 0xdc, 0xe0": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "fsubr st0, st0", + "Needs manual encoding since otherwise nasm will emit the 0xd8 variant.", + "0xdc 11b 0xe0 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x0 (0)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1392]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fsubr st1, st0": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "0xdc 11b 0xe1 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1392]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fsubr st2, st0": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "0xdc 11b 0xe2 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1392]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fsubr st3, st0": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "0xdc 11b 0xe3 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1392]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fsubr st4, st0": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "0xdc 11b 0xe4 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x4 (4)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1392]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fsubr st5, st0": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "0xdc 11b 0xe5 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x5 (5)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1392]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fsubr st6, st0": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "0xdc 11b 0xe6 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x6 (6)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1392]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fsubr st7, st0": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "0xdc 11b 0xe7 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x7 (7)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1392]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "db 0xdc, 0xe8": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "fsub st0, st0", + "Needs manual encoding since otherwise nasm will emit the 0xd8 variant.", + "0xdc 11b 0xe8 /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x0 (0)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1392]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fsub st1, st0": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "0xdc 11b 0xe9 /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1392]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fsub st2, st0": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "0xdc 11b 0xea /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1392]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fsub st3, st0": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "0xdc 11b 0xeb /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1392]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fsub st4, st0": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "0xdc 11b 0xec /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x4 (4)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1392]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fsub st5, st0": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "0xdc 11b 0xed /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x5 (5)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1392]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fsub st6, st0": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "0xdc 11b 0xee /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x6 (6)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1392]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fsub st7, st0": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "0xdc 11b 0xef /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x7 (7)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1392]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "db 0xdc, 0xf0": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "fdivr st0, st0", + "Needs manual encoding since otherwise nasm will emit the 0xd8 variant.", + "0xdc 11b 0xf0 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x0 (0)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1408]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fdivr st1, st0": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "0xdc 11b 0xf1 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1408]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fdivr st2, st0": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "0xdc 11b 0xf2 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1408]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fdivr st3, st0": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "0xdc 11b 0xf3 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1408]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fdivr st4, st0": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "0xdc 11b 0xf4 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x4 (4)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1408]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fdivr st5, st0": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "0xdc 11b 0xf5 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x5 (5)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1408]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fdivr st6, st0": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "0xdc 11b 0xf6 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x6 (6)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1408]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fdivr st7, st0": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "0xdc 11b 0xf7 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x7 (7)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1408]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "db 0xdc, 0xf8": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "fdiv st0, st0", + "Needs manual encoding since otherwise nasm will emit the 0xd8 variant.", + "0xdc 11b 0xf8 /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x0 (0)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1408]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fdiv st1, st0": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "0xdc 11b 0xf9 /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1408]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fdiv st2, st0": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "0xdc 11b 0xfa /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1408]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fdiv st3, st0": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "0xdc 11b 0xfb /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1408]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fdiv st4, st0": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "0xdc 11b 0xfc /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x4 (4)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1408]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fdiv st5, st0": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "0xdc 11b 0xfd /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x5 (5)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1408]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fdiv st6, st0": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "0xdc 11b 0xfe /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x6 (6)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1408]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fdiv st7, st0": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "0xdc 11b 0xff /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x7 (7)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1408]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fld qword [rax]": { + "ExpectedInstructionCount": 57, + "Optimal": "No", + "Comment": [ + "0xdd !11b /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldr d2, [x4]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov v0.8b, v2.8b", + "ldrh w0, [x28, #1008]", + "ldr x1, [x28, #1152]", + "blr x1", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov w21, #0x1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "ldrb w22, [x28, #1010]", + "lsl w21, w21, w20", + "orr w21, w22, w21", + "strb w21, [x28, #1010]", + "strb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fisttp qword [rax]": { + "ExpectedInstructionCount": 56, + "Optimal": "No", + "Comment": [ + "0xdd !11b /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1216]", + "blr x3", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x21, x0", + "str x21, [x4]", + "ldrb w21, [x28, #1010]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "fst qword [rax]": { + "ExpectedInstructionCount": 48, + "Optimal": "No", + "Comment": [ + "0xdd !11b /2" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1168]", + "blr x3", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov v2.8b, v0.8b", + "str d2, [x4]" + ] + }, + "fstp qword [rax]": { + "ExpectedInstructionCount": 56, + "Optimal": "No", + "Comment": [ + "0xdd !11b /3" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1168]", + "blr x3", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov v2.8b, v0.8b", + "str d2, [x4]", + "ldrb w21, [x28, #1010]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "frstor [rax]": { + "ExpectedInstructionCount": 105, + "Optimal": "No", + "Comment": [ + "0xdd !11b /4" + ], + "ExpectedArm64ASM": [ + "ldrh w20, [x4]", + "strh w20, [x28, #1008]", + "ldr w20, [x4, #4]", + "ubfx w21, w20, #11, #3", + "strb w21, [x28, #747]", + "ubfx w22, w20, #8, #1", + "ubfx w23, w20, #9, #1", + "ubfx w24, w20, #10, #1", + "ubfx w20, w20, #14, #1", + "strb w22, [x28, #744]", + "strb w23, [x28, #745]", + "strb w24, [x28, #746]", + "strb w20, [x28, #750]", + "ldr w20, [x4, #8]", + "ubfx w22, w20, #0, #2", + "cmp x22, #0x3 (3)", + "cset x22, ne", + "ubfx w23, w20, #2, #2", + "cmp x23, #0x3 (3)", + "cset x23, ne", + "orr w22, w22, w23, lsl #1", + "ubfx w23, w20, #4, #2", + "cmp x23, #0x3 (3)", + "cset x23, ne", + "orr w22, w22, w23, lsl #2", + "ubfx w23, w20, #6, #2", + "cmp x23, #0x3 (3)", + "cset x23, ne", + "orr w22, w22, w23, lsl #3", + "ubfx w23, w20, #8, #2", + "cmp x23, #0x3 (3)", + "cset x23, ne", + "orr w22, w22, w23, lsl #4", + "ubfx w23, w20, #10, #2", + "cmp x23, #0x3 (3)", + "cset x23, ne", + "orr w22, w22, w23, lsl #5", + "ubfx w23, w20, #12, #2", + "cmp x23, #0x3 (3)", + "cset x23, ne", + "orr w22, w22, w23, lsl #6", + "ubfx w20, w20, #14, #2", + "cmp x20, #0x3 (3)", + "cset x20, ne", + "orr w20, w22, w20, lsl #7", + "strb w20, [x28, #1010]", + "add x20, x4, #0x1c (28)", + "mov x22, #0xffffffffffffffff", + "mov w23, #0xffff", + "fmov d2, x22", + "mov v2.d[1], x23", + "ldur q3, [x4, #28]", + "and v3.16b, v3.16b, v2.16b", + "add x0, x28, x21, lsl #4", + "str q3, [x0, #752]", + "add x22, x20, #0xa (10)", + "add w21, w21, #0x1 (1)", + "and w21, w21, #0x7", + "ldur q3, [x20, #10]", + "and v3.16b, v3.16b, v2.16b", + "add x0, x28, x21, lsl #4", + "str q3, [x0, #752]", + "add x20, x22, #0xa (10)", + "add w21, w21, #0x1 (1)", + "and w21, w21, #0x7", + "ldur q3, [x22, #10]", + "and v3.16b, v3.16b, v2.16b", + "add x0, x28, x21, lsl #4", + "str q3, [x0, #752]", + "add x22, x20, #0xa (10)", + "add w21, w21, #0x1 (1)", + "and w21, w21, #0x7", + "ldur q3, [x20, #10]", + "and v3.16b, v3.16b, v2.16b", + "add x0, x28, x21, lsl #4", + "str q3, [x0, #752]", + "add x20, x22, #0xa (10)", + "add w21, w21, #0x1 (1)", + "and w21, w21, #0x7", + "ldur q3, [x22, #10]", + "and v3.16b, v3.16b, v2.16b", + "add x0, x28, x21, lsl #4", + "str q3, [x0, #752]", + "add x22, x20, #0xa (10)", + "add w21, w21, #0x1 (1)", + "and w21, w21, #0x7", + "ldur q3, [x20, #10]", + "and v3.16b, v3.16b, v2.16b", + "add x0, x28, x21, lsl #4", + "str q3, [x0, #752]", + "add x20, x22, #0xa (10)", + "add w21, w21, #0x1 (1)", + "and w21, w21, #0x7", + "ldur q3, [x22, #10]", + "and v2.16b, v3.16b, v2.16b", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]", + "add x22, x20, #0xa (10)", + "add w21, w21, #0x1 (1)", + "and w21, w21, #0x7", + "ldur d2, [x20, #10]", + "ldr h3, [x22, #8]", + "mov v2.h[4], v3.h[0]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fnsave [rax]": { + "ExpectedInstructionCount": 118, + "Optimal": "No", + "Comment": [ + "0xdd !11b /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldrh w21, [x28, #1008]", + "str w21, [x4]", + "mov w21, #0x0", + "mov x0, x21", + "bfi x0, x20, #11, #3", + "mov x22, x0", + "ldrb w23, [x28, #744]", + "ldrb w24, [x28, #745]", + "ldrb w25, [x28, #746]", + "ldrb w26, [x28, #750]", + "orr x22, x22, x23, lsl #8", + "orr x22, x22, x24, lsl #9", + "orr x22, x22, x25, lsl #10", + "orr x22, x22, x26, lsl #14", + "str w22, [x4, #4]", + "ldrb w22, [x28, #1010]", + "and w23, w22, #0x1", + "mov w24, #0x3", + "cmp x23, #0x0 (0)", + "csel x23, x24, x21, eq", + "orr w23, w21, w23", + "lsr w25, w22, #1", + "and w25, w25, #0x1", + "cmp x25, #0x0 (0)", + "csel x25, x24, x21, eq", + "orr w23, w23, w25, lsl #2", + "lsr w25, w22, #2", + "and w25, w25, #0x1", + "cmp x25, #0x0 (0)", + "csel x25, x24, x21, eq", + "orr w23, w23, w25, lsl #4", + "lsr w25, w22, #3", + "and w25, w25, #0x1", + "cmp x25, #0x0 (0)", + "csel x25, x24, x21, eq", + "orr w23, w23, w25, lsl #6", + "lsr w25, w22, #4", + "and w25, w25, #0x1", + "cmp x25, #0x0 (0)", + "csel x25, x24, x21, eq", + "orr w23, w23, w25, lsl #8", + "lsr w25, w22, #5", + "and w25, w25, #0x1", + "cmp x25, #0x0 (0)", + "csel x25, x24, x21, eq", + "orr w23, w23, w25, lsl #10", + "lsr w25, w22, #6", + "and w25, w25, #0x1", + "cmp x25, #0x0 (0)", + "csel x25, x24, x21, eq", + "orr w23, w23, w25, lsl #12", + "lsr w22, w22, #7", + "and w22, w22, #0x1", + "cmp x22, #0x0 (0)", + "csel x22, x24, x21, eq", + "orr w22, w23, w22, lsl #14", + "str w22, [x4, #8]", + "str w21, [x4, #12]", + "str w21, [x4, #16]", + "str w21, [x4, #20]", + "str w21, [x4, #24]", + "add x22, x4, #0x1c (28)", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #752]", + "stur q2, [x4, #28]", + "add x23, x22, #0xa (10)", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #752]", + "stur q2, [x22, #10]", + "add x22, x23, #0xa (10)", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #752]", + "stur q2, [x23, #10]", + "add x23, x22, #0xa (10)", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #752]", + "stur q2, [x22, #10]", + "add x22, x23, #0xa (10)", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #752]", + "stur q2, [x23, #10]", + "add x23, x22, #0xa (10)", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #752]", + "stur q2, [x22, #10]", + "add x22, x23, #0xa (10)", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #752]", + "stur q2, [x23, #10]", + "add x23, x22, #0xa (10)", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #752]", + "stur d2, [x22, #10]", + "dup v2.8h, v2.h[4]", + "str h2, [x23, #8]", + "mov w20, #0x37f", + "strh w20, [x28, #1008]", + "strb w21, [x28, #747]", + "strb w21, [x28, #744]", + "strb w21, [x28, #745]", + "strb w21, [x28, #746]", + "strb w21, [x28, #750]", + "strb w21, [x28, #1010]" + ] + }, + "fnstsw [rax]": { + "ExpectedInstructionCount": 12, + "Optimal": "No", + "Comment": [ + "0xdd !11b /7" + ], + "ExpectedArm64ASM": [ + "mov w20, #0x0", + "ldrb w21, [x28, #747]", + "bfi x20, x21, #11, #3", + "ldrb w21, [x28, #744]", + "ldrb w22, [x28, #745]", + "ldrb w23, [x28, #746]", + "ldrb w24, [x28, #750]", + "orr x20, x20, x21, lsl #8", + "orr x20, x20, x22, lsl #9", + "orr x20, x20, x23, lsl #10", + "orr x20, x20, x24, lsl #14", + "strh w20, [x4]" + ] + }, + "ffree st0": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": [ + "0xdd 11b 0xc0 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w20, w20, #0x0 (0)", + "and w20, w20, #0x7", + "ldrb w21, [x28, #1010]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "bic w20, w21, w20", + "strb w20, [x28, #1010]" + ] + }, + "ffree st1": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": [ + "0xdd 11b 0xc1 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "mov w21, #0x1", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "ldrb w22, [x28, #1010]", + "lsl w20, w21, w20", + "bic w20, w22, w20", + "strb w20, [x28, #1010]" + ] + }, + "ffree st2": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": [ + "0xdd 11b 0xc2 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w20, w20, #0x2 (2)", + "and w20, w20, #0x7", + "ldrb w21, [x28, #1010]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "bic w20, w21, w20", + "strb w20, [x28, #1010]" + ] + }, + "ffree st3": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": [ + "0xdd 11b 0xc3 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w20, w20, #0x3 (3)", + "and w20, w20, #0x7", + "ldrb w21, [x28, #1010]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "bic w20, w21, w20", + "strb w20, [x28, #1010]" + ] + }, + "ffree st4": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": [ + "0xdd 11b 0xc4 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w20, w20, #0x4 (4)", + "and w20, w20, #0x7", + "ldrb w21, [x28, #1010]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "bic w20, w21, w20", + "strb w20, [x28, #1010]" + ] + }, + "ffree st5": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": [ + "0xdd 11b 0xc5 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w20, w20, #0x5 (5)", + "and w20, w20, #0x7", + "ldrb w21, [x28, #1010]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "bic w20, w21, w20", + "strb w20, [x28, #1010]" + ] + }, + "ffree st6": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": [ + "0xdd 11b 0xc6 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w20, w20, #0x6 (6)", + "and w20, w20, #0x7", + "ldrb w21, [x28, #1010]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "bic w20, w21, w20", + "strb w20, [x28, #1010]" + ] + }, + "ffree st7": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": [ + "0xdd 11b 0xc7 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w20, w20, #0x7 (7)", + "and w20, w20, #0x7", + "ldrb w21, [x28, #1010]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "bic w20, w21, w20", + "strb w20, [x28, #1010]" + ] + }, + "fst st0": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": [ + "0xdd 11b 0xd0 /2" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x0 (0)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fst st1": { + "ExpectedInstructionCount": 7, + "Optimal": "Yes", + "Comment": [ + "0xdd 11b 0xd1 /2" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fst st2": { + "ExpectedInstructionCount": 7, + "Optimal": "Yes", + "Comment": [ + "0xdd 11b 0xd2 /2" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fst st3": { + "ExpectedInstructionCount": 7, + "Optimal": "Yes", + "Comment": [ + "0xdd 11b 0xd3 /2" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fst st4": { + "ExpectedInstructionCount": 7, + "Optimal": "Yes", + "Comment": [ + "0xdd 11b 0xd4 /2" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x4 (4)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fst st5": { + "ExpectedInstructionCount": 7, + "Optimal": "Yes", + "Comment": [ + "0xdd 11b 0xd5 /2" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x5 (5)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fst st6": { + "ExpectedInstructionCount": 7, + "Optimal": "Yes", + "Comment": [ + "0xdd 11b 0xd6 /2" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x6 (6)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fst st7": { + "ExpectedInstructionCount": 7, + "Optimal": "Yes", + "Comment": [ + "0xdd 11b 0xd7 /2" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x7 (7)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fstp st0": { + "ExpectedInstructionCount": 15, + "Optimal": "No", + "Comment": [ + "0xdd 11b 0xd8 /3" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x0 (0)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]", + "ldrb w21, [x28, #1010]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "fstp st1": { + "ExpectedInstructionCount": 15, + "Optimal": "No", + "Comment": [ + "0xdd 11b 0xd9 /3" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "mov w21, #0x1", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x22, lsl #4", + "str q2, [x0, #752]", + "ldrb w22, [x28, #1010]", + "lsl w21, w21, w20", + "bic w21, w22, w21", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "fstp st2": { + "ExpectedInstructionCount": 15, + "Optimal": "No", + "Comment": [ + "0xdd 11b 0xda /3" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]", + "ldrb w21, [x28, #1010]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "fstp st3": { + "ExpectedInstructionCount": 15, + "Optimal": "No", + "Comment": [ + "0xdd 11b 0xdb /3" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]", + "ldrb w21, [x28, #1010]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "fstp st4": { + "ExpectedInstructionCount": 15, + "Optimal": "No", + "Comment": [ + "0xdd 11b 0xdc /3" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x4 (4)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]", + "ldrb w21, [x28, #1010]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "fstp st5": { + "ExpectedInstructionCount": 15, + "Optimal": "No", + "Comment": [ + "0xdd 11b 0xdd /3" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x5 (5)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]", + "ldrb w21, [x28, #1010]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "fstp st6": { + "ExpectedInstructionCount": 15, + "Optimal": "No", + "Comment": [ + "0xdd 11b 0xde /3" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x6 (6)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]", + "ldrb w21, [x28, #1010]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "fstp st7": { + "ExpectedInstructionCount": 15, + "Optimal": "No", + "Comment": [ + "0xdd 11b 0xdf /3" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x7 (7)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]", + "ldrb w21, [x28, #1010]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "fucom st0": { + "ExpectedInstructionCount": 63, + "Optimal": "No", + "Comment": [ + "0xdd 11b 0xe0 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "mov w21, #0x0", + "add w22, w20, #0x0 (0)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1280]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x20, x0", + "ubfx x22, x20, #1, #1", + "ubfx x23, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w22, w22, w20", + "orr w23, w23, w20", + "strb w22, [x28, #744]", + "strb w21, [x28, #745]", + "strb w20, [x28, #746]", + "strb w23, [x28, #750]" + ] + }, + "fucom st1": { + "ExpectedInstructionCount": 63, + "Optimal": "No", + "Comment": [ + "0xdd 11b 0xe1 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1280]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x20, x0", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "strb w21, [x28, #744]", + "mov w21, #0x0", + "strb w21, [x28, #745]", + "strb w20, [x28, #746]", + "strb w22, [x28, #750]" + ] + }, + "fucom st2": { + "ExpectedInstructionCount": 63, + "Optimal": "No", + "Comment": [ + "0xdd 11b 0xe2 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1280]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x20, x0", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "strb w21, [x28, #744]", + "mov w21, #0x0", + "strb w21, [x28, #745]", + "strb w20, [x28, #746]", + "strb w22, [x28, #750]" + ] + }, + "fucom st3": { + "ExpectedInstructionCount": 63, + "Optimal": "No", + "Comment": [ + "0xdd 11b 0xe3 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1280]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x20, x0", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "strb w21, [x28, #744]", + "mov w21, #0x0", + "strb w21, [x28, #745]", + "strb w20, [x28, #746]", + "strb w22, [x28, #750]" + ] + }, + "fucom st4": { + "ExpectedInstructionCount": 63, + "Optimal": "No", + "Comment": [ + "0xdd 11b 0xe4 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x4 (4)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1280]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x20, x0", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "strb w21, [x28, #744]", + "mov w21, #0x0", + "strb w21, [x28, #745]", + "strb w20, [x28, #746]", + "strb w22, [x28, #750]" + ] + }, + "fucom st5": { + "ExpectedInstructionCount": 63, + "Optimal": "No", + "Comment": [ + "0xdd 11b 0xe5 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x5 (5)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1280]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x20, x0", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "strb w21, [x28, #744]", + "mov w21, #0x0", + "strb w21, [x28, #745]", + "strb w20, [x28, #746]", + "strb w22, [x28, #750]" + ] + }, + "fucom st6": { + "ExpectedInstructionCount": 63, + "Optimal": "No", + "Comment": [ + "0xdd 11b 0xe6 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x6 (6)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1280]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x20, x0", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "strb w21, [x28, #744]", + "mov w21, #0x0", + "strb w21, [x28, #745]", + "strb w20, [x28, #746]", + "strb w22, [x28, #750]" + ] + }, + "fucom st7": { + "ExpectedInstructionCount": 63, + "Optimal": "No", + "Comment": [ + "0xdd 11b 0xe7 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x7 (7)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1280]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x20, x0", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "strb w21, [x28, #744]", + "mov w21, #0x0", + "strb w21, [x28, #745]", + "strb w20, [x28, #746]", + "strb w22, [x28, #750]" + ] + }, + "fucomp st0": { + "ExpectedInstructionCount": 71, + "Optimal": "No", + "Comment": [ + "0xdd 11b 0xe8 /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "mov w21, #0x0", + "add w22, w20, #0x0 (0)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1280]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x22, x0", + "ubfx x23, x22, #1, #1", + "ubfx x24, x22, #0, #1", + "ubfx x22, x22, #2, #1", + "orr w23, w23, w22", + "orr w24, w24, w22", + "strb w23, [x28, #744]", + "strb w21, [x28, #745]", + "strb w22, [x28, #746]", + "strb w24, [x28, #750]", + "ldrb w21, [x28, #1010]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "fucomp st1": { + "ExpectedInstructionCount": 71, + "Optimal": "No", + "Comment": [ + "0xdd 11b 0xe9 /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "mov w21, #0x1", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1280]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x22, x0", + "ubfx x23, x22, #1, #1", + "ubfx x24, x22, #0, #1", + "ubfx x22, x22, #2, #1", + "orr w23, w23, w22", + "orr w24, w24, w22", + "strb w23, [x28, #744]", + "mov w23, #0x0", + "strb w23, [x28, #745]", + "strb w22, [x28, #746]", + "strb w24, [x28, #750]", + "ldrb w22, [x28, #1010]", + "lsl w21, w21, w20", + "bic w21, w22, w21", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "fucomp st2": { + "ExpectedInstructionCount": 71, + "Optimal": "No", + "Comment": [ + "0xdd 11b 0xea /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1280]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x21, x0", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "strb w22, [x28, #744]", + "mov w22, #0x0", + "strb w22, [x28, #745]", + "strb w21, [x28, #746]", + "strb w23, [x28, #750]", + "ldrb w21, [x28, #1010]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "fucomp st3": { + "ExpectedInstructionCount": 71, + "Optimal": "No", + "Comment": [ + "0xdd 11b 0xeb /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1280]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x21, x0", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "strb w22, [x28, #744]", + "mov w22, #0x0", + "strb w22, [x28, #745]", + "strb w21, [x28, #746]", + "strb w23, [x28, #750]", + "ldrb w21, [x28, #1010]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "fucomp st4": { + "ExpectedInstructionCount": 71, + "Optimal": "No", + "Comment": [ + "0xdd 11b 0xec /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x4 (4)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1280]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x21, x0", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "strb w22, [x28, #744]", + "mov w22, #0x0", + "strb w22, [x28, #745]", + "strb w21, [x28, #746]", + "strb w23, [x28, #750]", + "ldrb w21, [x28, #1010]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "fucomp st5": { + "ExpectedInstructionCount": 71, + "Optimal": "No", + "Comment": [ + "0xdd 11b 0xed /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x5 (5)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1280]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x21, x0", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "strb w22, [x28, #744]", + "mov w22, #0x0", + "strb w22, [x28, #745]", + "strb w21, [x28, #746]", + "strb w23, [x28, #750]", + "ldrb w21, [x28, #1010]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "fucomp st6": { + "ExpectedInstructionCount": 71, + "Optimal": "No", + "Comment": [ + "0xdd 11b 0xee /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x6 (6)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1280]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x21, x0", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "strb w22, [x28, #744]", + "mov w22, #0x0", + "strb w22, [x28, #745]", + "strb w21, [x28, #746]", + "strb w23, [x28, #750]", + "ldrb w21, [x28, #1010]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "fucomp st7": { + "ExpectedInstructionCount": 71, + "Optimal": "No", + "Comment": [ + "0xdd 11b 0xef /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x7 (7)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1280]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x21, x0", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "strb w22, [x28, #744]", + "mov w22, #0x0", + "strb w22, [x28, #745]", + "strb w21, [x28, #746]", + "strb w23, [x28, #750]", + "ldrb w21, [x28, #1010]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "fiadd word [rax]": { + "ExpectedInstructionCount": 99, + "Optimal": "No", + "Comment": [ + "0xde !11b /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldrh w21, [x4]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "sxth w1, w21", + "ldr x2, [x28, #1288]", + "blr x2", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1384]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fimul word [rax]": { + "ExpectedInstructionCount": 99, + "Optimal": "No", + "Comment": [ + "0xde !11b /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldrh w21, [x4]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "sxth w1, w21", + "ldr x2, [x28, #1288]", + "blr x2", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "ficom word [rax]": { + "ExpectedInstructionCount": 105, + "Optimal": "No", + "Comment": [ + "0xde !11b /2" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldrh w21, [x4]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "sxth w1, w21", + "ldr x2, [x28, #1288]", + "blr x2", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1280]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x20, x0", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "strb w21, [x28, #744]", + "mov w21, #0x0", + "strb w21, [x28, #745]", + "strb w20, [x28, #746]", + "strb w22, [x28, #750]" + ] + }, + "ficomp word [rax]": { + "ExpectedInstructionCount": 113, + "Optimal": "No", + "Comment": [ + "0xde !11b /3" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldrh w21, [x4]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "sxth w1, w21", + "ldr x2, [x28, #1288]", + "blr x2", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1280]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x21, x0", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "strb w22, [x28, #744]", + "mov w22, #0x0", + "strb w22, [x28, #745]", + "strb w21, [x28, #746]", + "strb w23, [x28, #750]", + "ldrb w21, [x28, #1010]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "fisub word [rax]": { + "ExpectedInstructionCount": 99, + "Optimal": "No", + "Comment": [ + "0xde !11b /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldrh w21, [x4]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "sxth w1, w21", + "ldr x2, [x28, #1288]", + "blr x2", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1392]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fisubr word [rax]": { + "ExpectedInstructionCount": 99, + "Optimal": "No", + "Comment": [ + "0xde !11b /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldrh w21, [x4]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "sxth w1, w21", + "ldr x2, [x28, #1288]", + "blr x2", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1392]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fidiv word [rax]": { + "ExpectedInstructionCount": 99, + "Optimal": "No", + "Comment": [ + "0xde !11b /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldrh w21, [x4]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "sxth w1, w21", + "ldr x2, [x28, #1288]", + "blr x2", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1408]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fidivr word [rax]": { + "ExpectedInstructionCount": 99, + "Optimal": "No", + "Comment": [ + "0xde !11b /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldrh w21, [x4]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "sxth w1, w21", + "ldr x2, [x28, #1288]", + "blr x2", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1408]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "faddp st0": { + "ExpectedInstructionCount": 65, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xc0 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x0 (0)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1384]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldrb w22, [x28, #1010]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "faddp st1": { + "ExpectedInstructionCount": 65, + "Optimal": "No", + "Comment": [ + "0xde 11b 0xc1 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "mov w21, #0x1", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1384]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldrb w23, [x28, #1010]", + "lsl w21, w21, w20", + "bic w21, w23, w21", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x22, lsl #4", + "str q2, [x0, #752]" + ] + }, + "faddp st2": { + "ExpectedInstructionCount": 65, + "Optimal": "No", + "Comment": [ + "0xde 11b 0xc2 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1384]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldrb w22, [x28, #1010]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "faddp st3": { + "ExpectedInstructionCount": 65, + "Optimal": "No", + "Comment": [ + "0xde 11b 0xc3 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1384]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldrb w22, [x28, #1010]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "faddp st4": { + "ExpectedInstructionCount": 65, + "Optimal": "No", + "Comment": [ + "0xde 11b 0xc4 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x4 (4)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1384]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldrb w22, [x28, #1010]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "faddp st5": { + "ExpectedInstructionCount": 65, + "Optimal": "No", + "Comment": [ + "0xde 11b 0xc5 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x5 (5)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1384]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldrb w22, [x28, #1010]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "faddp st6": { + "ExpectedInstructionCount": 65, + "Optimal": "No", + "Comment": [ + "0xde 11b 0xc6 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x6 (6)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1384]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldrb w22, [x28, #1010]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "faddp st7": { + "ExpectedInstructionCount": 65, + "Optimal": "No", + "Comment": [ + "0xde 11b 0xc7 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x7 (7)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1384]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldrb w22, [x28, #1010]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fmulp st0": { + "ExpectedInstructionCount": 65, + "Optimal": "No", + "Comment": [ + "0xde 11b 0xc8 /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x0 (0)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldrb w22, [x28, #1010]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fmulp st1": { + "ExpectedInstructionCount": 65, + "Optimal": "No", + "Comment": [ + "0xde 11b 0xc9 /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "mov w21, #0x1", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldrb w23, [x28, #1010]", + "lsl w21, w21, w20", + "bic w21, w23, w21", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x22, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fmulp st2": { + "ExpectedInstructionCount": 65, + "Optimal": "No", + "Comment": [ + "0xde 11b 0xca /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldrb w22, [x28, #1010]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fmulp st3": { + "ExpectedInstructionCount": 65, + "Optimal": "No", + "Comment": [ + "0xde 11b 0xcb /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldrb w22, [x28, #1010]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fmulp st4": { + "ExpectedInstructionCount": 65, + "Optimal": "No", + "Comment": [ + "0xde 11b 0xcc /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x4 (4)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldrb w22, [x28, #1010]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fmulp st5": { + "ExpectedInstructionCount": 65, + "Optimal": "No", + "Comment": [ + "0xde 11b 0xcd /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x5 (5)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldrb w22, [x28, #1010]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fmulp st6": { + "ExpectedInstructionCount": 65, + "Optimal": "No", + "Comment": [ + "0xde 11b 0xce /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x6 (6)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldrb w22, [x28, #1010]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fmulp st7": { + "ExpectedInstructionCount": 65, + "Optimal": "No", + "Comment": [ + "0xde 11b 0xcf /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x7 (7)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldrb w22, [x28, #1010]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcompp": { + "ExpectedInstructionCount": 76, + "Optimal": "No", + "Comment": [ + "0xde 11b 0xd9 /3" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "mov w21, #0x1", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1280]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x22, x0", + "ubfx x23, x22, #1, #1", + "ubfx x24, x22, #0, #1", + "ubfx x22, x22, #2, #1", + "orr w23, w23, w22", + "orr w24, w24, w22", + "strb w23, [x28, #744]", + "mov w23, #0x0", + "strb w23, [x28, #745]", + "strb w22, [x28, #746]", + "strb w24, [x28, #750]", + "ldrb w22, [x28, #1010]", + "lsl w23, w21, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "lsl w21, w21, w20", + "bic w21, w22, w21", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "db 0xde, 0xe0": { + "ExpectedInstructionCount": 65, + "Optimal": "No", + "Comment": [ + "fsubrp st0, st0", + "Needs manual encoding since otherwise nasm will emit the 0xd8 variant.", + "0xde 11b 0xe0 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x0 (0)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1392]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldrb w22, [x28, #1010]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fsubrp st1, st0": { + "ExpectedInstructionCount": 65, + "Optimal": "No", + "Comment": [ + "0xde 11b 0xe1 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "mov w21, #0x1", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1392]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldrb w23, [x28, #1010]", + "lsl w21, w21, w20", + "bic w21, w23, w21", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x22, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fsubrp st2, st0": { + "ExpectedInstructionCount": 65, + "Optimal": "No", + "Comment": [ + "0xde 11b 0xe2 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1392]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldrb w22, [x28, #1010]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fsubrp st3, st0": { + "ExpectedInstructionCount": 65, + "Optimal": "No", + "Comment": [ + "0xde 11b 0xe3 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1392]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldrb w22, [x28, #1010]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fsubrp st4, st0": { + "ExpectedInstructionCount": 65, + "Optimal": "No", + "Comment": [ + "0xde 11b 0xe4 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x4 (4)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1392]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldrb w22, [x28, #1010]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fsubrp st5, st0": { + "ExpectedInstructionCount": 65, + "Optimal": "No", + "Comment": [ + "0xde 11b 0xe5 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x5 (5)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1392]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldrb w22, [x28, #1010]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fsubrp st6, st0": { + "ExpectedInstructionCount": 65, + "Optimal": "No", + "Comment": [ + "0xde 11b 0xe6 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x6 (6)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1392]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldrb w22, [x28, #1010]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fsubrp st7, st0": { + "ExpectedInstructionCount": 65, + "Optimal": "No", + "Comment": [ + "0xde 11b 0xe7 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x7 (7)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1392]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldrb w22, [x28, #1010]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "db 0xde, 0xe8": { + "ExpectedInstructionCount": 65, + "Optimal": "No", + "Comment": [ + "fsubp st0, st0", + "Needs manual encoding since otherwise nasm will emit the 0xd8 variant.", + "0xde 11b 0xe8 /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x0 (0)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1392]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldrb w22, [x28, #1010]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fsubp st1, st0": { + "ExpectedInstructionCount": 65, + "Optimal": "No", + "Comment": [ + "0xde 11b 0xe9 /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "mov w21, #0x1", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1392]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldrb w23, [x28, #1010]", + "lsl w21, w21, w20", + "bic w21, w23, w21", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x22, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fsubp st2, st0": { + "ExpectedInstructionCount": 65, + "Optimal": "No", + "Comment": [ + "0xde 11b 0xea /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1392]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldrb w22, [x28, #1010]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fsubp st3, st0": { + "ExpectedInstructionCount": 65, + "Optimal": "No", + "Comment": [ + "0xde 11b 0xeb /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1392]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldrb w22, [x28, #1010]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fsubp st4, st0": { + "ExpectedInstructionCount": 65, + "Optimal": "No", + "Comment": [ + "0xde 11b 0xec /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x4 (4)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1392]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldrb w22, [x28, #1010]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fsubp st5, st0": { + "ExpectedInstructionCount": 65, + "Optimal": "No", + "Comment": [ + "0xde 11b 0xed /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x5 (5)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1392]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldrb w22, [x28, #1010]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fsubp st6, st0": { + "ExpectedInstructionCount": 65, + "Optimal": "No", + "Comment": [ + "0xde 11b 0xee /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x6 (6)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1392]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldrb w22, [x28, #1010]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fsubp st7, st0": { + "ExpectedInstructionCount": 65, + "Optimal": "No", + "Comment": [ + "0xde 11b 0xef /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x7 (7)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1392]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldrb w22, [x28, #1010]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "db 0xde, 0xf0": { + "ExpectedInstructionCount": 65, + "Optimal": "No", + "Comment": [ + "fdivrp st0, st0", + "Needs manual encoding since otherwise nasm will emit the 0xd8 variant.", + "0xde 11b 0xf0 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x0 (0)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1408]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldrb w22, [x28, #1010]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fdivrp st1, st0": { + "ExpectedInstructionCount": 65, + "Optimal": "No", + "Comment": [ + "0xde 11b 0xf1 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "mov w21, #0x1", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1408]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldrb w23, [x28, #1010]", + "lsl w21, w21, w20", + "bic w21, w23, w21", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x22, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fdivrp st2, st0": { + "ExpectedInstructionCount": 65, + "Optimal": "No", + "Comment": [ + "0xde 11b 0xf2 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1408]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldrb w22, [x28, #1010]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fdivrp st3, st0": { + "ExpectedInstructionCount": 65, + "Optimal": "No", + "Comment": [ + "0xde 11b 0xf3 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1408]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldrb w22, [x28, #1010]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fdivrp st4, st0": { + "ExpectedInstructionCount": 65, + "Optimal": "No", + "Comment": [ + "0xde 11b 0xf4 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x4 (4)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1408]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldrb w22, [x28, #1010]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fdivrp st5, st0": { + "ExpectedInstructionCount": 65, + "Optimal": "No", + "Comment": [ + "0xde 11b 0xf5 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x5 (5)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1408]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldrb w22, [x28, #1010]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fdivrp st6, st0": { + "ExpectedInstructionCount": 65, + "Optimal": "No", + "Comment": [ + "0xde 11b 0xf6 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x6 (6)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1408]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldrb w22, [x28, #1010]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fdivrp st7, st0": { + "ExpectedInstructionCount": 65, + "Optimal": "No", + "Comment": [ + "0xde 11b 0xf7 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x7 (7)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1408]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldrb w22, [x28, #1010]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "db 0xde, 0xf8": { + "ExpectedInstructionCount": 65, + "Optimal": "No", + "Comment": [ + "fdivp st0, st0", + "Needs manual encoding since otherwise nasm will emit the 0xd8 variant.", + "0xde 11b 0xf8 /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x0 (0)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1408]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldrb w22, [x28, #1010]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fdivp st1, st0": { + "ExpectedInstructionCount": 65, + "Optimal": "No", + "Comment": [ + "0xde 11b 0xf9 /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "mov w21, #0x1", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1408]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldrb w23, [x28, #1010]", + "lsl w21, w21, w20", + "bic w21, w23, w21", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x22, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fdivp st2, st0": { + "ExpectedInstructionCount": 65, + "Optimal": "No", + "Comment": [ + "0xde 11b 0xfa /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1408]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldrb w22, [x28, #1010]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fdivp st3, st0": { + "ExpectedInstructionCount": 65, + "Optimal": "No", + "Comment": [ + "0xde 11b 0xfb /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1408]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldrb w22, [x28, #1010]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fdivp st4, st0": { + "ExpectedInstructionCount": 65, + "Optimal": "No", + "Comment": [ + "0xde 11b 0xfc /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x4 (4)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1408]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldrb w22, [x28, #1010]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fdivp st5, st0": { + "ExpectedInstructionCount": 65, + "Optimal": "No", + "Comment": [ + "0xde 11b 0xfd /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x5 (5)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1408]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldrb w22, [x28, #1010]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fdivp st6, st0": { + "ExpectedInstructionCount": 65, + "Optimal": "No", + "Comment": [ + "0xde 11b 0xfe /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x6 (6)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1408]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldrb w22, [x28, #1010]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fdivp st7, st0": { + "ExpectedInstructionCount": 65, + "Optimal": "No", + "Comment": [ + "0xde 11b 0xff /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x7 (7)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1408]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldrb w22, [x28, #1010]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fild word [rax]": { + "ExpectedInstructionCount": 33, + "Optimal": "No", + "Comment": [ + "0xdf !11b /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "mov w21, #0x1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "ldrb w22, [x28, #1010]", + "lsl w21, w21, w20", + "orr w21, w22, w21", + "strb w21, [x28, #1010]", + "strb w20, [x28, #747]", + "ldrh w21, [x4]", + "mov w22, #0x0", + "sxth x21, w21", + "mov w23, #0x8000", + "cmp x21, #0x0 (0)", + "csel x23, x23, x22, lt", + "cmp x21, #0x0 (0)", + "cneg x21, x21, mi", + "mov w24, #0x3f", + "mov x0, #0x3f", + "clz x25, x21", + "sub x25, x0, x25", + "sub x24, x24, x25", + "lsl x25, x21, x24", + "mov w26, #0x403e", + "sub x24, x26, x24", + "cmp x21, #0x0 (0)", + "csel x21, x22, x24, eq", + "orr x21, x23, x21", + "fmov d2, x25", + "fmov d3, x21", + "mov v2.d[1], v3.d[0]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fisttp word [rax]": { + "ExpectedInstructionCount": 56, + "Optimal": "No", + "Comment": [ + "0xdf !11b /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1200]", + "blr x3", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "sxth x21, w0", + "strh w21, [x4]", + "ldrb w21, [x28, #1010]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "fist word [rax]": { + "ExpectedInstructionCount": 48, + "Optimal": "No", + "Comment": [ + "0xdf !11b /2" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1176]", + "blr x3", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "sxth x20, w0", + "strh w20, [x4]" + ] + }, + "fistp word [rax]": { + "ExpectedInstructionCount": 56, + "Optimal": "No", + "Comment": [ + "0xdf !11b /3" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1176]", + "blr x3", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "sxth x21, w0", + "strh w21, [x4]", + "ldrb w21, [x28, #1010]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "fbld tword [rax]": { + "ExpectedInstructionCount": 58, + "Optimal": "No", + "Comment": [ + "0xdf !11b /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "mov w21, #0x1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "ldrb w22, [x28, #1010]", + "lsl w21, w21, w20", + "orr w21, w22, w21", + "strb w21, [x28, #1010]", + "strb w20, [x28, #747]", + "ldr q2, [x4]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1376]", + "blr x3", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fbstp tword [rax]": { + "ExpectedInstructionCount": 60, + "Optimal": "No", + "Comment": [ + "0xdf !11b /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1368]", + "blr x3", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "str d2, [x4]", + "mov x21, v2.d[1]", + "strh w21, [x4, #8]", + "ldrb w21, [x28, #1010]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "ffreep st0": { + "ExpectedInstructionCount": 4, + "Optimal": "Yes", + "Comment": [ + "0xdf 11b 0xc0 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "ffreep st1": { + "ExpectedInstructionCount": 4, + "Optimal": "Yes", + "Comment": [ + "0xdf 11b 0xc1 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "ffreep st2": { + "ExpectedInstructionCount": 4, + "Optimal": "Yes", + "Comment": [ + "0xdf 11b 0xc2 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "ffreep st3": { + "ExpectedInstructionCount": 4, + "Optimal": "Yes", + "Comment": [ + "0xdf 11b 0xc3 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "ffreep st4": { + "ExpectedInstructionCount": 4, + "Optimal": "Yes", + "Comment": [ + "0xdf 11b 0xc4 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "ffreep st5": { + "ExpectedInstructionCount": 4, + "Optimal": "Yes", + "Comment": [ + "0xdf 11b 0xc5 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "ffreep st6": { + "ExpectedInstructionCount": 4, + "Optimal": "Yes", + "Comment": [ + "0xdf 11b 0xc6 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "ffreep st7": { + "ExpectedInstructionCount": 4, + "Optimal": "Yes", + "Comment": [ + "0xdf 11b 0xc7 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "fnstsw ax": { + "ExpectedInstructionCount": 12, + "Optimal": "No", + "Comment": [ + "0xdf 11b 0xe0 /4" + ], + "ExpectedArm64ASM": [ + "mov w20, #0x0", + "ldrb w21, [x28, #747]", + "bfi x20, x21, #11, #3", + "ldrb w21, [x28, #744]", + "ldrb w22, [x28, #745]", + "ldrb w23, [x28, #746]", + "ldrb w24, [x28, #750]", + "orr x20, x20, x21, lsl #8", + "orr x20, x20, x22, lsl #9", + "orr x20, x20, x23, lsl #10", + "orr x20, x20, x24, lsl #14", + "bfxil x4, x20, #0, #16" + ] + }, + "fucomip st0": { + "ExpectedInstructionCount": 71, + "Optimal": "No", + "Comment": [ + "0xdf 11b 0xe8 /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x0 (0)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1280]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x21, x0", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "lsl x22, x22, #29", + "orr w22, w22, w23, lsl #30", + "mov w23, #0x1", + "eor w21, w21, #0x1", + "strb w21, [x28, #706]", + "ldrb w21, [x28, #1010]", + "lsl w23, w23, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "str w22, [x28, #728]" + ] + }, + "fucomip st1": { + "ExpectedInstructionCount": 71, + "Optimal": "No", + "Comment": [ + "0xdf 11b 0xe9 /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "mov w21, #0x1", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1280]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x22, x0", + "ubfx x23, x22, #1, #1", + "ubfx x24, x22, #0, #1", + "ubfx x22, x22, #2, #1", + "orr w23, w23, w22", + "orr w24, w24, w22", + "lsl x23, x23, #29", + "orr w23, w23, w24, lsl #30", + "eor w22, w22, #0x1", + "strb w22, [x28, #706]", + "ldrb w22, [x28, #1010]", + "lsl w21, w21, w20", + "bic w21, w22, w21", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "str w23, [x28, #728]" + ] + }, + "fucomip st2": { + "ExpectedInstructionCount": 71, + "Optimal": "No", + "Comment": [ + "0xdf 11b 0xea /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1280]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x21, x0", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "lsl x22, x22, #29", + "orr w22, w22, w23, lsl #30", + "mov w23, #0x1", + "eor w21, w21, #0x1", + "strb w21, [x28, #706]", + "ldrb w21, [x28, #1010]", + "lsl w23, w23, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "str w22, [x28, #728]" + ] + }, + "fucomip st3": { + "ExpectedInstructionCount": 71, + "Optimal": "No", + "Comment": [ + "0xdf 11b 0xeb /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1280]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x21, x0", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "lsl x22, x22, #29", + "orr w22, w22, w23, lsl #30", + "mov w23, #0x1", + "eor w21, w21, #0x1", + "strb w21, [x28, #706]", + "ldrb w21, [x28, #1010]", + "lsl w23, w23, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "str w22, [x28, #728]" + ] + }, + "fucomip st4": { + "ExpectedInstructionCount": 71, + "Optimal": "No", + "Comment": [ + "0xdf 11b 0xec /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x4 (4)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1280]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x21, x0", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "lsl x22, x22, #29", + "orr w22, w22, w23, lsl #30", + "mov w23, #0x1", + "eor w21, w21, #0x1", + "strb w21, [x28, #706]", + "ldrb w21, [x28, #1010]", + "lsl w23, w23, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "str w22, [x28, #728]" + ] + }, + "fucomip st5": { + "ExpectedInstructionCount": 71, + "Optimal": "No", + "Comment": [ + "0xdf 11b 0xed /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x5 (5)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1280]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x21, x0", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "lsl x22, x22, #29", + "orr w22, w22, w23, lsl #30", + "mov w23, #0x1", + "eor w21, w21, #0x1", + "strb w21, [x28, #706]", + "ldrb w21, [x28, #1010]", + "lsl w23, w23, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "str w22, [x28, #728]" + ] + }, + "fucomip st6": { + "ExpectedInstructionCount": 71, + "Optimal": "No", + "Comment": [ + "0xdf 11b 0xee /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x6 (6)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1280]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x21, x0", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "lsl x22, x22, #29", + "orr w22, w22, w23, lsl #30", + "mov w23, #0x1", + "eor w21, w21, #0x1", + "strb w21, [x28, #706]", + "ldrb w21, [x28, #1010]", + "lsl w23, w23, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "str w22, [x28, #728]" + ] + }, + "fucomip st7": { + "ExpectedInstructionCount": 71, + "Optimal": "No", + "Comment": [ + "0xdf 11b 0xef /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x7 (7)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1280]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x21, x0", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "lsl x22, x22, #29", + "orr w22, w22, w23, lsl #30", + "mov w23, #0x1", + "eor w21, w21, #0x1", + "strb w21, [x28, #706]", + "ldrb w21, [x28, #1010]", + "lsl w23, w23, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "str w22, [x28, #728]" + ] + }, + "fcomip st0": { + "ExpectedInstructionCount": 71, + "Optimal": "No", + "Comment": [ + "0xdf 11b 0xf0 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x0 (0)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1280]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x21, x0", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "lsl x22, x22, #29", + "orr w22, w22, w23, lsl #30", + "mov w23, #0x1", + "eor w21, w21, #0x1", + "strb w21, [x28, #706]", + "ldrb w21, [x28, #1010]", + "lsl w23, w23, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "str w22, [x28, #728]" + ] + }, + "fcomip st1": { + "ExpectedInstructionCount": 71, + "Optimal": "No", + "Comment": [ + "0xdf 11b 0xf1 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "mov w21, #0x1", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1280]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x22, x0", + "ubfx x23, x22, #1, #1", + "ubfx x24, x22, #0, #1", + "ubfx x22, x22, #2, #1", + "orr w23, w23, w22", + "orr w24, w24, w22", + "lsl x23, x23, #29", + "orr w23, w23, w24, lsl #30", + "eor w22, w22, #0x1", + "strb w22, [x28, #706]", + "ldrb w22, [x28, #1010]", + "lsl w21, w21, w20", + "bic w21, w22, w21", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "str w23, [x28, #728]" + ] + }, + "fcomip st2": { + "ExpectedInstructionCount": 71, + "Optimal": "No", + "Comment": [ + "0xdf 11b 0xf2 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1280]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x21, x0", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "lsl x22, x22, #29", + "orr w22, w22, w23, lsl #30", + "mov w23, #0x1", + "eor w21, w21, #0x1", + "strb w21, [x28, #706]", + "ldrb w21, [x28, #1010]", + "lsl w23, w23, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "str w22, [x28, #728]" + ] + }, + "fcomip st3": { + "ExpectedInstructionCount": 71, + "Optimal": "No", + "Comment": [ + "0xdf 11b 0xf3 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1280]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x21, x0", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "lsl x22, x22, #29", + "orr w22, w22, w23, lsl #30", + "mov w23, #0x1", + "eor w21, w21, #0x1", + "strb w21, [x28, #706]", + "ldrb w21, [x28, #1010]", + "lsl w23, w23, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "str w22, [x28, #728]" + ] + }, + "fcomip st4": { + "ExpectedInstructionCount": 71, + "Optimal": "No", + "Comment": [ + "0xdf 11b 0xf4 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x4 (4)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1280]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x21, x0", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "lsl x22, x22, #29", + "orr w22, w22, w23, lsl #30", + "mov w23, #0x1", + "eor w21, w21, #0x1", + "strb w21, [x28, #706]", + "ldrb w21, [x28, #1010]", + "lsl w23, w23, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "str w22, [x28, #728]" + ] + }, + "fcomip st5": { + "ExpectedInstructionCount": 71, + "Optimal": "No", + "Comment": [ + "0xdf 11b 0xf5 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x5 (5)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1280]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x21, x0", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "lsl x22, x22, #29", + "orr w22, w22, w23, lsl #30", + "mov w23, #0x1", + "eor w21, w21, #0x1", + "strb w21, [x28, #706]", + "ldrb w21, [x28, #1010]", + "lsl w23, w23, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "str w22, [x28, #728]" + ] + }, + "fcomip st6": { + "ExpectedInstructionCount": 71, + "Optimal": "No", + "Comment": [ + "0xdf 11b 0xf6 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x6 (6)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1280]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x21, x0", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "lsl x22, x22, #29", + "orr w22, w22, w23, lsl #30", + "mov w23, #0x1", + "eor w21, w21, #0x1", + "strb w21, [x28, #706]", + "ldrb w21, [x28, #1010]", + "lsl w23, w23, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "str w22, [x28, #728]" + ] + }, + "fcomip st7": { + "ExpectedInstructionCount": 71, + "Optimal": "No", + "Comment": [ + "0xdf 11b 0xf7 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x7 (7)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1280]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov x21, x0", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "lsl x22, x22, #29", + "orr w22, w22, w23, lsl #30", + "mov w23, #0x1", + "eor w21, w21, #0x1", + "strb w21, [x28, #706]", + "ldrb w21, [x28, #1010]", + "lsl w23, w23, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "str w22, [x28, #728]" + ] + } + } +} diff --git a/unittests/InstructionCountCI/FlagM/x87_f64.json b/unittests/InstructionCountCI/FlagM/x87_f64.json new file mode 100644 index 000000000..a67c0dc90 --- /dev/null +++ b/unittests/InstructionCountCI/FlagM/x87_f64.json @@ -0,0 +1,11704 @@ +{ + "Features": { + "Env": { + "FEX_X87REDUCEDPRECISION": "1" + }, + "Bitness": 64, + "EnabledHostFeatures": [ + "FLAGM", + "FLAGM2" + ], + "DisabledHostFeatures": [ + "SVE128", + "SVE256", + "AFP" + ] + }, + "Instructions": { + "fadd dword [rax]": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": [ + "0xd8 !11b /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldr s2, [x4]", + "fcvt d2, s2", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fadd d2, d3, d2", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fmul dword [rax]": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": [ + "0xd8 !11b /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldr s2, [x4]", + "fcvt d2, s2", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fmul d2, d3, d2", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fcom dword [rax]": { + "ExpectedInstructionCount": 22, + "Optimal": "No", + "Comment": [ + "0xd8 !11b /2" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldr s2, [x4]", + "fcvt d2, s2", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fcmp d3, d2", + "cset x20, eq", + "csinc x20, x20, xzr, vc", + "cset x1, lt", + "bfi x20, x1, #1, #1", + "cset x1, vs", + "bfi x20, x1, #2, #1", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "strb w21, [x28, #744]", + "mov w21, #0x0", + "strb w21, [x28, #745]", + "strb w20, [x28, #746]", + "strb w22, [x28, #750]" + ] + }, + "fcomp dword [rax]": { + "ExpectedInstructionCount": 30, + "Optimal": "No", + "Comment": [ + "0xd8 !11b /3" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldr s2, [x4]", + "fcvt d2, s2", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fcmp d3, d2", + "cset x21, eq", + "csinc x21, x21, xzr, vc", + "cset x1, lt", + "bfi x21, x1, #1, #1", + "cset x1, vs", + "bfi x21, x1, #2, #1", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "strb w22, [x28, #744]", + "mov w22, #0x0", + "strb w22, [x28, #745]", + "strb w21, [x28, #746]", + "strb w23, [x28, #750]", + "ldrb w21, [x28, #1010]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "fsub dword [rax]": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": [ + "0xd8 !11b /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldr s2, [x4]", + "fcvt d2, s2", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fsub d2, d3, d2", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fsubr dword [rax]": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": [ + "0xd8 !11b /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldr s2, [x4]", + "fcvt d2, s2", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fsub d2, d2, d3", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fdiv dword [rax]": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": [ + "0xd8 !11b /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldr s2, [x4]", + "fcvt d2, s2", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fdiv d2, d3, d2", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fdivr dword [rax]": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": [ + "0xd8 !11b /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldr s2, [x4]", + "fcvt d2, s2", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fdiv d2, d2, d3", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fadd st0, st0": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xc0 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x0 (0)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fadd d2, d3, d2", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fadd st0, st1": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xc1 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fadd d2, d3, d2", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fadd st0, st2": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xc2 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fadd d2, d3, d2", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fadd st0, st3": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xc3 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fadd d2, d3, d2", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fadd st0, st4": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xc4 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x4 (4)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fadd d2, d3, d2", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fadd st0, st5": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xc5 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x5 (5)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fadd d2, d3, d2", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fadd st0, st6": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xc6 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x6 (6)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fadd d2, d3, d2", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fadd st0, st7": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xc7 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x7 (7)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fadd d2, d3, d2", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fmul st0, st0": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xc8 /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x0 (0)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fmul d2, d3, d2", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fmul st0, st1": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xc9 /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fmul d2, d3, d2", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fmul st0, st2": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xca /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fmul d2, d3, d2", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fmul st0, st3": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xcb /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fmul d2, d3, d2", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fmul st0, st4": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xcc /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x4 (4)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fmul d2, d3, d2", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fmul st0, st5": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xcd /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x5 (5)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fmul d2, d3, d2", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fmul st0, st6": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xce /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x6 (6)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fmul d2, d3, d2", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fmul st0, st7": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xcf /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x7 (7)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fmul d2, d3, d2", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fcom st0, st0": { + "ExpectedInstructionCount": 24, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xd0 /2" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "mov w21, #0x0", + "add w22, w20, #0x0 (0)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fcmp d3, d2", + "cset x20, eq", + "csinc x20, x20, xzr, vc", + "cset x1, lt", + "bfi x20, x1, #1, #1", + "cset x1, vs", + "bfi x20, x1, #2, #1", + "ubfx x22, x20, #1, #1", + "ubfx x23, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w22, w22, w20", + "orr w23, w23, w20", + "strb w22, [x28, #744]", + "strb w21, [x28, #745]", + "strb w20, [x28, #746]", + "strb w23, [x28, #750]" + ] + }, + "fcom st0, st1": { + "ExpectedInstructionCount": 24, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xd1 /2" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fcmp d3, d2", + "cset x20, eq", + "csinc x20, x20, xzr, vc", + "cset x1, lt", + "bfi x20, x1, #1, #1", + "cset x1, vs", + "bfi x20, x1, #2, #1", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "strb w21, [x28, #744]", + "mov w21, #0x0", + "strb w21, [x28, #745]", + "strb w20, [x28, #746]", + "strb w22, [x28, #750]" + ] + }, + "fcom st0, st2": { + "ExpectedInstructionCount": 24, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xd2 /2" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fcmp d3, d2", + "cset x20, eq", + "csinc x20, x20, xzr, vc", + "cset x1, lt", + "bfi x20, x1, #1, #1", + "cset x1, vs", + "bfi x20, x1, #2, #1", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "strb w21, [x28, #744]", + "mov w21, #0x0", + "strb w21, [x28, #745]", + "strb w20, [x28, #746]", + "strb w22, [x28, #750]" + ] + }, + "fcom st0, st3": { + "ExpectedInstructionCount": 24, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xd3 /2" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fcmp d3, d2", + "cset x20, eq", + "csinc x20, x20, xzr, vc", + "cset x1, lt", + "bfi x20, x1, #1, #1", + "cset x1, vs", + "bfi x20, x1, #2, #1", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "strb w21, [x28, #744]", + "mov w21, #0x0", + "strb w21, [x28, #745]", + "strb w20, [x28, #746]", + "strb w22, [x28, #750]" + ] + }, + "fcom st0, st4": { + "ExpectedInstructionCount": 24, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xd4 /2" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x4 (4)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fcmp d3, d2", + "cset x20, eq", + "csinc x20, x20, xzr, vc", + "cset x1, lt", + "bfi x20, x1, #1, #1", + "cset x1, vs", + "bfi x20, x1, #2, #1", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "strb w21, [x28, #744]", + "mov w21, #0x0", + "strb w21, [x28, #745]", + "strb w20, [x28, #746]", + "strb w22, [x28, #750]" + ] + }, + "fcom st0, st5": { + "ExpectedInstructionCount": 24, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xd5 /2" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x5 (5)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fcmp d3, d2", + "cset x20, eq", + "csinc x20, x20, xzr, vc", + "cset x1, lt", + "bfi x20, x1, #1, #1", + "cset x1, vs", + "bfi x20, x1, #2, #1", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "strb w21, [x28, #744]", + "mov w21, #0x0", + "strb w21, [x28, #745]", + "strb w20, [x28, #746]", + "strb w22, [x28, #750]" + ] + }, + "fcom st0, st6": { + "ExpectedInstructionCount": 24, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xd6 /2" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x6 (6)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fcmp d3, d2", + "cset x20, eq", + "csinc x20, x20, xzr, vc", + "cset x1, lt", + "bfi x20, x1, #1, #1", + "cset x1, vs", + "bfi x20, x1, #2, #1", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "strb w21, [x28, #744]", + "mov w21, #0x0", + "strb w21, [x28, #745]", + "strb w20, [x28, #746]", + "strb w22, [x28, #750]" + ] + }, + "fcom st0, st7": { + "ExpectedInstructionCount": 24, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xd7 /2" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x7 (7)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fcmp d3, d2", + "cset x20, eq", + "csinc x20, x20, xzr, vc", + "cset x1, lt", + "bfi x20, x1, #1, #1", + "cset x1, vs", + "bfi x20, x1, #2, #1", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "strb w21, [x28, #744]", + "mov w21, #0x0", + "strb w21, [x28, #745]", + "strb w20, [x28, #746]", + "strb w22, [x28, #750]" + ] + }, + "fcomp st0, st0": { + "ExpectedInstructionCount": 32, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xd8 /3" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "mov w21, #0x0", + "add w22, w20, #0x0 (0)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fcmp d3, d2", + "cset x22, eq", + "csinc x22, x22, xzr, vc", + "cset x1, lt", + "bfi x22, x1, #1, #1", + "cset x1, vs", + "bfi x22, x1, #2, #1", + "ubfx x23, x22, #1, #1", + "ubfx x24, x22, #0, #1", + "ubfx x22, x22, #2, #1", + "orr w23, w23, w22", + "orr w24, w24, w22", + "strb w23, [x28, #744]", + "strb w21, [x28, #745]", + "strb w22, [x28, #746]", + "strb w24, [x28, #750]", + "ldrb w21, [x28, #1010]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "fcomp st0, st1": { + "ExpectedInstructionCount": 32, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xd9 /3" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "mov w21, #0x1", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fcmp d3, d2", + "cset x22, eq", + "csinc x22, x22, xzr, vc", + "cset x1, lt", + "bfi x22, x1, #1, #1", + "cset x1, vs", + "bfi x22, x1, #2, #1", + "ubfx x23, x22, #1, #1", + "ubfx x24, x22, #0, #1", + "ubfx x22, x22, #2, #1", + "orr w23, w23, w22", + "orr w24, w24, w22", + "strb w23, [x28, #744]", + "mov w23, #0x0", + "strb w23, [x28, #745]", + "strb w22, [x28, #746]", + "strb w24, [x28, #750]", + "ldrb w22, [x28, #1010]", + "lsl w21, w21, w20", + "bic w21, w22, w21", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "fcomp st0, st2": { + "ExpectedInstructionCount": 32, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xda /3" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fcmp d3, d2", + "cset x21, eq", + "csinc x21, x21, xzr, vc", + "cset x1, lt", + "bfi x21, x1, #1, #1", + "cset x1, vs", + "bfi x21, x1, #2, #1", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "strb w22, [x28, #744]", + "mov w22, #0x0", + "strb w22, [x28, #745]", + "strb w21, [x28, #746]", + "strb w23, [x28, #750]", + "ldrb w21, [x28, #1010]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "fcomp st0, st3": { + "ExpectedInstructionCount": 32, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xdb /3" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fcmp d3, d2", + "cset x21, eq", + "csinc x21, x21, xzr, vc", + "cset x1, lt", + "bfi x21, x1, #1, #1", + "cset x1, vs", + "bfi x21, x1, #2, #1", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "strb w22, [x28, #744]", + "mov w22, #0x0", + "strb w22, [x28, #745]", + "strb w21, [x28, #746]", + "strb w23, [x28, #750]", + "ldrb w21, [x28, #1010]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "fcomp st0, st4": { + "ExpectedInstructionCount": 32, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xdc /3" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x4 (4)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fcmp d3, d2", + "cset x21, eq", + "csinc x21, x21, xzr, vc", + "cset x1, lt", + "bfi x21, x1, #1, #1", + "cset x1, vs", + "bfi x21, x1, #2, #1", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "strb w22, [x28, #744]", + "mov w22, #0x0", + "strb w22, [x28, #745]", + "strb w21, [x28, #746]", + "strb w23, [x28, #750]", + "ldrb w21, [x28, #1010]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "fcomp st0, st5": { + "ExpectedInstructionCount": 32, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xdd /3" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x5 (5)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fcmp d3, d2", + "cset x21, eq", + "csinc x21, x21, xzr, vc", + "cset x1, lt", + "bfi x21, x1, #1, #1", + "cset x1, vs", + "bfi x21, x1, #2, #1", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "strb w22, [x28, #744]", + "mov w22, #0x0", + "strb w22, [x28, #745]", + "strb w21, [x28, #746]", + "strb w23, [x28, #750]", + "ldrb w21, [x28, #1010]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "fcomp st0, st6": { + "ExpectedInstructionCount": 32, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xde /3" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x6 (6)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fcmp d3, d2", + "cset x21, eq", + "csinc x21, x21, xzr, vc", + "cset x1, lt", + "bfi x21, x1, #1, #1", + "cset x1, vs", + "bfi x21, x1, #2, #1", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "strb w22, [x28, #744]", + "mov w22, #0x0", + "strb w22, [x28, #745]", + "strb w21, [x28, #746]", + "strb w23, [x28, #750]", + "ldrb w21, [x28, #1010]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "fcomp st0, st7": { + "ExpectedInstructionCount": 32, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xdf /3" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x7 (7)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fcmp d3, d2", + "cset x21, eq", + "csinc x21, x21, xzr, vc", + "cset x1, lt", + "bfi x21, x1, #1, #1", + "cset x1, vs", + "bfi x21, x1, #2, #1", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "strb w22, [x28, #744]", + "mov w22, #0x0", + "strb w22, [x28, #745]", + "strb w21, [x28, #746]", + "strb w23, [x28, #750]", + "ldrb w21, [x28, #1010]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "fsub st0, st0": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xe0 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x0 (0)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fsub d2, d2, d3", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fsub st0, st1": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xe1 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fsub d2, d3, d2", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fsub st0, st2": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xe2 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fsub d2, d3, d2", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fsub st0, st3": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xe3 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fsub d2, d3, d2", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fsub st0, st4": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xe4 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x4 (4)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fsub d2, d3, d2", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fsub st0, st5": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xe5 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x5 (5)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fsub d2, d3, d2", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fsub st0, st6": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xe6 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x6 (6)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fsub d2, d3, d2", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fsub st0, st7": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xe7 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x7 (7)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fsub d2, d3, d2", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fsubr st0, st0": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xe8 /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x0 (0)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fsub d2, d3, d2", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fsubr st0, st1": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xe9 /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fsub d2, d2, d3", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fsubr st0, st2": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xea /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fsub d2, d2, d3", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fsubr st0, st3": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xeb /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fsub d2, d2, d3", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fsubr st0, st4": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xec /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x4 (4)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fsub d2, d2, d3", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fsubr st0, st5": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xed /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x5 (5)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fsub d2, d2, d3", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fsubr st0, st6": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xee /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x6 (6)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fsub d2, d2, d3", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fsubr st0, st7": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xef /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x7 (7)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fsub d2, d2, d3", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fdiv st0, st0": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xf0 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x0 (0)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fdiv d2, d2, d3", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fdiv st0, st1": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xf1 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fdiv d2, d3, d2", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fdiv st0, st2": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xf2 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fdiv d2, d3, d2", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fdiv st0, st3": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xf3 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fdiv d2, d3, d2", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fdiv st0, st4": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xf4 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x4 (4)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fdiv d2, d3, d2", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fdiv st0, st5": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xf5 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x5 (5)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fdiv d2, d3, d2", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fdiv st0, st6": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xf6 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x6 (6)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fdiv d2, d3, d2", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fdiv st0, st7": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xf7 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x7 (7)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fdiv d2, d3, d2", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fdivr st0, st0": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xf8 /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x0 (0)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fdiv d2, d3, d2", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fdivr st0, st1": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xf9 /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fdiv d2, d2, d3", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fdivr st0, st2": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xfa /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fdiv d2, d2, d3", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fdivr st0, st3": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xfb /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fdiv d2, d2, d3", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fdivr st0, st4": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xfc /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x4 (4)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fdiv d2, d2, d3", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fdivr st0, st5": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xfd /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x5 (5)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fdiv d2, d2, d3", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fdivr st0, st6": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xfe /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x6 (6)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fdiv d2, d2, d3", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fdivr st0, st7": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xff /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x7 (7)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fdiv d2, d2, d3", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fld dword [rax]": { + "ExpectedInstructionCount": 13, + "Optimal": "No", + "Comment": [ + "0xd9 !11b /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldr s2, [x4]", + "fcvt d2, s2", + "mov w21, #0x1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "ldrb w22, [x28, #1010]", + "lsl w21, w21, w20", + "orr w21, w22, w21", + "strb w21, [x28, #1010]", + "strb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fst dword [rax]": { + "ExpectedInstructionCount": 5, + "Optimal": "No", + "Comment": [ + "0xd9 !11b /2" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #752]", + "fcvt s2, d2", + "str s2, [x4]" + ] + }, + "fstp dword [rax]": { + "ExpectedInstructionCount": 13, + "Optimal": "No", + "Comment": [ + "0xd9 !11b /3" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #752]", + "fcvt s2, d2", + "str s2, [x4]", + "ldrb w21, [x28, #1010]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "fldenv [rax]": { + "ExpectedInstructionCount": 54, + "Optimal": "No", + "Comment": [ + "0xd9 !11b /4" + ], + "ExpectedArm64ASM": [ + "ldrh w20, [x4]", + "ubfx w21, w20, #10, #3", + "rbit w1, w21", + "lsr w1, w1, #30", + "mrs x0, fpcr", + "bfi x0, x1, #22, #2", + "lsr x1, x21, #2", + "bfi x0, x1, #24, #1", + "msr fpcr, x0", + "strh w20, [x28, #1008]", + "ldr w20, [x4, #4]", + "ubfx w21, w20, #11, #3", + "strb w21, [x28, #747]", + "ubfx w21, w20, #8, #1", + "ubfx w22, w20, #9, #1", + "ubfx w23, w20, #10, #1", + "ubfx w20, w20, #14, #1", + "strb w21, [x28, #744]", + "strb w22, [x28, #745]", + "strb w23, [x28, #746]", + "strb w20, [x28, #750]", + "ldr w20, [x4, #8]", + "ubfx w21, w20, #0, #2", + "cmp x21, #0x3 (3)", + "cset x21, ne", + "ubfx w22, w20, #2, #2", + "cmp x22, #0x3 (3)", + "cset x22, ne", + "orr w21, w21, w22, lsl #1", + "ubfx w22, w20, #4, #2", + "cmp x22, #0x3 (3)", + "cset x22, ne", + "orr w21, w21, w22, lsl #2", + "ubfx w22, w20, #6, #2", + "cmp x22, #0x3 (3)", + "cset x22, ne", + "orr w21, w21, w22, lsl #3", + "ubfx w22, w20, #8, #2", + "cmp x22, #0x3 (3)", + "cset x22, ne", + "orr w21, w21, w22, lsl #4", + "ubfx w22, w20, #10, #2", + "cmp x22, #0x3 (3)", + "cset x22, ne", + "orr w21, w21, w22, lsl #5", + "ubfx w22, w20, #12, #2", + "cmp x22, #0x3 (3)", + "cset x22, ne", + "orr w21, w21, w22, lsl #6", + "ubfx w20, w20, #14, #2", + "cmp x20, #0x3 (3)", + "cset x20, ne", + "orr w20, w21, w20, lsl #7", + "strb w20, [x28, #1010]" + ] + }, + "fldcw [rax]": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "0xd9 !11b /5" + ], + "ExpectedArm64ASM": [ + "ldrh w20, [x4]", + "ubfx w21, w20, #10, #3", + "rbit w1, w21", + "lsr w1, w1, #30", + "mrs x0, fpcr", + "bfi x0, x1, #22, #2", + "lsr x1, x21, #2", + "bfi x0, x1, #24, #1", + "msr fpcr, x0", + "strh w20, [x28, #1008]" + ] + }, + "fnstenv [rax]": { + "ExpectedInstructionCount": 62, + "Optimal": "No", + "Comment": [ + "0xd9 !11b /6" + ], + "ExpectedArm64ASM": [ + "ldrh w20, [x28, #1008]", + "str w20, [x4]", + "mov w20, #0x0", + "ldrb w21, [x28, #747]", + "mov x0, x20", + "bfi x0, x21, #11, #3", + "mov x21, x0", + "ldrb w22, [x28, #744]", + "ldrb w23, [x28, #745]", + "ldrb w24, [x28, #746]", + "ldrb w25, [x28, #750]", + "orr x21, x21, x22, lsl #8", + "orr x21, x21, x23, lsl #9", + "orr x21, x21, x24, lsl #10", + "orr x21, x21, x25, lsl #14", + "str w21, [x4, #4]", + "ldrb w21, [x28, #1010]", + "and w22, w21, #0x1", + "mov w23, #0x3", + "cmp x22, #0x0 (0)", + "csel x22, x23, x20, eq", + "orr w22, w20, w22", + "lsr w24, w21, #1", + "and w24, w24, #0x1", + "cmp x24, #0x0 (0)", + "csel x24, x23, x20, eq", + "orr w22, w22, w24, lsl #2", + "lsr w24, w21, #2", + "and w24, w24, #0x1", + "cmp x24, #0x0 (0)", + "csel x24, x23, x20, eq", + "orr w22, w22, w24, lsl #4", + "lsr w24, w21, #3", + "and w24, w24, #0x1", + "cmp x24, #0x0 (0)", + "csel x24, x23, x20, eq", + "orr w22, w22, w24, lsl #6", + "lsr w24, w21, #4", + "and w24, w24, #0x1", + "cmp x24, #0x0 (0)", + "csel x24, x23, x20, eq", + "orr w22, w22, w24, lsl #8", + "lsr w24, w21, #5", + "and w24, w24, #0x1", + "cmp x24, #0x0 (0)", + "csel x24, x23, x20, eq", + "orr w22, w22, w24, lsl #10", + "lsr w24, w21, #6", + "and w24, w24, #0x1", + "cmp x24, #0x0 (0)", + "csel x24, x23, x20, eq", + "orr w22, w22, w24, lsl #12", + "lsr w21, w21, #7", + "and w21, w21, #0x1", + "cmp x21, #0x0 (0)", + "csel x21, x23, x20, eq", + "orr w21, w22, w21, lsl #14", + "str w21, [x4, #8]", + "str w20, [x4, #12]", + "str w20, [x4, #16]", + "str w20, [x4, #20]", + "str w20, [x4, #24]" + ] + }, + "fnstcw [rax]": { + "ExpectedInstructionCount": 2, + "Optimal": "Yes", + "Comment": [ + "0xd9 !11b /7" + ], + "ExpectedArm64ASM": [ + "ldrh w20, [x28, #1008]", + "strh w20, [x4]" + ] + }, + "fld st0": { + "ExpectedInstructionCount": 15, + "Optimal": "No", + "Comment": [ + "0xd9 11b 0xc0 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x0 (0)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "mov w21, #0x1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "ldrb w22, [x28, #1010]", + "lsl w21, w21, w20", + "orr w21, w22, w21", + "strb w21, [x28, #1010]", + "strb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fld st1": { + "ExpectedInstructionCount": 15, + "Optimal": "No", + "Comment": [ + "0xd9 11b 0xc1 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "mov w21, #0x1", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr d2, [x0, #752]", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "ldrb w22, [x28, #1010]", + "lsl w21, w21, w20", + "orr w21, w22, w21", + "strb w21, [x28, #1010]", + "strb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fld st2": { + "ExpectedInstructionCount": 15, + "Optimal": "No", + "Comment": [ + "0xd9 11b 0xc2 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "mov w21, #0x1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "ldrb w22, [x28, #1010]", + "lsl w21, w21, w20", + "orr w21, w22, w21", + "strb w21, [x28, #1010]", + "strb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fld st3": { + "ExpectedInstructionCount": 15, + "Optimal": "No", + "Comment": [ + "0xd9 11b 0xc3 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "mov w21, #0x1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "ldrb w22, [x28, #1010]", + "lsl w21, w21, w20", + "orr w21, w22, w21", + "strb w21, [x28, #1010]", + "strb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fld st4": { + "ExpectedInstructionCount": 15, + "Optimal": "No", + "Comment": [ + "0xd9 11b 0xc4 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x4 (4)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "mov w21, #0x1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "ldrb w22, [x28, #1010]", + "lsl w21, w21, w20", + "orr w21, w22, w21", + "strb w21, [x28, #1010]", + "strb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fld st5": { + "ExpectedInstructionCount": 15, + "Optimal": "No", + "Comment": [ + "0xd9 11b 0xc5 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x5 (5)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "mov w21, #0x1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "ldrb w22, [x28, #1010]", + "lsl w21, w21, w20", + "orr w21, w22, w21", + "strb w21, [x28, #1010]", + "strb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fld st6": { + "ExpectedInstructionCount": 15, + "Optimal": "No", + "Comment": [ + "0xd9 11b 0xc6 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x6 (6)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "mov w21, #0x1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "ldrb w22, [x28, #1010]", + "lsl w21, w21, w20", + "orr w21, w22, w21", + "strb w21, [x28, #1010]", + "strb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fld st7": { + "ExpectedInstructionCount": 15, + "Optimal": "No", + "Comment": [ + "0xd9 11b 0xc7 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x7 (7)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "mov w21, #0x1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "ldrb w22, [x28, #1010]", + "lsl w21, w21, w20", + "orr w21, w22, w21", + "strb w21, [x28, #1010]", + "strb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fxch st0, st0": { + "ExpectedInstructionCount": 11, + "Optimal": "No", + "Comment": [ + "0xd9 11b 0xc8 /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x0 (0)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x20, lsl #4", + "str q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fxch st0, st1": { + "ExpectedInstructionCount": 11, + "Optimal": "No", + "Comment": [ + "0xd9 11b 0xc9 /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x20, lsl #4", + "str q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fxch st0, st2": { + "ExpectedInstructionCount": 11, + "Optimal": "No", + "Comment": [ + "0xd9 11b 0xca /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x20, lsl #4", + "str q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fxch st0, st3": { + "ExpectedInstructionCount": 11, + "Optimal": "No", + "Comment": [ + "0xd9 11b 0xcb /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x20, lsl #4", + "str q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fxch st0, st4": { + "ExpectedInstructionCount": 11, + "Optimal": "No", + "Comment": [ + "0xd9 11b 0xcc /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x4 (4)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x20, lsl #4", + "str q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fxch st0, st5": { + "ExpectedInstructionCount": 11, + "Optimal": "No", + "Comment": [ + "0xd9 11b 0xcd /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x5 (5)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x20, lsl #4", + "str q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fxch st0, st6": { + "ExpectedInstructionCount": 11, + "Optimal": "No", + "Comment": [ + "0xd9 11b 0xce /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x6 (6)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x20, lsl #4", + "str q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fxch st0, st7": { + "ExpectedInstructionCount": 11, + "Optimal": "No", + "Comment": [ + "0xd9 11b 0xcf /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x7 (7)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x20, lsl #4", + "str q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fnop": { + "ExpectedInstructionCount": 0, + "Optimal": "Yes", + "Comment": [ + "0xd9 11b 0xd0 /2" + ], + "ExpectedArm64ASM": [] + }, + "fchs": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "0xd9 11b 0xe0 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #752]", + "fneg v2.2d, v2.2d", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fabs": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "0xd9 11b 0xe1 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #752]", + "fabs d2, d2", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "ftst": { + "ExpectedInstructionCount": 21, + "Optimal": "No", + "Comment": [ + "0xd9 11b 0xe4 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #752]", + "mov w20, #0x0", + "fmov d3, x20", + "fcmp d2, d3", + "cset x21, eq", + "csinc x21, x21, xzr, vc", + "cset x1, lt", + "bfi x21, x1, #1, #1", + "cset x1, vs", + "bfi x21, x1, #2, #1", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "strb w22, [x28, #744]", + "strb w20, [x28, #745]", + "strb w21, [x28, #746]", + "strb w23, [x28, #750]" + ] + }, + "fxam": { + "ExpectedInstructionCount": 16, + "Optimal": "No", + "Comment": [ + "0xd9 11b 0xe5 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #752]", + "mov x21, v2.d[0]", + "lsr x21, x21, #63", + "strb w21, [x28, #745]", + "ldrb w21, [x28, #1010]", + "lsr w20, w21, w20", + "mov w21, #0x1", + "and w20, w20, #0x1", + "mov w22, #0x0", + "cmp x20, #0x1 (1)", + "csel x21, x22, x21, eq", + "strb w21, [x28, #744]", + "strb w20, [x28, #746]", + "strb w21, [x28, #750]" + ] + }, + "fld1": { + "ExpectedInstructionCount": 13, + "Optimal": "No", + "Comment": [ + "0xd9 11b 0xe8 /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "mov w21, #0x1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "ldrb w22, [x28, #1010]", + "lsl w21, w21, w20", + "orr w21, w22, w21", + "strb w21, [x28, #1010]", + "strb w20, [x28, #747]", + "mov x21, #0x3ff0000000000000", + "fmov d2, x21", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fldl2t": { + "ExpectedInstructionCount": 16, + "Optimal": "No", + "Comment": [ + "0xd9 11b 0xe9 /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "mov w21, #0x1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "ldrb w22, [x28, #1010]", + "lsl w21, w21, w20", + "orr w21, w22, w21", + "strb w21, [x28, #1010]", + "strb w20, [x28, #747]", + "mov x21, #0xa372", + "movk x21, #0x979, lsl #16", + "movk x21, #0x934f, lsl #32", + "movk x21, #0x400a, lsl #48", + "fmov d2, x21", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fldl2e": { + "ExpectedInstructionCount": 16, + "Optimal": "No", + "Comment": [ + "0xd9 11b 0xea /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "mov w21, #0x1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "ldrb w22, [x28, #1010]", + "lsl w21, w21, w20", + "orr w21, w22, w21", + "strb w21, [x28, #1010]", + "strb w20, [x28, #747]", + "mov x21, #0x82fe", + "movk x21, #0x652b, lsl #16", + "movk x21, #0x1547, lsl #32", + "movk x21, #0x3ff7, lsl #48", + "fmov d2, x21", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fldpi": { + "ExpectedInstructionCount": 16, + "Optimal": "No", + "Comment": [ + "0xd9 11b 0xeb /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "mov w21, #0x1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "ldrb w22, [x28, #1010]", + "lsl w21, w21, w20", + "orr w21, w22, w21", + "strb w21, [x28, #1010]", + "strb w20, [x28, #747]", + "mov x21, #0x2d18", + "movk x21, #0x5444, lsl #16", + "movk x21, #0x21fb, lsl #32", + "movk x21, #0x4009, lsl #48", + "fmov d2, x21", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fldlg2": { + "ExpectedInstructionCount": 16, + "Optimal": "No", + "Comment": [ + "0xd9 11b 0xec /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "mov w21, #0x1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "ldrb w22, [x28, #1010]", + "lsl w21, w21, w20", + "orr w21, w22, w21", + "strb w21, [x28, #1010]", + "strb w20, [x28, #747]", + "mov x21, #0x79ff", + "movk x21, #0x509f, lsl #16", + "movk x21, #0x4413, lsl #32", + "movk x21, #0x3fd3, lsl #48", + "fmov d2, x21", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fldln2": { + "ExpectedInstructionCount": 16, + "Optimal": "No", + "Comment": [ + "0xd9 11b 0xed /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "mov w21, #0x1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "ldrb w22, [x28, #1010]", + "lsl w21, w21, w20", + "orr w21, w22, w21", + "strb w21, [x28, #1010]", + "strb w20, [x28, #747]", + "mov x21, #0x39ef", + "movk x21, #0xfefa, lsl #16", + "movk x21, #0x2e42, lsl #32", + "movk x21, #0x3fe6, lsl #48", + "fmov d2, x21", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fldz": { + "ExpectedInstructionCount": 13, + "Optimal": "No", + "Comment": [ + "0xd9 11b 0xee /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "mov w21, #0x1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "ldrb w22, [x28, #1010]", + "lsl w21, w21, w20", + "orr w21, w22, w21", + "strb w21, [x28, #1010]", + "strb w20, [x28, #747]", + "mov w21, #0x0", + "fmov d2, x21", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "f2xm1": { + "ExpectedInstructionCount": 48, + "Optimal": "No", + "Comment": [ + "0xd9 11b 0xf0 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov v0.8b, v2.8b", + "ldrh w0, [x28, #1008]", + "ldr x1, [x28, #1488]", + "blr x1", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov v2.8b, v0.8b", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fyl2x": { + "ExpectedInstructionCount": 59, + "Optimal": "No", + "Comment": [ + "0xd9 11b 0xf1 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldrb w21, [x28, #1010]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1010]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "strb w21, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr d3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov v0.8b, v2.8b", + "mov v1.8b, v3.8b", + "ldrh w0, [x28, #1008]", + "ldr x1, [x28, #1496]", + "blr x1", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov v2.8b, v0.8b", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fptan": { + "ExpectedInstructionCount": 62, + "Optimal": "No", + "Comment": [ + "0xd9 11b 0xf2 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "mov w21, #0x1", + "sub w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "ldrb w23, [x28, #1010]", + "lsl w21, w21, w22", + "orr w21, w23, w21", + "strb w21, [x28, #1010]", + "strb w22, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov v0.8b, v2.8b", + "ldrh w0, [x28, #1008]", + "ldr x1, [x28, #1472]", + "blr x1", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov v2.8b, v0.8b", + "mov x21, #0x3ff0000000000000", + "fmov d3, x21", + "mov w21, #0x0", + "strb w21, [x28, #746]", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]", + "add x0, x28, x22, lsl #4", + "str d3, [x0, #752]" + ] + }, + "fpatan": { + "ExpectedInstructionCount": 59, + "Optimal": "No", + "Comment": [ + "0xd9 11b 0xf3 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldrb w21, [x28, #1010]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1010]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "strb w21, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr d3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov v0.8b, v3.8b", + "mov v1.8b, v2.8b", + "ldrh w0, [x28, #1008]", + "ldr x1, [x28, #1480]", + "blr x1", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov v2.8b, v0.8b", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fxtract": { + "ExpectedInstructionCount": 23, + "Optimal": "No", + "Comment": [ + "0xd9 11b 0xf4 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "mov w21, #0x1", + "sub w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "ldrb w23, [x28, #1010]", + "lsl w21, w21, w22", + "orr w21, w23, w21", + "strb w21, [x28, #1010]", + "strb w22, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #752]", + "mov x21, v2.d[0]", + "and x23, x21, #0x7ff0000000000000", + "lsr x23, x23, #52", + "sub x23, x23, #0x3ff (1023)", + "scvtf d2, x23", + "and x21, x21, #0x800fffffffffffff", + "orr x21, x21, #0x3ff0000000000000", + "fmov d3, x21", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]", + "add x0, x28, x22, lsl #4", + "str d3, [x0, #752]" + ] + }, + "fprem1": { + "ExpectedInstructionCount": 55, + "Optimal": "No", + "Comment": [ + "0xd9 11b 0xf5 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr d3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov v0.8b, v2.8b", + "mov v1.8b, v3.8b", + "ldrh w0, [x28, #1008]", + "ldr x1, [x28, #1512]", + "blr x1", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov v2.8b, v0.8b", + "mov w21, #0x0", + "strb w21, [x28, #746]", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fdecstp": { + "ExpectedInstructionCount": 4, + "Optimal": "Yes", + "Comment": [ + "0xd9 11b 0xf6 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "fincstp": { + "ExpectedInstructionCount": 4, + "Optimal": "Yes", + "Comment": [ + "0xd9 11b 0xf7 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "fprem": { + "ExpectedInstructionCount": 55, + "Optimal": "No", + "Comment": [ + "0xd9 11b 0xf8 /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr d3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov v0.8b, v2.8b", + "mov v1.8b, v3.8b", + "ldrh w0, [x28, #1008]", + "ldr x1, [x28, #1504]", + "blr x1", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov v2.8b, v0.8b", + "mov w21, #0x0", + "strb w21, [x28, #746]", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fyl2xp1": { + "ExpectedInstructionCount": 62, + "Optimal": "No", + "Comment": [ + "0xd9 11b 0xf9 /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldrb w21, [x28, #1010]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1010]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "strb w21, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr d3, [x0, #752]", + "mov x20, #0x3ff0000000000000", + "fmov d4, x20", + "fadd d2, d2, d4", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov v0.8b, v2.8b", + "mov v1.8b, v3.8b", + "ldrh w0, [x28, #1008]", + "ldr x1, [x28, #1496]", + "blr x1", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov v2.8b, v0.8b", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fsqrt": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "0xd9 11b 0xfa /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #752]", + "fsqrt d2, d2", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fsincos": { + "ExpectedInstructionCount": 103, + "Optimal": "No", + "Comment": [ + "0xd9 11b 0xfb /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "mov w21, #0x1", + "sub w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "ldrb w23, [x28, #1010]", + "lsl w21, w21, w22", + "orr w21, w23, w21", + "strb w21, [x28, #1010]", + "strb w22, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov v0.8b, v2.8b", + "ldrh w0, [x28, #1008]", + "ldr x1, [x28, #1456]", + "blr x1", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov v3.8b, v0.8b", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov v0.8b, v2.8b", + "ldrh w0, [x28, #1008]", + "ldr x1, [x28, #1464]", + "blr x1", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov v2.8b, v0.8b", + "mov w21, #0x0", + "strb w21, [x28, #746]", + "add x0, x28, x20, lsl #4", + "str d3, [x0, #752]", + "add x0, x28, x22, lsl #4", + "str d2, [x0, #752]" + ] + }, + "frndint": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "0xd9 11b 0xfc /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #752]", + "frinti d2, d2", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fscale": { + "ExpectedInstructionCount": 53, + "Optimal": "No", + "Comment": [ + "0xd9 11b 0xfd /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr d3, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov v0.8b, v2.8b", + "mov v1.8b, v3.8b", + "ldrh w0, [x28, #1008]", + "ldr x1, [x28, #1520]", + "blr x1", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov v2.8b, v0.8b", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fsin": { + "ExpectedInstructionCount": 50, + "Optimal": "No", + "Comment": [ + "0xd9 11b 0xfe /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov v0.8b, v2.8b", + "ldrh w0, [x28, #1008]", + "ldr x1, [x28, #1456]", + "blr x1", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov v2.8b, v0.8b", + "mov w21, #0x0", + "strb w21, [x28, #746]", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fcos": { + "ExpectedInstructionCount": 50, + "Optimal": "No", + "Comment": [ + "0xd9 11b 0xff /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov v0.8b, v2.8b", + "ldrh w0, [x28, #1008]", + "ldr x1, [x28, #1464]", + "blr x1", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov v2.8b, v0.8b", + "mov w21, #0x0", + "strb w21, [x28, #746]", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fiadd dword [rax]": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": [ + "0xda !11b /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldr w21, [x4]", + "scvtf d2, w21", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fadd d2, d3, d2", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fimul dword [rax]": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": [ + "0xda !11b /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldr w21, [x4]", + "scvtf d2, w21", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fmul d2, d3, d2", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "ficom dword [rax]": { + "ExpectedInstructionCount": 22, + "Optimal": "No", + "Comment": [ + "0xda !11b /2" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldr w21, [x4]", + "scvtf d2, w21", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fcmp d3, d2", + "cset x20, eq", + "csinc x20, x20, xzr, vc", + "cset x1, lt", + "bfi x20, x1, #1, #1", + "cset x1, vs", + "bfi x20, x1, #2, #1", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "strb w21, [x28, #744]", + "mov w21, #0x0", + "strb w21, [x28, #745]", + "strb w20, [x28, #746]", + "strb w22, [x28, #750]" + ] + }, + "ficomp dword [rax]": { + "ExpectedInstructionCount": 30, + "Optimal": "No", + "Comment": [ + "0xda !11b /3" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldr w21, [x4]", + "scvtf d2, w21", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fcmp d3, d2", + "cset x21, eq", + "csinc x21, x21, xzr, vc", + "cset x1, lt", + "bfi x21, x1, #1, #1", + "cset x1, vs", + "bfi x21, x1, #2, #1", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "strb w22, [x28, #744]", + "mov w22, #0x0", + "strb w22, [x28, #745]", + "strb w21, [x28, #746]", + "strb w23, [x28, #750]", + "ldrb w21, [x28, #1010]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "fisub dword [rax]": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": [ + "0xda !11b /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldr w21, [x4]", + "scvtf d2, w21", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fsub d2, d3, d2", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fisubr dword [rax]": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": [ + "0xda !11b /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldr w21, [x4]", + "scvtf d2, w21", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fsub d2, d2, d3", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fidiv dword [rax]": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": [ + "0xda !11b /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldr w21, [x4]", + "scvtf d2, w21", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fdiv d2, d3, d2", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fidivr dword [rax]": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": [ + "0xda !11b /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldr w21, [x4]", + "scvtf d2, w21", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fdiv d2, d2, d3", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fcmovb st0, st0": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xda 11b 0xc0 /0" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x20000000", + "csetm x20, ne", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x0 (0)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovb st0, st1": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xda 11b 0xc1 /0" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x20000000", + "csetm x20, ne", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovb st0, st2": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xda 11b 0xc2 /0" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x20000000", + "csetm x20, ne", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovb st0, st3": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xda 11b 0xc3 /0" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x20000000", + "csetm x20, ne", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovb st0, st4": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xda 11b 0xc4 /0" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x20000000", + "csetm x20, ne", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x4 (4)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovb st0, st5": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xda 11b 0xc5 /0" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x20000000", + "csetm x20, ne", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x5 (5)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovb st0, st6": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xda 11b 0xc6 /0" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x20000000", + "csetm x20, ne", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x6 (6)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovb st0, st7": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xda 11b 0xc7 /0" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x20000000", + "csetm x20, ne", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x7 (7)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmove st0, st0": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xda 11b 0xc8 /1" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x40000000", + "csetm x20, ne", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x0 (0)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmove st0, st1": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xda 11b 0xc9 /1" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x40000000", + "csetm x20, ne", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmove st0, st2": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xda 11b 0xca /1" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x40000000", + "csetm x20, ne", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmove st0, st3": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xda 11b 0xcb /1" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x40000000", + "csetm x20, ne", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmove st0, st4": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xda 11b 0xcc /1" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x40000000", + "csetm x20, ne", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x4 (4)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmove st0, st5": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xda 11b 0xcd /1" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x40000000", + "csetm x20, ne", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x5 (5)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmove st0, st6": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xda 11b 0xce /1" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x40000000", + "csetm x20, ne", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x6 (6)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmove st0, st7": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xda 11b 0xcf /1" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x40000000", + "csetm x20, ne", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x7 (7)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovbe st0, st0": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xda 11b 0xd0 /0" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x60000000", + "csetm x20, ne", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x0 (0)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovbe st0, st1": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xda 11b 0xd1 /0" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x60000000", + "csetm x20, ne", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovbe st0, st2": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xda 11b 0xd2 /0" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x60000000", + "csetm x20, ne", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovbe st0, st3": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xda 11b 0xd3 /0" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x60000000", + "csetm x20, ne", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovbe st0, st4": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xda 11b 0xd4 /0" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x60000000", + "csetm x20, ne", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x4 (4)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovbe st0, st5": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xda 11b 0xd5 /0" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x60000000", + "csetm x20, ne", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x5 (5)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovbe st0, st6": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xda 11b 0xd6 /0" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x60000000", + "csetm x20, ne", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x6 (6)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovbe st0, st7": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xda 11b 0xd7 /0" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x60000000", + "csetm x20, ne", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x7 (7)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovu st0, st0": { + "ExpectedInstructionCount": 17, + "Optimal": "No", + "Comment": [ + "0xda 11b 0xd8 /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #706]", + "fmov s2, w20", + "cnt v2.16b, v2.16b", + "umov w20, v2.b[0]", + "tst w20, #0x1", + "csetm x20, eq", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x0 (0)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovu st0, st1": { + "ExpectedInstructionCount": 17, + "Optimal": "No", + "Comment": [ + "0xda 11b 0xd9 /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #706]", + "fmov s2, w20", + "cnt v2.16b, v2.16b", + "umov w20, v2.b[0]", + "tst w20, #0x1", + "csetm x20, eq", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovu st0, st2": { + "ExpectedInstructionCount": 17, + "Optimal": "No", + "Comment": [ + "0xda 11b 0xda /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #706]", + "fmov s2, w20", + "cnt v2.16b, v2.16b", + "umov w20, v2.b[0]", + "tst w20, #0x1", + "csetm x20, eq", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovu st0, st3": { + "ExpectedInstructionCount": 17, + "Optimal": "No", + "Comment": [ + "0xda 11b 0xdb /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #706]", + "fmov s2, w20", + "cnt v2.16b, v2.16b", + "umov w20, v2.b[0]", + "tst w20, #0x1", + "csetm x20, eq", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovu st0, st4": { + "ExpectedInstructionCount": 17, + "Optimal": "No", + "Comment": [ + "0xda 11b 0xdc /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #706]", + "fmov s2, w20", + "cnt v2.16b, v2.16b", + "umov w20, v2.b[0]", + "tst w20, #0x1", + "csetm x20, eq", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x4 (4)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovu st0, st5": { + "ExpectedInstructionCount": 17, + "Optimal": "No", + "Comment": [ + "0xda 11b 0xdd /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #706]", + "fmov s2, w20", + "cnt v2.16b, v2.16b", + "umov w20, v2.b[0]", + "tst w20, #0x1", + "csetm x20, eq", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x5 (5)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovu st0, st6": { + "ExpectedInstructionCount": 17, + "Optimal": "No", + "Comment": [ + "0xda 11b 0xde /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #706]", + "fmov s2, w20", + "cnt v2.16b, v2.16b", + "umov w20, v2.b[0]", + "tst w20, #0x1", + "csetm x20, eq", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x6 (6)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovu st0, st7": { + "ExpectedInstructionCount": 17, + "Optimal": "No", + "Comment": [ + "0xda 11b 0xdf /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #706]", + "fmov s2, w20", + "cnt v2.16b, v2.16b", + "umov w20, v2.b[0]", + "tst w20, #0x1", + "csetm x20, eq", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x7 (7)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fucompp": { + "ExpectedInstructionCount": 37, + "Optimal": "No", + "Comment": [ + "0xda 11b 0xe9 /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "mov w21, #0x1", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fcmp d3, d2", + "cset x22, eq", + "csinc x22, x22, xzr, vc", + "cset x1, lt", + "bfi x22, x1, #1, #1", + "cset x1, vs", + "bfi x22, x1, #2, #1", + "ubfx x23, x22, #1, #1", + "ubfx x24, x22, #0, #1", + "ubfx x22, x22, #2, #1", + "orr w23, w23, w22", + "orr w24, w24, w22", + "strb w23, [x28, #744]", + "mov w23, #0x0", + "strb w23, [x28, #745]", + "strb w22, [x28, #746]", + "strb w24, [x28, #750]", + "ldrb w22, [x28, #1010]", + "lsl w23, w21, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "lsl w21, w21, w20", + "bic w21, w22, w21", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "fild dword [rax]": { + "ExpectedInstructionCount": 13, + "Optimal": "No", + "Comment": [ + "0xdf !11b /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "mov w21, #0x1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "ldrb w22, [x28, #1010]", + "lsl w21, w21, w20", + "orr w21, w22, w21", + "strb w21, [x28, #1010]", + "strb w20, [x28, #747]", + "ldr w21, [x4]", + "scvtf d2, w21", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fisttp dword [rax]": { + "ExpectedInstructionCount": 13, + "Optimal": "No", + "Comment": [ + "0xdb !11b /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #752]", + "fcvtzs w21, d2", + "str w21, [x4]", + "ldrb w21, [x28, #1010]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "fist dword [rax]": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "0xdb !11b /2" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #752]", + "frinti d0, d2", + "fcvtzs w20, d0", + "str w20, [x4]" + ] + }, + "fistp dword [rax]": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xdf !11b /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #752]", + "frinti d0, d2", + "fcvtzs w21, d0", + "str w21, [x4]", + "ldrb w21, [x28, #1010]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "fld tword [rax]": { + "ExpectedInstructionCount": 56, + "Optimal": "No", + "Comment": [ + "0xdb !11b /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldr q2, [x4]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1168]", + "blr x3", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov v2.8b, v0.8b", + "mov w21, #0x1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "ldrb w22, [x28, #1010]", + "lsl w21, w21, w20", + "orr w21, w22, w21", + "strb w21, [x28, #1010]", + "strb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fstp tword [rax]": { + "ExpectedInstructionCount": 59, + "Optimal": "No", + "Comment": [ + "0xdb !11b /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov v0.8b, v2.8b", + "ldrh w0, [x28, #1008]", + "ldr x1, [x28, #1152]", + "blr x1", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "str d2, [x4]", + "mov x21, v2.d[1]", + "strh w21, [x4, #8]", + "ldrb w21, [x28, #1010]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "fcmovnb st0, st0": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xc0 /0" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x20000000", + "csetm x20, eq", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x0 (0)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovnb st0, st1": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xc1 /0" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x20000000", + "csetm x20, eq", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovnb st0, st2": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xc2 /0" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x20000000", + "csetm x20, eq", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovnb st0, st3": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xc3 /0" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x20000000", + "csetm x20, eq", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovnb st0, st4": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xc4 /0" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x20000000", + "csetm x20, eq", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x4 (4)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovnb st0, st5": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xc5 /0" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x20000000", + "csetm x20, eq", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x5 (5)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovnb st0, st6": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xc6 /0" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x20000000", + "csetm x20, eq", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x6 (6)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovnb st0, st7": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xc7 /0" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x20000000", + "csetm x20, eq", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x7 (7)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovne st0, st0": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xc8 /1" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x40000000", + "csetm x20, eq", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x0 (0)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovne st0, st1": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xc9 /1" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x40000000", + "csetm x20, eq", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovne st0, st2": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xca /1" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x40000000", + "csetm x20, eq", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovne st0, st3": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xcb /1" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x40000000", + "csetm x20, eq", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovne st0, st4": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xcc /1" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x40000000", + "csetm x20, eq", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x4 (4)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovne st0, st5": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xcd /1" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x40000000", + "csetm x20, eq", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x5 (5)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovne st0, st6": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xce /1" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x40000000", + "csetm x20, eq", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x6 (6)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovne st0, st7": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xcf /1" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x40000000", + "csetm x20, eq", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x7 (7)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovnbe st0, st0": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xd0 /2" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x60000000", + "csetm x20, eq", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x0 (0)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovnbe st0, st1": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xd1 /2" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x60000000", + "csetm x20, eq", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovnbe st0, st2": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xd2 /2" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x60000000", + "csetm x20, eq", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovnbe st0, st3": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xd3 /2" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x60000000", + "csetm x20, eq", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovnbe st0, st4": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xd4 /2" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x60000000", + "csetm x20, eq", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x4 (4)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovnbe st0, st5": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xd5 /2" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x60000000", + "csetm x20, eq", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x5 (5)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovnbe st0, st6": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xd6 /2" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x60000000", + "csetm x20, eq", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x6 (6)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovnbe st0, st7": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xd7 /2" + ], + "ExpectedArm64ASM": [ + "ldr w20, [x28, #728]", + "tst w20, #0x60000000", + "csetm x20, eq", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x7 (7)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovnu st0, st0": { + "ExpectedInstructionCount": 17, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xd8 /3" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #706]", + "fmov s2, w20", + "cnt v2.16b, v2.16b", + "umov w20, v2.b[0]", + "tst w20, #0x1", + "csetm x20, ne", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x0 (0)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovnu st0, st1": { + "ExpectedInstructionCount": 17, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xd9 /3" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #706]", + "fmov s2, w20", + "cnt v2.16b, v2.16b", + "umov w20, v2.b[0]", + "tst w20, #0x1", + "csetm x20, ne", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovnu st0, st2": { + "ExpectedInstructionCount": 17, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xda /3" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #706]", + "fmov s2, w20", + "cnt v2.16b, v2.16b", + "umov w20, v2.b[0]", + "tst w20, #0x1", + "csetm x20, ne", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovnu st0, st3": { + "ExpectedInstructionCount": 17, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xdb /3" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #706]", + "fmov s2, w20", + "cnt v2.16b, v2.16b", + "umov w20, v2.b[0]", + "tst w20, #0x1", + "csetm x20, ne", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovnu st0, st4": { + "ExpectedInstructionCount": 17, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xdc /3" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #706]", + "fmov s2, w20", + "cnt v2.16b, v2.16b", + "umov w20, v2.b[0]", + "tst w20, #0x1", + "csetm x20, ne", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x4 (4)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovnu st0, st5": { + "ExpectedInstructionCount": 17, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xdd /3" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #706]", + "fmov s2, w20", + "cnt v2.16b, v2.16b", + "umov w20, v2.b[0]", + "tst w20, #0x1", + "csetm x20, ne", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x5 (5)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovnu st0, st6": { + "ExpectedInstructionCount": 17, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xde /3" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #706]", + "fmov s2, w20", + "cnt v2.16b, v2.16b", + "umov w20, v2.b[0]", + "tst w20, #0x1", + "csetm x20, ne", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x6 (6)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fcmovnu st0, st7": { + "ExpectedInstructionCount": 17, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xdf /3" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #706]", + "fmov s2, w20", + "cnt v2.16b, v2.16b", + "umov w20, v2.b[0]", + "tst w20, #0x1", + "csetm x20, ne", + "dup v2.2d, x20", + "ldrb w20, [x28, #747]", + "add w21, w20, #0x7 (7)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #752]", + "add x0, x28, x21, lsl #4", + "ldr q4, [x0, #752]", + "bsl v2.16b, v4.16b, v3.16b", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fnclex": { + "ExpectedInstructionCount": 0, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xe2 /4" + ], + "ExpectedArm64ASM": [] + }, + "fninit": { + "ExpectedInstructionCount": 16, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xe3 /4" + ], + "ExpectedArm64ASM": [ + "mov w20, #0x37f", + "mov w21, #0x0", + "rbit w1, w21", + "lsr w1, w1, #30", + "mrs x0, fpcr", + "bfi x0, x1, #22, #2", + "lsr x1, x21, #2", + "bfi x0, x1, #24, #1", + "msr fpcr, x0", + "strh w20, [x28, #1008]", + "strb w21, [x28, #747]", + "strb w21, [x28, #744]", + "strb w21, [x28, #745]", + "strb w21, [x28, #746]", + "strb w21, [x28, #750]", + "strb w21, [x28, #1010]" + ] + }, + "fucomi st0, st0": { + "ExpectedInstructionCount": 24, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xe8 /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x0 (0)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fcmp d3, d2", + "cset x20, eq", + "csinc x20, x20, xzr, vc", + "cset x1, lt", + "bfi x20, x1, #1, #1", + "cset x1, vs", + "bfi x20, x1, #2, #1", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "lsl x21, x21, #29", + "orr w21, w21, w22, lsl #30", + "eor w20, w20, #0x1", + "strb w20, [x28, #706]", + "str w21, [x28, #728]" + ] + }, + "fucomi st0, st1": { + "ExpectedInstructionCount": 24, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xe9 /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fcmp d3, d2", + "cset x20, eq", + "csinc x20, x20, xzr, vc", + "cset x1, lt", + "bfi x20, x1, #1, #1", + "cset x1, vs", + "bfi x20, x1, #2, #1", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "lsl x21, x21, #29", + "orr w21, w21, w22, lsl #30", + "eor w20, w20, #0x1", + "strb w20, [x28, #706]", + "str w21, [x28, #728]" + ] + }, + "fucomi st0, st2": { + "ExpectedInstructionCount": 24, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xea /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fcmp d3, d2", + "cset x20, eq", + "csinc x20, x20, xzr, vc", + "cset x1, lt", + "bfi x20, x1, #1, #1", + "cset x1, vs", + "bfi x20, x1, #2, #1", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "lsl x21, x21, #29", + "orr w21, w21, w22, lsl #30", + "eor w20, w20, #0x1", + "strb w20, [x28, #706]", + "str w21, [x28, #728]" + ] + }, + "fucomi st0, st3": { + "ExpectedInstructionCount": 24, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xeb /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fcmp d3, d2", + "cset x20, eq", + "csinc x20, x20, xzr, vc", + "cset x1, lt", + "bfi x20, x1, #1, #1", + "cset x1, vs", + "bfi x20, x1, #2, #1", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "lsl x21, x21, #29", + "orr w21, w21, w22, lsl #30", + "eor w20, w20, #0x1", + "strb w20, [x28, #706]", + "str w21, [x28, #728]" + ] + }, + "fucomi st0, st4": { + "ExpectedInstructionCount": 24, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xec /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x4 (4)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fcmp d3, d2", + "cset x20, eq", + "csinc x20, x20, xzr, vc", + "cset x1, lt", + "bfi x20, x1, #1, #1", + "cset x1, vs", + "bfi x20, x1, #2, #1", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "lsl x21, x21, #29", + "orr w21, w21, w22, lsl #30", + "eor w20, w20, #0x1", + "strb w20, [x28, #706]", + "str w21, [x28, #728]" + ] + }, + "fucomi st0, st5": { + "ExpectedInstructionCount": 24, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xed /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x5 (5)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fcmp d3, d2", + "cset x20, eq", + "csinc x20, x20, xzr, vc", + "cset x1, lt", + "bfi x20, x1, #1, #1", + "cset x1, vs", + "bfi x20, x1, #2, #1", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "lsl x21, x21, #29", + "orr w21, w21, w22, lsl #30", + "eor w20, w20, #0x1", + "strb w20, [x28, #706]", + "str w21, [x28, #728]" + ] + }, + "fucomi st0, st6": { + "ExpectedInstructionCount": 24, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xee /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x6 (6)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fcmp d3, d2", + "cset x20, eq", + "csinc x20, x20, xzr, vc", + "cset x1, lt", + "bfi x20, x1, #1, #1", + "cset x1, vs", + "bfi x20, x1, #2, #1", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "lsl x21, x21, #29", + "orr w21, w21, w22, lsl #30", + "eor w20, w20, #0x1", + "strb w20, [x28, #706]", + "str w21, [x28, #728]" + ] + }, + "fucomi st0, st7": { + "ExpectedInstructionCount": 24, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xef /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x7 (7)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fcmp d3, d2", + "cset x20, eq", + "csinc x20, x20, xzr, vc", + "cset x1, lt", + "bfi x20, x1, #1, #1", + "cset x1, vs", + "bfi x20, x1, #2, #1", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "lsl x21, x21, #29", + "orr w21, w21, w22, lsl #30", + "eor w20, w20, #0x1", + "strb w20, [x28, #706]", + "str w21, [x28, #728]" + ] + }, + "fcomi st0, st0": { + "ExpectedInstructionCount": 24, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xf0 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x0 (0)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fcmp d3, d2", + "cset x20, eq", + "csinc x20, x20, xzr, vc", + "cset x1, lt", + "bfi x20, x1, #1, #1", + "cset x1, vs", + "bfi x20, x1, #2, #1", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "lsl x21, x21, #29", + "orr w21, w21, w22, lsl #30", + "eor w20, w20, #0x1", + "strb w20, [x28, #706]", + "str w21, [x28, #728]" + ] + }, + "fcomi st0, st1": { + "ExpectedInstructionCount": 24, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xf1 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fcmp d3, d2", + "cset x20, eq", + "csinc x20, x20, xzr, vc", + "cset x1, lt", + "bfi x20, x1, #1, #1", + "cset x1, vs", + "bfi x20, x1, #2, #1", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "lsl x21, x21, #29", + "orr w21, w21, w22, lsl #30", + "eor w20, w20, #0x1", + "strb w20, [x28, #706]", + "str w21, [x28, #728]" + ] + }, + "fcomi st0, st2": { + "ExpectedInstructionCount": 24, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xf2 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fcmp d3, d2", + "cset x20, eq", + "csinc x20, x20, xzr, vc", + "cset x1, lt", + "bfi x20, x1, #1, #1", + "cset x1, vs", + "bfi x20, x1, #2, #1", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "lsl x21, x21, #29", + "orr w21, w21, w22, lsl #30", + "eor w20, w20, #0x1", + "strb w20, [x28, #706]", + "str w21, [x28, #728]" + ] + }, + "fcomi st0, st3": { + "ExpectedInstructionCount": 24, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xf3 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fcmp d3, d2", + "cset x20, eq", + "csinc x20, x20, xzr, vc", + "cset x1, lt", + "bfi x20, x1, #1, #1", + "cset x1, vs", + "bfi x20, x1, #2, #1", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "lsl x21, x21, #29", + "orr w21, w21, w22, lsl #30", + "eor w20, w20, #0x1", + "strb w20, [x28, #706]", + "str w21, [x28, #728]" + ] + }, + "fcomi st0, st4": { + "ExpectedInstructionCount": 24, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xf4 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x4 (4)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fcmp d3, d2", + "cset x20, eq", + "csinc x20, x20, xzr, vc", + "cset x1, lt", + "bfi x20, x1, #1, #1", + "cset x1, vs", + "bfi x20, x1, #2, #1", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "lsl x21, x21, #29", + "orr w21, w21, w22, lsl #30", + "eor w20, w20, #0x1", + "strb w20, [x28, #706]", + "str w21, [x28, #728]" + ] + }, + "fcomi st0, st5": { + "ExpectedInstructionCount": 24, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xf5 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x5 (5)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fcmp d3, d2", + "cset x20, eq", + "csinc x20, x20, xzr, vc", + "cset x1, lt", + "bfi x20, x1, #1, #1", + "cset x1, vs", + "bfi x20, x1, #2, #1", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "lsl x21, x21, #29", + "orr w21, w21, w22, lsl #30", + "eor w20, w20, #0x1", + "strb w20, [x28, #706]", + "str w21, [x28, #728]" + ] + }, + "fcomi st0, st6": { + "ExpectedInstructionCount": 24, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xf6 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x6 (6)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fcmp d3, d2", + "cset x20, eq", + "csinc x20, x20, xzr, vc", + "cset x1, lt", + "bfi x20, x1, #1, #1", + "cset x1, vs", + "bfi x20, x1, #2, #1", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "lsl x21, x21, #29", + "orr w21, w21, w22, lsl #30", + "eor w20, w20, #0x1", + "strb w20, [x28, #706]", + "str w21, [x28, #728]" + ] + }, + "fcomi st0, st7": { + "ExpectedInstructionCount": 24, + "Optimal": "No", + "Comment": [ + "0xdb 11b 0xf7 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x7 (7)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fcmp d3, d2", + "cset x20, eq", + "csinc x20, x20, xzr, vc", + "cset x1, lt", + "bfi x20, x1, #1, #1", + "cset x1, vs", + "bfi x20, x1, #2, #1", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "lsl x21, x21, #29", + "orr w21, w21, w22, lsl #30", + "eor w20, w20, #0x1", + "strb w20, [x28, #706]", + "str w21, [x28, #728]" + ] + }, + "fadd qword [rax]": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": [ + "0xdc !11b /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldr d2, [x4]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fadd d2, d3, d2", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fmul qword [rax]": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": [ + "0xdc !11b /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldr d2, [x4]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fmul d2, d3, d2", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fcom qword [rax]": { + "ExpectedInstructionCount": 21, + "Optimal": "No", + "Comment": [ + "0xdc !11b /2" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldr d2, [x4]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fcmp d3, d2", + "cset x20, eq", + "csinc x20, x20, xzr, vc", + "cset x1, lt", + "bfi x20, x1, #1, #1", + "cset x1, vs", + "bfi x20, x1, #2, #1", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "strb w21, [x28, #744]", + "mov w21, #0x0", + "strb w21, [x28, #745]", + "strb w20, [x28, #746]", + "strb w22, [x28, #750]" + ] + }, + "fcomp qword [rax]": { + "ExpectedInstructionCount": 29, + "Optimal": "No", + "Comment": [ + "0xdc !11b /3" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldr d2, [x4]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fcmp d3, d2", + "cset x21, eq", + "csinc x21, x21, xzr, vc", + "cset x1, lt", + "bfi x21, x1, #1, #1", + "cset x1, vs", + "bfi x21, x1, #2, #1", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "strb w22, [x28, #744]", + "mov w22, #0x0", + "strb w22, [x28, #745]", + "strb w21, [x28, #746]", + "strb w23, [x28, #750]", + "ldrb w21, [x28, #1010]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "fsub qword [rax]": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": [ + "0xdc !11b /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldr d2, [x4]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fsub d2, d3, d2", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fsubr qword [rax]": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": [ + "0xdc !11b /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldr d2, [x4]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fsub d2, d2, d3", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fdiv qword [rax]": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": [ + "0xdc !11b /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldr d2, [x4]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fdiv d2, d3, d2", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fdivr qword [rax]": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": [ + "0xdc !11b /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldr d2, [x4]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fdiv d2, d2, d3", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "db 0xdc, 0xc0": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "fadd st0, st0", + "Needs manual encoding since otherwise nasm will emit the 0xd8 variant.", + "0xdc 11b 0xc0 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x0 (0)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fadd d2, d3, d2", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fadd st1, st0": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "0xdc 11b 0xc1 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fadd d2, d3, d2", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fadd st2, st0": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "0xdc 11b 0xc2 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fadd d2, d3, d2", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fadd st3, st0": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "0xdc 11b 0xc3 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fadd d2, d3, d2", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fadd st4, st0": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "0xdc 11b 0xc4 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x4 (4)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fadd d2, d3, d2", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fadd st5, st0": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "0xdc 11b 0xc5 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x5 (5)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fadd d2, d3, d2", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fadd st6, st0": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "0xdc 11b 0xc6 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x6 (6)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fadd d2, d3, d2", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fadd st7, st0": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "0xdc 11b 0xc7 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x7 (7)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fadd d2, d3, d2", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "db 0xdc, 0xc8": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "fmul st0, st0", + "Needs manual encoding since otherwise nasm will emit the 0xd8 variant.", + "0xdc 11b 0xc8 /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x0 (0)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fmul d2, d3, d2", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fmul st1, st0": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "0xdc 11b 0xc9 /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fmul d2, d3, d2", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fmul st2, st0": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "0xdc 11b 0xca /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fmul d2, d3, d2", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fmul st3, st0": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "0xdc 11b 0xcb /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fmul d2, d3, d2", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fmul st4, st0": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "0xdc 11b 0xcc /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x4 (4)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fmul d2, d3, d2", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fmul st5, st0": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "0xdc 11b 0xcd /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x5 (5)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fmul d2, d3, d2", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fmul st6, st0": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "0xdc 11b 0xce /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x6 (6)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fmul d2, d3, d2", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fmul st7, st0": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "0xdc 11b 0xcf /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x7 (7)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fmul d2, d3, d2", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "db 0xdc, 0xe0": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "fsubr st0, st0", + "Needs manual encoding since otherwise nasm will emit the 0xd8 variant.", + "0xdc 11b 0xe0 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x0 (0)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fsub d2, d3, d2", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fsubr st1, st0": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "0xdc 11b 0xe1 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fsub d2, d3, d2", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fsubr st2, st0": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "0xdc 11b 0xe2 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fsub d2, d3, d2", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fsubr st3, st0": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "0xdc 11b 0xe3 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fsub d2, d3, d2", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fsubr st4, st0": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "0xdc 11b 0xe4 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x4 (4)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fsub d2, d3, d2", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fsubr st5, st0": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "0xdc 11b 0xe5 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x5 (5)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fsub d2, d3, d2", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fsubr st6, st0": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "0xdc 11b 0xe6 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x6 (6)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fsub d2, d3, d2", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fsubr st7, st0": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "0xdc 11b 0xe7 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x7 (7)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fsub d2, d3, d2", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "db 0xdc, 0xe8": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "fsub st0, st0", + "Needs manual encoding since otherwise nasm will emit the 0xd8 variant.", + "0xdc 11b 0xe8 /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x0 (0)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fsub d2, d2, d3", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fsub st1, st0": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "0xdc 11b 0xe9 /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fsub d2, d2, d3", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fsub st2, st0": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "0xdc 11b 0xea /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fsub d2, d2, d3", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fsub st3, st0": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "0xdc 11b 0xeb /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fsub d2, d2, d3", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fsub st4, st0": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "0xdc 11b 0xec /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x4 (4)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fsub d2, d2, d3", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fsub st5, st0": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "0xdc 11b 0xed /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x5 (5)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fsub d2, d2, d3", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fsub st6, st0": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "0xdc 11b 0xee /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x6 (6)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fsub d2, d2, d3", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fsub st7, st0": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "0xdc 11b 0xef /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x7 (7)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fsub d2, d2, d3", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "db 0xdc, 0xf0": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "fdivr st0, st0", + "Needs manual encoding since otherwise nasm will emit the 0xd8 variant.", + "0xdc 11b 0xf0 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x0 (0)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fdiv d2, d3, d2", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fdivr st1, st0": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "0xdc 11b 0xf1 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fdiv d2, d3, d2", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fdivr st2, st0": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "0xdc 11b 0xf2 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fdiv d2, d3, d2", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fdivr st3, st0": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "0xdc 11b 0xf3 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fdiv d2, d3, d2", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fdivr st4, st0": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "0xdc 11b 0xf4 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x4 (4)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fdiv d2, d3, d2", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fdivr st5, st0": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "0xdc 11b 0xf5 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x5 (5)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fdiv d2, d3, d2", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fdivr st6, st0": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "0xdc 11b 0xf6 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x6 (6)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fdiv d2, d3, d2", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fdivr st7, st0": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "0xdc 11b 0xf7 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x7 (7)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fdiv d2, d3, d2", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "db 0xdc, 0xf8": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "fdiv st0, st0", + "Needs manual encoding since otherwise nasm will emit the 0xd8 variant.", + "0xdc 11b 0xf8 /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x0 (0)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fdiv d2, d2, d3", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fdiv st1, st0": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "0xdc 11b 0xf9 /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fdiv d2, d2, d3", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fdiv st2, st0": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "0xdc 11b 0xfa /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fdiv d2, d2, d3", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fdiv st3, st0": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "0xdc 11b 0xfb /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fdiv d2, d2, d3", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fdiv st4, st0": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "0xdc 11b 0xfc /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x4 (4)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fdiv d2, d2, d3", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fdiv st5, st0": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "0xdc 11b 0xfd /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x5 (5)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fdiv d2, d2, d3", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fdiv st6, st0": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "0xdc 11b 0xfe /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x6 (6)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fdiv d2, d2, d3", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fdiv st7, st0": { + "ExpectedInstructionCount": 10, + "Optimal": "No", + "Comment": [ + "0xdc 11b 0xff /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x7 (7)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fdiv d2, d2, d3", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fld qword [rax]": { + "ExpectedInstructionCount": 12, + "Optimal": "No", + "Comment": [ + "0xdd !11b /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldr d2, [x4]", + "mov w21, #0x1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "ldrb w22, [x28, #1010]", + "lsl w21, w21, w20", + "orr w21, w22, w21", + "strb w21, [x28, #1010]", + "strb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fisttp qword [rax]": { + "ExpectedInstructionCount": 13, + "Optimal": "No", + "Comment": [ + "0xdd !11b /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #752]", + "fcvtzs x21, d2", + "str x21, [x4]", + "ldrb w21, [x28, #1010]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "fst qword [rax]": { + "ExpectedInstructionCount": 4, + "Optimal": "No", + "Comment": [ + "0xdd !11b /2" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #752]", + "str d2, [x4]" + ] + }, + "fstp qword [rax]": { + "ExpectedInstructionCount": 12, + "Optimal": "No", + "Comment": [ + "0xdd !11b /3" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #752]", + "str d2, [x4]", + "ldrb w21, [x28, #1010]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "frstor [rax]": { + "ExpectedInstructionCount": 467, + "Optimal": "No", + "Comment": [ + "0xdd !11b /4" + ], + "ExpectedArm64ASM": [ + "ldrh w20, [x4]", + "lsr w21, w20, #10", + "and w21, w21, #0x3", + "rbit w1, w21", + "lsr w1, w1, #30", + "mrs x0, fpcr", + "bfi x0, x1, #22, #2", + "lsr x1, x21, #2", + "bfi x0, x1, #24, #1", + "msr fpcr, x0", + "strh w20, [x28, #1008]", + "strh w20, [x28, #1008]", + "ldr w20, [x4, #4]", + "ubfx w21, w20, #11, #3", + "strb w21, [x28, #747]", + "ubfx w22, w20, #8, #1", + "ubfx w23, w20, #9, #1", + "ubfx w24, w20, #10, #1", + "ubfx w20, w20, #14, #1", + "strb w22, [x28, #744]", + "strb w23, [x28, #745]", + "strb w24, [x28, #746]", + "strb w20, [x28, #750]", + "ldr w20, [x4, #8]", + "ubfx w22, w20, #0, #2", + "cmp x22, #0x3 (3)", + "cset x22, ne", + "ubfx w23, w20, #2, #2", + "cmp x23, #0x3 (3)", + "cset x23, ne", + "orr w22, w22, w23, lsl #1", + "ubfx w23, w20, #4, #2", + "cmp x23, #0x3 (3)", + "cset x23, ne", + "orr w22, w22, w23, lsl #2", + "ubfx w23, w20, #6, #2", + "cmp x23, #0x3 (3)", + "cset x23, ne", + "orr w22, w22, w23, lsl #3", + "ubfx w23, w20, #8, #2", + "cmp x23, #0x3 (3)", + "cset x23, ne", + "orr w22, w22, w23, lsl #4", + "ubfx w23, w20, #10, #2", + "cmp x23, #0x3 (3)", + "cset x23, ne", + "orr w22, w22, w23, lsl #5", + "ubfx w23, w20, #12, #2", + "cmp x23, #0x3 (3)", + "cset x23, ne", + "orr w22, w22, w23, lsl #6", + "ubfx w20, w20, #14, #2", + "cmp x20, #0x3 (3)", + "cset x20, ne", + "orr w20, w22, w20, lsl #7", + "strb w20, [x28, #1010]", + "add x20, x4, #0x1c (28)", + "mov x22, #0xffffffffffffffff", + "mov w23, #0xffff", + "fmov d2, x22", + "mov v2.d[1], x23", + "ldur q3, [x4, #28]", + "and v3.16b, v3.16b, v2.16b", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1168]", + "blr x3", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov v3.8b, v0.8b", + "add x0, x28, x21, lsl #4", + "str d3, [x0, #752]", + "add x22, x20, #0xa (10)", + "add w21, w21, #0x1 (1)", + "and w21, w21, #0x7", + "ldur q3, [x20, #10]", + "and v3.16b, v3.16b, v2.16b", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1168]", + "blr x3", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov v3.8b, v0.8b", + "add x0, x28, x21, lsl #4", + "str d3, [x0, #752]", + "add x20, x22, #0xa (10)", + "add w21, w21, #0x1 (1)", + "and w21, w21, #0x7", + "ldur q3, [x22, #10]", + "and v3.16b, v3.16b, v2.16b", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1168]", + "blr x3", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov v3.8b, v0.8b", + "add x0, x28, x21, lsl #4", + "str d3, [x0, #752]", + "add x22, x20, #0xa (10)", + "add w21, w21, #0x1 (1)", + "and w21, w21, #0x7", + "ldur q3, [x20, #10]", + "and v3.16b, v3.16b, v2.16b", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1168]", + "blr x3", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov v3.8b, v0.8b", + "add x0, x28, x21, lsl #4", + "str d3, [x0, #752]", + "add x20, x22, #0xa (10)", + "add w21, w21, #0x1 (1)", + "and w21, w21, #0x7", + "ldur q3, [x22, #10]", + "and v3.16b, v3.16b, v2.16b", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1168]", + "blr x3", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov v3.8b, v0.8b", + "add x0, x28, x21, lsl #4", + "str d3, [x0, #752]", + "add x22, x20, #0xa (10)", + "add w21, w21, #0x1 (1)", + "and w21, w21, #0x7", + "ldur q3, [x20, #10]", + "and v3.16b, v3.16b, v2.16b", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "ldr x3, [x28, #1168]", + "blr x3", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov v3.8b, v0.8b", + "add x0, x28, x21, lsl #4", + "str d3, [x0, #752]", + "add x20, x22, #0xa (10)", + "add w21, w21, #0x1 (1)", + "and w21, w21, #0x7", + "ldur q3, [x22, #10]", + "and v2.16b, v3.16b, v2.16b", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1168]", + "blr x3", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov v2.8b, v0.8b", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]", + "add x22, x20, #0xa (10)", + "add w21, w21, #0x1 (1)", + "and w21, w21, #0x7", + "ldur d2, [x20, #10]", + "ldr h3, [x22, #8]", + "mov v2.h[4], v3.h[0]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1168]", + "blr x3", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov v2.8b, v0.8b", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fnsave [rax]": { + "ExpectedInstructionCount": 478, + "Optimal": "No", + "Comment": [ + "0xdd !11b /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldrh w21, [x28, #1008]", + "str w21, [x4]", + "mov w21, #0x0", + "mov x0, x21", + "bfi x0, x20, #11, #3", + "mov x22, x0", + "ldrb w23, [x28, #744]", + "ldrb w24, [x28, #745]", + "ldrb w25, [x28, #746]", + "ldrb w26, [x28, #750]", + "orr x22, x22, x23, lsl #8", + "orr x22, x22, x24, lsl #9", + "orr x22, x22, x25, lsl #10", + "orr x22, x22, x26, lsl #14", + "str w22, [x4, #4]", + "ldrb w22, [x28, #1010]", + "and w23, w22, #0x1", + "mov w24, #0x3", + "cmp x23, #0x0 (0)", + "csel x23, x24, x21, eq", + "orr w23, w21, w23", + "lsr w25, w22, #1", + "and w25, w25, #0x1", + "cmp x25, #0x0 (0)", + "csel x25, x24, x21, eq", + "orr w23, w23, w25, lsl #2", + "lsr w25, w22, #2", + "and w25, w25, #0x1", + "cmp x25, #0x0 (0)", + "csel x25, x24, x21, eq", + "orr w23, w23, w25, lsl #4", + "lsr w25, w22, #3", + "and w25, w25, #0x1", + "cmp x25, #0x0 (0)", + "csel x25, x24, x21, eq", + "orr w23, w23, w25, lsl #6", + "lsr w25, w22, #4", + "and w25, w25, #0x1", + "cmp x25, #0x0 (0)", + "csel x25, x24, x21, eq", + "orr w23, w23, w25, lsl #8", + "lsr w25, w22, #5", + "and w25, w25, #0x1", + "cmp x25, #0x0 (0)", + "csel x25, x24, x21, eq", + "orr w23, w23, w25, lsl #10", + "lsr w25, w22, #6", + "and w25, w25, #0x1", + "cmp x25, #0x0 (0)", + "csel x25, x24, x21, eq", + "orr w23, w23, w25, lsl #12", + "lsr w22, w22, #7", + "and w22, w22, #0x1", + "cmp x22, #0x0 (0)", + "csel x22, x24, x21, eq", + "orr w22, w23, w22, lsl #14", + "str w22, [x4, #8]", + "str w21, [x4, #12]", + "str w21, [x4, #16]", + "str w21, [x4, #20]", + "str w21, [x4, #24]", + "add x22, x4, #0x1c (28)", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov v0.8b, v2.8b", + "ldrh w0, [x28, #1008]", + "ldr x1, [x28, #1152]", + "blr x1", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "stur q2, [x4, #28]", + "add x23, x22, #0xa (10)", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov v0.8b, v2.8b", + "ldrh w0, [x28, #1008]", + "ldr x1, [x28, #1152]", + "blr x1", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "stur q2, [x22, #10]", + "add x22, x23, #0xa (10)", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov v0.8b, v2.8b", + "ldrh w0, [x28, #1008]", + "ldr x1, [x28, #1152]", + "blr x1", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "stur q2, [x23, #10]", + "add x23, x22, #0xa (10)", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov v0.8b, v2.8b", + "ldrh w0, [x28, #1008]", + "ldr x1, [x28, #1152]", + "blr x1", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "stur q2, [x22, #10]", + "add x22, x23, #0xa (10)", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov v0.8b, v2.8b", + "ldrh w0, [x28, #1008]", + "ldr x1, [x28, #1152]", + "blr x1", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "stur q2, [x23, #10]", + "add x23, x22, #0xa (10)", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov v0.8b, v2.8b", + "ldrh w0, [x28, #1008]", + "ldr x1, [x28, #1152]", + "blr x1", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "stur q2, [x22, #10]", + "add x22, x23, #0xa (10)", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov v0.8b, v2.8b", + "ldrh w0, [x28, #1008]", + "ldr x1, [x28, #1152]", + "blr x1", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "stur q2, [x23, #10]", + "add x23, x22, #0xa (10)", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov v0.8b, v2.8b", + "ldrh w0, [x28, #1008]", + "ldr x1, [x28, #1152]", + "blr x1", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "stur d2, [x22, #10]", + "dup v2.8h, v2.h[4]", + "str h2, [x23, #8]", + "mov w20, #0x37f", + "strh w20, [x28, #1008]", + "strb w21, [x28, #747]", + "strb w21, [x28, #744]", + "strb w21, [x28, #745]", + "strb w21, [x28, #746]", + "strb w21, [x28, #750]", + "strb w21, [x28, #1010]" + ] + }, + "fnstsw [rax]": { + "ExpectedInstructionCount": 12, + "Optimal": "No", + "Comment": [ + "0xdd !11b /7" + ], + "ExpectedArm64ASM": [ + "mov w20, #0x0", + "ldrb w21, [x28, #747]", + "bfi x20, x21, #11, #3", + "ldrb w21, [x28, #744]", + "ldrb w22, [x28, #745]", + "ldrb w23, [x28, #746]", + "ldrb w24, [x28, #750]", + "orr x20, x20, x21, lsl #8", + "orr x20, x20, x22, lsl #9", + "orr x20, x20, x23, lsl #10", + "orr x20, x20, x24, lsl #14", + "strh w20, [x4]" + ] + }, + "ffree st0": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": [ + "0xdd 11b 0xc0 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w20, w20, #0x0 (0)", + "and w20, w20, #0x7", + "ldrb w21, [x28, #1010]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "bic w20, w21, w20", + "strb w20, [x28, #1010]" + ] + }, + "ffree st1": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": [ + "0xdd 11b 0xc1 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "mov w21, #0x1", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "ldrb w22, [x28, #1010]", + "lsl w20, w21, w20", + "bic w20, w22, w20", + "strb w20, [x28, #1010]" + ] + }, + "ffree st2": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": [ + "0xdd 11b 0xc2 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w20, w20, #0x2 (2)", + "and w20, w20, #0x7", + "ldrb w21, [x28, #1010]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "bic w20, w21, w20", + "strb w20, [x28, #1010]" + ] + }, + "ffree st3": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": [ + "0xdd 11b 0xc3 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w20, w20, #0x3 (3)", + "and w20, w20, #0x7", + "ldrb w21, [x28, #1010]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "bic w20, w21, w20", + "strb w20, [x28, #1010]" + ] + }, + "ffree st4": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": [ + "0xdd 11b 0xc4 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w20, w20, #0x4 (4)", + "and w20, w20, #0x7", + "ldrb w21, [x28, #1010]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "bic w20, w21, w20", + "strb w20, [x28, #1010]" + ] + }, + "ffree st5": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": [ + "0xdd 11b 0xc5 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w20, w20, #0x5 (5)", + "and w20, w20, #0x7", + "ldrb w21, [x28, #1010]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "bic w20, w21, w20", + "strb w20, [x28, #1010]" + ] + }, + "ffree st6": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": [ + "0xdd 11b 0xc6 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w20, w20, #0x6 (6)", + "and w20, w20, #0x7", + "ldrb w21, [x28, #1010]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "bic w20, w21, w20", + "strb w20, [x28, #1010]" + ] + }, + "ffree st7": { + "ExpectedInstructionCount": 8, + "Optimal": "No", + "Comment": [ + "0xdd 11b 0xc7 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w20, w20, #0x7 (7)", + "and w20, w20, #0x7", + "ldrb w21, [x28, #1010]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "bic w20, w21, w20", + "strb w20, [x28, #1010]" + ] + }, + "fst st0": { + "ExpectedInstructionCount": 7, + "Optimal": "No", + "Comment": [ + "0xdd 11b 0xd0 /2" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x0 (0)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fst st1": { + "ExpectedInstructionCount": 7, + "Optimal": "Yes", + "Comment": [ + "0xdd 11b 0xd1 /2" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fst st2": { + "ExpectedInstructionCount": 7, + "Optimal": "Yes", + "Comment": [ + "0xdd 11b 0xd2 /2" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fst st3": { + "ExpectedInstructionCount": 7, + "Optimal": "Yes", + "Comment": [ + "0xdd 11b 0xd3 /2" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fst st4": { + "ExpectedInstructionCount": 7, + "Optimal": "Yes", + "Comment": [ + "0xdd 11b 0xd4 /2" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x4 (4)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fst st5": { + "ExpectedInstructionCount": 7, + "Optimal": "Yes", + "Comment": [ + "0xdd 11b 0xd5 /2" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x5 (5)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fst st6": { + "ExpectedInstructionCount": 7, + "Optimal": "Yes", + "Comment": [ + "0xdd 11b 0xd6 /2" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x6 (6)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fst st7": { + "ExpectedInstructionCount": 7, + "Optimal": "Yes", + "Comment": [ + "0xdd 11b 0xd7 /2" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x7 (7)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]" + ] + }, + "fstp st0": { + "ExpectedInstructionCount": 15, + "Optimal": "No", + "Comment": [ + "0xdd 11b 0xd8 /3" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x0 (0)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]", + "ldrb w21, [x28, #1010]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "fstp st1": { + "ExpectedInstructionCount": 15, + "Optimal": "No", + "Comment": [ + "0xdd 11b 0xd9 /3" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "mov w21, #0x1", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x22, lsl #4", + "str q2, [x0, #752]", + "ldrb w22, [x28, #1010]", + "lsl w21, w21, w20", + "bic w21, w22, w21", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "fstp st2": { + "ExpectedInstructionCount": 15, + "Optimal": "No", + "Comment": [ + "0xdd 11b 0xda /3" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]", + "ldrb w21, [x28, #1010]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "fstp st3": { + "ExpectedInstructionCount": 15, + "Optimal": "No", + "Comment": [ + "0xdd 11b 0xdb /3" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]", + "ldrb w21, [x28, #1010]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "fstp st4": { + "ExpectedInstructionCount": 15, + "Optimal": "No", + "Comment": [ + "0xdd 11b 0xdc /3" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x4 (4)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]", + "ldrb w21, [x28, #1010]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "fstp st5": { + "ExpectedInstructionCount": 15, + "Optimal": "No", + "Comment": [ + "0xdd 11b 0xdd /3" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x5 (5)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]", + "ldrb w21, [x28, #1010]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "fstp st6": { + "ExpectedInstructionCount": 15, + "Optimal": "No", + "Comment": [ + "0xdd 11b 0xde /3" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x6 (6)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]", + "ldrb w21, [x28, #1010]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "fstp st7": { + "ExpectedInstructionCount": 15, + "Optimal": "No", + "Comment": [ + "0xdd 11b 0xdf /3" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x7 (7)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #752]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #752]", + "ldrb w21, [x28, #1010]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "fucom st0": { + "ExpectedInstructionCount": 24, + "Optimal": "No", + "Comment": [ + "0xdd 11b 0xe0 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "mov w21, #0x0", + "add w22, w20, #0x0 (0)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fcmp d3, d2", + "cset x20, eq", + "csinc x20, x20, xzr, vc", + "cset x1, lt", + "bfi x20, x1, #1, #1", + "cset x1, vs", + "bfi x20, x1, #2, #1", + "ubfx x22, x20, #1, #1", + "ubfx x23, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w22, w22, w20", + "orr w23, w23, w20", + "strb w22, [x28, #744]", + "strb w21, [x28, #745]", + "strb w20, [x28, #746]", + "strb w23, [x28, #750]" + ] + }, + "fucom st1": { + "ExpectedInstructionCount": 24, + "Optimal": "No", + "Comment": [ + "0xdd 11b 0xe1 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fcmp d3, d2", + "cset x20, eq", + "csinc x20, x20, xzr, vc", + "cset x1, lt", + "bfi x20, x1, #1, #1", + "cset x1, vs", + "bfi x20, x1, #2, #1", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "strb w21, [x28, #744]", + "mov w21, #0x0", + "strb w21, [x28, #745]", + "strb w20, [x28, #746]", + "strb w22, [x28, #750]" + ] + }, + "fucom st2": { + "ExpectedInstructionCount": 24, + "Optimal": "No", + "Comment": [ + "0xdd 11b 0xe2 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fcmp d3, d2", + "cset x20, eq", + "csinc x20, x20, xzr, vc", + "cset x1, lt", + "bfi x20, x1, #1, #1", + "cset x1, vs", + "bfi x20, x1, #2, #1", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "strb w21, [x28, #744]", + "mov w21, #0x0", + "strb w21, [x28, #745]", + "strb w20, [x28, #746]", + "strb w22, [x28, #750]" + ] + }, + "fucom st3": { + "ExpectedInstructionCount": 24, + "Optimal": "No", + "Comment": [ + "0xdd 11b 0xe3 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fcmp d3, d2", + "cset x20, eq", + "csinc x20, x20, xzr, vc", + "cset x1, lt", + "bfi x20, x1, #1, #1", + "cset x1, vs", + "bfi x20, x1, #2, #1", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "strb w21, [x28, #744]", + "mov w21, #0x0", + "strb w21, [x28, #745]", + "strb w20, [x28, #746]", + "strb w22, [x28, #750]" + ] + }, + "fucom st4": { + "ExpectedInstructionCount": 24, + "Optimal": "No", + "Comment": [ + "0xdd 11b 0xe4 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x4 (4)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fcmp d3, d2", + "cset x20, eq", + "csinc x20, x20, xzr, vc", + "cset x1, lt", + "bfi x20, x1, #1, #1", + "cset x1, vs", + "bfi x20, x1, #2, #1", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "strb w21, [x28, #744]", + "mov w21, #0x0", + "strb w21, [x28, #745]", + "strb w20, [x28, #746]", + "strb w22, [x28, #750]" + ] + }, + "fucom st5": { + "ExpectedInstructionCount": 24, + "Optimal": "No", + "Comment": [ + "0xdd 11b 0xe5 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x5 (5)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fcmp d3, d2", + "cset x20, eq", + "csinc x20, x20, xzr, vc", + "cset x1, lt", + "bfi x20, x1, #1, #1", + "cset x1, vs", + "bfi x20, x1, #2, #1", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "strb w21, [x28, #744]", + "mov w21, #0x0", + "strb w21, [x28, #745]", + "strb w20, [x28, #746]", + "strb w22, [x28, #750]" + ] + }, + "fucom st6": { + "ExpectedInstructionCount": 24, + "Optimal": "No", + "Comment": [ + "0xdd 11b 0xe6 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x6 (6)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fcmp d3, d2", + "cset x20, eq", + "csinc x20, x20, xzr, vc", + "cset x1, lt", + "bfi x20, x1, #1, #1", + "cset x1, vs", + "bfi x20, x1, #2, #1", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "strb w21, [x28, #744]", + "mov w21, #0x0", + "strb w21, [x28, #745]", + "strb w20, [x28, #746]", + "strb w22, [x28, #750]" + ] + }, + "fucom st7": { + "ExpectedInstructionCount": 24, + "Optimal": "No", + "Comment": [ + "0xdd 11b 0xe7 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x7 (7)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fcmp d3, d2", + "cset x20, eq", + "csinc x20, x20, xzr, vc", + "cset x1, lt", + "bfi x20, x1, #1, #1", + "cset x1, vs", + "bfi x20, x1, #2, #1", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "strb w21, [x28, #744]", + "mov w21, #0x0", + "strb w21, [x28, #745]", + "strb w20, [x28, #746]", + "strb w22, [x28, #750]" + ] + }, + "fucomp st0": { + "ExpectedInstructionCount": 32, + "Optimal": "No", + "Comment": [ + "0xdd 11b 0xe8 /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "mov w21, #0x0", + "add w22, w20, #0x0 (0)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fcmp d3, d2", + "cset x22, eq", + "csinc x22, x22, xzr, vc", + "cset x1, lt", + "bfi x22, x1, #1, #1", + "cset x1, vs", + "bfi x22, x1, #2, #1", + "ubfx x23, x22, #1, #1", + "ubfx x24, x22, #0, #1", + "ubfx x22, x22, #2, #1", + "orr w23, w23, w22", + "orr w24, w24, w22", + "strb w23, [x28, #744]", + "strb w21, [x28, #745]", + "strb w22, [x28, #746]", + "strb w24, [x28, #750]", + "ldrb w21, [x28, #1010]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "fucomp st1": { + "ExpectedInstructionCount": 32, + "Optimal": "No", + "Comment": [ + "0xdd 11b 0xe9 /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "mov w21, #0x1", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fcmp d3, d2", + "cset x22, eq", + "csinc x22, x22, xzr, vc", + "cset x1, lt", + "bfi x22, x1, #1, #1", + "cset x1, vs", + "bfi x22, x1, #2, #1", + "ubfx x23, x22, #1, #1", + "ubfx x24, x22, #0, #1", + "ubfx x22, x22, #2, #1", + "orr w23, w23, w22", + "orr w24, w24, w22", + "strb w23, [x28, #744]", + "mov w23, #0x0", + "strb w23, [x28, #745]", + "strb w22, [x28, #746]", + "strb w24, [x28, #750]", + "ldrb w22, [x28, #1010]", + "lsl w21, w21, w20", + "bic w21, w22, w21", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "fucomp st2": { + "ExpectedInstructionCount": 32, + "Optimal": "No", + "Comment": [ + "0xdd 11b 0xea /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fcmp d3, d2", + "cset x21, eq", + "csinc x21, x21, xzr, vc", + "cset x1, lt", + "bfi x21, x1, #1, #1", + "cset x1, vs", + "bfi x21, x1, #2, #1", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "strb w22, [x28, #744]", + "mov w22, #0x0", + "strb w22, [x28, #745]", + "strb w21, [x28, #746]", + "strb w23, [x28, #750]", + "ldrb w21, [x28, #1010]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "fucomp st3": { + "ExpectedInstructionCount": 32, + "Optimal": "No", + "Comment": [ + "0xdd 11b 0xeb /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fcmp d3, d2", + "cset x21, eq", + "csinc x21, x21, xzr, vc", + "cset x1, lt", + "bfi x21, x1, #1, #1", + "cset x1, vs", + "bfi x21, x1, #2, #1", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "strb w22, [x28, #744]", + "mov w22, #0x0", + "strb w22, [x28, #745]", + "strb w21, [x28, #746]", + "strb w23, [x28, #750]", + "ldrb w21, [x28, #1010]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "fucomp st4": { + "ExpectedInstructionCount": 32, + "Optimal": "No", + "Comment": [ + "0xdd 11b 0xec /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x4 (4)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fcmp d3, d2", + "cset x21, eq", + "csinc x21, x21, xzr, vc", + "cset x1, lt", + "bfi x21, x1, #1, #1", + "cset x1, vs", + "bfi x21, x1, #2, #1", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "strb w22, [x28, #744]", + "mov w22, #0x0", + "strb w22, [x28, #745]", + "strb w21, [x28, #746]", + "strb w23, [x28, #750]", + "ldrb w21, [x28, #1010]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "fucomp st5": { + "ExpectedInstructionCount": 32, + "Optimal": "No", + "Comment": [ + "0xdd 11b 0xed /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x5 (5)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fcmp d3, d2", + "cset x21, eq", + "csinc x21, x21, xzr, vc", + "cset x1, lt", + "bfi x21, x1, #1, #1", + "cset x1, vs", + "bfi x21, x1, #2, #1", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "strb w22, [x28, #744]", + "mov w22, #0x0", + "strb w22, [x28, #745]", + "strb w21, [x28, #746]", + "strb w23, [x28, #750]", + "ldrb w21, [x28, #1010]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "fucomp st6": { + "ExpectedInstructionCount": 32, + "Optimal": "No", + "Comment": [ + "0xdd 11b 0xee /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x6 (6)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fcmp d3, d2", + "cset x21, eq", + "csinc x21, x21, xzr, vc", + "cset x1, lt", + "bfi x21, x1, #1, #1", + "cset x1, vs", + "bfi x21, x1, #2, #1", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "strb w22, [x28, #744]", + "mov w22, #0x0", + "strb w22, [x28, #745]", + "strb w21, [x28, #746]", + "strb w23, [x28, #750]", + "ldrb w21, [x28, #1010]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "fucomp st7": { + "ExpectedInstructionCount": 32, + "Optimal": "No", + "Comment": [ + "0xdd 11b 0xef /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x7 (7)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fcmp d3, d2", + "cset x21, eq", + "csinc x21, x21, xzr, vc", + "cset x1, lt", + "bfi x21, x1, #1, #1", + "cset x1, vs", + "bfi x21, x1, #2, #1", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "strb w22, [x28, #744]", + "mov w22, #0x0", + "strb w22, [x28, #745]", + "strb w21, [x28, #746]", + "strb w23, [x28, #750]", + "ldrb w21, [x28, #1010]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "fiadd word [rax]": { + "ExpectedInstructionCount": 9, + "Optimal": "No", + "Comment": [ + "0xde !11b /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldrh w21, [x4]", + "sxth x21, w21", + "scvtf d2, w21", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fadd d2, d3, d2", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fimul word [rax]": { + "ExpectedInstructionCount": 9, + "Optimal": "No", + "Comment": [ + "0xde !11b /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldrh w21, [x4]", + "sxth x21, w21", + "scvtf d2, w21", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fmul d2, d3, d2", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "ficom word [rax]": { + "ExpectedInstructionCount": 23, + "Optimal": "No", + "Comment": [ + "0xde !11b /2" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldrh w21, [x4]", + "sxth x21, w21", + "scvtf d2, w21", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fcmp d3, d2", + "cset x20, eq", + "csinc x20, x20, xzr, vc", + "cset x1, lt", + "bfi x20, x1, #1, #1", + "cset x1, vs", + "bfi x20, x1, #2, #1", + "ubfx x21, x20, #1, #1", + "ubfx x22, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w22, w22, w20", + "strb w21, [x28, #744]", + "mov w21, #0x0", + "strb w21, [x28, #745]", + "strb w20, [x28, #746]", + "strb w22, [x28, #750]" + ] + }, + "ficomp word [rax]": { + "ExpectedInstructionCount": 31, + "Optimal": "No", + "Comment": [ + "0xde !11b /3" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldrh w21, [x4]", + "sxth x21, w21", + "scvtf d2, w21", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fcmp d3, d2", + "cset x21, eq", + "csinc x21, x21, xzr, vc", + "cset x1, lt", + "bfi x21, x1, #1, #1", + "cset x1, vs", + "bfi x21, x1, #2, #1", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "strb w22, [x28, #744]", + "mov w22, #0x0", + "strb w22, [x28, #745]", + "strb w21, [x28, #746]", + "strb w23, [x28, #750]", + "ldrb w21, [x28, #1010]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "fisub word [rax]": { + "ExpectedInstructionCount": 9, + "Optimal": "No", + "Comment": [ + "0xde !11b /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldrh w21, [x4]", + "sxth x21, w21", + "scvtf d2, w21", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fsub d2, d3, d2", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fisubr word [rax]": { + "ExpectedInstructionCount": 9, + "Optimal": "No", + "Comment": [ + "0xde !11b /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldrh w21, [x4]", + "sxth x21, w21", + "scvtf d2, w21", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fsub d2, d2, d3", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fidiv word [rax]": { + "ExpectedInstructionCount": 9, + "Optimal": "No", + "Comment": [ + "0xde !11b /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldrh w21, [x4]", + "sxth x21, w21", + "scvtf d2, w21", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fdiv d2, d3, d2", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fidivr word [rax]": { + "ExpectedInstructionCount": 9, + "Optimal": "No", + "Comment": [ + "0xde !11b /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldrh w21, [x4]", + "sxth x21, w21", + "scvtf d2, w21", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fdiv d2, d2, d3", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "faddp st0": { + "ExpectedInstructionCount": 18, + "Optimal": "No", + "Comment": [ + "0xd8 11b 0xc0 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x0 (0)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fadd d2, d3, d2", + "ldrb w22, [x28, #1010]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "faddp st1": { + "ExpectedInstructionCount": 18, + "Optimal": "No", + "Comment": [ + "0xde 11b 0xc1 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "mov w21, #0x1", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fadd d2, d3, d2", + "ldrb w23, [x28, #1010]", + "lsl w21, w21, w20", + "bic w21, w23, w21", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x22, lsl #4", + "str d2, [x0, #752]" + ] + }, + "faddp st2": { + "ExpectedInstructionCount": 18, + "Optimal": "No", + "Comment": [ + "0xde 11b 0xc2 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fadd d2, d3, d2", + "ldrb w22, [x28, #1010]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "faddp st3": { + "ExpectedInstructionCount": 18, + "Optimal": "No", + "Comment": [ + "0xde 11b 0xc3 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fadd d2, d3, d2", + "ldrb w22, [x28, #1010]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "faddp st4": { + "ExpectedInstructionCount": 18, + "Optimal": "No", + "Comment": [ + "0xde 11b 0xc4 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x4 (4)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fadd d2, d3, d2", + "ldrb w22, [x28, #1010]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "faddp st5": { + "ExpectedInstructionCount": 18, + "Optimal": "No", + "Comment": [ + "0xde 11b 0xc5 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x5 (5)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fadd d2, d3, d2", + "ldrb w22, [x28, #1010]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "faddp st6": { + "ExpectedInstructionCount": 18, + "Optimal": "No", + "Comment": [ + "0xde 11b 0xc6 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x6 (6)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fadd d2, d3, d2", + "ldrb w22, [x28, #1010]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "faddp st7": { + "ExpectedInstructionCount": 18, + "Optimal": "No", + "Comment": [ + "0xde 11b 0xc7 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x7 (7)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fadd d2, d3, d2", + "ldrb w22, [x28, #1010]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fmulp st0": { + "ExpectedInstructionCount": 18, + "Optimal": "No", + "Comment": [ + "0xde 11b 0xc8 /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x0 (0)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fmul d2, d3, d2", + "ldrb w22, [x28, #1010]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fmulp st1": { + "ExpectedInstructionCount": 18, + "Optimal": "No", + "Comment": [ + "0xde 11b 0xc9 /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "mov w21, #0x1", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fmul d2, d3, d2", + "ldrb w23, [x28, #1010]", + "lsl w21, w21, w20", + "bic w21, w23, w21", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x22, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fmulp st2": { + "ExpectedInstructionCount": 18, + "Optimal": "No", + "Comment": [ + "0xde 11b 0xca /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fmul d2, d3, d2", + "ldrb w22, [x28, #1010]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fmulp st3": { + "ExpectedInstructionCount": 18, + "Optimal": "No", + "Comment": [ + "0xde 11b 0xcb /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fmul d2, d3, d2", + "ldrb w22, [x28, #1010]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fmulp st4": { + "ExpectedInstructionCount": 18, + "Optimal": "No", + "Comment": [ + "0xde 11b 0xcc /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x4 (4)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fmul d2, d3, d2", + "ldrb w22, [x28, #1010]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fmulp st5": { + "ExpectedInstructionCount": 18, + "Optimal": "No", + "Comment": [ + "0xde 11b 0xcd /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x5 (5)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fmul d2, d3, d2", + "ldrb w22, [x28, #1010]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fmulp st6": { + "ExpectedInstructionCount": 18, + "Optimal": "No", + "Comment": [ + "0xde 11b 0xce /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x6 (6)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fmul d2, d3, d2", + "ldrb w22, [x28, #1010]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fmulp st7": { + "ExpectedInstructionCount": 18, + "Optimal": "No", + "Comment": [ + "0xde 11b 0xcf /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x7 (7)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fmul d2, d3, d2", + "ldrb w22, [x28, #1010]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fcompp": { + "ExpectedInstructionCount": 37, + "Optimal": "No", + "Comment": [ + "0xde 11b 0xd9 /3" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "mov w21, #0x1", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fcmp d3, d2", + "cset x22, eq", + "csinc x22, x22, xzr, vc", + "cset x1, lt", + "bfi x22, x1, #1, #1", + "cset x1, vs", + "bfi x22, x1, #2, #1", + "ubfx x23, x22, #1, #1", + "ubfx x24, x22, #0, #1", + "ubfx x22, x22, #2, #1", + "orr w23, w23, w22", + "orr w24, w24, w22", + "strb w23, [x28, #744]", + "mov w23, #0x0", + "strb w23, [x28, #745]", + "strb w22, [x28, #746]", + "strb w24, [x28, #750]", + "ldrb w22, [x28, #1010]", + "lsl w23, w21, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "lsl w21, w21, w20", + "bic w21, w22, w21", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "db 0xde, 0xe0": { + "ExpectedInstructionCount": 18, + "Optimal": "No", + "Comment": [ + "fsubrp st0, st0", + "Needs manual encoding since otherwise nasm will emit the 0xd8 variant.", + "0xde 11b 0xe0 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x0 (0)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fsub d2, d3, d2", + "ldrb w22, [x28, #1010]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fsubrp st1, st0": { + "ExpectedInstructionCount": 18, + "Optimal": "No", + "Comment": [ + "0xde 11b 0xe1 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "mov w21, #0x1", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fsub d2, d3, d2", + "ldrb w23, [x28, #1010]", + "lsl w21, w21, w20", + "bic w21, w23, w21", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x22, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fsubrp st2, st0": { + "ExpectedInstructionCount": 18, + "Optimal": "No", + "Comment": [ + "0xde 11b 0xe2 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fsub d2, d3, d2", + "ldrb w22, [x28, #1010]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fsubrp st3, st0": { + "ExpectedInstructionCount": 18, + "Optimal": "No", + "Comment": [ + "0xde 11b 0xe3 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fsub d2, d3, d2", + "ldrb w22, [x28, #1010]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fsubrp st4, st0": { + "ExpectedInstructionCount": 18, + "Optimal": "No", + "Comment": [ + "0xde 11b 0xe4 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x4 (4)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fsub d2, d3, d2", + "ldrb w22, [x28, #1010]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fsubrp st5, st0": { + "ExpectedInstructionCount": 18, + "Optimal": "No", + "Comment": [ + "0xde 11b 0xe5 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x5 (5)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fsub d2, d3, d2", + "ldrb w22, [x28, #1010]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fsubrp st6, st0": { + "ExpectedInstructionCount": 18, + "Optimal": "No", + "Comment": [ + "0xde 11b 0xe6 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x6 (6)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fsub d2, d3, d2", + "ldrb w22, [x28, #1010]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fsubrp st7, st0": { + "ExpectedInstructionCount": 18, + "Optimal": "No", + "Comment": [ + "0xde 11b 0xe7 /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x7 (7)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fsub d2, d3, d2", + "ldrb w22, [x28, #1010]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "db 0xde, 0xe8": { + "ExpectedInstructionCount": 18, + "Optimal": "No", + "Comment": [ + "fsubp st0, st0", + "Needs manual encoding since otherwise nasm will emit the 0xd8 variant.", + "0xde 11b 0xe8 /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x0 (0)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fsub d2, d2, d3", + "ldrb w22, [x28, #1010]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fsubp st1, st0": { + "ExpectedInstructionCount": 18, + "Optimal": "No", + "Comment": [ + "0xde 11b 0xe9 /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "mov w21, #0x1", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fsub d2, d2, d3", + "ldrb w23, [x28, #1010]", + "lsl w21, w21, w20", + "bic w21, w23, w21", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x22, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fsubp st2, st0": { + "ExpectedInstructionCount": 18, + "Optimal": "No", + "Comment": [ + "0xde 11b 0xea /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fsub d2, d2, d3", + "ldrb w22, [x28, #1010]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fsubp st3, st0": { + "ExpectedInstructionCount": 18, + "Optimal": "No", + "Comment": [ + "0xde 11b 0xeb /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fsub d2, d2, d3", + "ldrb w22, [x28, #1010]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fsubp st4, st0": { + "ExpectedInstructionCount": 18, + "Optimal": "No", + "Comment": [ + "0xde 11b 0xec /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x4 (4)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fsub d2, d2, d3", + "ldrb w22, [x28, #1010]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fsubp st5, st0": { + "ExpectedInstructionCount": 18, + "Optimal": "No", + "Comment": [ + "0xde 11b 0xed /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x5 (5)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fsub d2, d2, d3", + "ldrb w22, [x28, #1010]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fsubp st6, st0": { + "ExpectedInstructionCount": 18, + "Optimal": "No", + "Comment": [ + "0xde 11b 0xee /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x6 (6)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fsub d2, d2, d3", + "ldrb w22, [x28, #1010]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fsubp st7, st0": { + "ExpectedInstructionCount": 18, + "Optimal": "No", + "Comment": [ + "0xde 11b 0xef /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x7 (7)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fsub d2, d2, d3", + "ldrb w22, [x28, #1010]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "db 0xde, 0xf0": { + "ExpectedInstructionCount": 18, + "Optimal": "No", + "Comment": [ + "fdivrp st0, st0", + "Needs manual encoding since otherwise nasm will emit the 0xd8 variant.", + "0xde 11b 0xf0 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x0 (0)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fdiv d2, d3, d2", + "ldrb w22, [x28, #1010]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fdivrp st1, st0": { + "ExpectedInstructionCount": 18, + "Optimal": "No", + "Comment": [ + "0xde 11b 0xf1 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "mov w21, #0x1", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fdiv d2, d3, d2", + "ldrb w23, [x28, #1010]", + "lsl w21, w21, w20", + "bic w21, w23, w21", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x22, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fdivrp st2, st0": { + "ExpectedInstructionCount": 18, + "Optimal": "No", + "Comment": [ + "0xde 11b 0xf2 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fdiv d2, d3, d2", + "ldrb w22, [x28, #1010]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fdivrp st3, st0": { + "ExpectedInstructionCount": 18, + "Optimal": "No", + "Comment": [ + "0xde 11b 0xf3 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fdiv d2, d3, d2", + "ldrb w22, [x28, #1010]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fdivrp st4, st0": { + "ExpectedInstructionCount": 18, + "Optimal": "No", + "Comment": [ + "0xde 11b 0xf4 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x4 (4)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fdiv d2, d3, d2", + "ldrb w22, [x28, #1010]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fdivrp st5, st0": { + "ExpectedInstructionCount": 18, + "Optimal": "No", + "Comment": [ + "0xde 11b 0xf5 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x5 (5)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fdiv d2, d3, d2", + "ldrb w22, [x28, #1010]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fdivrp st6, st0": { + "ExpectedInstructionCount": 18, + "Optimal": "No", + "Comment": [ + "0xde 11b 0xf6 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x6 (6)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fdiv d2, d3, d2", + "ldrb w22, [x28, #1010]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fdivrp st7, st0": { + "ExpectedInstructionCount": 18, + "Optimal": "No", + "Comment": [ + "0xde 11b 0xf7 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x7 (7)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fdiv d2, d3, d2", + "ldrb w22, [x28, #1010]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "db 0xde, 0xf8": { + "ExpectedInstructionCount": 18, + "Optimal": "No", + "Comment": [ + "fdivp st0, st0", + "Needs manual encoding since otherwise nasm will emit the 0xd8 variant.", + "0xde 11b 0xf8 /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x0 (0)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fdiv d2, d2, d3", + "ldrb w22, [x28, #1010]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fdivp st1, st0": { + "ExpectedInstructionCount": 18, + "Optimal": "No", + "Comment": [ + "0xde 11b 0xf9 /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "mov w21, #0x1", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fdiv d2, d2, d3", + "ldrb w23, [x28, #1010]", + "lsl w21, w21, w20", + "bic w21, w23, w21", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x22, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fdivp st2, st0": { + "ExpectedInstructionCount": 18, + "Optimal": "No", + "Comment": [ + "0xde 11b 0xfa /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fdiv d2, d2, d3", + "ldrb w22, [x28, #1010]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fdivp st3, st0": { + "ExpectedInstructionCount": 18, + "Optimal": "No", + "Comment": [ + "0xde 11b 0xfb /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fdiv d2, d2, d3", + "ldrb w22, [x28, #1010]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fdivp st4, st0": { + "ExpectedInstructionCount": 18, + "Optimal": "No", + "Comment": [ + "0xde 11b 0xfc /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x4 (4)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fdiv d2, d2, d3", + "ldrb w22, [x28, #1010]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fdivp st5, st0": { + "ExpectedInstructionCount": 18, + "Optimal": "No", + "Comment": [ + "0xde 11b 0xfd /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x5 (5)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fdiv d2, d2, d3", + "ldrb w22, [x28, #1010]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fdivp st6, st0": { + "ExpectedInstructionCount": 18, + "Optimal": "No", + "Comment": [ + "0xde 11b 0xfe /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x6 (6)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fdiv d2, d2, d3", + "ldrb w22, [x28, #1010]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fdivp st7, st0": { + "ExpectedInstructionCount": 18, + "Optimal": "No", + "Comment": [ + "0xde 11b 0xff /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x7 (7)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fdiv d2, d2, d3", + "ldrb w22, [x28, #1010]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fild word [rax]": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xdf !11b /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "mov w21, #0x1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "ldrb w22, [x28, #1010]", + "lsl w21, w21, w20", + "orr w21, w22, w21", + "strb w21, [x28, #1010]", + "strb w20, [x28, #747]", + "ldrh w21, [x4]", + "sxth x21, w21", + "scvtf d2, x21", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fisttp word [rax]": { + "ExpectedInstructionCount": 13, + "Optimal": "No", + "Comment": [ + "0xdf !11b /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #752]", + "fcvtzs x21, d2", + "strh w21, [x4]", + "ldrb w21, [x28, #1010]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "fist word [rax]": { + "ExpectedInstructionCount": 6, + "Optimal": "No", + "Comment": [ + "0xdf !11b /2" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #752]", + "frinti d0, d2", + "fcvtzs x20, d0", + "strh w20, [x4]" + ] + }, + "fistp word [rax]": { + "ExpectedInstructionCount": 14, + "Optimal": "No", + "Comment": [ + "0xdf !11b /3" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #752]", + "frinti d0, d2", + "fcvtzs x21, d0", + "strh w21, [x4]", + "ldrb w21, [x28, #1010]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "fbld tword [rax]": { + "ExpectedInstructionCount": 102, + "Optimal": "No", + "Comment": [ + "0xdf !11b /4" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "mov w21, #0x1", + "sub w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "ldrb w22, [x28, #1010]", + "lsl w21, w21, w20", + "orr w21, w22, w21", + "strb w21, [x28, #1010]", + "strb w20, [x28, #747]", + "ldr q2, [x4]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1376]", + "blr x3", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1168]", + "blr x3", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "mov v2.8b, v0.8b", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #752]" + ] + }, + "fbstp tword [rax]": { + "ExpectedInstructionCount": 105, + "Optimal": "No", + "Comment": [ + "0xdf !11b /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #752]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov v0.8b, v2.8b", + "ldrh w0, [x28, #1008]", + "ldr x1, [x28, #1152]", + "blr x1", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1368]", + "blr x3", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "add x5, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "str d2, [x4]", + "mov x21, v2.d[1]", + "strh w21, [x4, #8]", + "ldrb w21, [x28, #1010]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "ffreep st0": { + "ExpectedInstructionCount": 4, + "Optimal": "Yes", + "Comment": [ + "0xdf 11b 0xc0 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "ffreep st1": { + "ExpectedInstructionCount": 4, + "Optimal": "Yes", + "Comment": [ + "0xdf 11b 0xc1 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "ffreep st2": { + "ExpectedInstructionCount": 4, + "Optimal": "Yes", + "Comment": [ + "0xdf 11b 0xc2 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "ffreep st3": { + "ExpectedInstructionCount": 4, + "Optimal": "Yes", + "Comment": [ + "0xdf 11b 0xc3 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "ffreep st4": { + "ExpectedInstructionCount": 4, + "Optimal": "Yes", + "Comment": [ + "0xdf 11b 0xc4 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "ffreep st5": { + "ExpectedInstructionCount": 4, + "Optimal": "Yes", + "Comment": [ + "0xdf 11b 0xc5 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "ffreep st6": { + "ExpectedInstructionCount": 4, + "Optimal": "Yes", + "Comment": [ + "0xdf 11b 0xc6 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "ffreep st7": { + "ExpectedInstructionCount": 4, + "Optimal": "Yes", + "Comment": [ + "0xdf 11b 0xc7 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]" + ] + }, + "fnstsw ax": { + "ExpectedInstructionCount": 12, + "Optimal": "No", + "Comment": [ + "0xdf 11b 0xe0 /4" + ], + "ExpectedArm64ASM": [ + "mov w20, #0x0", + "ldrb w21, [x28, #747]", + "bfi x20, x21, #11, #3", + "ldrb w21, [x28, #744]", + "ldrb w22, [x28, #745]", + "ldrb w23, [x28, #746]", + "ldrb w24, [x28, #750]", + "orr x20, x20, x21, lsl #8", + "orr x20, x20, x22, lsl #9", + "orr x20, x20, x23, lsl #10", + "orr x20, x20, x24, lsl #14", + "bfxil x4, x20, #0, #16" + ] + }, + "fucomip st0": { + "ExpectedInstructionCount": 32, + "Optimal": "No", + "Comment": [ + "0xdf 11b 0xe8 /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x0 (0)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fcmp d3, d2", + "cset x21, eq", + "csinc x21, x21, xzr, vc", + "cset x1, lt", + "bfi x21, x1, #1, #1", + "cset x1, vs", + "bfi x21, x1, #2, #1", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "lsl x22, x22, #29", + "orr w22, w22, w23, lsl #30", + "mov w23, #0x1", + "eor w21, w21, #0x1", + "strb w21, [x28, #706]", + "ldrb w21, [x28, #1010]", + "lsl w23, w23, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "str w22, [x28, #728]" + ] + }, + "fucomip st1": { + "ExpectedInstructionCount": 32, + "Optimal": "No", + "Comment": [ + "0xdf 11b 0xe9 /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "mov w21, #0x1", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fcmp d3, d2", + "cset x22, eq", + "csinc x22, x22, xzr, vc", + "cset x1, lt", + "bfi x22, x1, #1, #1", + "cset x1, vs", + "bfi x22, x1, #2, #1", + "ubfx x23, x22, #1, #1", + "ubfx x24, x22, #0, #1", + "ubfx x22, x22, #2, #1", + "orr w23, w23, w22", + "orr w24, w24, w22", + "lsl x23, x23, #29", + "orr w23, w23, w24, lsl #30", + "eor w22, w22, #0x1", + "strb w22, [x28, #706]", + "ldrb w22, [x28, #1010]", + "lsl w21, w21, w20", + "bic w21, w22, w21", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "str w23, [x28, #728]" + ] + }, + "fucomip st2": { + "ExpectedInstructionCount": 32, + "Optimal": "No", + "Comment": [ + "0xdf 11b 0xea /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fcmp d3, d2", + "cset x21, eq", + "csinc x21, x21, xzr, vc", + "cset x1, lt", + "bfi x21, x1, #1, #1", + "cset x1, vs", + "bfi x21, x1, #2, #1", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "lsl x22, x22, #29", + "orr w22, w22, w23, lsl #30", + "mov w23, #0x1", + "eor w21, w21, #0x1", + "strb w21, [x28, #706]", + "ldrb w21, [x28, #1010]", + "lsl w23, w23, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "str w22, [x28, #728]" + ] + }, + "fucomip st3": { + "ExpectedInstructionCount": 32, + "Optimal": "No", + "Comment": [ + "0xdf 11b 0xeb /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fcmp d3, d2", + "cset x21, eq", + "csinc x21, x21, xzr, vc", + "cset x1, lt", + "bfi x21, x1, #1, #1", + "cset x1, vs", + "bfi x21, x1, #2, #1", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "lsl x22, x22, #29", + "orr w22, w22, w23, lsl #30", + "mov w23, #0x1", + "eor w21, w21, #0x1", + "strb w21, [x28, #706]", + "ldrb w21, [x28, #1010]", + "lsl w23, w23, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "str w22, [x28, #728]" + ] + }, + "fucomip st4": { + "ExpectedInstructionCount": 32, + "Optimal": "No", + "Comment": [ + "0xdf 11b 0xec /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x4 (4)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fcmp d3, d2", + "cset x21, eq", + "csinc x21, x21, xzr, vc", + "cset x1, lt", + "bfi x21, x1, #1, #1", + "cset x1, vs", + "bfi x21, x1, #2, #1", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "lsl x22, x22, #29", + "orr w22, w22, w23, lsl #30", + "mov w23, #0x1", + "eor w21, w21, #0x1", + "strb w21, [x28, #706]", + "ldrb w21, [x28, #1010]", + "lsl w23, w23, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "str w22, [x28, #728]" + ] + }, + "fucomip st5": { + "ExpectedInstructionCount": 32, + "Optimal": "No", + "Comment": [ + "0xdf 11b 0xed /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x5 (5)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fcmp d3, d2", + "cset x21, eq", + "csinc x21, x21, xzr, vc", + "cset x1, lt", + "bfi x21, x1, #1, #1", + "cset x1, vs", + "bfi x21, x1, #2, #1", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "lsl x22, x22, #29", + "orr w22, w22, w23, lsl #30", + "mov w23, #0x1", + "eor w21, w21, #0x1", + "strb w21, [x28, #706]", + "ldrb w21, [x28, #1010]", + "lsl w23, w23, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "str w22, [x28, #728]" + ] + }, + "fucomip st6": { + "ExpectedInstructionCount": 32, + "Optimal": "No", + "Comment": [ + "0xdf 11b 0xee /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x6 (6)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fcmp d3, d2", + "cset x21, eq", + "csinc x21, x21, xzr, vc", + "cset x1, lt", + "bfi x21, x1, #1, #1", + "cset x1, vs", + "bfi x21, x1, #2, #1", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "lsl x22, x22, #29", + "orr w22, w22, w23, lsl #30", + "mov w23, #0x1", + "eor w21, w21, #0x1", + "strb w21, [x28, #706]", + "ldrb w21, [x28, #1010]", + "lsl w23, w23, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "str w22, [x28, #728]" + ] + }, + "fucomip st7": { + "ExpectedInstructionCount": 32, + "Optimal": "No", + "Comment": [ + "0xdf 11b 0xef /5" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x7 (7)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fcmp d3, d2", + "cset x21, eq", + "csinc x21, x21, xzr, vc", + "cset x1, lt", + "bfi x21, x1, #1, #1", + "cset x1, vs", + "bfi x21, x1, #2, #1", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "lsl x22, x22, #29", + "orr w22, w22, w23, lsl #30", + "mov w23, #0x1", + "eor w21, w21, #0x1", + "strb w21, [x28, #706]", + "ldrb w21, [x28, #1010]", + "lsl w23, w23, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "str w22, [x28, #728]" + ] + }, + "fcomip st0": { + "ExpectedInstructionCount": 32, + "Optimal": "No", + "Comment": [ + "0xdf 11b 0xf0 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x0 (0)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fcmp d3, d2", + "cset x21, eq", + "csinc x21, x21, xzr, vc", + "cset x1, lt", + "bfi x21, x1, #1, #1", + "cset x1, vs", + "bfi x21, x1, #2, #1", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "lsl x22, x22, #29", + "orr w22, w22, w23, lsl #30", + "mov w23, #0x1", + "eor w21, w21, #0x1", + "strb w21, [x28, #706]", + "ldrb w21, [x28, #1010]", + "lsl w23, w23, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "str w22, [x28, #728]" + ] + }, + "fcomip st1": { + "ExpectedInstructionCount": 32, + "Optimal": "No", + "Comment": [ + "0xdf 11b 0xf1 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "mov w21, #0x1", + "add w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "add x0, x28, x22, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fcmp d3, d2", + "cset x22, eq", + "csinc x22, x22, xzr, vc", + "cset x1, lt", + "bfi x22, x1, #1, #1", + "cset x1, vs", + "bfi x22, x1, #2, #1", + "ubfx x23, x22, #1, #1", + "ubfx x24, x22, #0, #1", + "ubfx x22, x22, #2, #1", + "orr w23, w23, w22", + "orr w24, w24, w22", + "lsl x23, x23, #29", + "orr w23, w23, w24, lsl #30", + "eor w22, w22, #0x1", + "strb w22, [x28, #706]", + "ldrb w22, [x28, #1010]", + "lsl w21, w21, w20", + "bic w21, w22, w21", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "str w23, [x28, #728]" + ] + }, + "fcomip st2": { + "ExpectedInstructionCount": 32, + "Optimal": "No", + "Comment": [ + "0xdf 11b 0xf2 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fcmp d3, d2", + "cset x21, eq", + "csinc x21, x21, xzr, vc", + "cset x1, lt", + "bfi x21, x1, #1, #1", + "cset x1, vs", + "bfi x21, x1, #2, #1", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "lsl x22, x22, #29", + "orr w22, w22, w23, lsl #30", + "mov w23, #0x1", + "eor w21, w21, #0x1", + "strb w21, [x28, #706]", + "ldrb w21, [x28, #1010]", + "lsl w23, w23, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "str w22, [x28, #728]" + ] + }, + "fcomip st3": { + "ExpectedInstructionCount": 32, + "Optimal": "No", + "Comment": [ + "0xdf 11b 0xf3 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fcmp d3, d2", + "cset x21, eq", + "csinc x21, x21, xzr, vc", + "cset x1, lt", + "bfi x21, x1, #1, #1", + "cset x1, vs", + "bfi x21, x1, #2, #1", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "lsl x22, x22, #29", + "orr w22, w22, w23, lsl #30", + "mov w23, #0x1", + "eor w21, w21, #0x1", + "strb w21, [x28, #706]", + "ldrb w21, [x28, #1010]", + "lsl w23, w23, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "str w22, [x28, #728]" + ] + }, + "fcomip st4": { + "ExpectedInstructionCount": 32, + "Optimal": "No", + "Comment": [ + "0xdf 11b 0xf4 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x4 (4)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fcmp d3, d2", + "cset x21, eq", + "csinc x21, x21, xzr, vc", + "cset x1, lt", + "bfi x21, x1, #1, #1", + "cset x1, vs", + "bfi x21, x1, #2, #1", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "lsl x22, x22, #29", + "orr w22, w22, w23, lsl #30", + "mov w23, #0x1", + "eor w21, w21, #0x1", + "strb w21, [x28, #706]", + "ldrb w21, [x28, #1010]", + "lsl w23, w23, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "str w22, [x28, #728]" + ] + }, + "fcomip st5": { + "ExpectedInstructionCount": 32, + "Optimal": "No", + "Comment": [ + "0xdf 11b 0xf5 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x5 (5)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fcmp d3, d2", + "cset x21, eq", + "csinc x21, x21, xzr, vc", + "cset x1, lt", + "bfi x21, x1, #1, #1", + "cset x1, vs", + "bfi x21, x1, #2, #1", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "lsl x22, x22, #29", + "orr w22, w22, w23, lsl #30", + "mov w23, #0x1", + "eor w21, w21, #0x1", + "strb w21, [x28, #706]", + "ldrb w21, [x28, #1010]", + "lsl w23, w23, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "str w22, [x28, #728]" + ] + }, + "fcomip st6": { + "ExpectedInstructionCount": 32, + "Optimal": "No", + "Comment": [ + "0xdf 11b 0xf6 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x6 (6)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fcmp d3, d2", + "cset x21, eq", + "csinc x21, x21, xzr, vc", + "cset x1, lt", + "bfi x21, x1, #1, #1", + "cset x1, vs", + "bfi x21, x1, #2, #1", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "lsl x22, x22, #29", + "orr w22, w22, w23, lsl #30", + "mov w23, #0x1", + "eor w21, w21, #0x1", + "strb w21, [x28, #706]", + "ldrb w21, [x28, #1010]", + "lsl w23, w23, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "str w22, [x28, #728]" + ] + }, + "fcomip st7": { + "ExpectedInstructionCount": 32, + "Optimal": "No", + "Comment": [ + "0xdf 11b 0xf7 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x7 (7)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr d2, [x0, #752]", + "add x0, x28, x20, lsl #4", + "ldr d3, [x0, #752]", + "fcmp d3, d2", + "cset x21, eq", + "csinc x21, x21, xzr, vc", + "cset x1, lt", + "bfi x21, x1, #1, #1", + "cset x1, vs", + "bfi x21, x1, #2, #1", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "lsl x22, x22, #29", + "orr w22, w22, w23, lsl #30", + "mov w23, #0x1", + "eor w21, w21, #0x1", + "strb w21, [x28, #706]", + "ldrb w21, [x28, #1010]", + "lsl w23, w23, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1010]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "str w22, [x28, #728]" + ] + } + } +}