From 9e1840e9743ac15cadc8f6f7eec0f5b88fba8ef7 Mon Sep 17 00:00:00 2001 From: Ryan Houdek Date: Wed, 8 May 2024 12:00:08 -0700 Subject: [PATCH] FEXCore: Moves CodeEmitter to FHU Now that the vixl dependency is gone, this gets moved to FHU since the frontend is going to need it for a microjit. --- CMakeLists.txt | 1 + CodeEmitter/CMakeLists.txt | 2 + CodeEmitter/CodeEmitter/ALUOps.inl | 1171 ++++++++ .../CodeEmitter/ASIMDOps.inl | 2600 ++++++++--------- .../CodeEmitter/BranchOps.inl | 64 +- .../CodeEmitter/Buffer.h | 4 +- .../CodeEmitter/Emitter.h | 29 +- .../CodeEmitter/LoadstoreOps.inl | 954 +++--- .../CodeEmitter/Registers.h | 4 +- .../CodeEmitter/SVEOps.inl | 14 +- .../CodeEmitter/ScalarOps.inl | 14 +- .../CodeEmitter/SystemOps.inl | 52 +- .../CodeEmitter/VixlUtils.inl | 0 FEXCore/Source/CMakeLists.txt | 2 +- .../Core/ArchHelpers/Arm64Emitter.cpp | 309 +- .../Interface/Core/ArchHelpers/Arm64Emitter.h | 79 +- .../Core/ArchHelpers/CodeEmitter/ALUOps.inl | 1171 -------- .../Interface/Core/Dispatcher/Dispatcher.cpp | 3 +- .../Interface/Core/JIT/Arm64/ALUOps.cpp | 12 +- .../Interface/Core/JIT/Arm64/AtomicOps.cpp | 1 - .../Interface/Core/JIT/Arm64/BranchOps.cpp | 1 - .../Core/JIT/Arm64/ConversionOps.cpp | 19 +- .../Core/JIT/Arm64/EncryptionOps.cpp | 2 - .../Source/Interface/Core/JIT/Arm64/JIT.cpp | 11 +- .../Interface/Core/JIT/Arm64/JITClass.h | 19 +- .../Interface/Core/JIT/Arm64/MemoryOps.cpp | 49 +- .../Interface/Core/JIT/Arm64/MiscOps.cpp | 7 +- .../Interface/Core/JIT/Arm64/VectorOps.cpp | 7 +- FEXCore/unittests/Emitter/ALU_Tests.cpp | 2 +- FEXCore/unittests/Emitter/ASIMD_Tests.cpp | 2 +- FEXCore/unittests/Emitter/Branch_Tests.cpp | 2 +- FEXCore/unittests/Emitter/Loadstore_Tests.cpp | 2 +- FEXCore/unittests/Emitter/SVE_Tests.cpp | 18 +- FEXCore/unittests/Emitter/Scalar_Tests.cpp | 2 +- FEXCore/unittests/Emitter/System_Tests.cpp | 2 +- FEXCore/unittests/Emitter/TestDisassembler.h | 5 +- 36 files changed, 3308 insertions(+), 3328 deletions(-) create mode 100644 CodeEmitter/CMakeLists.txt create mode 100644 CodeEmitter/CodeEmitter/ALUOps.inl rename {FEXCore/Source/Interface/Core/ArchHelpers => CodeEmitter}/CodeEmitter/ASIMDOps.inl (53%) rename {FEXCore/Source/Interface/Core/ArchHelpers => CodeEmitter}/CodeEmitter/BranchOps.inl (79%) rename {FEXCore/Source/Interface/Core/ArchHelpers => CodeEmitter}/CodeEmitter/Buffer.h (97%) rename {FEXCore/Source/Interface/Core/ArchHelpers => CodeEmitter}/CodeEmitter/Emitter.h (97%) rename {FEXCore/Source/Interface/Core/ArchHelpers => CodeEmitter}/CodeEmitter/LoadstoreOps.inl (76%) rename {FEXCore/Source/Interface/Core/ArchHelpers => CodeEmitter}/CodeEmitter/Registers.h (99%) rename {FEXCore/Source/Interface/Core/ArchHelpers => CodeEmitter}/CodeEmitter/SVEOps.inl (99%) rename {FEXCore/Source/Interface/Core/ArchHelpers => CodeEmitter}/CodeEmitter/ScalarOps.inl (99%) rename {FEXCore/Source/Interface/Core/ArchHelpers => CodeEmitter}/CodeEmitter/SystemOps.inl (65%) rename {FEXCore/Source/Interface/Core/ArchHelpers => CodeEmitter}/CodeEmitter/VixlUtils.inl (100%) delete mode 100644 FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/ALUOps.inl diff --git a/CMakeLists.txt b/CMakeLists.txt index 2980aae2a..95168cffa 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -357,6 +357,7 @@ if (BUILD_TESTS) endif() add_subdirectory(FEXHeaderUtils/) +add_subdirectory(CodeEmitter/) add_subdirectory(FEXCore/) # Binfmt_misc files must be installed prior to Source/ installs diff --git a/CodeEmitter/CMakeLists.txt b/CodeEmitter/CMakeLists.txt new file mode 100644 index 000000000..92a4c8e37 --- /dev/null +++ b/CodeEmitter/CMakeLists.txt @@ -0,0 +1,2 @@ +add_library(CodeEmitter INTERFACE) +target_include_directories(CodeEmitter INTERFACE .) diff --git a/CodeEmitter/CodeEmitter/ALUOps.inl b/CodeEmitter/CodeEmitter/ALUOps.inl new file mode 100644 index 000000000..f76a61473 --- /dev/null +++ b/CodeEmitter/CodeEmitter/ALUOps.inl @@ -0,0 +1,1171 @@ +// SPDX-License-Identifier: MIT +/* ALU instruction emitters. + * + * Almost all of these operations have `ARMEmitter::Size` as their first argument. + * This allows both 32-bit and 64-bit selection of how that instruction is going to operate. + * + * Some emitter operations explicitly use `XRegister` or `WRegister`. + * This is usually due to the instruction only supporting one operating size. + * Although in some cases is a minor convenience without any performance implications. + * + * FEX-Emu ALU operations usually have a 32-bit or 64-bit operating size encoded in the IR operation, + * This allows FEX to use a single helper function which decodes to both handlers. + */ +private: + static bool IsADRRange(int64_t Imm) { + return Imm >= -1048576 && Imm <= 1048575; + } + static bool IsADRPRange(int64_t Imm) { + return Imm >= -4294967296 && Imm <= 4294963200; + } + static bool IsADRPAligned(int64_t Imm) { + return (Imm & 0xFFF) == 0; + } +public: + // PC relative + void adr(ARMEmitter::Register rd, uint32_t Imm) { + constexpr uint32_t Op = 0b0001'0000 << 24; + DataProcessing_PCRel_Imm(Op, rd, Imm); + } + + void adr(ARMEmitter::Register rd, BackwardLabel const* Label) { + int32_t Imm = static_cast(Label->Location - GetCursorAddress()); + LOGMAN_THROW_A_FMT(IsADRRange(Imm), "Unscaled offset too large"); + + constexpr uint32_t Op = 0b0001'0000 << 24; + DataProcessing_PCRel_Imm(Op, rd, Imm); + } + template + requires (std::is_same_v || std::is_same_v) + void adr(ARMEmitter::Register rd, LabelType *Label) { + AddLocationToLabel(Label, SingleUseForwardLabel{ .Location = GetCursorAddress(), .Type = SingleUseForwardLabel::InstType::ADR }); + constexpr uint32_t Op = 0b0001'0000 << 24; + DataProcessing_PCRel_Imm(Op, rd, 0); + } + + void adr(ARMEmitter::Register rd, BiDirectionalLabel *Label) { + if (Label->Backward.Location) { + adr(rd, &Label->Backward); + } + else { + adr(rd, &Label->Forward); + } + } + + void adrp(ARMEmitter::Register rd, uint32_t Imm) { + constexpr uint32_t Op = 0b1001'0000 << 24; + DataProcessing_PCRel_Imm(Op, rd, Imm); + } + + void adrp(ARMEmitter::Register rd, BackwardLabel const* Label) { + int64_t Imm = reinterpret_cast(Label->Location) - (GetCursorAddress() & ~0xFFFLL); + LOGMAN_THROW_A_FMT(IsADRPRange(Imm) && IsADRPAligned(Imm), "Unscaled offset too large"); + + constexpr uint32_t Op = 0b1001'0000 << 24; + DataProcessing_PCRel_Imm(Op, rd, Imm); + } + template + requires (std::is_same_v || std::is_same_v) + void adrp(ARMEmitter::Register rd, LabelType *Label) { + AddLocationToLabel(Label, SingleUseForwardLabel{ .Location = GetCursorAddress(), .Type = SingleUseForwardLabel::InstType::ADRP }); + constexpr uint32_t Op = 0b1001'0000 << 24; + DataProcessing_PCRel_Imm(Op, rd, 0); + } + + void adrp(ARMEmitter::Register rd, BiDirectionalLabel *Label) { + if (Label->Backward.Location) { + adrp(rd, &Label->Backward); + } + else { + adrp(rd, &Label->Forward); + } + } + + void LongAddressGen(ARMEmitter::Register rd, BackwardLabel const* Label) { + int64_t Imm = reinterpret_cast(Label->Location) - (GetCursorAddress()); + if (IsADRRange(Imm)) { + // If the range is in ADR range then we can just use ADR. + adr(rd, Label); + } + else if (IsADRPRange(Imm)) { + int64_t ADRPImm = (reinterpret_cast(Label->Location) & ~0xFFFLL) + - (GetCursorAddress() & ~0xFFFLL); + + // If the range is in the ADRP range then we can use ADRP. + bool NeedsOffset = !IsADRPAligned(reinterpret_cast(Label->Location)); + uint64_t AlignedOffset = reinterpret_cast(Label->Location) & 0xFFFULL; + + // First emit ADRP + adrp(rd, ADRPImm >> 12); + + if (NeedsOffset) { + // Now even an add + add(ARMEmitter::Size::i64Bit, rd, rd, AlignedOffset); + } + } + else { + LOGMAN_MSG_A_FMT("Unscaled offset too large"); + FEX_UNREACHABLE; + } + } + void LongAddressGen(ARMEmitter::Register rd, ForwardLabel* Label) { + Label->Insts.emplace_back(SingleUseForwardLabel{ .Location = GetCursorAddress(), .Type = SingleUseForwardLabel::InstType::LONG_ADDRESS_GEN }); + // Emit a register index and a nop. These will be backpatched. + dc32(rd.Idx()); + nop(); + } + + void LongAddressGen(ARMEmitter::Register rd, BiDirectionalLabel *Label) { + if (Label->Backward.Location) { + LongAddressGen(rd, &Label->Backward); + } + else { + LongAddressGen(rd, &Label->Forward); + } + } + + // Add/subtract immediate + void add(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, uint32_t Imm, bool LSL12 = false) { + constexpr uint32_t Op = 0b0001'0001'0 << 23; + DataProcessing_AddSub_Imm(Op, s, rd, rn, Imm, LSL12); + } + + void adds(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, uint32_t Imm, bool LSL12 = false) { + constexpr uint32_t Op = 0b0011'0001'0 << 23; + DataProcessing_AddSub_Imm(Op, s, rd, rn, Imm, LSL12); + } + void cmn(ARMEmitter::Size s, ARMEmitter::Register rn, uint32_t Imm, bool LSL12 = false) { + adds(s, ARMEmitter::Reg::zr, rn, Imm, LSL12); + } + void sub(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, uint32_t Imm, bool LSL12 = false) { + constexpr uint32_t Op = 0b0101'0001'0 << 23; + DataProcessing_AddSub_Imm(Op, s, rd, rn, Imm, LSL12); + } + + void cmp(ARMEmitter::Size s, ARMEmitter::Register rn, uint32_t Imm, bool LSL12 = false) { + constexpr uint32_t Op = 0b0111'0001'0 << 23; + DataProcessing_AddSub_Imm(Op, s, ARMEmitter::Reg::rsp, rn, Imm, LSL12); + } + + void subs(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, uint32_t Imm, bool LSL12 = false) { + constexpr uint32_t Op = 0b0111'0001'0 << 23; + DataProcessing_AddSub_Imm(Op, s, rd, rn, Imm, LSL12); + } + + // Min/max immediate + void smax(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, int64_t Imm) { + LOGMAN_THROW_A_FMT(Imm >= -128 && Imm <= 127, "{} Immediate too large", __func__); + MinMaxImmediate(0b0000, s, rd, rn, Imm); + } + + void umax(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, uint64_t Imm) { + LOGMAN_THROW_A_FMT(Imm <= 255, "{} Immediate too large", __func__); + MinMaxImmediate(0b0001, s, rd, rn, Imm); + } + + void smin(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, int64_t Imm) { + LOGMAN_THROW_A_FMT(Imm >= -128 && Imm <= 127, "{} Immediate too large", __func__); + MinMaxImmediate(0b0010, s, rd, rn, Imm); + } + + void umin(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, uint64_t Imm) { + LOGMAN_THROW_A_FMT(Imm <= 255, "{} Immediate too large", __func__); + MinMaxImmediate(0b0011, s, rd, rn, Imm); + } + + // Logical immediate + void and_(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, uint64_t Imm) { + uint32_t n, immr, imms; + [[maybe_unused]] const auto IsImm = IsImmLogical(Imm, + RegSizeInBits(s), + &n, + &imms, + &immr); + LOGMAN_THROW_A_FMT(IsImm, "Couldn't encode immediate to logical op"); + and_(s, rd, rn, n, immr, imms); + } + + void bic(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, uint64_t Imm) { + and_(s, rd, rn, ~Imm); + } + + void ands(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, uint64_t Imm) { + uint32_t n, immr, imms; + [[maybe_unused]] const auto IsImm = IsImmLogical(Imm, + RegSizeInBits(s), + &n, + &imms, + &immr); + LOGMAN_THROW_A_FMT(IsImm, "Couldn't encode immediate to logical op"); + ands(s, rd, rn, n, immr, imms); + } + + void bics(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, uint64_t Imm) { + ands(s, rd, rn, ~Imm); + } + + void orr(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, uint64_t Imm) { + uint32_t n, immr, imms; + [[maybe_unused]] const auto IsImm = IsImmLogical(Imm, + RegSizeInBits(s), + &n, + &imms, + &immr); + LOGMAN_THROW_A_FMT(IsImm, "Couldn't encode immediate to logical op"); + orr(s, rd, rn, n, immr, imms); + } + + void eor(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, uint64_t Imm) { + uint32_t n, immr, imms; + [[maybe_unused]] const auto IsImm = IsImmLogical(Imm, + RegSizeInBits(s), + &n, + &imms, + &immr); + LOGMAN_THROW_A_FMT(IsImm, "Couldn't encode immediate to logical op"); + eor(s, rd, rn, n, immr, imms); + } + + void tst(ARMEmitter::Size s, Register rn, uint64_t imm) { + ands(s, Reg::zr, rn, imm); + } + + // Move wide immediate + void movn(ARMEmitter::Size s, ARMEmitter::Register rd, uint32_t Imm, uint32_t Offset = 0) { + LOGMAN_THROW_A_FMT((Imm & 0xFFFF0000U) == 0, "Upper bits of move wide not valid"); + LOGMAN_THROW_A_FMT((Offset % 16) == 0, "Offset must be 16bit aligned"); + + constexpr uint32_t Op = 0b001'0010'100 << 21; + DataProcessing_MoveWide(Op, s, rd, Imm, Offset >> 4); + } + void mov(ARMEmitter::Size s, ARMEmitter::Register rd, uint32_t Imm) { + movz(s, rd, Imm, 0); + } + void mov(ARMEmitter::XRegister rd, uint32_t Imm) { + movz(ARMEmitter::Size::i64Bit, rd.R(), Imm, 0); + } + void mov(ARMEmitter::WRegister rd, uint32_t Imm) { + movz(ARMEmitter::Size::i32Bit, rd.R(), Imm, 0); + } + + void movz(ARMEmitter::Size s, ARMEmitter::Register rd, uint32_t Imm, uint32_t Offset = 0) { + LOGMAN_THROW_A_FMT((Imm & 0xFFFF0000U) == 0, "Upper bits of move wide not valid"); + LOGMAN_THROW_A_FMT((Offset % 16) == 0, "Offset must be 16bit aligned"); + + constexpr uint32_t Op = 0b101'0010'100 << 21; + DataProcessing_MoveWide(Op, s, rd, Imm, Offset >> 4); + } + void movk(ARMEmitter::Size s, ARMEmitter::Register rd, uint32_t Imm, uint32_t Offset = 0) { + LOGMAN_THROW_A_FMT((Imm & 0xFFFF0000U) == 0, "Upper bits of move wide not valid"); + LOGMAN_THROW_A_FMT((Offset % 16) == 0, "Offset must be 16bit aligned"); + + constexpr uint32_t Op = 0b111'0010'100 << 21; + DataProcessing_MoveWide(Op, s, rd, Imm, Offset >> 4); + } + + void movn(ARMEmitter::XRegister rd, uint32_t Imm, uint32_t Offset = 0) { + movn(ARMEmitter::Size::i64Bit, rd.R(), Imm, Offset); + } + void movz(ARMEmitter::XRegister rd, uint32_t Imm, uint32_t Offset = 0) { + movz(ARMEmitter::Size::i64Bit, rd.R(), Imm, Offset); + } + void movk(ARMEmitter::XRegister rd, uint32_t Imm, uint32_t Offset = 0) { + movk(ARMEmitter::Size::i64Bit, rd.R(), Imm, Offset); + } + void movn(ARMEmitter::WRegister rd, uint32_t Imm, uint32_t Offset = 0) { + movn(ARMEmitter::Size::i32Bit, rd.R(), Imm, Offset); + } + void movz(ARMEmitter::WRegister rd, uint32_t Imm, uint32_t Offset = 0) { + movz(ARMEmitter::Size::i32Bit, rd.R(), Imm, Offset); + } + void movk(ARMEmitter::WRegister rd, uint32_t Imm, uint32_t Offset = 0) { + movk(ARMEmitter::Size::i32Bit, rd.R(), Imm, Offset); + } + + // Bitfield + void sxtb(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn) { + sbfm(s, rd, rn, 0, 7); + } + void sxth(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn) { + sbfm(s, rd, rn, 0, 15); + } + void sxtw(ARMEmitter::XRegister rd, ARMEmitter::WRegister rn) { + sbfm(ARMEmitter::Size::i64Bit, rd, rn.X(), 0, 31); + } + void sbfx(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, uint32_t lsb, uint32_t width) { + LOGMAN_THROW_A_FMT(width > 0, "sbfx needs width > 0"); + LOGMAN_THROW_A_FMT((lsb + width) <= RegSizeInBits(s), "Tried to sbfx a region larger than the register"); + sbfm(s, rd, rn, lsb, lsb + width - 1); + } + void sbfiz(ARMEmitter::Size s, Register rd, Register rn, uint32_t lsb, uint32_t width) { + xbfiz_helper(true, s, rd, rn, lsb, width); + } + void asr(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, uint32_t shift) { + LOGMAN_THROW_A_FMT(shift <= RegSizeInBits(s), "Tried to asr a region larger than the register"); + sbfm(s, rd, rn, shift, RegSizeInBits(s) - 1); + } + + void uxtb(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn) { + ubfm(s, rd, rn, 0, 7); + } + void uxth(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn) { + ubfm(s, rd, rn, 0, 15); + } + void uxtw(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn) { + ubfm(s, rd, rn, 0, 31); + } + + void ubfm(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, uint32_t immr, uint32_t imms) { + constexpr uint32_t Op = 0b0101'0011'00 << 22; + DataProcessing_Logical_Imm(Op, s, rd, rn, s == ARMEmitter::Size::i64Bit, immr, imms); + } + + void ubfiz(ARMEmitter::Size s, Register rd, Register rn, uint32_t lsb, uint32_t width) { + xbfiz_helper(false, s, rd, rn, lsb, width); + } + + void lsl(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, uint32_t shift) { + const auto RegSize = RegSizeInBits(s); + LOGMAN_THROW_A_FMT(shift < RegSize, "Tried to lsl a region larger than the register"); + ubfm(s, rd, rn, (RegSize - shift) % RegSize, RegSize - shift - 1); + } + void lsr(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, uint32_t shift) { + const auto RegSize = RegSizeInBits(s); + LOGMAN_THROW_A_FMT(shift < RegSize, "Tried to lsr a region larger than the register"); + ubfm(s, rd, rn, shift, RegSize - 1); + } + void ubfx(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, uint32_t lsb, uint32_t width) { + LOGMAN_THROW_A_FMT(width > 0, "ubfx needs width > 0"); + LOGMAN_THROW_A_FMT((lsb + width) <= RegSizeInBits(s), "Tried to ubfx a region larger than the register"); + ubfm(s, rd, rn, lsb, lsb + width - 1); + } + + void bfi(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, uint32_t lsb, uint32_t width) { + const auto RegSize = RegSizeInBits(s); + LOGMAN_THROW_A_FMT(width > 0, "bfc/bfi needs width > 0"); + LOGMAN_THROW_A_FMT((lsb + width) <= RegSize, "Tried to bfc/bfi a region larger than the register"); + bfm(s, rd, rn, (RegSize - lsb) & (RegSize - 1), width - 1); + } + void bfc(ARMEmitter::Size s, Register rd, uint32_t lsb, uint32_t width) { + bfi(s, rd, Reg::zr, lsb, width); + } + void bfxil(ARMEmitter::Size s, Register rd, Register rn, uint32_t lsb, uint32_t width) { + [[maybe_unused]] const auto reg_size_bits = RegSizeInBits(s); + const auto lsb_p_width = lsb + width; + + LOGMAN_THROW_A_FMT(width >= 1, "bfxil needs width >= 1"); + LOGMAN_THROW_A_FMT(lsb_p_width <= reg_size_bits, "bfxil lsb + width ({}) must be <= {}. lsb={}, width={}", + lsb_p_width, reg_size_bits, lsb, width); + + bfm(s, rd, rn, lsb, lsb_p_width - 1); + } + + // Extract + void extr(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, ARMEmitter::Register rm, uint32_t Imm) { + constexpr uint32_t Op = 0b001'0011'100 << 21; + LOGMAN_THROW_A_FMT(Imm < RegSizeInBits(s), "Tried to extr a region larger than the register"); + DataProcessing_Extract(Op, s, rd, rn, rm, Imm); + } + + void ror(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, uint32_t Imm) { + extr(s, rd, rn, rn, Imm); + } + + // Data processing - 2 source + void udiv(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, ARMEmitter::Register rm) { + constexpr uint32_t Op = (0b001'1010'110U << 21) | + (0b0000'10U << 10); + DataProcessing_2Source(Op, s, rd, rn, rm); + } + void sdiv(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, ARMEmitter::Register rm) { + constexpr uint32_t Op = (0b001'1010'110U << 21) | + (0b0000'11U << 10); + DataProcessing_2Source(Op, s, rd, rn, rm); + } + + void lslv(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, ARMEmitter::Register rm) { + constexpr uint32_t Op = (0b001'1010'110U << 21) | + (0b0010'00U << 10); + DataProcessing_2Source(Op, s, rd, rn, rm); + } + void lsrv(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, ARMEmitter::Register rm) { + constexpr uint32_t Op = (0b001'1010'110U << 21) | + (0b0010'01U << 10); + DataProcessing_2Source(Op, s, rd, rn, rm); + } + void asrv(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, ARMEmitter::Register rm) { + constexpr uint32_t Op = (0b001'1010'110U << 21) | + (0b0010'10U << 10); + DataProcessing_2Source(Op, s, rd, rn, rm); + } + void rorv(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, ARMEmitter::Register rm) { + constexpr uint32_t Op = (0b001'1010'110U << 21) | + (0b0010'11U << 10); + DataProcessing_2Source(Op, s, rd, rn, rm); + } + void crc32b(ARMEmitter::WRegister rd, ARMEmitter::WRegister rn, ARMEmitter::WRegister rm) { + constexpr uint32_t Op = (0b001'1010'110U << 21) | + (0b0100'00U << 10); + DataProcessing_2Source(Op, ARMEmitter::Size::i32Bit, rd, rn, rm); + } + void crc32h(ARMEmitter::WRegister rd, ARMEmitter::WRegister rn, ARMEmitter::WRegister rm) { + constexpr uint32_t Op = (0b001'1010'110U << 21) | + (0b0100'01U << 10); + DataProcessing_2Source(Op, ARMEmitter::Size::i32Bit, rd, rn, rm); + } + void crc32w(ARMEmitter::WRegister rd, ARMEmitter::WRegister rn, ARMEmitter::WRegister rm) { + constexpr uint32_t Op = (0b001'1010'110U << 21) | + (0b0100'10U << 10); + DataProcessing_2Source(Op, ARMEmitter::Size::i32Bit, rd, rn, rm); + } + void crc32cb(ARMEmitter::WRegister rd, ARMEmitter::WRegister rn, ARMEmitter::WRegister rm) { + constexpr uint32_t Op = (0b001'1010'110U << 21) | + (0b0101'00U << 10); + DataProcessing_2Source(Op, ARMEmitter::Size::i32Bit, rd, rn, rm); + } + void crc32ch(ARMEmitter::WRegister rd, ARMEmitter::WRegister rn, ARMEmitter::WRegister rm) { + constexpr uint32_t Op = (0b001'1010'110U << 21) | + (0b0101'01U << 10); + DataProcessing_2Source(Op, ARMEmitter::Size::i32Bit, rd, rn, rm); + } + void crc32cw(ARMEmitter::WRegister rd, ARMEmitter::WRegister rn, ARMEmitter::WRegister rm) { + constexpr uint32_t Op = (0b001'1010'110U << 21) | + (0b0101'10U << 10); + DataProcessing_2Source(Op, ARMEmitter::Size::i32Bit, rd, rn, rm); + } + void smax(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, ARMEmitter::Register rm) { + constexpr uint32_t Op = (0b001'1010'110U << 21) | + (0b0110'00U << 10); + DataProcessing_2Source(Op, s, rd, rn, rm); + } + void umax(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, ARMEmitter::Register rm) { + constexpr uint32_t Op = (0b001'1010'110U << 21) | + (0b0110'01U << 10); + DataProcessing_2Source(Op, s, rd, rn, rm); + } + void smin(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, ARMEmitter::Register rm) { + constexpr uint32_t Op = (0b001'1010'110U << 21) | + (0b0110'10U << 10); + DataProcessing_2Source(Op, s, rd, rn, rm); + } + void umin(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, ARMEmitter::Register rm) { + constexpr uint32_t Op = (0b001'1010'110U << 21) | + (0b0110'11U << 10); + DataProcessing_2Source(Op, s, rd, rn, rm); + } + void subp(ARMEmitter::XRegister rd, ARMEmitter::XRegister rn, ARMEmitter::XRegister rm) { + constexpr uint32_t Op = (0b001'1010'110U << 21) | + (0b0000'00U << 10); + DataProcessing_2Source(Op, ARMEmitter::Size::i64Bit, rd, rn, rm); + } + void irg(ARMEmitter::XRegister rd, ARMEmitter::XRegister rn, ARMEmitter::XRegister rm) { + constexpr uint32_t Op = (0b001'1010'110U << 21) | + (0b0001'00U << 10); + DataProcessing_2Source(Op, ARMEmitter::Size::i64Bit, rd, rn, rm); + } + void gmi(ARMEmitter::XRegister rd, ARMEmitter::XRegister rn, ARMEmitter::XRegister rm) { + constexpr uint32_t Op = (0b001'1010'110U << 21) | + (0b0001'01U << 10); + DataProcessing_2Source(Op, ARMEmitter::Size::i64Bit, rd, rn, rm); + } + void pacga(ARMEmitter::XRegister rd, ARMEmitter::XRegister rn, ARMEmitter::XRegister rm) { + constexpr uint32_t Op = (0b001'1010'110U << 21) | + (0b0011'00U << 10); + DataProcessing_2Source(Op, ARMEmitter::Size::i64Bit, rd, rn, rm); + } + void crc32x(ARMEmitter::XRegister rd, ARMEmitter::XRegister rn, ARMEmitter::XRegister rm) { + constexpr uint32_t Op = (0b001'1010'110U << 21) | + (0b0100'11U << 10); + DataProcessing_2Source(Op, ARMEmitter::Size::i64Bit, rd, rn, rm); + } + void crc32cx(ARMEmitter::XRegister rd, ARMEmitter::XRegister rn, ARMEmitter::XRegister rm) { + constexpr uint32_t Op = (0b001'1010'110U << 21) | + (0b0101'11U << 10); + DataProcessing_2Source(Op, ARMEmitter::Size::i64Bit, rd, rn, rm); + } + void subps(ARMEmitter::XRegister rd, ARMEmitter::XRegister rn, ARMEmitter::XRegister rm) { + constexpr uint32_t Op = (0b011'1010'110U << 21) | + (0b0000'00U << 10); + DataProcessing_2Source(Op, ARMEmitter::Size::i64Bit, rd, rn, rm); + } + + // Data processing - 1 source + void rbit(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn) { + constexpr uint32_t Op = (0b101'1010'110U << 21) | + (0b0'0000U << 16) | + (0b0000'00U << 10); + DataProcessing_1Source(Op, s, rd, rn); + } + void rev16(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn) { + constexpr uint32_t Op = (0b101'1010'110U << 21) | + (0b0'0000U << 16) | + (0b0000'01U << 10); + DataProcessing_1Source(Op, s, rd, rn); + } + void rev(ARMEmitter::WRegister rd, ARMEmitter::WRegister rn) { + constexpr uint32_t Op = (0b101'1010'110U << 21) | + (0b0'0000U << 16) | + (0b0000'10U << 10); + DataProcessing_1Source(Op, ARMEmitter::Size::i32Bit, rd, rn); + } + void rev32(ARMEmitter::XRegister rd, ARMEmitter::XRegister rn) { + constexpr uint32_t Op = (0b101'1010'110U << 21) | + (0b0'0000U << 16) | + (0b0000'10U << 10); + DataProcessing_1Source(Op, ARMEmitter::Size::i64Bit, rd, rn); + } + void clz(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn) { + constexpr uint32_t Op = (0b101'1010'110U << 21) | + (0b0'0000U << 16) | + (0b0001'00U << 10); + DataProcessing_1Source(Op, s, rd, rn); + } + void cls(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn) { + constexpr uint32_t Op = (0b101'1010'110U << 21) | + (0b0'0000U << 16) | + (0b0001'01U << 10); + DataProcessing_1Source(Op, s, rd, rn); + } + void rev(ARMEmitter::XRegister rd, ARMEmitter::XRegister rn) { + constexpr uint32_t Op = (0b101'1010'110U << 21) | + (0b0'0000U << 16) | + (0b0000'11U << 10); + DataProcessing_1Source(Op, ARMEmitter::Size::i64Bit, rd, rn); + } + void rev(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn) { + uint32_t Op = (0b101'1010'110U << 21) | + (0b0'0000U << 16) | + (0b0000'10U << 10) | + (s == ARMEmitter::Size::i64Bit ? (1U << 10) : 0); + DataProcessing_1Source(Op, s, rd, rn); + } + void ctz(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn) { + constexpr uint32_t Op = (0b101'1010'110U << 21) | + (0b0'0000U << 16) | + (0b0001'10U << 10); + DataProcessing_1Source(Op, s, rd, rn); + } + void cnt(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn) { + constexpr uint32_t Op = (0b101'1010'110U << 21) | + (0b0'0000U << 16) | + (0b0001'11U << 10); + DataProcessing_1Source(Op, s, rd, rn); + } + void abs(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn) { + constexpr uint32_t Op = (0b101'1010'110U << 21) | + (0b0'0000U << 16) | + (0b0010'00U << 10); + DataProcessing_1Source(Op, s, rd, rn); + } + + // TODO: PAUTH + + // Logical - shifted register + void mov(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn) { + orr(s, rd, ARMEmitter::Reg::zr, rn, ARMEmitter::ShiftType::LSL, 0); + } + void mov(ARMEmitter::XRegister rd, ARMEmitter::XRegister rn) { + orr(ARMEmitter::Size::i64Bit, rd.R(), ARMEmitter::Reg::zr, rn.R(), ARMEmitter::ShiftType::LSL, 0); + } + void mov(ARMEmitter::WRegister rd, ARMEmitter::WRegister rn) { + orr(ARMEmitter::Size::i32Bit, rd.R(), ARMEmitter::Reg::zr, rn.R(), ARMEmitter::ShiftType::LSL, 0); + } + + void mvn(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, ARMEmitter::ShiftType Shift = ARMEmitter::ShiftType::LSL, uint32_t amt = 0) { + orn(s, rd, ARMEmitter::Reg::zr, rn, Shift, amt); + } + + void and_(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, ARMEmitter::Register rm, ARMEmitter::ShiftType Shift = ARMEmitter::ShiftType::LSL, uint32_t amt = 0) { + constexpr uint32_t Op = 0b000'1010'000U << 21; + DataProcessing_Shifted_Reg(Op, s, rd, rn, rm, Shift, amt); + } + void ands(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, ARMEmitter::Register rm, ARMEmitter::ShiftType Shift = ARMEmitter::ShiftType::LSL, uint32_t amt = 0) { + constexpr uint32_t Op = 0b110'1010'000U << 21; + DataProcessing_Shifted_Reg(Op, s, rd, rn, rm, Shift, amt); + } + void bic(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, ARMEmitter::Register rm, ARMEmitter::ShiftType Shift = ARMEmitter::ShiftType::LSL, uint32_t amt = 0) { + constexpr uint32_t Op = 0b000'1010'001U << 21; + DataProcessing_Shifted_Reg(Op, s, rd, rn, rm, Shift, amt); + } + void bics(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, ARMEmitter::Register rm, ARMEmitter::ShiftType Shift = ARMEmitter::ShiftType::LSL, uint32_t amt = 0) { + constexpr uint32_t Op = 0b110'1010'001U << 21; + DataProcessing_Shifted_Reg(Op, s, rd, rn, rm, Shift, amt); + } + void orr(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, ARMEmitter::Register rm, ARMEmitter::ShiftType Shift = ARMEmitter::ShiftType::LSL, uint32_t amt = 0) { + constexpr uint32_t Op = 0b010'1010'000U << 21; + DataProcessing_Shifted_Reg(Op, s, rd, rn, rm, Shift, amt); + } + void tst(ARMEmitter::Size s, Register rn, Register rm, ShiftType shift = ShiftType::LSL, uint32_t amt = 0) { + ands(s, Reg::zr, rn, rm, shift, amt); + } + + void orn(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, ARMEmitter::Register rm, ARMEmitter::ShiftType Shift = ARMEmitter::ShiftType::LSL, uint32_t amt = 0) { + constexpr uint32_t Op = 0b010'1010'001U << 21; + DataProcessing_Shifted_Reg(Op, s, rd, rn, rm, Shift, amt); + } + void eor(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, ARMEmitter::Register rm, ARMEmitter::ShiftType Shift = ARMEmitter::ShiftType::LSL, uint32_t amt = 0) { + constexpr uint32_t Op = 0b100'1010'000U << 21; + DataProcessing_Shifted_Reg(Op, s, rd, rn, rm, Shift, amt); + } + void eon(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, ARMEmitter::Register rm, ARMEmitter::ShiftType Shift = ARMEmitter::ShiftType::LSL, uint32_t amt = 0) { + constexpr uint32_t Op = 0b100'1010'001U << 21; + DataProcessing_Shifted_Reg(Op, s, rd, rn, rm, Shift, amt); + } + + // AddSub - shifted register + void add(ARMEmitter::XRegister rd, ARMEmitter::XRegister rn, ARMEmitter::XRegister rm, ARMEmitter::ShiftType Shift = ARMEmitter::ShiftType::LSL, uint32_t amt = 0) { + add(ARMEmitter::Size::i64Bit, rd.R(), rn.R(), rm.R(), Shift, amt); + } + void adds(ARMEmitter::XRegister rd, ARMEmitter::XRegister rn, ARMEmitter::XRegister rm, ARMEmitter::ShiftType Shift = ARMEmitter::ShiftType::LSL, uint32_t amt = 0) { + adds(ARMEmitter::Size::i64Bit, rd.R(), rn.R(), rm.R(), Shift, amt); + } + void cmn(ARMEmitter::XRegister rn, ARMEmitter::XRegister rm, ARMEmitter::ShiftType Shift = ARMEmitter::ShiftType::LSL, uint32_t amt = 0) { + adds(ARMEmitter::Size::i64Bit, ARMEmitter::XReg::zr, rn.R(), rm.R(), Shift, amt); + } + void sub(ARMEmitter::XRegister rd, ARMEmitter::XRegister rn, ARMEmitter::XRegister rm, ARMEmitter::ShiftType Shift = ARMEmitter::ShiftType::LSL, uint32_t amt = 0) { + sub(ARMEmitter::Size::i64Bit, rd.R(), rn.R(), rm.R(), Shift, amt); + } + void neg(ARMEmitter::XRegister rd, ARMEmitter::XRegister rm, ARMEmitter::ShiftType Shift = ARMEmitter::ShiftType::LSL, uint32_t amt = 0) { + sub(rd, ARMEmitter::XReg::zr, rm, Shift, amt); + } + void cmp(ARMEmitter::XRegister rn, ARMEmitter::XRegister rm, ARMEmitter::ShiftType Shift = ARMEmitter::ShiftType::LSL, uint32_t amt = 0) { + subs(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::rsp, rn.R(), rm.R(), Shift, amt); + } + void subs(ARMEmitter::XRegister rd, ARMEmitter::XRegister rn, ARMEmitter::XRegister rm, ARMEmitter::ShiftType Shift = ARMEmitter::ShiftType::LSL, uint32_t amt = 0) { + subs(ARMEmitter::Size::i64Bit, rd.R(), rn.R(), rm.R(), Shift, amt); + } + void negs(ARMEmitter::XRegister rd, ARMEmitter::XRegister rm, ARMEmitter::ShiftType Shift = ARMEmitter::ShiftType::LSL, uint32_t amt = 0) { + subs(rd, ARMEmitter::XReg::zr, rm, Shift, amt); + } + + void add(ARMEmitter::WRegister rd, ARMEmitter::WRegister rn, ARMEmitter::WRegister rm, ARMEmitter::ShiftType Shift = ARMEmitter::ShiftType::LSL, uint32_t amt = 0) { + add(ARMEmitter::Size::i32Bit, rd.R(), rn.R(), rm.R(), Shift, amt); + } + void adds(ARMEmitter::WRegister rd, ARMEmitter::WRegister rn, ARMEmitter::WRegister rm, ARMEmitter::ShiftType Shift = ARMEmitter::ShiftType::LSL, uint32_t amt = 0) { + adds(ARMEmitter::Size::i32Bit, rd.R(), rn.R(), rm.R(), Shift, amt); + } + void cmn(ARMEmitter::WRegister rn, ARMEmitter::WRegister rm, ARMEmitter::ShiftType Shift = ARMEmitter::ShiftType::LSL, uint32_t amt = 0) { + adds(ARMEmitter::Size::i32Bit, ARMEmitter::WReg::zr, rn.R(), rm.R(), Shift, amt); + } + void sub(ARMEmitter::WRegister rd, ARMEmitter::WRegister rn, ARMEmitter::WRegister rm, ARMEmitter::ShiftType Shift = ARMEmitter::ShiftType::LSL, uint32_t amt = 0) { + sub(ARMEmitter::Size::i32Bit, rd.R(), rn.R(), rm.R(), Shift, amt); + } + void neg(ARMEmitter::WRegister rd, ARMEmitter::WRegister rm, ARMEmitter::ShiftType Shift = ARMEmitter::ShiftType::LSL, uint32_t amt = 0) { + sub(rd, ARMEmitter::WReg::zr, rm, Shift, amt); + } + void cmp(ARMEmitter::WRegister rn, ARMEmitter::WRegister rm, ARMEmitter::ShiftType Shift = ARMEmitter::ShiftType::LSL, uint32_t amt = 0) { + subs(ARMEmitter::Size::i32Bit, ARMEmitter::Reg::rsp, rn.R(), rm.R(), Shift, amt); + } + void subs(ARMEmitter::WRegister rd, ARMEmitter::WRegister rn, ARMEmitter::WRegister rm, ARMEmitter::ShiftType Shift = ARMEmitter::ShiftType::LSL, uint32_t amt = 0) { + subs(ARMEmitter::Size::i32Bit, rd.R(), rn.R(), rm.R(), Shift, amt); + } + void negs(ARMEmitter::WRegister rd, ARMEmitter::WRegister rm, ARMEmitter::ShiftType Shift = ARMEmitter::ShiftType::LSL, uint32_t amt = 0) { + subs(rd, ARMEmitter::WReg::zr, rm, Shift, amt); + } + + void add(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, ARMEmitter::Register rm, ARMEmitter::ShiftType Shift = ARMEmitter::ShiftType::LSL, uint32_t amt = 0) { + LOGMAN_THROW_AA_FMT(Shift != ARMEmitter::ShiftType::ROR, "Doesn't support ROR"); + constexpr uint32_t Op = 0b000'1011'000U << 21; + DataProcessing_Shifted_Reg(Op, s, rd, rn, rm, Shift, amt); + } + void adds(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, ARMEmitter::Register rm, ARMEmitter::ShiftType Shift = ARMEmitter::ShiftType::LSL, uint32_t amt = 0) { + LOGMAN_THROW_AA_FMT(Shift != ARMEmitter::ShiftType::ROR, "Doesn't support ROR"); + constexpr uint32_t Op = 0b010'1011'000U << 21; + DataProcessing_Shifted_Reg(Op, s, rd, rn, rm, Shift, amt); + } + void cmn(ARMEmitter::Size s, ARMEmitter::Register rn, ARMEmitter::Register rm, ARMEmitter::ShiftType Shift = ARMEmitter::ShiftType::LSL, uint32_t amt = 0) { + adds(s, ARMEmitter::Reg::zr, rn, rm, Shift, amt); + } + void sub(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, ARMEmitter::Register rm, ARMEmitter::ShiftType Shift = ARMEmitter::ShiftType::LSL, uint32_t amt = 0) { + LOGMAN_THROW_AA_FMT(Shift != ARMEmitter::ShiftType::ROR, "Doesn't support ROR"); + constexpr uint32_t Op = 0b100'1011'000U << 21; + DataProcessing_Shifted_Reg(Op, s, rd, rn, rm, Shift, amt); + } + void neg(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rm, ARMEmitter::ShiftType Shift = ARMEmitter::ShiftType::LSL, uint32_t amt = 0) { + sub(s, rd, ARMEmitter::Reg::zr, rm, Shift, amt); + } + void cmp(ARMEmitter::Size s, ARMEmitter::Register rn, ARMEmitter::Register rm, ARMEmitter::ShiftType Shift = ARMEmitter::ShiftType::LSL, uint32_t amt = 0) { + subs(s, ARMEmitter::Reg::zr, rn, rm, Shift, amt); + } + + void subs(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, ARMEmitter::Register rm, ARMEmitter::ShiftType Shift = ARMEmitter::ShiftType::LSL, uint32_t amt = 0) { + LOGMAN_THROW_AA_FMT(Shift != ARMEmitter::ShiftType::ROR, "Doesn't support ROR"); + constexpr uint32_t Op = 0b110'1011'000U << 21; + DataProcessing_Shifted_Reg(Op, s, rd, rn, rm, Shift, amt); + } + void negs(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rm, ARMEmitter::ShiftType Shift = ARMEmitter::ShiftType::LSL, uint32_t amt = 0) { + subs(s, rd, ARMEmitter::Reg::zr, rm, Shift, amt); + } + + // AddSub - extended register + void add(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, ARMEmitter::Register rm, ARMEmitter::ExtendedType Option, uint32_t Shift = 0) { + LOGMAN_THROW_AA_FMT(Shift <= 4, "Shift amount is too large"); + constexpr uint32_t Op = 0b000'1011'001U << 21; + DataProcessing_Extended_Reg(Op, s, rd, rn, rm, Option, Shift); + } + void adds(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, ARMEmitter::Register rm, ARMEmitter::ExtendedType Option, uint32_t Shift = 0) { + constexpr uint32_t Op = 0b010'1011'001U << 21; + DataProcessing_Extended_Reg(Op, s, rd, rn, rm, Option, Shift); + } + void cmn(ARMEmitter::Size s, ARMEmitter::Register rn, ARMEmitter::Register rm, ARMEmitter::ExtendedType Option, uint32_t Shift = 0) { + adds(s, ARMEmitter::Reg::zr, rn, rm, Option, Shift); + } + void sub(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, ARMEmitter::Register rm, ARMEmitter::ExtendedType Option, uint32_t Shift = 0) { + constexpr uint32_t Op = 0b100'1011'001U << 21; + DataProcessing_Extended_Reg(Op, s, rd, rn, rm, Option, Shift); + } + void subs(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, ARMEmitter::Register rm, ARMEmitter::ExtendedType Option, uint32_t Shift = 0) { + constexpr uint32_t Op = 0b110'1011'001U << 21; + DataProcessing_Extended_Reg(Op, s, rd, rn, rm, Option, Shift); + } + void cmp(ARMEmitter::Size s, ARMEmitter::Register rn, ARMEmitter::Register rm, ARMEmitter::ExtendedType Option, uint32_t Shift = 0) { + constexpr uint32_t Op = 0b110'1011'001U << 21; + DataProcessing_Extended_Reg(Op, s, ARMEmitter::Reg::zr, rn, rm, Option, Shift); + } + + // AddSub - with carry + void adc(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, ARMEmitter::Register rm) { + constexpr uint32_t Op = 0b0001'1010'000U << 21; + DataProcessing_Extended_Reg(Op, s, rd, rn, rm, ARMEmitter::ExtendedType::UXTB, 0); + } + void adcs(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, ARMEmitter::Register rm) { + constexpr uint32_t Op = 0b0011'1010'000U << 21; + DataProcessing_Extended_Reg(Op, s, rd, rn, rm, ARMEmitter::ExtendedType::UXTB, 0); + } + void sbc(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, ARMEmitter::Register rm) { + constexpr uint32_t Op = 0b0101'1010'000U << 21; + DataProcessing_Extended_Reg(Op, s, rd, rn, rm, ARMEmitter::ExtendedType::UXTB, 0); + } + void sbcs(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, ARMEmitter::Register rm) { + constexpr uint32_t Op = 0b0111'1010'000U << 21; + DataProcessing_Extended_Reg(Op, s, rd, rn, rm, ARMEmitter::ExtendedType::UXTB, 0); + } + void ngc(ARMEmitter::Size s, Register rd, Register rm) { + sbc(s, rd, Reg::zr, rm); + } + void ngcs(ARMEmitter::Size s, Register rd, Register rm) { + sbcs(s, rd, Reg::zr, rm); + } + + // Rotate right into flags + void rmif(XRegister rn, uint32_t shift, uint32_t mask) { + LOGMAN_THROW_AA_FMT(shift <= 63, "Shift must be within 0-63. Shift: {}", shift); + LOGMAN_THROW_AA_FMT(mask <= 15, "Mask must be within 0-15. Mask: {}", mask); + + uint32_t Op = 0b1011'1010'0000'0000'0000'0100'0000'0000; + Op |= rn.Idx() << 5; + Op |= shift << 15; + Op |= mask; + + dc32(Op); + } + + // Evaluate into flags + void setf8(WRegister rn) { + constexpr uint32_t Op = 0b0011'1010'0000'0000'0000'1000'0000'1101; + EvaluateIntoFlags(Op, 0, rn); + } + void setf16(WRegister rn) { + constexpr uint32_t Op = 0b0011'1010'0000'0000'0000'1000'0000'1101; + EvaluateIntoFlags(Op, 1, rn); + } + + void cfinv() { + constexpr uint32_t Op = 0b1101'0101'0000'0000'0100'0000'0001'1111; + dc32(Op); + } + + void axflag() { + constexpr uint32_t Op = 0b1101'0101'0000'0000'0100'0000'0101'1111; + dc32(Op); + } + + void xaflag() { + constexpr uint32_t Op = 0b1101'0101'0000'0000'0100'0000'0011'1111; + dc32(Op); + } + + // Conditional compare - register + void ccmn(ARMEmitter::Size s, ARMEmitter::Register rn, ARMEmitter::Register rm, ARMEmitter::StatusFlags flags, ARMEmitter::Condition Cond) { + constexpr uint32_t Op = 0b0011'1010'010 << 21; + ConditionalCompare(Op, 0, 0b00, 0, s, rn, rm, flags, Cond); + } + void ccmp(ARMEmitter::Size s, ARMEmitter::Register rn, ARMEmitter::Register rm, ARMEmitter::StatusFlags flags, ARMEmitter::Condition Cond) { + constexpr uint32_t Op = 0b0011'1010'010 << 21; + ConditionalCompare(Op, 1, 0b00, 0, s, rn, rm, flags, Cond); + } + + // Conditional compare - immediate + void ccmn(ARMEmitter::Size s, ARMEmitter::Register rn, uint32_t rm, ARMEmitter::StatusFlags flags, ARMEmitter::Condition Cond) { + LOGMAN_THROW_A_FMT((rm & ~0b1'1111) == 0, "Comparison imm too large"); + constexpr uint32_t Op = 0b0011'1010'010 << 21; + ConditionalCompare(Op, 0, 0b10, 0, s, rn, rm, flags, Cond); + } + void ccmp(ARMEmitter::Size s, ARMEmitter::Register rn, uint32_t rm, ARMEmitter::StatusFlags flags, ARMEmitter::Condition Cond) { + LOGMAN_THROW_A_FMT((rm & ~0b1'1111) == 0, "Comparison imm too large"); + constexpr uint32_t Op = 0b0011'1010'010 << 21; + ConditionalCompare(Op, 1, 0b10, 0, s, rn, rm, flags, Cond); + } + + // Conditional select + void csel(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, ARMEmitter::Register rm, ARMEmitter::Condition Cond) { + constexpr uint32_t Op = 0b0001'1010'100 << 21; + ConditionalCompare(Op, 0, 0b00, s, rd, rn, rm, Cond); + } + void cset(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Condition Cond) { + constexpr uint32_t Op = 0b0001'1010'100 << 21; + ConditionalCompare(Op, 0, 0b01, s, rd, ARMEmitter::Reg::zr, ARMEmitter::Reg::zr, static_cast(FEXCore::ToUnderlying(Cond) ^ FEXCore::ToUnderlying(ARMEmitter::Condition::CC_NE))); + } + void csinc(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, ARMEmitter::Register rm, ARMEmitter::Condition Cond) { + constexpr uint32_t Op = 0b0001'1010'100 << 21; + ConditionalCompare(Op, 0, 0b01, s, rd, rn, rm, Cond); + } + void csinv(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, ARMEmitter::Register rm, ARMEmitter::Condition Cond) { + constexpr uint32_t Op = 0b0001'1010'100 << 21; + ConditionalCompare(Op, 1, 0b00, s, rd, rn, rm, Cond); + } + void csneg(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, ARMEmitter::Register rm, ARMEmitter::Condition Cond) { + constexpr uint32_t Op = 0b0001'1010'100 << 21; + ConditionalCompare(Op, 1, 0b01, s, rd, rn, rm, Cond); + } + void cneg(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, ARMEmitter::Condition Cond) { + csneg(s, rd, rn, rn, InvertCondition(Cond)); + } + void cinc(ARMEmitter::Size s, Register rd, Register rn, Condition cond) { + csinc(s, rd, rn, rn, InvertCondition(cond)); + } + void cinv(ARMEmitter::Size s, Register rd, Register rn, Condition cond) { + csinv(s, rd, rn, rn, InvertCondition(cond)); + } + void csetm(ARMEmitter::Size s, Register rd, Condition cond) { + csinv(s, rd, Reg::zr, Reg::zr, InvertCondition(cond)); + } + + // Data processing - 3 source + void madd(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, ARMEmitter::Register rm, ARMEmitter::Register ra) { + constexpr uint32_t Op = 0b001'1011'000U << 21; + DataProcessing_3Source(Op, 0, s, rd, rn, rm, ra); + } + void mul(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, ARMEmitter::Register rm) { + madd(s, rd, rn, rm, XReg::zr); + } + void msub(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, ARMEmitter::Register rm, ARMEmitter::Register ra) { + constexpr uint32_t Op = 0b001'1011'000U << 21; + DataProcessing_3Source(Op, 1, s, rd, rn, rm, ra); + } + void mneg(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, ARMEmitter::Register rm) { + msub(s, rd, rn, rm, XReg::zr); + } + void smaddl(ARMEmitter::XRegister rd, ARMEmitter::WRegister rn, ARMEmitter::WRegister rm, ARMEmitter::XRegister ra) { + constexpr uint32_t Op = 0b001'1011'001U << 21; + DataProcessing_3Source(Op, 0, ARMEmitter::Size::i64Bit, rd, rn, rm, ra); + } + void smull(ARMEmitter::XRegister rd, ARMEmitter::WRegister rn, ARMEmitter::WRegister rm) { + smaddl(rd, rn, rm, XReg::zr); + } + void smsubl(ARMEmitter::XRegister rd, ARMEmitter::WRegister rn, ARMEmitter::WRegister rm, ARMEmitter::XRegister ra) { + constexpr uint32_t Op = 0b001'1011'001U << 21; + DataProcessing_3Source(Op, 1, ARMEmitter::Size::i64Bit, rd, rn, rm, ra); + } + void smnegl(ARMEmitter::XRegister rd, ARMEmitter::WRegister rn, ARMEmitter::WRegister rm) { + smsubl(rd, rn, rm, XReg::zr); + } + void smulh(ARMEmitter::XRegister rd, ARMEmitter::XRegister rn, ARMEmitter::XRegister rm) { + constexpr uint32_t Op = 0b001'1011'010U << 21; + DataProcessing_3Source(Op, 0, ARMEmitter::Size::i64Bit, rd, rn, rm, ARMEmitter::Reg::zr); + } + void umaddl(ARMEmitter::XRegister rd, ARMEmitter::WRegister rn, ARMEmitter::WRegister rm, ARMEmitter::XRegister ra) { + constexpr uint32_t Op = 0b001'1011'101U << 21; + DataProcessing_3Source(Op, 0, ARMEmitter::Size::i64Bit, rd, rn, rm, ra); + } + void umull(ARMEmitter::XRegister rd, ARMEmitter::WRegister rn, ARMEmitter::WRegister rm) { + umaddl(rd, rn, rm, XReg::zr); + } + void umsubl(ARMEmitter::XRegister rd, ARMEmitter::WRegister rn, ARMEmitter::WRegister rm, ARMEmitter::XRegister ra) { + constexpr uint32_t Op = 0b001'1011'101U << 21; + DataProcessing_3Source(Op, 1, ARMEmitter::Size::i64Bit, rd, rn, rm, ra); + } + void umnegl(ARMEmitter::XRegister rd, ARMEmitter::WRegister rn, ARMEmitter::WRegister rm) { + umsubl(rd, rn, rm, XReg::zr); + } + void umulh(ARMEmitter::XRegister rd, ARMEmitter::XRegister rn, ARMEmitter::XRegister rm) { + constexpr uint32_t Op = 0b001'1011'110U << 21; + DataProcessing_3Source(Op, 0, ARMEmitter::Size::i64Bit, rd, rn, rm, ARMEmitter::Reg::zr); + } + +private: + static constexpr Condition InvertCondition(Condition cond) { + // These behave as always, so it makes no sense to allow inverting these. + LOGMAN_THROW_AA_FMT(cond != Condition::CC_AL && cond != Condition::CC_NV, + "Cannot invert CC_AL or CC_NV"); + return static_cast(FEXCore::ToUnderlying(cond) ^ 1); + } + + void and_(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, uint32_t n, uint32_t immr, uint32_t imms) { + constexpr uint32_t Op = 0b001'0010'00 << 22; + DataProcessing_Logical_Imm(Op, s, rd, rn, n, immr, imms); + } + void ands(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, uint32_t n, uint32_t immr, uint32_t imms) { + constexpr uint32_t Op = 0b111'0010'00 << 22; + DataProcessing_Logical_Imm(Op, s, rd, rn, n, immr, imms); + } + void orr(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, uint32_t n, uint32_t immr, uint32_t imms) { + constexpr uint32_t Op = 0b011'0010'00 << 22; + DataProcessing_Logical_Imm(Op, s, rd, rn, n, immr, imms); + } + void eor(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, uint32_t n, uint32_t immr, uint32_t imms) { + constexpr uint32_t Op = 0b101'0010'00 << 22; + DataProcessing_Logical_Imm(Op, s, rd, rn, n, immr, imms); + } + + void sbfm(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, uint32_t immr, uint32_t imms) { + constexpr uint32_t Op = 0b0001'0011'00 << 22; + DataProcessing_Logical_Imm(Op, s, rd, rn, s == ARMEmitter::Size::i64Bit, immr, imms); + } + void bfm(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, uint32_t immr, uint32_t imms) { + constexpr uint32_t Op = 0b0011'0011'00 << 22; + DataProcessing_Logical_Imm(Op, s, rd, rn, s == ARMEmitter::Size::i64Bit, immr, imms); + } + // 4.1.64 - Data processing - Immediate + void DataProcessing_PCRel_Imm(uint32_t Op, ARMEmitter::Register rd, uint32_t Imm) { + // Ensure the immediate is masked. + Imm &= 0b1'1111'1111'1111'1111'1111U; + + uint32_t Instr = Op; + + Instr |= (Imm & 0b11) << 29; + Instr |= (Imm >> 2) << 5; + Instr |= Encode_rd(rd); + + dc32(Instr); + } + + void DataProcessing_AddSub_Imm(uint32_t Op, ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, uint32_t Imm, bool LSL12) { + bool TooLarge = (Imm & ~0b1111'1111'1111U) != 0; + if (TooLarge && !LSL12 && ((Imm >> 12) & ~0b1111'1111'1111U) == 0) { + // We can convert an immediate + TooLarge = false; + LSL12 = true; + Imm >>= 12; + } + LOGMAN_THROW_AA_FMT(TooLarge == false, "Imm amount too large: 0x{:x}", Imm); + + const uint32_t SF = s == ARMEmitter::Size::i64Bit ? (1U << 31) : 0; + + uint32_t Instr = Op; + + Instr |= SF; + Instr |= LSL12 << 22; + Instr |= Imm << 10; + Instr |= Encode_rn(rn); + Instr |= Encode_rd(rd); + + dc32(Instr); + } + + // Min/max immediate + void MinMaxImmediate(uint32_t opc, ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, uint64_t Imm) { + const uint32_t SF = s == ARMEmitter::Size::i64Bit ? (1U << 31) : 0; + + uint32_t Instr = 0b1'0001'11U << 22; + + Instr |= SF; + Instr |= opc << 18; + Instr |= (Imm & 0xFF) << 10; + Instr |= Encode_rn(rn); + Instr |= Encode_rd(rd); + + dc32(Instr); + } + + // Move Wide + void DataProcessing_MoveWide(uint32_t Op, ARMEmitter::Size s, ARMEmitter::Register rd, uint32_t Imm, uint32_t Offset) { + const uint32_t SF = s == ARMEmitter::Size::i64Bit ? (1U << 31) : 0; + + uint32_t Instr = Op; + + Instr |= SF; + Instr |= Imm << 5; + Instr |= Offset << 21; + Instr |= Encode_rd(rd); + + dc32(Instr); + } + + // Logical immediate + void DataProcessing_Logical_Imm(uint32_t Op, ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, uint32_t n, uint32_t immr, uint32_t imms) { + const uint32_t SF = s == ARMEmitter::Size::i64Bit ? (1U << 31) : 0; + + uint32_t Instr = Op; + + Instr |= SF; + Instr |= n << 22; + Instr |= immr << 16; + Instr |= imms << 10; + Instr |= Encode_rn(rn); + Instr |= Encode_rd(rd); + + dc32(Instr); + } + + void xbfiz_helper(bool is_signed, ARMEmitter::Size s, Register rd, Register rn, uint32_t lsb, uint32_t width) { + [[maybe_unused]] const auto lsb_p_width = lsb + width; + const auto reg_size_bits = RegSizeInBits(s); + + LOGMAN_THROW_AA_FMT(lsb_p_width <= reg_size_bits, "lsb + width ({}) must be <= {}. lsb={}, width={}", + lsb_p_width, reg_size_bits, lsb, width); + LOGMAN_THROW_AA_FMT(width >= 1, "xbfiz width must be >= 1"); + + const auto immr = (reg_size_bits - lsb) & (reg_size_bits - 1); + const auto imms = width - 1; + + if (is_signed) { + sbfm(s, rd, rn, immr, imms); + } else { + ubfm(s, rd, rn, immr, imms); + } + } + + void DataProcessing_Extract(uint32_t Op, ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, ARMEmitter::Register rm, uint32_t Imm) { + const uint32_t SF = s == ARMEmitter::Size::i64Bit ? (1U << 31) : 0; + + // Current ARMv8 spec hardcodes SF == N for this class of instructions. + // Anythign else is undefined behaviour. + const uint32_t N = s == ARMEmitter::Size::i64Bit ? (1U << 22) : 0; + + uint32_t Instr = Op; + + Instr |= SF; + Instr |= N; + Instr |= Encode_rm(rm); + Instr |= Imm << 10; + Instr |= Encode_rn(rn); + Instr |= Encode_rd(rd); + + dc32(Instr); + } + + // Data-processing - 2 source + void DataProcessing_2Source(uint32_t Op, ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, ARMEmitter::Register rm) { + const uint32_t SF = s == ARMEmitter::Size::i64Bit ? (1U << 31) : 0; + + uint32_t Instr = Op; + + Instr |= SF; + Instr |= Encode_rm(rm); + Instr |= Encode_rn(rn); + Instr |= Encode_rd(rd); + + dc32(Instr); + } + + // Data processing - 1 source + template + void DataProcessing_1Source(uint32_t Op, ARMEmitter::Size s, T rd, T rn) { + const uint32_t SF = s == ARMEmitter::Size::i64Bit ? (1U << 31) : 0; + + uint32_t Instr = Op; + + Instr |= SF; + Instr |= Encode_rn(rn); + Instr |= Encode_rd(rd); + + dc32(Instr); + } + + // AddSub - shifted register + void DataProcessing_Shifted_Reg(uint32_t Op, ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, ARMEmitter::Register rm, ARMEmitter::ShiftType Shift, uint32_t amt) { + LOGMAN_THROW_AA_FMT((amt & ~0b11'1111U) == 0, "Shift amount too large"); + if (s == ARMEmitter::Size::i32Bit) { + LOGMAN_THROW_AA_FMT(amt < 32, "Shift amount for 32-bit must be below 32"); + } + + const uint32_t SF = s == ARMEmitter::Size::i64Bit ? (1U << 31) : 0; + + uint32_t Instr = Op; + + Instr |= SF; + Instr |= FEXCore::ToUnderlying(Shift) << 22; + Instr |= Encode_rm(rm); + Instr |= static_cast(amt) << 10; + Instr |= Encode_rn(rn); + Instr |= Encode_rd(rd); + + dc32(Instr); + } + + // AddSub - extended register + void DataProcessing_Extended_Reg(uint32_t Op, ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, ARMEmitter::Register rm, ARMEmitter::ExtendedType Option, uint32_t Shift) { + const uint32_t SF = s == ARMEmitter::Size::i64Bit ? (1U << 31) : 0; + + uint32_t Instr = Op; + + Instr |= SF; + Instr |= Encode_rm(rm); + Instr |= FEXCore::ToUnderlying(Option) << 13; + Instr |= static_cast(Shift) << 10; + Instr |= Encode_rn(rn); + Instr |= Encode_rd(rd); + + dc32(Instr); + } + // Conditional compare - register + template + void ConditionalCompare(uint32_t Op, uint32_t o1, uint32_t o2, uint32_t o3, ARMEmitter::Size s, ARMEmitter::Register rn, T rm, ARMEmitter::StatusFlags flags, ARMEmitter::Condition Cond) { + const uint32_t SF = s == ARMEmitter::Size::i64Bit ? (1U << 31) : 0; + + uint32_t Instr = Op; + + Instr |= SF; + Instr |= o1 << 30; + Instr |= Encode_rm(rm); + Instr |= FEXCore::ToUnderlying(Cond) << 12; + Instr |= o2 << 10; + Instr |= Encode_rn(rn); + Instr |= o3 << 4; + Instr |= FEXCore::ToUnderlying(flags); + + dc32(Instr); + } + + template + void ConditionalCompare(uint32_t Op, uint32_t o1, uint32_t o2, ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, T rm, ARMEmitter::Condition Cond) { + const uint32_t SF = s == ARMEmitter::Size::i64Bit ? (1U << 31) : 0; + + uint32_t Instr = Op; + + Instr |= SF; + Instr |= o1 << 30; + Instr |= Encode_rm(rm); + Instr |= FEXCore::ToUnderlying(Cond) << 12; + Instr |= o2 << 10; + Instr |= Encode_rn(rn); + Instr |= Encode_rd(rd); + + dc32(Instr); + } + + // Data-processing - 3 source + void DataProcessing_3Source(uint32_t Op, uint32_t Op0, ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, ARMEmitter::Register rm, ARMEmitter::Register ra) { + const uint32_t SF = s == ARMEmitter::Size::i64Bit ? (1U << 31) : 0; + + uint32_t Instr = Op; + + Instr |= SF; + Instr |= Encode_rm(rm); + Instr |= Op0 << 15; + Instr |= Encode_ra(ra); + Instr |= Encode_rn(rn); + Instr |= Encode_rd(rd); + + dc32(Instr); + } + + void EvaluateIntoFlags(uint32_t op, uint32_t size, WRegister rn) { + uint32_t Instr = op; + Instr |= size << 14; + Instr |= rn.Idx() << 5; + dc32(Instr); + } + + diff --git a/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/ASIMDOps.inl b/CodeEmitter/CodeEmitter/ASIMDOps.inl similarity index 53% rename from FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/ASIMDOps.inl rename to CodeEmitter/CodeEmitter/ASIMDOps.inl index 2f4c2bf47..5a4565e6f 100644 --- a/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/ASIMDOps.inl +++ b/CodeEmitter/CodeEmitter/ASIMDOps.inl @@ -16,80 +16,80 @@ public: // Data Processing -- Scalar Floating-Point and Advanced SIMD // Cryptographic AES - void aese(FEXCore::ARMEmitter::VRegister rd, FEXCore::ARMEmitter::VRegister rn) { + void aese(ARMEmitter::VRegister rd, ARMEmitter::VRegister rn) { constexpr uint32_t Op = 0b0100'1110'0010'1000'0000'10 << 10; CryptoAES(Op, 0b00100, rd, rn); } - void aesd(FEXCore::ARMEmitter::VRegister rd, FEXCore::ARMEmitter::VRegister rn) { + void aesd(ARMEmitter::VRegister rd, ARMEmitter::VRegister rn) { constexpr uint32_t Op = 0b0100'1110'0010'1000'0000'10 << 10; CryptoAES(Op, 0b00101, rd, rn); } - void aesmc(FEXCore::ARMEmitter::VRegister rd, FEXCore::ARMEmitter::VRegister rn) { + void aesmc(ARMEmitter::VRegister rd, ARMEmitter::VRegister rn) { constexpr uint32_t Op = 0b0100'1110'0010'1000'0000'10 << 10; CryptoAES(Op, 0b00110, rd, rn); } - void aesimc(FEXCore::ARMEmitter::VRegister rd, FEXCore::ARMEmitter::VRegister rn) { + void aesimc(ARMEmitter::VRegister rd, ARMEmitter::VRegister rn) { constexpr uint32_t Op = 0b0100'1110'0010'1000'0000'10 << 10; CryptoAES(Op, 0b00111, rd, rn); } // Cryptographic three-register SHA - void sha1c(FEXCore::ARMEmitter::VRegister rd, FEXCore::ARMEmitter::SRegister rn, FEXCore::ARMEmitter::VRegister rm) { + void sha1c(ARMEmitter::VRegister rd, ARMEmitter::SRegister rn, ARMEmitter::VRegister rm) { constexpr uint32_t Op = 0b0101'1110'0000'0000'0000'00 << 10; Crypto3RegSHA(Op, 0b000, rd, rn.V(), rm); } - void sha1p(FEXCore::ARMEmitter::VRegister rd, FEXCore::ARMEmitter::SRegister rn, FEXCore::ARMEmitter::VRegister rm) { + void sha1p(ARMEmitter::VRegister rd, ARMEmitter::SRegister rn, ARMEmitter::VRegister rm) { constexpr uint32_t Op = 0b0101'1110'0000'0000'0000'00 << 10; Crypto3RegSHA(Op, 0b001, rd, rn.V(), rm); } - void sha1m(FEXCore::ARMEmitter::VRegister rd, FEXCore::ARMEmitter::SRegister rn, FEXCore::ARMEmitter::VRegister rm) { + void sha1m(ARMEmitter::VRegister rd, ARMEmitter::SRegister rn, ARMEmitter::VRegister rm) { constexpr uint32_t Op = 0b0101'1110'0000'0000'0000'00 << 10; Crypto3RegSHA(Op, 0b010, rd, rn.V(), rm); } - void sha1su0(FEXCore::ARMEmitter::VRegister rd, FEXCore::ARMEmitter::VRegister rn, FEXCore::ARMEmitter::VRegister rm) { + void sha1su0(ARMEmitter::VRegister rd, ARMEmitter::VRegister rn, ARMEmitter::VRegister rm) { constexpr uint32_t Op = 0b0101'1110'0000'0000'0000'00 << 10; Crypto3RegSHA(Op, 0b011, rd, rn, rm); } - void sha256h(FEXCore::ARMEmitter::VRegister rd, FEXCore::ARMEmitter::VRegister rn, FEXCore::ARMEmitter::VRegister rm) { + void sha256h(ARMEmitter::VRegister rd, ARMEmitter::VRegister rn, ARMEmitter::VRegister rm) { constexpr uint32_t Op = 0b0101'1110'0000'0000'0000'00 << 10; Crypto3RegSHA(Op, 0b100, rd, rn, rm); } - void sha256h2(FEXCore::ARMEmitter::VRegister rd, FEXCore::ARMEmitter::VRegister rn, FEXCore::ARMEmitter::VRegister rm) { + void sha256h2(ARMEmitter::VRegister rd, ARMEmitter::VRegister rn, ARMEmitter::VRegister rm) { constexpr uint32_t Op = 0b0101'1110'0000'0000'0000'00 << 10; Crypto3RegSHA(Op, 0b100, rd, rn, rm); } - void sha256su1(FEXCore::ARMEmitter::VRegister rd, FEXCore::ARMEmitter::VRegister rn, FEXCore::ARMEmitter::VRegister rm) { + void sha256su1(ARMEmitter::VRegister rd, ARMEmitter::VRegister rn, ARMEmitter::VRegister rm) { constexpr uint32_t Op = 0b0101'1110'0000'0000'0000'00 << 10; Crypto3RegSHA(Op, 0b110, rd, rn, rm); } // Cryptographic two-register SHA - void sha1h(FEXCore::ARMEmitter::SRegister rd, FEXCore::ARMEmitter::SRegister rn) { + void sha1h(ARMEmitter::SRegister rd, ARMEmitter::SRegister rn) { constexpr uint32_t Op = 0b0101'1110'0010'1000'0000'10 << 10; Crypto2RegSHA(Op, 0b00000, rd.V(), rn.V()); } - void sha1su1(FEXCore::ARMEmitter::VRegister rd, FEXCore::ARMEmitter::VRegister rn) { + void sha1su1(ARMEmitter::VRegister rd, ARMEmitter::VRegister rn) { constexpr uint32_t Op = 0b0101'1110'0010'1000'0000'10 << 10; Crypto2RegSHA(Op, 0b00001, rd, rn); } - void sha256su0(FEXCore::ARMEmitter::VRegister rd, FEXCore::ARMEmitter::VRegister rn) { + void sha256su0(ARMEmitter::VRegister rd, ARMEmitter::VRegister rn) { constexpr uint32_t Op = 0b0101'1110'0010'1000'0000'10 << 10; Crypto2RegSHA(Op, 0b00010, rd, rn); } // Advanced SIMD table lookup - void tbl(FEXCore::ARMEmitter::QRegister rd, FEXCore::ARMEmitter::QRegister rn, FEXCore::ARMEmitter::QRegister rm) { + void tbl(ARMEmitter::QRegister rd, ARMEmitter::QRegister rn, ARMEmitter::QRegister rm) { constexpr uint32_t Op = 0b0000'1110'000 << 21; ASIMDTable(Op, 1, 0b00, 0b00, 0b0, rd.V(), rn.V(), rm.V()); } - void tbl(FEXCore::ARMEmitter::DRegister rd, FEXCore::ARMEmitter::QRegister rn, FEXCore::ARMEmitter::DRegister rm) { + void tbl(ARMEmitter::DRegister rd, ARMEmitter::QRegister rn, ARMEmitter::DRegister rm) { constexpr uint32_t Op = 0b0000'1110'000 << 21; ASIMDTable(Op, 0, 0b00, 0b00, 0b0, rd.V(), rn.V(), rm.V()); } - void tbx(FEXCore::ARMEmitter::QRegister rd, FEXCore::ARMEmitter::QRegister rn, FEXCore::ARMEmitter::QRegister rm) { + void tbx(ARMEmitter::QRegister rd, ARMEmitter::QRegister rn, ARMEmitter::QRegister rm) { constexpr uint32_t Op = 0b0000'1110'000 << 21; ASIMDTable(Op, 1, 0b00, 0b00, 0b1, rd.V(), rn.V(), rm.V()); } - void tbx(FEXCore::ARMEmitter::DRegister rd, FEXCore::ARMEmitter::QRegister rn, FEXCore::ARMEmitter::DRegister rm) { + void tbx(ARMEmitter::DRegister rd, ARMEmitter::QRegister rn, ARMEmitter::DRegister rm) { constexpr uint32_t Op = 0b0000'1110'000 << 21; ASIMDTable(Op, 0, 0b00, 0b00, 0b1, rd.V(), rn.V(), rm.V()); } @@ -158,136 +158,136 @@ public: } // Advanced SIMD permute - template - void uzp1(FEXCore::ARMEmitter::QRegister rd, FEXCore::ARMEmitter::QRegister rn, FEXCore::ARMEmitter::QRegister rm) { + template + void uzp1(ARMEmitter::QRegister rd, ARMEmitter::QRegister rn, ARMEmitter::QRegister rm) { constexpr uint32_t Op = 0b0000'1110'0000'0000'0000'10 << 10; ASIMDPermute(Op, 1, size, 0b001, rd.V(), rn.V(), rm.V()); } - template - requires (size != FEXCore::ARMEmitter::SubRegSize::i64Bit) - void uzp1(FEXCore::ARMEmitter::DRegister rd, FEXCore::ARMEmitter::DRegister rn, FEXCore::ARMEmitter::DRegister rm) { + template + requires (size != ARMEmitter::SubRegSize::i64Bit) + void uzp1(ARMEmitter::DRegister rd, ARMEmitter::DRegister rn, ARMEmitter::DRegister rm) { constexpr uint32_t Op = 0b0000'1110'0000'0000'0000'10 << 10; ASIMDPermute(Op, 0, size, 0b001, rd.V(), rn.V(), rm.V()); } - template - void trn1(FEXCore::ARMEmitter::QRegister rd, FEXCore::ARMEmitter::QRegister rn, FEXCore::ARMEmitter::QRegister rm) { + template + void trn1(ARMEmitter::QRegister rd, ARMEmitter::QRegister rn, ARMEmitter::QRegister rm) { constexpr uint32_t Op = 0b0000'1110'0000'0000'0000'10 << 10; ASIMDPermute(Op, 1, size, 0b010, rd.V(), rn.V(), rm.V()); } - template - requires (size != FEXCore::ARMEmitter::SubRegSize::i64Bit) - void trn1(FEXCore::ARMEmitter::DRegister rd, FEXCore::ARMEmitter::DRegister rn, FEXCore::ARMEmitter::DRegister rm) { + template + requires (size != ARMEmitter::SubRegSize::i64Bit) + void trn1(ARMEmitter::DRegister rd, ARMEmitter::DRegister rn, ARMEmitter::DRegister rm) { constexpr uint32_t Op = 0b0000'1110'0000'0000'0000'10 << 10; ASIMDPermute(Op, 0, size, 0b010, rd.V(), rn.V(), rm.V()); } - template - void zip1(FEXCore::ARMEmitter::QRegister rd, FEXCore::ARMEmitter::QRegister rn, FEXCore::ARMEmitter::QRegister rm) { + template + void zip1(ARMEmitter::QRegister rd, ARMEmitter::QRegister rn, ARMEmitter::QRegister rm) { constexpr uint32_t Op = 0b0000'1110'0000'0000'0000'10 << 10; ASIMDPermute(Op, 1, size, 0b011, rd.V(), rn.V(), rm.V()); } - template - requires (size != FEXCore::ARMEmitter::SubRegSize::i64Bit) - void zip1(FEXCore::ARMEmitter::DRegister rd, FEXCore::ARMEmitter::DRegister rn, FEXCore::ARMEmitter::DRegister rm) { + template + requires (size != ARMEmitter::SubRegSize::i64Bit) + void zip1(ARMEmitter::DRegister rd, ARMEmitter::DRegister rn, ARMEmitter::DRegister rm) { constexpr uint32_t Op = 0b0000'1110'0000'0000'0000'10 << 10; ASIMDPermute(Op, 0, size, 0b011, rd.V(), rn.V(), rm.V()); } - template - void uzp2(FEXCore::ARMEmitter::QRegister rd, FEXCore::ARMEmitter::QRegister rn, FEXCore::ARMEmitter::QRegister rm) { + template + void uzp2(ARMEmitter::QRegister rd, ARMEmitter::QRegister rn, ARMEmitter::QRegister rm) { constexpr uint32_t Op = 0b0000'1110'0000'0000'0000'10 << 10; ASIMDPermute(Op, 1, size, 0b101, rd.V(), rn.V(), rm.V()); } - template - requires (size != FEXCore::ARMEmitter::SubRegSize::i64Bit) - void uzp2(FEXCore::ARMEmitter::DRegister rd, FEXCore::ARMEmitter::DRegister rn, FEXCore::ARMEmitter::DRegister rm) { + template + requires (size != ARMEmitter::SubRegSize::i64Bit) + void uzp2(ARMEmitter::DRegister rd, ARMEmitter::DRegister rn, ARMEmitter::DRegister rm) { constexpr uint32_t Op = 0b0000'1110'0000'0000'0000'10 << 10; ASIMDPermute(Op, 0, size, 0b101, rd.V(), rn.V(), rm.V()); } - template - void trn2(FEXCore::ARMEmitter::QRegister rd, FEXCore::ARMEmitter::QRegister rn, FEXCore::ARMEmitter::QRegister rm) { + template + void trn2(ARMEmitter::QRegister rd, ARMEmitter::QRegister rn, ARMEmitter::QRegister rm) { constexpr uint32_t Op = 0b0000'1110'0000'0000'0000'10 << 10; ASIMDPermute(Op, 1, size, 0b110, rd.V(), rn.V(), rm.V()); } - template - requires (size != FEXCore::ARMEmitter::SubRegSize::i64Bit) - void trn2(FEXCore::ARMEmitter::DRegister rd, FEXCore::ARMEmitter::DRegister rn, FEXCore::ARMEmitter::DRegister rm) { + template + requires (size != ARMEmitter::SubRegSize::i64Bit) + void trn2(ARMEmitter::DRegister rd, ARMEmitter::DRegister rn, ARMEmitter::DRegister rm) { constexpr uint32_t Op = 0b0000'1110'0000'0000'0000'10 << 10; ASIMDPermute(Op, 0, size, 0b110, rd.V(), rn.V(), rm.V()); } - template - void zip2(FEXCore::ARMEmitter::QRegister rd, FEXCore::ARMEmitter::QRegister rn, FEXCore::ARMEmitter::QRegister rm) { + template + void zip2(ARMEmitter::QRegister rd, ARMEmitter::QRegister rn, ARMEmitter::QRegister rm) { constexpr uint32_t Op = 0b0000'1110'0000'0000'0000'10 << 10; ASIMDPermute(Op, 1, size, 0b111, rd.V(), rn.V(), rm.V()); } - template - requires (size != FEXCore::ARMEmitter::SubRegSize::i64Bit) - void zip2(FEXCore::ARMEmitter::DRegister rd, FEXCore::ARMEmitter::DRegister rn, FEXCore::ARMEmitter::DRegister rm) { + template + requires (size != ARMEmitter::SubRegSize::i64Bit) + void zip2(ARMEmitter::DRegister rd, ARMEmitter::DRegister rn, ARMEmitter::DRegister rm) { constexpr uint32_t Op = 0b0000'1110'0000'0000'0000'10 << 10; ASIMDPermute(Op, 0, size, 0b111, rd.V(), rn.V(), rm.V()); } - void uzp1(FEXCore::ARMEmitter::SubRegSize size, FEXCore::ARMEmitter::QRegister rd, FEXCore::ARMEmitter::QRegister rn, FEXCore::ARMEmitter::QRegister rm) { + void uzp1(ARMEmitter::SubRegSize size, ARMEmitter::QRegister rd, ARMEmitter::QRegister rn, ARMEmitter::QRegister rm) { constexpr uint32_t Op = 0b0000'1110'0000'0000'0000'10 << 10; ASIMDPermute(Op, 1, size, 0b001, rd.V(), rn.V(), rm.V()); } - void uzp1(FEXCore::ARMEmitter::SubRegSize size, FEXCore::ARMEmitter::DRegister rd, FEXCore::ARMEmitter::DRegister rn, FEXCore::ARMEmitter::DRegister rm) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid 64-bit size on 64-bit permute"); + void uzp1(ARMEmitter::SubRegSize size, ARMEmitter::DRegister rd, ARMEmitter::DRegister rn, ARMEmitter::DRegister rm) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid 64-bit size on 64-bit permute"); constexpr uint32_t Op = 0b0000'1110'0000'0000'0000'10 << 10; ASIMDPermute(Op, 0, size, 0b001, rd.V(), rn.V(), rm.V()); } - void trn1(FEXCore::ARMEmitter::SubRegSize size, FEXCore::ARMEmitter::QRegister rd, FEXCore::ARMEmitter::QRegister rn, FEXCore::ARMEmitter::QRegister rm) { + void trn1(ARMEmitter::SubRegSize size, ARMEmitter::QRegister rd, ARMEmitter::QRegister rn, ARMEmitter::QRegister rm) { constexpr uint32_t Op = 0b0000'1110'0000'0000'0000'10 << 10; ASIMDPermute(Op, 1, size, 0b010, rd.V(), rn.V(), rm.V()); } - void trn1(FEXCore::ARMEmitter::SubRegSize size, FEXCore::ARMEmitter::DRegister rd, FEXCore::ARMEmitter::DRegister rn, FEXCore::ARMEmitter::DRegister rm) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid 64-bit size on 64-bit permute"); + void trn1(ARMEmitter::SubRegSize size, ARMEmitter::DRegister rd, ARMEmitter::DRegister rn, ARMEmitter::DRegister rm) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid 64-bit size on 64-bit permute"); constexpr uint32_t Op = 0b0000'1110'0000'0000'0000'10 << 10; ASIMDPermute(Op, 0, size, 0b010, rd.V(), rn.V(), rm.V()); } - void zip1(FEXCore::ARMEmitter::SubRegSize size, FEXCore::ARMEmitter::QRegister rd, FEXCore::ARMEmitter::QRegister rn, FEXCore::ARMEmitter::QRegister rm) { + void zip1(ARMEmitter::SubRegSize size, ARMEmitter::QRegister rd, ARMEmitter::QRegister rn, ARMEmitter::QRegister rm) { constexpr uint32_t Op = 0b0000'1110'0000'0000'0000'10 << 10; ASIMDPermute(Op, 1, size, 0b011, rd.V(), rn.V(), rm.V()); } - void zip1(FEXCore::ARMEmitter::SubRegSize size, FEXCore::ARMEmitter::DRegister rd, FEXCore::ARMEmitter::DRegister rn, FEXCore::ARMEmitter::DRegister rm) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid 64-bit size on 64-bit permute"); + void zip1(ARMEmitter::SubRegSize size, ARMEmitter::DRegister rd, ARMEmitter::DRegister rn, ARMEmitter::DRegister rm) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid 64-bit size on 64-bit permute"); constexpr uint32_t Op = 0b0000'1110'0000'0000'0000'10 << 10; ASIMDPermute(Op, 0, size, 0b011, rd.V(), rn.V(), rm.V()); } - void uzp2(FEXCore::ARMEmitter::SubRegSize size, FEXCore::ARMEmitter::QRegister rd, FEXCore::ARMEmitter::QRegister rn, FEXCore::ARMEmitter::QRegister rm) { + void uzp2(ARMEmitter::SubRegSize size, ARMEmitter::QRegister rd, ARMEmitter::QRegister rn, ARMEmitter::QRegister rm) { constexpr uint32_t Op = 0b0000'1110'0000'0000'0000'10 << 10; ASIMDPermute(Op, 1, size, 0b101, rd.V(), rn.V(), rm.V()); } - void uzp2(FEXCore::ARMEmitter::SubRegSize size, FEXCore::ARMEmitter::DRegister rd, FEXCore::ARMEmitter::DRegister rn, FEXCore::ARMEmitter::DRegister rm) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid 64-bit size on 64-bit permute"); + void uzp2(ARMEmitter::SubRegSize size, ARMEmitter::DRegister rd, ARMEmitter::DRegister rn, ARMEmitter::DRegister rm) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid 64-bit size on 64-bit permute"); constexpr uint32_t Op = 0b0000'1110'0000'0000'0000'10 << 10; ASIMDPermute(Op, 0, size, 0b101, rd.V(), rn.V(), rm.V()); } - void trn2(FEXCore::ARMEmitter::SubRegSize size, FEXCore::ARMEmitter::QRegister rd, FEXCore::ARMEmitter::QRegister rn, FEXCore::ARMEmitter::QRegister rm) { + void trn2(ARMEmitter::SubRegSize size, ARMEmitter::QRegister rd, ARMEmitter::QRegister rn, ARMEmitter::QRegister rm) { constexpr uint32_t Op = 0b0000'1110'0000'0000'0000'10 << 10; ASIMDPermute(Op, 1, size, 0b110, rd.V(), rn.V(), rm.V()); } - void trn2(FEXCore::ARMEmitter::SubRegSize size, FEXCore::ARMEmitter::DRegister rd, FEXCore::ARMEmitter::DRegister rn, FEXCore::ARMEmitter::DRegister rm) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid 64-bit size on 64-bit permute"); + void trn2(ARMEmitter::SubRegSize size, ARMEmitter::DRegister rd, ARMEmitter::DRegister rn, ARMEmitter::DRegister rm) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid 64-bit size on 64-bit permute"); constexpr uint32_t Op = 0b0000'1110'0000'0000'0000'10 << 10; ASIMDPermute(Op, 0, size, 0b110, rd.V(), rn.V(), rm.V()); } - void zip2(FEXCore::ARMEmitter::SubRegSize size, FEXCore::ARMEmitter::QRegister rd, FEXCore::ARMEmitter::QRegister rn, FEXCore::ARMEmitter::QRegister rm) { + void zip2(ARMEmitter::SubRegSize size, ARMEmitter::QRegister rd, ARMEmitter::QRegister rn, ARMEmitter::QRegister rm) { constexpr uint32_t Op = 0b0000'1110'0000'0000'0000'10 << 10; ASIMDPermute(Op, 1, size, 0b111, rd.V(), rn.V(), rm.V()); } - void zip2(FEXCore::ARMEmitter::SubRegSize size, FEXCore::ARMEmitter::DRegister rd, FEXCore::ARMEmitter::DRegister rn, FEXCore::ARMEmitter::DRegister rm) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid 64-bit size on 64-bit permute"); + void zip2(ARMEmitter::SubRegSize size, ARMEmitter::DRegister rd, ARMEmitter::DRegister rn, ARMEmitter::DRegister rm) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid 64-bit size on 64-bit permute"); constexpr uint32_t Op = 0b0000'1110'0000'0000'0000'10 << 10; ASIMDPermute(Op, 0, size, 0b111, rd.V(), rn.V(), rm.V()); } // Advanced SIMD extract - void ext(FEXCore::ARMEmitter::QRegister rd, FEXCore::ARMEmitter::QRegister rn, FEXCore::ARMEmitter::QRegister rm, uint32_t Index) { + void ext(ARMEmitter::QRegister rd, ARMEmitter::QRegister rn, ARMEmitter::QRegister rm, uint32_t Index) { LOGMAN_THROW_AA_FMT(Index < 16, "Index can't be more than 15"); constexpr uint32_t Op = 0b0010'1110'000 << 21; ASIMDExtract(Op, 1, 0b00, Index, rd.V(), rn.V(), rm.V()); } - void ext(FEXCore::ARMEmitter::DRegister rd, FEXCore::ARMEmitter::DRegister rn, FEXCore::ARMEmitter::DRegister rm, uint32_t Index) { + void ext(ARMEmitter::DRegister rd, ARMEmitter::DRegister rn, ARMEmitter::DRegister rm, uint32_t Index) { LOGMAN_THROW_AA_FMT(Index < 8, "Index can't be more than 7"); constexpr uint32_t Op = 0b0010'1110'000 << 21; ASIMDExtract(Op, 0, 0b00, Index, rd.V(), rn.V(), rm.V()); @@ -318,9 +318,9 @@ public: // Advanced SIMD three same (FP16) template - requires(std::is_same_v || std::is_same_v) + requires(std::is_same_v || std::is_same_v) void ASIMDThreeSameFP16(uint32_t U, uint32_t a, uint32_t opcode, T rm, T rn, T rd) { - constexpr uint32_t Q = std::is_same_v ? 1U << 30 : 0; + constexpr uint32_t Q = std::is_same_v ? 1U << 30 : 0; constexpr uint32_t Op = 0b0000'1110'0100'0000'0000'01 << 10; uint32_t Instr = Op; @@ -336,9 +336,9 @@ public: // Advanced SIMD two-register miscellaneous (FP16) template - requires(std::is_same_v || std::is_same_v) + requires(std::is_same_v || std::is_same_v) void ASIMDTwoRegMiscFP16(uint32_t U, uint32_t a, uint32_t opcode, T rn, T rd) { - constexpr uint32_t Q = std::is_same_v ? 1U << 30 : 0; + constexpr uint32_t Q = std::is_same_v ? 1U << 30 : 0; constexpr uint32_t Op = 0b0000'1110'0111'1000'0000'10 << 10; uint32_t Instr = Op; @@ -353,9 +353,9 @@ public: // Advanced SIMD three-register extension template - requires(std::is_same_v || std::is_same_v) - void ASIMDThreeRegisterExt(uint32_t U, uint32_t opcode, FEXCore::ARMEmitter::SubRegSize size, T rm, T rn, T rd) { - constexpr uint32_t Q = std::is_same_v ? 1U << 30 : 0; + requires(std::is_same_v || std::is_same_v) + void ASIMDThreeRegisterExt(uint32_t U, uint32_t opcode, ARMEmitter::SubRegSize size, T rm, T rn, T rd) { + constexpr uint32_t Q = std::is_same_v ? 1U << 30 : 0; constexpr uint32_t Op = 0b0000'1110'0000'0000'1000'01 << 10; uint32_t Instr = Op; @@ -497,433 +497,433 @@ public: } // Advanced SIMD three same (FP16) - template - requires(size == FEXCore::ARMEmitter::SubRegSize::i16Bit && - (std::is_same_v || std::is_same_v)) + template + requires(size == ARMEmitter::SubRegSize::i16Bit && + (std::is_same_v || std::is_same_v)) void fmaxnm(T rd, T rn, T rm) { ASIMDThreeSameFP16(0, 0, 0b000, rm, rn, rd); } - template - requires(size == FEXCore::ARMEmitter::SubRegSize::i16Bit && - (std::is_same_v || std::is_same_v)) + template + requires(size == ARMEmitter::SubRegSize::i16Bit && + (std::is_same_v || std::is_same_v)) void fmla(T rd, T rn, T rm) { ASIMDThreeSameFP16(0, 0, 0b001, rm, rn, rd); } - template - requires(size == FEXCore::ARMEmitter::SubRegSize::i16Bit && - (std::is_same_v || std::is_same_v)) + template + requires(size == ARMEmitter::SubRegSize::i16Bit && + (std::is_same_v || std::is_same_v)) void fadd(T rd, T rn, T rm) { ASIMDThreeSameFP16(0, 0, 0b010, rm, rn, rd); } - template - requires(size == FEXCore::ARMEmitter::SubRegSize::i16Bit && - (std::is_same_v || std::is_same_v)) + template + requires(size == ARMEmitter::SubRegSize::i16Bit && + (std::is_same_v || std::is_same_v)) void fmulx(T rd, T rn, T rm) { ASIMDThreeSameFP16(0, 0, 0b011, rm, rn, rd); } - template - requires(size == FEXCore::ARMEmitter::SubRegSize::i16Bit && - (std::is_same_v || std::is_same_v)) + template + requires(size == ARMEmitter::SubRegSize::i16Bit && + (std::is_same_v || std::is_same_v)) void fcmeq(T rd, T rn, T rm) { ASIMDThreeSameFP16(0, 0, 0b100, rm, rn, rd); } - template - requires(size == FEXCore::ARMEmitter::SubRegSize::i16Bit && - (std::is_same_v || std::is_same_v)) + template + requires(size == ARMEmitter::SubRegSize::i16Bit && + (std::is_same_v || std::is_same_v)) void fmax(T rd, T rn, T rm) { ASIMDThreeSameFP16(0, 0, 0b110, rm, rn, rd); } - template - requires(size == FEXCore::ARMEmitter::SubRegSize::i16Bit && - (std::is_same_v || std::is_same_v)) + template + requires(size == ARMEmitter::SubRegSize::i16Bit && + (std::is_same_v || std::is_same_v)) void frecps(T rd, T rn, T rm) { ASIMDThreeSameFP16(0, 0, 0b111, rm, rn, rd); } - template - requires(size == FEXCore::ARMEmitter::SubRegSize::i16Bit && - (std::is_same_v || std::is_same_v)) + template + requires(size == ARMEmitter::SubRegSize::i16Bit && + (std::is_same_v || std::is_same_v)) void fminnm(T rd, T rn, T rm) { ASIMDThreeSameFP16(0, 1, 0b000, rm, rn, rd); } - template - requires(size == FEXCore::ARMEmitter::SubRegSize::i16Bit && - (std::is_same_v || std::is_same_v)) + template + requires(size == ARMEmitter::SubRegSize::i16Bit && + (std::is_same_v || std::is_same_v)) void fmls(T rd, T rn, T rm) { ASIMDThreeSameFP16(0, 1, 0b001, rm, rn, rd); } - template - requires(size == FEXCore::ARMEmitter::SubRegSize::i16Bit && - (std::is_same_v || std::is_same_v)) + template + requires(size == ARMEmitter::SubRegSize::i16Bit && + (std::is_same_v || std::is_same_v)) void fsub(T rd, T rn, T rm) { ASIMDThreeSameFP16(0, 1, 0b010, rm, rn, rd); } - template - requires(size == FEXCore::ARMEmitter::SubRegSize::i16Bit && - (std::is_same_v || std::is_same_v)) + template + requires(size == ARMEmitter::SubRegSize::i16Bit && + (std::is_same_v || std::is_same_v)) void fmin(T rd, T rn, T rm) { ASIMDThreeSameFP16(0, 1, 0b110, rm, rn, rd); } - template - requires(size == FEXCore::ARMEmitter::SubRegSize::i16Bit && - (std::is_same_v || std::is_same_v)) + template + requires(size == ARMEmitter::SubRegSize::i16Bit && + (std::is_same_v || std::is_same_v)) void frsqrts(T rd, T rn, T rm) { ASIMDThreeSameFP16(0, 1, 0b111, rm, rn, rd); } - template - requires(size == FEXCore::ARMEmitter::SubRegSize::i16Bit && - (std::is_same_v || std::is_same_v)) + template + requires(size == ARMEmitter::SubRegSize::i16Bit && + (std::is_same_v || std::is_same_v)) void fmaxnmp(T rd, T rn, T rm) { ASIMDThreeSameFP16(1, 0, 0b000, rm, rn, rd); } - template - requires(size == FEXCore::ARMEmitter::SubRegSize::i16Bit && - (std::is_same_v || std::is_same_v)) + template + requires(size == ARMEmitter::SubRegSize::i16Bit && + (std::is_same_v || std::is_same_v)) void faddp(T rd, T rn, T rm) { ASIMDThreeSameFP16(1, 0, 0b010, rm, rn, rd); } - template - requires(size == FEXCore::ARMEmitter::SubRegSize::i16Bit && - (std::is_same_v || std::is_same_v)) + template + requires(size == ARMEmitter::SubRegSize::i16Bit && + (std::is_same_v || std::is_same_v)) void fmul(T rd, T rn, T rm) { ASIMDThreeSameFP16(1, 0, 0b011, rm, rn, rd); } - template - requires(size == FEXCore::ARMEmitter::SubRegSize::i16Bit && - (std::is_same_v || std::is_same_v)) + template + requires(size == ARMEmitter::SubRegSize::i16Bit && + (std::is_same_v || std::is_same_v)) void fcmge(T rd, T rn, T rm) { ASIMDThreeSameFP16(1, 0, 0b100, rm, rn, rd); } - template - requires(size == FEXCore::ARMEmitter::SubRegSize::i16Bit && - (std::is_same_v || std::is_same_v)) + template + requires(size == ARMEmitter::SubRegSize::i16Bit && + (std::is_same_v || std::is_same_v)) void facge(T rd, T rn, T rm) { ASIMDThreeSameFP16(1, 0, 0b101, rm, rn, rd); } - template - requires(size == FEXCore::ARMEmitter::SubRegSize::i16Bit && - (std::is_same_v || std::is_same_v)) + template + requires(size == ARMEmitter::SubRegSize::i16Bit && + (std::is_same_v || std::is_same_v)) void fmaxp(T rd, T rn, T rm) { ASIMDThreeSameFP16(1, 0, 0b110, rm, rn, rd); } - template - requires(size == FEXCore::ARMEmitter::SubRegSize::i16Bit && - (std::is_same_v || std::is_same_v)) + template + requires(size == ARMEmitter::SubRegSize::i16Bit && + (std::is_same_v || std::is_same_v)) void fdiv(T rd, T rn, T rm) { ASIMDThreeSameFP16(1, 0, 0b111, rm, rn, rd); } - template - requires(size == FEXCore::ARMEmitter::SubRegSize::i16Bit && - (std::is_same_v || std::is_same_v)) + template + requires(size == ARMEmitter::SubRegSize::i16Bit && + (std::is_same_v || std::is_same_v)) void fminnmp(T rd, T rn, T rm) { ASIMDThreeSameFP16(1, 1, 0b000, rm, rn, rd); } - template - requires(size == FEXCore::ARMEmitter::SubRegSize::i16Bit && - (std::is_same_v || std::is_same_v)) + template + requires(size == ARMEmitter::SubRegSize::i16Bit && + (std::is_same_v || std::is_same_v)) void fabd(T rd, T rn, T rm) { ASIMDThreeSameFP16(1, 1, 0b010, rm, rn, rd); } - template - requires(size == FEXCore::ARMEmitter::SubRegSize::i16Bit && - (std::is_same_v || std::is_same_v)) + template + requires(size == ARMEmitter::SubRegSize::i16Bit && + (std::is_same_v || std::is_same_v)) void fcmgt(T rd, T rn, T rm) { ASIMDThreeSameFP16(1, 1, 0b100, rm, rn, rd); } - template - requires(size == FEXCore::ARMEmitter::SubRegSize::i16Bit && - (std::is_same_v || std::is_same_v)) + template + requires(size == ARMEmitter::SubRegSize::i16Bit && + (std::is_same_v || std::is_same_v)) void facgt(T rd, T rn, T rm) { ASIMDThreeSameFP16(1, 1, 0b101, rm, rn, rd); } - template - requires(size == FEXCore::ARMEmitter::SubRegSize::i16Bit && - (std::is_same_v || std::is_same_v)) + template + requires(size == ARMEmitter::SubRegSize::i16Bit && + (std::is_same_v || std::is_same_v)) void fminp(T rd, T rn, T rm) { ASIMDThreeSameFP16(1, 1, 0b110, rm, rn, rd); } // Advanced SIMD two-register miscellaneous (FP16) - template - requires(size == FEXCore::ARMEmitter::SubRegSize::i16Bit && - (std::is_same_v || std::is_same_v)) + template + requires(size == ARMEmitter::SubRegSize::i16Bit && + (std::is_same_v || std::is_same_v)) void frintn(T rd, T rn) { ASIMDTwoRegMiscFP16(0, 0, 0b11000, rn, rd); } - template - requires(size == FEXCore::ARMEmitter::SubRegSize::i16Bit && - (std::is_same_v || std::is_same_v)) + template + requires(size == ARMEmitter::SubRegSize::i16Bit && + (std::is_same_v || std::is_same_v)) void frintm(T rd, T rn) { ASIMDTwoRegMiscFP16(0, 0, 0b11001, rn, rd); } - template - requires(size == FEXCore::ARMEmitter::SubRegSize::i16Bit && - (std::is_same_v || std::is_same_v)) + template + requires(size == ARMEmitter::SubRegSize::i16Bit && + (std::is_same_v || std::is_same_v)) void fcvtns(T rd, T rn) { ASIMDTwoRegMiscFP16(0, 0, 0b11010, rn, rd); } - template - requires(size == FEXCore::ARMEmitter::SubRegSize::i16Bit && - (std::is_same_v || std::is_same_v)) + template + requires(size == ARMEmitter::SubRegSize::i16Bit && + (std::is_same_v || std::is_same_v)) void fcvtms(T rd, T rn) { ASIMDTwoRegMiscFP16(0, 0, 0b11011, rn, rd); } - template - requires(size == FEXCore::ARMEmitter::SubRegSize::i16Bit && - (std::is_same_v || std::is_same_v)) + template + requires(size == ARMEmitter::SubRegSize::i16Bit && + (std::is_same_v || std::is_same_v)) void fcvtas(T rd, T rn) { ASIMDTwoRegMiscFP16(0, 0, 0b11100, rn, rd); } - template - requires(size == FEXCore::ARMEmitter::SubRegSize::i16Bit && - (std::is_same_v || std::is_same_v)) + template + requires(size == ARMEmitter::SubRegSize::i16Bit && + (std::is_same_v || std::is_same_v)) void scvtf(T rd, T rn) { ASIMDTwoRegMiscFP16(0, 0, 0b11101, rn, rd); } - template - requires(size == FEXCore::ARMEmitter::SubRegSize::i16Bit && - (std::is_same_v || std::is_same_v)) + template + requires(size == ARMEmitter::SubRegSize::i16Bit && + (std::is_same_v || std::is_same_v)) void fcmgt(T rd, T rn) { ASIMDTwoRegMiscFP16(0, 1, 0b01100, rn, rd); } - template - requires(size == FEXCore::ARMEmitter::SubRegSize::i16Bit && - (std::is_same_v || std::is_same_v)) + template + requires(size == ARMEmitter::SubRegSize::i16Bit && + (std::is_same_v || std::is_same_v)) void fcmeq(T rd, T rn) { ASIMDTwoRegMiscFP16(0, 1, 0b01101, rn, rd); } - template - requires(size == FEXCore::ARMEmitter::SubRegSize::i16Bit && - (std::is_same_v || std::is_same_v)) + template + requires(size == ARMEmitter::SubRegSize::i16Bit && + (std::is_same_v || std::is_same_v)) void fcmlt(T rd, T rn) { ASIMDTwoRegMiscFP16(0, 1, 0b01110, rn, rd); } - template - requires(size == FEXCore::ARMEmitter::SubRegSize::i16Bit && - (std::is_same_v || std::is_same_v)) + template + requires(size == ARMEmitter::SubRegSize::i16Bit && + (std::is_same_v || std::is_same_v)) void fabs(T rd, T rn) { ASIMDTwoRegMiscFP16(0, 1, 0b01111, rn, rd); } - template - requires(size == FEXCore::ARMEmitter::SubRegSize::i16Bit && - (std::is_same_v || std::is_same_v)) + template + requires(size == ARMEmitter::SubRegSize::i16Bit && + (std::is_same_v || std::is_same_v)) void frintp(T rd, T rn) { ASIMDTwoRegMiscFP16(0, 1, 0b11000, rn, rd); } - template - requires(size == FEXCore::ARMEmitter::SubRegSize::i16Bit && - (std::is_same_v || std::is_same_v)) + template + requires(size == ARMEmitter::SubRegSize::i16Bit && + (std::is_same_v || std::is_same_v)) void frintz(T rd, T rn) { ASIMDTwoRegMiscFP16(0, 1, 0b11001, rn, rd); } - template - requires(size == FEXCore::ARMEmitter::SubRegSize::i16Bit && - (std::is_same_v || std::is_same_v)) + template + requires(size == ARMEmitter::SubRegSize::i16Bit && + (std::is_same_v || std::is_same_v)) void fcvtps(T rd, T rn) { ASIMDTwoRegMiscFP16(0, 1, 0b11010, rn, rd); } - template - requires(size == FEXCore::ARMEmitter::SubRegSize::i16Bit && - (std::is_same_v || std::is_same_v)) + template + requires(size == ARMEmitter::SubRegSize::i16Bit && + (std::is_same_v || std::is_same_v)) void fcvtzs(T rd, T rn) { ASIMDTwoRegMiscFP16(0, 1, 0b11011, rn, rd); } - template - requires(size == FEXCore::ARMEmitter::SubRegSize::i16Bit && - (std::is_same_v || std::is_same_v)) + template + requires(size == ARMEmitter::SubRegSize::i16Bit && + (std::is_same_v || std::is_same_v)) void frecpe(T rd, T rn) { ASIMDTwoRegMiscFP16(0, 1, 0b11101, rn, rd); } - template - requires(size == FEXCore::ARMEmitter::SubRegSize::i16Bit && - (std::is_same_v || std::is_same_v)) + template + requires(size == ARMEmitter::SubRegSize::i16Bit && + (std::is_same_v || std::is_same_v)) void frinta(T rd, T rn) { ASIMDTwoRegMiscFP16(1, 0, 0b11000, rn, rd); } - template - requires(size == FEXCore::ARMEmitter::SubRegSize::i16Bit && - (std::is_same_v || std::is_same_v)) + template + requires(size == ARMEmitter::SubRegSize::i16Bit && + (std::is_same_v || std::is_same_v)) void frintx(T rd, T rn) { ASIMDTwoRegMiscFP16(1, 0, 0b11001, rn, rd); } - template - requires(size == FEXCore::ARMEmitter::SubRegSize::i16Bit && - (std::is_same_v || std::is_same_v)) + template + requires(size == ARMEmitter::SubRegSize::i16Bit && + (std::is_same_v || std::is_same_v)) void fcvtnu(T rd, T rn) { ASIMDTwoRegMiscFP16(1, 0, 0b11010, rn, rd); } - template - requires(size == FEXCore::ARMEmitter::SubRegSize::i16Bit && - (std::is_same_v || std::is_same_v)) + template + requires(size == ARMEmitter::SubRegSize::i16Bit && + (std::is_same_v || std::is_same_v)) void fcvtmu(T rd, T rn) { ASIMDTwoRegMiscFP16(1, 0, 0b11011, rn, rd); } - template - requires(size == FEXCore::ARMEmitter::SubRegSize::i16Bit && - (std::is_same_v || std::is_same_v)) + template + requires(size == ARMEmitter::SubRegSize::i16Bit && + (std::is_same_v || std::is_same_v)) void fcvtau(T rd, T rn) { ASIMDTwoRegMiscFP16(1, 0, 0b11100, rn, rd); } - template - requires(size == FEXCore::ARMEmitter::SubRegSize::i16Bit && - (std::is_same_v || std::is_same_v)) + template + requires(size == ARMEmitter::SubRegSize::i16Bit && + (std::is_same_v || std::is_same_v)) void ucvtf(T rd, T rn) { ASIMDTwoRegMiscFP16(1, 0, 0b11101, rn, rd); } - template - requires(size == FEXCore::ARMEmitter::SubRegSize::i16Bit && - (std::is_same_v || std::is_same_v)) + template + requires(size == ARMEmitter::SubRegSize::i16Bit && + (std::is_same_v || std::is_same_v)) void fcmge(T rd, T rn) { ASIMDTwoRegMiscFP16(1, 1, 0b01100, rn, rd); } - template - requires(size == FEXCore::ARMEmitter::SubRegSize::i16Bit && - (std::is_same_v || std::is_same_v)) + template + requires(size == ARMEmitter::SubRegSize::i16Bit && + (std::is_same_v || std::is_same_v)) void fcmle(T rd, T rn) { ASIMDTwoRegMiscFP16(1, 1, 0b01101, rn, rd); } - template - requires(size == FEXCore::ARMEmitter::SubRegSize::i16Bit && - (std::is_same_v || std::is_same_v)) + template + requires(size == ARMEmitter::SubRegSize::i16Bit && + (std::is_same_v || std::is_same_v)) void fneg(T rd, T rn) { ASIMDTwoRegMiscFP16(1, 1, 0b01111, rn, rd); } - template - requires(size == FEXCore::ARMEmitter::SubRegSize::i16Bit && - (std::is_same_v || std::is_same_v)) + template + requires(size == ARMEmitter::SubRegSize::i16Bit && + (std::is_same_v || std::is_same_v)) void frinti(T rd, T rn) { ASIMDTwoRegMiscFP16(1, 1, 0b11001, rn, rd); } - template - requires(size == FEXCore::ARMEmitter::SubRegSize::i16Bit && - (std::is_same_v || std::is_same_v)) + template + requires(size == ARMEmitter::SubRegSize::i16Bit && + (std::is_same_v || std::is_same_v)) void fcvtpu(T rd, T rn) { ASIMDTwoRegMiscFP16(1, 1, 0b11010, rn, rd); } - template - requires(size == FEXCore::ARMEmitter::SubRegSize::i16Bit && - (std::is_same_v || std::is_same_v)) + template + requires(size == ARMEmitter::SubRegSize::i16Bit && + (std::is_same_v || std::is_same_v)) void fcvtzu(T rd, T rn) { ASIMDTwoRegMiscFP16(1, 1, 0b11011, rn, rd); } - template - requires(size == FEXCore::ARMEmitter::SubRegSize::i16Bit && - (std::is_same_v || std::is_same_v)) + template + requires(size == ARMEmitter::SubRegSize::i16Bit && + (std::is_same_v || std::is_same_v)) void frsqrte(T rd, T rn) { ASIMDTwoRegMiscFP16(1, 1, 0b11101, rn, rd); } - template - requires(size == FEXCore::ARMEmitter::SubRegSize::i16Bit && - (std::is_same_v || std::is_same_v)) + template + requires(size == ARMEmitter::SubRegSize::i16Bit && + (std::is_same_v || std::is_same_v)) void fsqrt(T rd, T rn) { ASIMDTwoRegMiscFP16(1, 1, 0b11111, rn, rd); } // Advanced SIMD three-register extension template - requires(std::is_same_v || std::is_same_v) - void sdot(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, T rm) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); + requires(std::is_same_v || std::is_same_v) + void sdot(ARMEmitter::SubRegSize size, T rd, T rn, T rm) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); } ASIMDThreeRegisterExt(0, 0b0010, size, rm, rn, rd); } template - requires(std::is_same_v || std::is_same_v) + requires(std::is_same_v || std::is_same_v) void usdot(T rd, T rn, T rm) { - ASIMDThreeRegisterExt(0, 0b0011, FEXCore::ARMEmitter::SubRegSize::i32Bit, rm, rn, rd); + ASIMDThreeRegisterExt(0, 0b0011, ARMEmitter::SubRegSize::i32Bit, rm, rn, rd); } template - requires(std::is_same_v || std::is_same_v) - void sqrdmlah(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, T rm) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); + requires(std::is_same_v || std::is_same_v) + void sqrdmlah(ARMEmitter::SubRegSize size, T rd, T rn, T rm) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); } ASIMDThreeRegisterExt(1, 0b0000, size, rm, rn, rd); } template - requires(std::is_same_v || std::is_same_v) - void sqrdmlsh(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, T rm) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); + requires(std::is_same_v || std::is_same_v) + void sqrdmlsh(ARMEmitter::SubRegSize size, T rd, T rn, T rm) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); } ASIMDThreeRegisterExt(1, 0b0001, size, rm, rn, rd); } template - requires(std::is_same_v || std::is_same_v) - void udot(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, T rm) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); + requires(std::is_same_v || std::is_same_v) + void udot(ARMEmitter::SubRegSize size, T rd, T rn, T rm) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); } ASIMDThreeRegisterExt(1, 0b0010, size, rm, rn, rd); } template - requires(std::is_same_v || std::is_same_v) - void fcmla(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, T rm, FEXCore::ARMEmitter::Rotation Rot) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i8Bit, "8-bit subregsize not supported"); + requires(std::is_same_v || std::is_same_v) + void fcmla(ARMEmitter::SubRegSize size, T rd, T rn, T rm, ARMEmitter::Rotation Rot) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i8Bit, "8-bit subregsize not supported"); - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); } ASIMDThreeRegisterExt(1, 0b1000 | FEXCore::ToUnderlying(Rot), size, rm, rn, rd); } template - requires(std::is_same_v || std::is_same_v) - void fcadd(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, T rm, FEXCore::ARMEmitter::Rotation Rot) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i8Bit, "8-bit subregsize not supported"); + requires(std::is_same_v || std::is_same_v) + void fcadd(ARMEmitter::SubRegSize size, T rd, T rn, T rm, ARMEmitter::Rotation Rot) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i8Bit, "8-bit subregsize not supported"); - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); } - LOGMAN_THROW_A_FMT(Rot == FEXCore::ARMEmitter::Rotation::ROTATE_90 || Rot == FEXCore::ARMEmitter::Rotation::ROTATE_270, "Invalid rotation"); + LOGMAN_THROW_A_FMT(Rot == ARMEmitter::Rotation::ROTATE_90 || Rot == ARMEmitter::Rotation::ROTATE_270, "Invalid rotation"); const uint32_t ConvertedRotation = - Rot == FEXCore::ARMEmitter::Rotation::ROTATE_90 ? 0b00 : 0b10; + Rot == ARMEmitter::Rotation::ROTATE_90 ? 0b00 : 0b10; ASIMDThreeRegisterExt(1, 0b1100 | ConvertedRotation, size, rm, rn, rd); } template - requires(std::is_same_v || std::is_same_v) + requires(std::is_same_v || std::is_same_v) void bfdot(T rd, T rn, T rm) { - ASIMDThreeRegisterExt(1, 0b1111, FEXCore::ARMEmitter::SubRegSize::i16Bit, rm, rn, rd); + ASIMDThreeRegisterExt(1, 0b1111, ARMEmitter::SubRegSize::i16Bit, rm, rn, rd); } void bfmlalb(ARMEmitter::VRegister rd, ARMEmitter::VRegister rn, ARMEmitter::VRegister rm) { - ASIMDThreeRegisterExt(1, 0b1111, FEXCore::ARMEmitter::SubRegSize::i64Bit, rm.D(), rn.D(), rd.D()); + ASIMDThreeRegisterExt(1, 0b1111, ARMEmitter::SubRegSize::i64Bit, rm.D(), rn.D(), rd.D()); } void bfmlalt(ARMEmitter::VRegister rd, ARMEmitter::VRegister rn, ARMEmitter::VRegister rm) { - ASIMDThreeRegisterExt(1, 0b1111, FEXCore::ARMEmitter::SubRegSize::i64Bit, rm.Q(), rn.Q(), rd.Q()); + ASIMDThreeRegisterExt(1, 0b1111, ARMEmitter::SubRegSize::i64Bit, rm.Q(), rn.Q(), rd.Q()); } void smmla(ARMEmitter::VRegister rd, ARMEmitter::VRegister rn, ARMEmitter::VRegister rm) { - ASIMDThreeRegisterExt(0, 0b0100, FEXCore::ARMEmitter::SubRegSize::i32Bit, rm.Q(), rn.Q(), rd.Q()); + ASIMDThreeRegisterExt(0, 0b0100, ARMEmitter::SubRegSize::i32Bit, rm.Q(), rn.Q(), rd.Q()); } void usmmla(ARMEmitter::VRegister rd, ARMEmitter::VRegister rn, ARMEmitter::VRegister rm) { - ASIMDThreeRegisterExt(0, 0b0101, FEXCore::ARMEmitter::SubRegSize::i32Bit, rm.Q(), rn.Q(), rd.Q()); + ASIMDThreeRegisterExt(0, 0b0101, ARMEmitter::SubRegSize::i32Bit, rm.Q(), rn.Q(), rd.Q()); } void bfmmla(ARMEmitter::VRegister rd, ARMEmitter::VRegister rn, ARMEmitter::VRegister rm) { - ASIMDThreeRegisterExt(1, 0b1101, FEXCore::ARMEmitter::SubRegSize::i16Bit, rm.Q(), rn.Q(), rd.Q()); + ASIMDThreeRegisterExt(1, 0b1101, ARMEmitter::SubRegSize::i16Bit, rm.Q(), rn.Q(), rd.Q()); } void ummla(ARMEmitter::VRegister rd, ARMEmitter::VRegister rn, ARMEmitter::VRegister rm) { - ASIMDThreeRegisterExt(1, 0b0100, FEXCore::ARMEmitter::SubRegSize::i32Bit, rm.Q(), rn.Q(), rd.Q()); + ASIMDThreeRegisterExt(1, 0b0100, ARMEmitter::SubRegSize::i32Bit, rm.Q(), rn.Q(), rd.Q()); } // Advanced SIMD two-register miscellaneous template - requires(std::is_same_v || std::is_same_v) - void rev64(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); + requires(std::is_same_v || std::is_same_v) + void rev64(ARMEmitter::SubRegSize size, T rd, T rn) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'10 << 10; ASIMD2RegMisc(Op, 0, size, 0b00000, rd, rn); } template - requires(std::is_same_v || std::is_same_v) - void rev16(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn) { - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i8Bit, "Only 8-bit subregsize supported"); + requires(std::is_same_v || std::is_same_v) + void rev16(ARMEmitter::SubRegSize size, T rd, T rn) { + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i8Bit, "Only 8-bit subregsize supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'10 << 10; ASIMD2RegMisc(Op, 0, size, 0b00001, rd, rn); } @@ -931,9 +931,9 @@ public: ///< size is the destination size. ///< source size is the next size up. template - requires(std::is_same_v || std::is_same_v) - void saddlp(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i8Bit, "Destination 8-bit subregsize unsupported"); + requires(std::is_same_v || std::is_same_v) + void saddlp(ARMEmitter::SubRegSize size, T rd, T rn) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i8Bit, "Destination 8-bit subregsize unsupported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'10 << 10; const auto ConvertedSize = size == ARMEmitter::SubRegSize::i64Bit ? ARMEmitter::SubRegSize::i32Bit : @@ -944,26 +944,26 @@ public: } template - requires(std::is_same_v || std::is_same_v) - void suqadd(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); + requires(std::is_same_v || std::is_same_v) + void suqadd(ARMEmitter::SubRegSize size, T rd, T rn) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); } constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'10 << 10; ASIMD2RegMisc(Op, 0, size, 0b00011, rd, rn); } template - requires(std::is_same_v || std::is_same_v) - void cls(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); + requires(std::is_same_v || std::is_same_v) + void cls(ARMEmitter::SubRegSize size, T rd, T rn) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'10 << 10; ASIMD2RegMisc(Op, 0, size, 0b00100, rd, rn); } template - requires(std::is_same_v || std::is_same_v) - void cnt(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn) { - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i8Bit, "Only 8-bit subregsize supported"); + requires(std::is_same_v || std::is_same_v) + void cnt(ARMEmitter::SubRegSize size, T rd, T rn) { + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i8Bit, "Only 8-bit subregsize supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'10 << 10; ASIMD2RegMisc(Op, 0, size, 0b00101, rd, rn); } @@ -971,9 +971,9 @@ public: ///< size is the destination size. ///< source size is the next size up. template - requires(std::is_same_v || std::is_same_v) - void sadalp(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i8Bit, "Destination 8-bit subregsize unsupported"); + requires(std::is_same_v || std::is_same_v) + void sadalp(ARMEmitter::SubRegSize size, T rd, T rn) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i8Bit, "Destination 8-bit subregsize unsupported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'10 << 10; const auto ConvertedSize = size == ARMEmitter::SubRegSize::i64Bit ? ARMEmitter::SubRegSize::i32Bit : @@ -984,49 +984,49 @@ public: } template - requires(std::is_same_v || std::is_same_v) - void sqabs(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); + requires(std::is_same_v || std::is_same_v) + void sqabs(ARMEmitter::SubRegSize size, T rd, T rn) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); } constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'10 << 10; ASIMD2RegMisc(Op, 0, size, 0b00111, rd, rn); } // Comparison against zero template - requires(std::is_same_v || std::is_same_v) - void cmgt(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); + requires(std::is_same_v || std::is_same_v) + void cmgt(ARMEmitter::SubRegSize size, T rd, T rn) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); } constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'10 << 10; ASIMD2RegMisc(Op, 0, size, 0b01000, rd, rn); } // Comparison against zero template - requires(std::is_same_v || std::is_same_v) - void cmeq(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); + requires(std::is_same_v || std::is_same_v) + void cmeq(ARMEmitter::SubRegSize size, T rd, T rn) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); } constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'10 << 10; ASIMD2RegMisc(Op, 0, size, 0b01001, rd, rn); } // Comparison against zero template - requires(std::is_same_v || std::is_same_v) - void cmlt(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); + requires(std::is_same_v || std::is_same_v) + void cmlt(ARMEmitter::SubRegSize size, T rd, T rn) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); } constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'10 << 10; ASIMD2RegMisc(Op, 0, size, 0b01010, rd, rn); } template - requires(std::is_same_v || std::is_same_v) - void abs(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); + requires(std::is_same_v || std::is_same_v) + void abs(ARMEmitter::SubRegSize size, T rd, T rn) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); } constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'10 << 10; ASIMD2RegMisc(Op, 0, size, 0b01011, rd, rn); @@ -1034,39 +1034,39 @@ public: ///< size is the destination size. ///< source size is the next size up. - void xtn(FEXCore::ARMEmitter::SubRegSize size, ARMEmitter::VRegister rd, ARMEmitter::VRegister rn) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "64-bit destination subregsize not supported"); + void xtn(ARMEmitter::SubRegSize size, ARMEmitter::VRegister rd, ARMEmitter::VRegister rn) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "64-bit destination subregsize not supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'10 << 10; ASIMD2RegMisc(Op, 0, size, 0b10010, rd.D(), rn.D()); } ///< size is the destination size. ///< source size is the next size up. - void xtn2(FEXCore::ARMEmitter::SubRegSize size, ARMEmitter::VRegister rd, ARMEmitter::VRegister rn) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "64-bit destination subregsize not supported"); + void xtn2(ARMEmitter::SubRegSize size, ARMEmitter::VRegister rd, ARMEmitter::VRegister rn) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "64-bit destination subregsize not supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'10 << 10; ASIMD2RegMisc(Op, 0, size, 0b10010, rd.Q(), rn.Q()); } ///< size is the destination size. ///< source size is the next size up. - void sqxtn(FEXCore::ARMEmitter::SubRegSize size, ARMEmitter::VRegister rd, ARMEmitter::VRegister rn) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "64-bit destination subregsize not supported"); + void sqxtn(ARMEmitter::SubRegSize size, ARMEmitter::VRegister rd, ARMEmitter::VRegister rn) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "64-bit destination subregsize not supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'10 << 10; ASIMD2RegMisc(Op, 0, size, 0b10100, rd.D(), rn.D()); } ///< size is the destination size. ///< source size is the next size up. - void sqxtn2(FEXCore::ARMEmitter::SubRegSize size, ARMEmitter::VRegister rd, ARMEmitter::VRegister rn) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "64-bit destination subregsize not supported"); + void sqxtn2(ARMEmitter::SubRegSize size, ARMEmitter::VRegister rd, ARMEmitter::VRegister rn) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "64-bit destination subregsize not supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'10 << 10; ASIMD2RegMisc(Op, 0, size, 0b10100, rd.Q(), rn.Q()); } ///< size is the destination size. ///< source size is the next size up. - void fcvtn(FEXCore::ARMEmitter::SubRegSize size, ARMEmitter::VRegister rd, ARMEmitter::VRegister rn) { - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i32Bit || - size == FEXCore::ARMEmitter::SubRegSize::i16Bit, "Only 16-bit & 32-bit subregsize supported"); + void fcvtn(ARMEmitter::SubRegSize size, ARMEmitter::VRegister rd, ARMEmitter::VRegister rn) { + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i32Bit || + size == ARMEmitter::SubRegSize::i16Bit, "Only 16-bit & 32-bit subregsize supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'10 << 10; const auto ConvertedSize = size == ARMEmitter::SubRegSize::i32Bit ? ARMEmitter::SubRegSize::i16Bit : @@ -1076,9 +1076,9 @@ public: } ///< size is the destination size. ///< source size is the next size up. - void fcvtn2(FEXCore::ARMEmitter::SubRegSize size, ARMEmitter::VRegister rd, ARMEmitter::VRegister rn) { - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i32Bit || - size == FEXCore::ARMEmitter::SubRegSize::i16Bit, "Only 16-bit & 32-bit subregsize supported"); + void fcvtn2(ARMEmitter::SubRegSize size, ARMEmitter::VRegister rd, ARMEmitter::VRegister rn) { + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i32Bit || + size == ARMEmitter::SubRegSize::i16Bit, "Only 16-bit & 32-bit subregsize supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'10 << 10; const auto ConvertedSize = size == ARMEmitter::SubRegSize::i32Bit ? ARMEmitter::SubRegSize::i16Bit : @@ -1089,9 +1089,9 @@ public: ///< size is the destination size. ///< source size is the next size up. - void fcvtl(FEXCore::ARMEmitter::SubRegSize size, ARMEmitter::VRegister rd, ARMEmitter::VRegister rn) { - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i64Bit || - size == FEXCore::ARMEmitter::SubRegSize::i32Bit, "Only 32-bit & 64-bit subregsize supported"); + void fcvtl(ARMEmitter::SubRegSize size, ARMEmitter::VRegister rd, ARMEmitter::VRegister rn) { + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i64Bit || + size == ARMEmitter::SubRegSize::i32Bit, "Only 32-bit & 64-bit subregsize supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'10 << 10; const auto ConvertedSize = size == ARMEmitter::SubRegSize::i64Bit ? ARMEmitter::SubRegSize::i16Bit : @@ -1101,9 +1101,9 @@ public: } ///< size is the destination size. ///< source size is the next size up. - void fcvtl2(FEXCore::ARMEmitter::SubRegSize size, ARMEmitter::VRegister rd, ARMEmitter::VRegister rn) { - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i64Bit || - size == FEXCore::ARMEmitter::SubRegSize::i32Bit, "Only 32-bit & 64-bit subregsize supported"); + void fcvtl2(ARMEmitter::SubRegSize size, ARMEmitter::VRegister rd, ARMEmitter::VRegister rn) { + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i64Bit || + size == ARMEmitter::SubRegSize::i32Bit, "Only 32-bit & 64-bit subregsize supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'10 << 10; const auto ConvertedSize = size == ARMEmitter::SubRegSize::i64Bit ? ARMEmitter::SubRegSize::i16Bit : @@ -1113,13 +1113,13 @@ public: } template - requires(std::is_same_v || std::is_same_v) - void frintn(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); + requires(std::is_same_v || std::is_same_v) + void frintn(ARMEmitter::SubRegSize size, T rd, T rn) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); } - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i64Bit || - size == FEXCore::ARMEmitter::SubRegSize::i32Bit, "Only 32-bit & 64-bit subregsize supported"); + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i64Bit || + size == ARMEmitter::SubRegSize::i32Bit, "Only 32-bit & 64-bit subregsize supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'10 << 10; const auto ConvertedSize = size == ARMEmitter::SubRegSize::i64Bit ? ARMEmitter::SubRegSize::i16Bit : @@ -1128,13 +1128,13 @@ public: ASIMD2RegMisc(Op, 0, ConvertedSize, 0b11000, rd, rn); } template - requires(std::is_same_v || std::is_same_v) - void frintm(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); + requires(std::is_same_v || std::is_same_v) + void frintm(ARMEmitter::SubRegSize size, T rd, T rn) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); } - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i64Bit || - size == FEXCore::ARMEmitter::SubRegSize::i32Bit, "Only 32-bit & 64-bit subregsize supported"); + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i64Bit || + size == ARMEmitter::SubRegSize::i32Bit, "Only 32-bit & 64-bit subregsize supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'10 << 10; const auto ConvertedSize = size == ARMEmitter::SubRegSize::i64Bit ? ARMEmitter::SubRegSize::i16Bit : @@ -1144,13 +1144,13 @@ public: } template - requires(std::is_same_v || std::is_same_v) - void fcvtns(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); + requires(std::is_same_v || std::is_same_v) + void fcvtns(ARMEmitter::SubRegSize size, T rd, T rn) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); } - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i64Bit || - size == FEXCore::ARMEmitter::SubRegSize::i32Bit, "Only 32-bit & 64-bit subregsize supported"); + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i64Bit || + size == ARMEmitter::SubRegSize::i32Bit, "Only 32-bit & 64-bit subregsize supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'10 << 10; const auto ConvertedSize = size == ARMEmitter::SubRegSize::i64Bit ? ARMEmitter::SubRegSize::i16Bit : @@ -1159,13 +1159,13 @@ public: ASIMD2RegMisc(Op, 0, ConvertedSize, 0b11010, rd, rn); } template - requires(std::is_same_v || std::is_same_v) - void fcvtms(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); + requires(std::is_same_v || std::is_same_v) + void fcvtms(ARMEmitter::SubRegSize size, T rd, T rn) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); } - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i64Bit || - size == FEXCore::ARMEmitter::SubRegSize::i32Bit, "Only 32-bit & 64-bit subregsize supported"); + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i64Bit || + size == ARMEmitter::SubRegSize::i32Bit, "Only 32-bit & 64-bit subregsize supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'10 << 10; const auto ConvertedSize = size == ARMEmitter::SubRegSize::i64Bit ? ARMEmitter::SubRegSize::i16Bit : @@ -1174,13 +1174,13 @@ public: ASIMD2RegMisc(Op, 0, ConvertedSize, 0b11011, rd, rn); } template - requires(std::is_same_v || std::is_same_v) - void fcvtas(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); + requires(std::is_same_v || std::is_same_v) + void fcvtas(ARMEmitter::SubRegSize size, T rd, T rn) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); } - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i64Bit || - size == FEXCore::ARMEmitter::SubRegSize::i32Bit, "Only 32-bit & 64-bit subregsize supported"); + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i64Bit || + size == ARMEmitter::SubRegSize::i32Bit, "Only 32-bit & 64-bit subregsize supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'10 << 10; const auto ConvertedSize = size == ARMEmitter::SubRegSize::i64Bit ? ARMEmitter::SubRegSize::i16Bit : @@ -1189,13 +1189,13 @@ public: ASIMD2RegMisc(Op, 0, ConvertedSize, 0b11100, rd, rn); } template - requires(std::is_same_v || std::is_same_v) - void scvtf(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); + requires(std::is_same_v || std::is_same_v) + void scvtf(ARMEmitter::SubRegSize size, T rd, T rn) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); } - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i64Bit || - size == FEXCore::ARMEmitter::SubRegSize::i32Bit, "Only 32-bit & 64-bit subregsize supported"); + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i64Bit || + size == ARMEmitter::SubRegSize::i32Bit, "Only 32-bit & 64-bit subregsize supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'10 << 10; const auto ConvertedSize = size == ARMEmitter::SubRegSize::i64Bit ? ARMEmitter::SubRegSize::i16Bit : @@ -1204,13 +1204,13 @@ public: ASIMD2RegMisc(Op, 0, ConvertedSize, 0b11101, rd, rn); } template - requires(std::is_same_v || std::is_same_v) - void frint32z(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); + requires(std::is_same_v || std::is_same_v) + void frint32z(ARMEmitter::SubRegSize size, T rd, T rn) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); } - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i64Bit || - size == FEXCore::ARMEmitter::SubRegSize::i32Bit, "Only 32-bit & 64-bit subregsize supported"); + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i64Bit || + size == ARMEmitter::SubRegSize::i32Bit, "Only 32-bit & 64-bit subregsize supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'10 << 10; const auto ConvertedSize = size == ARMEmitter::SubRegSize::i64Bit ? ARMEmitter::SubRegSize::i16Bit : @@ -1219,13 +1219,13 @@ public: ASIMD2RegMisc(Op, 0, ConvertedSize, 0b11110, rd, rn); } template - requires(std::is_same_v || std::is_same_v) - void frint64z(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); + requires(std::is_same_v || std::is_same_v) + void frint64z(ARMEmitter::SubRegSize size, T rd, T rn) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); } - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i64Bit || - size == FEXCore::ARMEmitter::SubRegSize::i32Bit, "Only 32-bit & 64-bit subregsize supported"); + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i64Bit || + size == ARMEmitter::SubRegSize::i32Bit, "Only 32-bit & 64-bit subregsize supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'10 << 10; const auto ConvertedSize = size == ARMEmitter::SubRegSize::i64Bit ? ARMEmitter::SubRegSize::i16Bit : @@ -1235,123 +1235,123 @@ public: } template - requires(std::is_same_v || std::is_same_v) - void fcmgt(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); + requires(std::is_same_v || std::is_same_v) + void fcmgt(ARMEmitter::SubRegSize size, T rd, T rn) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); } - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i64Bit || - size == FEXCore::ARMEmitter::SubRegSize::i32Bit, "Only 32-bit & 64-bit subregsize supported"); + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i64Bit || + size == ARMEmitter::SubRegSize::i32Bit, "Only 32-bit & 64-bit subregsize supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'10 << 10; ASIMD2RegMisc(Op, 0, size, 0b01100, rd, rn); } template - requires(std::is_same_v || std::is_same_v) - void fcmeq(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); + requires(std::is_same_v || std::is_same_v) + void fcmeq(ARMEmitter::SubRegSize size, T rd, T rn) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); } - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i64Bit || - size == FEXCore::ARMEmitter::SubRegSize::i32Bit, "Only 32-bit & 64-bit subregsize supported"); + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i64Bit || + size == ARMEmitter::SubRegSize::i32Bit, "Only 32-bit & 64-bit subregsize supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'10 << 10; ASIMD2RegMisc(Op, 0, size, 0b01101, rd, rn); } template - requires(std::is_same_v || std::is_same_v) - void fcmlt(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); + requires(std::is_same_v || std::is_same_v) + void fcmlt(ARMEmitter::SubRegSize size, T rd, T rn) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); } - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i64Bit || - size == FEXCore::ARMEmitter::SubRegSize::i32Bit, "Only 32-bit & 64-bit subregsize supported"); + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i64Bit || + size == ARMEmitter::SubRegSize::i32Bit, "Only 32-bit & 64-bit subregsize supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'10 << 10; ASIMD2RegMisc(Op, 0, size, 0b01110, rd, rn); } template - requires(std::is_same_v || std::is_same_v) - void fabs(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); + requires(std::is_same_v || std::is_same_v) + void fabs(ARMEmitter::SubRegSize size, T rd, T rn) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); } - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i64Bit || - size == FEXCore::ARMEmitter::SubRegSize::i32Bit, "Only 32-bit & 64-bit subregsize supported"); + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i64Bit || + size == ARMEmitter::SubRegSize::i32Bit, "Only 32-bit & 64-bit subregsize supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'10 << 10; ASIMD2RegMisc(Op, 0, size, 0b01111, rd, rn); } template - requires(std::is_same_v || std::is_same_v) - void frintp(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); + requires(std::is_same_v || std::is_same_v) + void frintp(ARMEmitter::SubRegSize size, T rd, T rn) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); } - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i64Bit || - size == FEXCore::ARMEmitter::SubRegSize::i32Bit, "Only 32-bit & 64-bit subregsize supported"); + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i64Bit || + size == ARMEmitter::SubRegSize::i32Bit, "Only 32-bit & 64-bit subregsize supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'10 << 10; ASIMD2RegMisc(Op, 0, size, 0b11000, rd, rn); } template - requires(std::is_same_v || std::is_same_v) - void frintz(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); + requires(std::is_same_v || std::is_same_v) + void frintz(ARMEmitter::SubRegSize size, T rd, T rn) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); } - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i64Bit || - size == FEXCore::ARMEmitter::SubRegSize::i32Bit, "Only 32-bit & 64-bit subregsize supported"); + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i64Bit || + size == ARMEmitter::SubRegSize::i32Bit, "Only 32-bit & 64-bit subregsize supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'10 << 10; ASIMD2RegMisc(Op, 0, size, 0b11001, rd, rn); } template - requires(std::is_same_v || std::is_same_v) - void fcvtps(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); + requires(std::is_same_v || std::is_same_v) + void fcvtps(ARMEmitter::SubRegSize size, T rd, T rn) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); } - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i64Bit || - size == FEXCore::ARMEmitter::SubRegSize::i32Bit, "Only 32-bit & 64-bit subregsize supported"); + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i64Bit || + size == ARMEmitter::SubRegSize::i32Bit, "Only 32-bit & 64-bit subregsize supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'10 << 10; ASIMD2RegMisc(Op, 0, size, 0b11010, rd, rn); } template - requires(std::is_same_v || std::is_same_v) - void fcvtzs(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); + requires(std::is_same_v || std::is_same_v) + void fcvtzs(ARMEmitter::SubRegSize size, T rd, T rn) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); } - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i64Bit || - size == FEXCore::ARMEmitter::SubRegSize::i32Bit, "Only 32-bit & 64-bit subregsize supported"); + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i64Bit || + size == ARMEmitter::SubRegSize::i32Bit, "Only 32-bit & 64-bit subregsize supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'10 << 10; ASIMD2RegMisc(Op, 0, size, 0b11011, rd, rn); } template - requires(std::is_same_v || std::is_same_v) - void urecpe(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn) { - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i32Bit, "Only 32-bit subregsize supported"); + requires(std::is_same_v || std::is_same_v) + void urecpe(ARMEmitter::SubRegSize size, T rd, T rn) { + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i32Bit, "Only 32-bit subregsize supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'10 << 10; ASIMD2RegMisc(Op, 0, size, 0b11100, rd, rn); } template - requires(std::is_same_v || std::is_same_v) - void frecpe(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn) { - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i64Bit || - size == FEXCore::ARMEmitter::SubRegSize::i32Bit, "Only 32-bit & 64-bit subregsize supported"); + requires(std::is_same_v || std::is_same_v) + void frecpe(ARMEmitter::SubRegSize size, T rd, T rn) { + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i64Bit || + size == ARMEmitter::SubRegSize::i32Bit, "Only 32-bit & 64-bit subregsize supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'10 << 10; ASIMD2RegMisc(Op, 0, size, 0b11101, rd, rn); } template - requires(std::is_same_v || std::is_same_v) - void rev32(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn) { - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i8Bit || - size == FEXCore::ARMEmitter::SubRegSize::i16Bit, "Only 8-bit & 16-bit subregsize supported"); + requires(std::is_same_v || std::is_same_v) + void rev32(ARMEmitter::SubRegSize size, T rd, T rn) { + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i8Bit || + size == ARMEmitter::SubRegSize::i16Bit, "Only 8-bit & 16-bit subregsize supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'10 << 10; ASIMD2RegMisc(Op, 1, size, 0b00000, rd, rn); } @@ -1359,9 +1359,9 @@ public: ///< size is the destination size. ///< source size is the next size up. template - requires(std::is_same_v || std::is_same_v) - void uaddlp(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i8Bit, "Destination 8-bit subregsize unsupported"); + requires(std::is_same_v || std::is_same_v) + void uaddlp(ARMEmitter::SubRegSize size, T rd, T rn) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i8Bit, "Destination 8-bit subregsize unsupported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'10 << 10; const auto ConvertedSize = size == ARMEmitter::SubRegSize::i64Bit ? ARMEmitter::SubRegSize::i32Bit : @@ -1372,19 +1372,19 @@ public: } template - requires(std::is_same_v || std::is_same_v) - void usqadd(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); + requires(std::is_same_v || std::is_same_v) + void usqadd(ARMEmitter::SubRegSize size, T rd, T rn) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); } constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'10 << 10; ASIMD2RegMisc(Op, 1, size, 0b00011, rd, rn); } template - requires(std::is_same_v || std::is_same_v) - void clz(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); + requires(std::is_same_v || std::is_same_v) + void clz(ARMEmitter::SubRegSize size, T rd, T rn) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'10 << 10; ASIMD2RegMisc(Op, 1, size, 0b00100, rd, rn); } @@ -1392,9 +1392,9 @@ public: ///< size is the destination size. ///< source size is the next size up. template - requires(std::is_same_v || std::is_same_v) - void uadalp(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i8Bit, "Destination 8-bit subregsize unsupported"); + requires(std::is_same_v || std::is_same_v) + void uadalp(ARMEmitter::SubRegSize size, T rd, T rn) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i8Bit, "Destination 8-bit subregsize unsupported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'10 << 10; const auto ConvertedSize = size == ARMEmitter::SubRegSize::i64Bit ? ARMEmitter::SubRegSize::i32Bit : @@ -1405,10 +1405,10 @@ public: } template - requires(std::is_same_v || std::is_same_v) - void sqneg(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); + requires(std::is_same_v || std::is_same_v) + void sqneg(ARMEmitter::SubRegSize size, T rd, T rn) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); } constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'10 << 10; ASIMD2RegMisc(Op, 1, size, 0b00111, rd, rn); @@ -1416,52 +1416,52 @@ public: // Comparison against zero template - requires(std::is_same_v || std::is_same_v) - void cmge(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); + requires(std::is_same_v || std::is_same_v) + void cmge(ARMEmitter::SubRegSize size, T rd, T rn) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); } constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'10 << 10; ASIMD2RegMisc(Op, 1, size, 0b01000, rd, rn); } // Comparison against zero template - requires(std::is_same_v || std::is_same_v) - void cmle(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); + requires(std::is_same_v || std::is_same_v) + void cmle(ARMEmitter::SubRegSize size, T rd, T rn) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); } constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'10 << 10; ASIMD2RegMisc(Op, 1, size, 0b01001, rd, rn); } template - requires(std::is_same_v || std::is_same_v) - void neg(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); + requires(std::is_same_v || std::is_same_v) + void neg(ARMEmitter::SubRegSize size, T rd, T rn) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); } constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'10 << 10; ASIMD2RegMisc(Op, 1, size, 0b01011, rd, rn); } ///< size is the destination size. ///< source size is the next size up. - void sqxtun(FEXCore::ARMEmitter::SubRegSize size, ARMEmitter::VRegister rd, ARMEmitter::VRegister rn) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "64-bit destination subregsize not supported"); + void sqxtun(ARMEmitter::SubRegSize size, ARMEmitter::VRegister rd, ARMEmitter::VRegister rn) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "64-bit destination subregsize not supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'10 << 10; ASIMD2RegMisc(Op, 1, size, 0b10010, rd.D(), rn.D()); } ///< size is the destination size. ///< source size is the next size up. - void sqxtun2(FEXCore::ARMEmitter::SubRegSize size, ARMEmitter::VRegister rd, ARMEmitter::VRegister rn) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "64-bit destination subregsize not supported"); + void sqxtun2(ARMEmitter::SubRegSize size, ARMEmitter::VRegister rd, ARMEmitter::VRegister rn) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "64-bit destination subregsize not supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'10 << 10; ASIMD2RegMisc(Op, 1, size, 0b10010, rd.Q(), rn.Q()); } ///< size is the destination size. ///< source size is the next size up. - void shll(FEXCore::ARMEmitter::SubRegSize size, ARMEmitter::DRegister rd, ARMEmitter::DRegister rn) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i8Bit, "Destination 8-bit subregsize unsupported"); + void shll(ARMEmitter::SubRegSize size, ARMEmitter::DRegister rd, ARMEmitter::DRegister rn) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i8Bit, "Destination 8-bit subregsize unsupported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'10 << 10; const auto ConvertedSize = size == ARMEmitter::SubRegSize::i64Bit ? ARMEmitter::SubRegSize::i32Bit : @@ -1472,8 +1472,8 @@ public: } ///< size is the destination size. ///< source size is the next size up. - void shll2(FEXCore::ARMEmitter::SubRegSize size, ARMEmitter::QRegister rd, ARMEmitter::QRegister rn) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i8Bit, "Destination 8-bit subregsize unsupported"); + void shll2(ARMEmitter::SubRegSize size, ARMEmitter::QRegister rd, ARMEmitter::QRegister rn) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i8Bit, "Destination 8-bit subregsize unsupported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'10 << 10; const auto ConvertedSize = size == ARMEmitter::SubRegSize::i64Bit ? ARMEmitter::SubRegSize::i32Bit : @@ -1484,20 +1484,20 @@ public: } ///< size is the destination size. ///< source size is the next size up. - void uqxtn(FEXCore::ARMEmitter::SubRegSize size, ARMEmitter::VRegister rd, ARMEmitter::VRegister rn) { + void uqxtn(ARMEmitter::SubRegSize size, ARMEmitter::VRegister rd, ARMEmitter::VRegister rn) { constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'10 << 10; ASIMD2RegMisc(Op, 1, size, 0b10100, rd.D(), rn.D()); } ///< size is the destination size. ///< source size is the next size up. - void uqxtn2(FEXCore::ARMEmitter::SubRegSize size, ARMEmitter::VRegister rd, ARMEmitter::VRegister rn) { + void uqxtn2(ARMEmitter::SubRegSize size, ARMEmitter::VRegister rd, ARMEmitter::VRegister rn) { constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'10 << 10; ASIMD2RegMisc(Op, 1, size, 0b10100, rd.Q(), rn.Q()); } ///< size is the destination size. ///< source size is the next size up. - void fcvtxn(FEXCore::ARMEmitter::SubRegSize size, ARMEmitter::VRegister rd, ARMEmitter::VRegister rn) { - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i32Bit, "Only 32-bit subregsize supported"); + void fcvtxn(ARMEmitter::SubRegSize size, ARMEmitter::VRegister rd, ARMEmitter::VRegister rn) { + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i32Bit, "Only 32-bit subregsize supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'10 << 10; const auto ConvertedSize = size == ARMEmitter::SubRegSize::i32Bit ? ARMEmitter::SubRegSize::i16Bit : @@ -1507,8 +1507,8 @@ public: } ///< size is the destination size. ///< source size is the next size up. - void fcvtxn2(FEXCore::ARMEmitter::SubRegSize size, ARMEmitter::VRegister rd, ARMEmitter::VRegister rn) { - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i32Bit, "Only 32-bit subregsize supported"); + void fcvtxn2(ARMEmitter::SubRegSize size, ARMEmitter::VRegister rd, ARMEmitter::VRegister rn) { + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i32Bit, "Only 32-bit subregsize supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'10 << 10; const auto ConvertedSize = size == ARMEmitter::SubRegSize::i32Bit ? ARMEmitter::SubRegSize::i16Bit : @@ -1517,10 +1517,10 @@ public: ASIMD2RegMisc(Op, 1, ConvertedSize, 0b10110, rd.Q(), rn.Q()); } template - requires(std::is_same_v || std::is_same_v) - void frinta(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn) { - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i64Bit || - size == FEXCore::ARMEmitter::SubRegSize::i32Bit, "Only 32-bit & 64-bit subregsize supported"); + requires(std::is_same_v || std::is_same_v) + void frinta(ARMEmitter::SubRegSize size, T rd, T rn) { + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i64Bit || + size == ARMEmitter::SubRegSize::i32Bit, "Only 32-bit & 64-bit subregsize supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'10 << 10; const auto ConvertedSize = size == ARMEmitter::SubRegSize::i64Bit ? ARMEmitter::SubRegSize::i16Bit : @@ -1529,10 +1529,10 @@ public: ASIMD2RegMisc(Op, 1, ConvertedSize, 0b11000, rd, rn); } template - requires(std::is_same_v || std::is_same_v) - void frintx(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn) { - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i64Bit || - size == FEXCore::ARMEmitter::SubRegSize::i32Bit, "Only 32-bit & 64-bit subregsize supported"); + requires(std::is_same_v || std::is_same_v) + void frintx(ARMEmitter::SubRegSize size, T rd, T rn) { + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i64Bit || + size == ARMEmitter::SubRegSize::i32Bit, "Only 32-bit & 64-bit subregsize supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'10 << 10; const auto ConvertedSize = size == ARMEmitter::SubRegSize::i64Bit ? ARMEmitter::SubRegSize::i16Bit : @@ -1542,10 +1542,10 @@ public: } template - requires(std::is_same_v || std::is_same_v) - void fcvtnu(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn) { - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i64Bit || - size == FEXCore::ARMEmitter::SubRegSize::i32Bit, "Only 32-bit & 64-bit subregsize supported"); + requires(std::is_same_v || std::is_same_v) + void fcvtnu(ARMEmitter::SubRegSize size, T rd, T rn) { + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i64Bit || + size == ARMEmitter::SubRegSize::i32Bit, "Only 32-bit & 64-bit subregsize supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'10 << 10; const auto ConvertedSize = size == ARMEmitter::SubRegSize::i64Bit ? ARMEmitter::SubRegSize::i16Bit : @@ -1554,10 +1554,10 @@ public: ASIMD2RegMisc(Op, 1, ConvertedSize, 0b11010, rd, rn); } template - requires(std::is_same_v || std::is_same_v) - void fcvtmu(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn) { - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i64Bit || - size == FEXCore::ARMEmitter::SubRegSize::i32Bit, "Only 32-bit & 64-bit subregsize supported"); + requires(std::is_same_v || std::is_same_v) + void fcvtmu(ARMEmitter::SubRegSize size, T rd, T rn) { + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i64Bit || + size == ARMEmitter::SubRegSize::i32Bit, "Only 32-bit & 64-bit subregsize supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'10 << 10; const auto ConvertedSize = size == ARMEmitter::SubRegSize::i64Bit ? ARMEmitter::SubRegSize::i16Bit : @@ -1566,10 +1566,10 @@ public: ASIMD2RegMisc(Op, 1, ConvertedSize, 0b11011, rd, rn); } template - requires(std::is_same_v || std::is_same_v) - void fcvtau(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn) { - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i64Bit || - size == FEXCore::ARMEmitter::SubRegSize::i32Bit, "Only 32-bit & 64-bit subregsize supported"); + requires(std::is_same_v || std::is_same_v) + void fcvtau(ARMEmitter::SubRegSize size, T rd, T rn) { + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i64Bit || + size == ARMEmitter::SubRegSize::i32Bit, "Only 32-bit & 64-bit subregsize supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'10 << 10; const auto ConvertedSize = size == ARMEmitter::SubRegSize::i64Bit ? ARMEmitter::SubRegSize::i16Bit : @@ -1578,10 +1578,10 @@ public: ASIMD2RegMisc(Op, 1, ConvertedSize, 0b11100, rd, rn); } template - requires(std::is_same_v || std::is_same_v) - void ucvtf(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn) { - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i64Bit || - size == FEXCore::ARMEmitter::SubRegSize::i32Bit, "Only 32-bit & 64-bit subregsize supported"); + requires(std::is_same_v || std::is_same_v) + void ucvtf(ARMEmitter::SubRegSize size, T rd, T rn) { + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i64Bit || + size == ARMEmitter::SubRegSize::i32Bit, "Only 32-bit & 64-bit subregsize supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'10 << 10; const auto ConvertedSize = size == ARMEmitter::SubRegSize::i64Bit ? ARMEmitter::SubRegSize::i16Bit : @@ -1590,10 +1590,10 @@ public: ASIMD2RegMisc(Op, 1, ConvertedSize, 0b11101, rd, rn); } template - requires(std::is_same_v || std::is_same_v) - void frint32x(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn) { - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i64Bit || - size == FEXCore::ARMEmitter::SubRegSize::i32Bit, "Only 32-bit & 64-bit subregsize supported"); + requires(std::is_same_v || std::is_same_v) + void frint32x(ARMEmitter::SubRegSize size, T rd, T rn) { + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i64Bit || + size == ARMEmitter::SubRegSize::i32Bit, "Only 32-bit & 64-bit subregsize supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'10 << 10; const auto ConvertedSize = size == ARMEmitter::SubRegSize::i64Bit ? ARMEmitter::SubRegSize::i16Bit : @@ -1602,10 +1602,10 @@ public: ASIMD2RegMisc(Op, 1, ConvertedSize, 0b11110, rd, rn); } template - requires(std::is_same_v || std::is_same_v) - void frint64x(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn) { - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i64Bit || - size == FEXCore::ARMEmitter::SubRegSize::i32Bit, "Only 32-bit & 64-bit subregsize supported"); + requires(std::is_same_v || std::is_same_v) + void frint64x(ARMEmitter::SubRegSize size, T rd, T rn) { + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i64Bit || + size == ARMEmitter::SubRegSize::i32Bit, "Only 32-bit & 64-bit subregsize supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'10 << 10; const auto ConvertedSize = size == ARMEmitter::SubRegSize::i64Bit ? ARMEmitter::SubRegSize::i16Bit : @@ -1615,125 +1615,125 @@ public: } template - requires(std::is_same_v || std::is_same_v) - void not_(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn) { - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i8Bit, "Only 8-bit subregsize supported"); + requires(std::is_same_v || std::is_same_v) + void not_(ARMEmitter::SubRegSize size, T rd, T rn) { + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i8Bit, "Only 8-bit subregsize supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'10 << 10; - ASIMD2RegMisc(Op, 1, FEXCore::ARMEmitter::SubRegSize::i8Bit, 0b00101, rd, rn); + ASIMD2RegMisc(Op, 1, ARMEmitter::SubRegSize::i8Bit, 0b00101, rd, rn); } template - requires(std::is_same_v || std::is_same_v) - void mvn(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn) { - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i8Bit, "Only 8-bit subregsize supported"); + requires(std::is_same_v || std::is_same_v) + void mvn(ARMEmitter::SubRegSize size, T rd, T rn) { + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i8Bit, "Only 8-bit subregsize supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'10 << 10; - ASIMD2RegMisc(Op, 1, FEXCore::ARMEmitter::SubRegSize::i8Bit, 0b00101, rd, rn); + ASIMD2RegMisc(Op, 1, ARMEmitter::SubRegSize::i8Bit, 0b00101, rd, rn); } template - requires(std::is_same_v || std::is_same_v) - void rbit(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn) { - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i8Bit, "Only 8-bit subregsize supported"); + requires(std::is_same_v || std::is_same_v) + void rbit(ARMEmitter::SubRegSize size, T rd, T rn) { + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i8Bit, "Only 8-bit subregsize supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'10 << 10; - ASIMD2RegMisc(Op, 1, FEXCore::ARMEmitter::SubRegSize::i16Bit, 0b00101, rd, rn); + ASIMD2RegMisc(Op, 1, ARMEmitter::SubRegSize::i16Bit, 0b00101, rd, rn); } template - requires(std::is_same_v || std::is_same_v) - void fcmge(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); + requires(std::is_same_v || std::is_same_v) + void fcmge(ARMEmitter::SubRegSize size, T rd, T rn) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); } - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i64Bit || - size == FEXCore::ARMEmitter::SubRegSize::i32Bit, "Only 32-bit & 64-bit subregsize supported"); + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i64Bit || + size == ARMEmitter::SubRegSize::i32Bit, "Only 32-bit & 64-bit subregsize supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'10 << 10; ASIMD2RegMisc(Op, 1, size, 0b01100, rd, rn); } template - requires(std::is_same_v || std::is_same_v) - void fcmle(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); + requires(std::is_same_v || std::is_same_v) + void fcmle(ARMEmitter::SubRegSize size, T rd, T rn) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); } - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i64Bit || - size == FEXCore::ARMEmitter::SubRegSize::i32Bit, "Only 32-bit & 64-bit subregsize supported"); + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i64Bit || + size == ARMEmitter::SubRegSize::i32Bit, "Only 32-bit & 64-bit subregsize supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'10 << 10; ASIMD2RegMisc(Op, 1, size, 0b01101, rd, rn); } template - requires(std::is_same_v || std::is_same_v) - void fneg(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); + requires(std::is_same_v || std::is_same_v) + void fneg(ARMEmitter::SubRegSize size, T rd, T rn) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); } - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i64Bit || - size == FEXCore::ARMEmitter::SubRegSize::i32Bit, "Only 32-bit & 64-bit subregsize supported"); + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i64Bit || + size == ARMEmitter::SubRegSize::i32Bit, "Only 32-bit & 64-bit subregsize supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'10 << 10; ASIMD2RegMisc(Op, 1, size, 0b01111, rd, rn); } template - requires(std::is_same_v || std::is_same_v) - void frinti(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); + requires(std::is_same_v || std::is_same_v) + void frinti(ARMEmitter::SubRegSize size, T rd, T rn) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); } - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i64Bit || - size == FEXCore::ARMEmitter::SubRegSize::i32Bit, "Only 32-bit & 64-bit subregsize supported"); + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i64Bit || + size == ARMEmitter::SubRegSize::i32Bit, "Only 32-bit & 64-bit subregsize supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'10 << 10; ASIMD2RegMisc(Op, 1, size, 0b11001, rd, rn); } template - requires(std::is_same_v || std::is_same_v) - void fcvtpu(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); + requires(std::is_same_v || std::is_same_v) + void fcvtpu(ARMEmitter::SubRegSize size, T rd, T rn) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); } - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i64Bit || - size == FEXCore::ARMEmitter::SubRegSize::i32Bit, "Only 32-bit & 64-bit subregsize supported"); + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i64Bit || + size == ARMEmitter::SubRegSize::i32Bit, "Only 32-bit & 64-bit subregsize supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'10 << 10; ASIMD2RegMisc(Op, 1, size, 0b11010, rd, rn); } template - requires(std::is_same_v || std::is_same_v) - void fcvtzu(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); + requires(std::is_same_v || std::is_same_v) + void fcvtzu(ARMEmitter::SubRegSize size, T rd, T rn) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); } - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i64Bit || - size == FEXCore::ARMEmitter::SubRegSize::i32Bit, "Only 32-bit & 64-bit subregsize supported"); + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i64Bit || + size == ARMEmitter::SubRegSize::i32Bit, "Only 32-bit & 64-bit subregsize supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'10 << 10; ASIMD2RegMisc(Op, 1, size, 0b11011, rd, rn); } template - requires(std::is_same_v || std::is_same_v) - void ursqrte(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn) { - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i32Bit, "Only 32-bit & 64-bit subregsize supported"); + requires(std::is_same_v || std::is_same_v) + void ursqrte(ARMEmitter::SubRegSize size, T rd, T rn) { + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i32Bit, "Only 32-bit & 64-bit subregsize supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'10 << 10; ASIMD2RegMisc(Op, 1, size, 0b11100, rd, rn); } template - requires(std::is_same_v || std::is_same_v) - void frsqrte(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); + requires(std::is_same_v || std::is_same_v) + void frsqrte(ARMEmitter::SubRegSize size, T rd, T rn) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); } - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i64Bit || - size == FEXCore::ARMEmitter::SubRegSize::i32Bit, "Only 32-bit & 64-bit subregsize supported"); + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i64Bit || + size == ARMEmitter::SubRegSize::i32Bit, "Only 32-bit & 64-bit subregsize supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'10 << 10; ASIMD2RegMisc(Op, 1, size, 0b11101, rd, rn); } template - requires(std::is_same_v || std::is_same_v) - void fsqrt(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); + requires(std::is_same_v || std::is_same_v) + void fsqrt(ARMEmitter::SubRegSize size, T rd, T rn) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); } - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i64Bit || - size == FEXCore::ARMEmitter::SubRegSize::i32Bit, "Only 32-bit & 64-bit subregsize supported"); + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i64Bit || + size == ARMEmitter::SubRegSize::i32Bit, "Only 32-bit & 64-bit subregsize supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'10 << 10; ASIMD2RegMisc(Op, 1, size, 0b11111, rd, rn); } @@ -1742,12 +1742,12 @@ public: ///< size is the destination size. ///< source size is the next size up. template - requires(std::is_same_v || std::is_same_v) - void saddlv(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); + requires(std::is_same_v || std::is_same_v) + void saddlv(ARMEmitter::SubRegSize size, T rd, T rn) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); } - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i8Bit, "Destination 8-bit subregsize unsupported"); + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i8Bit, "Destination 8-bit subregsize unsupported"); constexpr uint32_t Op = 0b0000'1110'0011'0000'0000'10 << 10; const auto ConvertedSize = size == ARMEmitter::SubRegSize::i64Bit ? ARMEmitter::SubRegSize::i32Bit : @@ -1758,40 +1758,40 @@ public: } template - requires(std::is_same_v || std::is_same_v) - void smaxv(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i32Bit && size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "32/64-bit subregsize not supported"); + requires(std::is_same_v || std::is_same_v) + void smaxv(ARMEmitter::SubRegSize size, T rd, T rn) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i32Bit && size != ARMEmitter::SubRegSize::i64Bit, "32/64-bit subregsize not supported"); } - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "Destination 64-bit subregsize unsupported"); + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Destination 64-bit subregsize unsupported"); constexpr uint32_t Op = 0b0000'1110'0011'0000'0000'10 << 10; ASIMDAcrossLanes(Op, 0, size, 0b01010, rd, rn); } template - requires(std::is_same_v || std::is_same_v) - void sminv(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i32Bit && size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "32/64-bit subregsize not supported"); + requires(std::is_same_v || std::is_same_v) + void sminv(ARMEmitter::SubRegSize size, T rd, T rn) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i32Bit && size != ARMEmitter::SubRegSize::i64Bit, "32/64-bit subregsize not supported"); } - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "Destination 64-bit subregsize unsupported"); + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Destination 64-bit subregsize unsupported"); constexpr uint32_t Op = 0b0000'1110'0011'0000'0000'10 << 10; ASIMDAcrossLanes(Op, 0, size, 0b11010, rd, rn); } template - requires(std::is_same_v || std::is_same_v) - void addv(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i32Bit && size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "32/64-bit subregsize not supported"); + requires(std::is_same_v || std::is_same_v) + void addv(ARMEmitter::SubRegSize size, T rd, T rn) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i32Bit && size != ARMEmitter::SubRegSize::i64Bit, "32/64-bit subregsize not supported"); } - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "Destination 64-bit subregsize unsupported"); + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Destination 64-bit subregsize unsupported"); constexpr uint32_t Op = 0b0000'1110'0011'0000'0000'10 << 10; ASIMDAcrossLanes(Op, 0, size, 0b11011, rd, rn); } template - requires(std::is_same_v || std::is_same_v) - void uaddlv(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); + requires(std::is_same_v || std::is_same_v) + void uaddlv(ARMEmitter::SubRegSize size, T rd, T rn) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); } constexpr uint32_t Op = 0b0000'1110'0011'0000'0000'10 << 10; const auto ConvertedSize = @@ -1802,32 +1802,32 @@ public: ASIMDAcrossLanes(Op, 1, ConvertedSize, 0b00011, rd, rn); } template - requires(std::is_same_v || std::is_same_v) - void umaxv(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i32Bit && size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "32/64-bit subregsize not supported"); + requires(std::is_same_v || std::is_same_v) + void umaxv(ARMEmitter::SubRegSize size, T rd, T rn) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i32Bit && size != ARMEmitter::SubRegSize::i64Bit, "32/64-bit subregsize not supported"); } - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "Destination 64-bit subregsize unsupported"); + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Destination 64-bit subregsize unsupported"); constexpr uint32_t Op = 0b0000'1110'0011'0000'0000'10 << 10; ASIMDAcrossLanes(Op, 1, size, 0b01010, rd, rn); } template - requires(std::is_same_v || std::is_same_v) - void uminv(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i32Bit && size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "32/64-bit subregsize not supported"); + requires(std::is_same_v || std::is_same_v) + void uminv(ARMEmitter::SubRegSize size, T rd, T rn) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i32Bit && size != ARMEmitter::SubRegSize::i64Bit, "32/64-bit subregsize not supported"); } - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "Destination 64-bit subregsize unsupported"); + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Destination 64-bit subregsize unsupported"); constexpr uint32_t Op = 0b0000'1110'0011'0000'0000'10 << 10; ASIMDAcrossLanes(Op, 1, size, 0b11010, rd, rn); } template - requires(std::is_same_v || std::is_same_v) - void fmaxnmv(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i32Bit, "32-bit subregsize not supported"); + requires(std::is_same_v || std::is_same_v) + void fmaxnmv(ARMEmitter::SubRegSize size, T rd, T rn) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i32Bit, "32-bit subregsize not supported"); } - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i8Bit && size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "Destination 8/64-bit subregsize unsupported"); + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i8Bit && size != ARMEmitter::SubRegSize::i64Bit, "Destination 8/64-bit subregsize unsupported"); constexpr uint32_t Op = 0b0000'1110'0011'0000'0000'10 << 10; const auto ConvertedSize = size == ARMEmitter::SubRegSize::i64Bit ? ARMEmitter::SubRegSize::i16Bit : @@ -1839,12 +1839,12 @@ public: ASIMDAcrossLanes(Op, U, ConvertedSize, 0b01100, rd, rn); } template - requires(std::is_same_v || std::is_same_v) - void fmaxv(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i32Bit, "32-bit subregsize not supported"); + requires(std::is_same_v || std::is_same_v) + void fmaxv(ARMEmitter::SubRegSize size, T rd, T rn) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i32Bit, "32-bit subregsize not supported"); } - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i8Bit && size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "Destination 8/64-bit subregsize unsupported"); + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i8Bit && size != ARMEmitter::SubRegSize::i64Bit, "Destination 8/64-bit subregsize unsupported"); constexpr uint32_t Op = 0b0000'1110'0011'0000'0000'10 << 10; const auto ConvertedSize = size == ARMEmitter::SubRegSize::i64Bit ? ARMEmitter::SubRegSize::i16Bit : @@ -1856,12 +1856,12 @@ public: ASIMDAcrossLanes(Op, U, ConvertedSize, 0b01111, rd, rn); } template - requires(std::is_same_v || std::is_same_v) - void fminnmv(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i32Bit, "32-bit subregsize not supported"); + requires(std::is_same_v || std::is_same_v) + void fminnmv(ARMEmitter::SubRegSize size, T rd, T rn) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i32Bit, "32-bit subregsize not supported"); } - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i8Bit && size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "Destination 8/64-bit subregsize unsupported"); + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i8Bit && size != ARMEmitter::SubRegSize::i64Bit, "Destination 8/64-bit subregsize unsupported"); constexpr uint32_t Op = 0b0000'1110'0011'0000'0000'10 << 10; const auto ConvertedSize = size == ARMEmitter::SubRegSize::i64Bit ? ARMEmitter::SubRegSize::i64Bit : @@ -1873,12 +1873,12 @@ public: ASIMDAcrossLanes(Op, U, ConvertedSize, 0b01100, rd, rn); } template - requires(std::is_same_v || std::is_same_v) - void fminv(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i32Bit, "32-bit subregsize not supported"); + requires(std::is_same_v || std::is_same_v) + void fminv(ARMEmitter::SubRegSize size, T rd, T rn) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i32Bit, "32-bit subregsize not supported"); } - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i8Bit && size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "Destination 8/64-bit subregsize unsupported"); + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i8Bit && size != ARMEmitter::SubRegSize::i64Bit, "Destination 8/64-bit subregsize unsupported"); constexpr uint32_t Op = 0b0000'1110'0011'0000'0000'10 << 10; const auto ConvertedSize = size == ARMEmitter::SubRegSize::i64Bit ? ARMEmitter::SubRegSize::i64Bit : @@ -2312,178 +2312,178 @@ public: // Advanced SIMD three same template - void shadd(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, T rm) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); + void shadd(ARMEmitter::SubRegSize size, T rd, T rn, T rm) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10; ASIMD3Same(Op, 0, size, 0b00000, rd, rn, rm); } template - void sqadd(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, T rm) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit sqadd"); + void sqadd(ARMEmitter::SubRegSize size, T rd, T rn, T rm) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit sqadd"); } constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10; ASIMD3Same(Op, 0, size, 0b00001, rd, rn, rm); } template - void srhadd(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, T rm) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); + void srhadd(ARMEmitter::SubRegSize size, T rd, T rn, T rm) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10; ASIMD3Same(Op, 0, size, 0b00010, rd, rn, rm); } template - void shsub(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, T rm) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); + void shsub(ARMEmitter::SubRegSize size, T rd, T rn, T rm) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10; ASIMD3Same(Op, 0, size, 0b00100, rd, rn, rm); } template - void sqsub(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, T rm) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit sqsub"); + void sqsub(ARMEmitter::SubRegSize size, T rd, T rn, T rm) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit sqsub"); } constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10; ASIMD3Same(Op, 0, size, 0b00101, rd, rn, rm); } template - void cmgt(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, T rm) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit cmgt"); + void cmgt(ARMEmitter::SubRegSize size, T rd, T rn, T rm) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit cmgt"); } constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10; ASIMD3Same(Op, 0, size, 0b00110, rd, rn, rm); } template - void cmge(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, T rm) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit cmge"); + void cmge(ARMEmitter::SubRegSize size, T rd, T rn, T rm) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit cmge"); } constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10; ASIMD3Same(Op, 0, size, 0b00111, rd, rn, rm); } template - void sshl(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, T rm) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit sshl"); + void sshl(ARMEmitter::SubRegSize size, T rd, T rn, T rm) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit sshl"); } constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10; ASIMD3Same(Op, 0, size, 0b01000, rd, rn, rm); } template - void sqshl(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, T rm) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit sqshl"); + void sqshl(ARMEmitter::SubRegSize size, T rd, T rn, T rm) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit sqshl"); } constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10; ASIMD3Same(Op, 0, size, 0b01001, rd, rn, rm); } template - void srshl(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, T rm) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit srshl"); + void srshl(ARMEmitter::SubRegSize size, T rd, T rn, T rm) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit srshl"); } constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10; ASIMD3Same(Op, 0, size, 0b01010, rd, rn, rm); } template - void sqrshl(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, T rm) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit sqrshl"); + void sqrshl(ARMEmitter::SubRegSize size, T rd, T rn, T rm) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit sqrshl"); } constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10; ASIMD3Same(Op, 0, size, 0b01011, rd, rn, rm); } template - void smax(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, T rm) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); + void smax(ARMEmitter::SubRegSize size, T rd, T rn, T rm) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10; ASIMD3Same(Op, 0, size, 0b01100, rd, rn, rm); } template - void smin(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, T rm) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); + void smin(ARMEmitter::SubRegSize size, T rd, T rn, T rm) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10; ASIMD3Same(Op, 0, size, 0b01101, rd, rn, rm); } template - void sabd(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, T rm) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); + void sabd(ARMEmitter::SubRegSize size, T rd, T rn, T rm) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10; ASIMD3Same(Op, 0, size, 0b01110, rd, rn, rm); } template - void saba(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, T rm) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); + void saba(ARMEmitter::SubRegSize size, T rd, T rn, T rm) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10; ASIMD3Same(Op, 0, size, 0b01111, rd, rn, rm); } template - void add(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, T rm) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit add"); + void add(ARMEmitter::SubRegSize size, T rd, T rn, T rm) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit add"); } constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10; ASIMD3Same(Op, 0, size, 0b10000, rd, rn, rm); } template - void cmtst(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, T rm) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit cmtst"); + void cmtst(ARMEmitter::SubRegSize size, T rd, T rn, T rm) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit cmtst"); } constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10; ASIMD3Same(Op, 0, size, 0b10001, rd, rn, rm); } template - void mla(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, T rm) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); + void mla(ARMEmitter::SubRegSize size, T rd, T rn, T rm) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10; ASIMD3Same(Op, 0, size, 0b10010, rd, rn, rm); } template - void mul(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, T rm) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); + void mul(ARMEmitter::SubRegSize size, T rd, T rn, T rm) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10; ASIMD3Same(Op, 0, size, 0b10011, rd, rn, rm); } template - void smaxp(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, T rm) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); + void smaxp(ARMEmitter::SubRegSize size, T rd, T rn, T rm) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10; ASIMD3Same(Op, 0, size, 0b10100, rd, rn, rm); } template - void sminp(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, T rm) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); + void sminp(ARMEmitter::SubRegSize size, T rd, T rn, T rm) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10; ASIMD3Same(Op, 0, size, 0b10101, rd, rn, rm); } template - void sqdmulh(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, T rm) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i8Bit, "No 8-bit dest support."); - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); + void sqdmulh(ARMEmitter::SubRegSize size, T rd, T rn, T rm) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i8Bit, "No 8-bit dest support."); + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10; ASIMD3Same(Op, 0, size, 0b10110, rd, rn, rm); } template - void addp(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, T rm) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); + void addp(ARMEmitter::SubRegSize size, T rd, T rn, T rm) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); } constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10; ASIMD3Same(Op, 0, size, 0b10111, rd, rn, rm); } template - void fmaxnm(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, T rm) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); + void fmaxnm(ARMEmitter::SubRegSize size, T rd, T rn, T rm) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); } - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i64Bit || - size == FEXCore::ARMEmitter::SubRegSize::i32Bit, "Only 32-bit and 64-bit subregsize supported"); + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i64Bit || + size == ARMEmitter::SubRegSize::i32Bit, "Only 32-bit and 64-bit subregsize supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10; - const FEXCore::ARMEmitter::SubRegSize ConvertedSize = + const ARMEmitter::SubRegSize ConvertedSize = size == ARMEmitter::SubRegSize::i64Bit ? ARMEmitter::SubRegSize::i16Bit : ARMEmitter::SubRegSize::i8Bit; @@ -2491,15 +2491,15 @@ public: ASIMD3Same(Op, 0, ConvertedSize, 0b11000, rd, rn, rm); } template - void fmla(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, T rm) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); + void fmla(ARMEmitter::SubRegSize size, T rd, T rn, T rm) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); } - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i64Bit || - size == FEXCore::ARMEmitter::SubRegSize::i32Bit, "Only 32-bit and 64-bit subregsize supported"); + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i64Bit || + size == ARMEmitter::SubRegSize::i32Bit, "Only 32-bit and 64-bit subregsize supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10; - const FEXCore::ARMEmitter::SubRegSize ConvertedSize = + const ARMEmitter::SubRegSize ConvertedSize = size == ARMEmitter::SubRegSize::i64Bit ? ARMEmitter::SubRegSize::i16Bit : ARMEmitter::SubRegSize::i8Bit; @@ -2507,15 +2507,15 @@ public: ASIMD3Same(Op, 0, ConvertedSize, 0b11001, rd, rn, rm); } template - void fadd(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, T rm) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); + void fadd(ARMEmitter::SubRegSize size, T rd, T rn, T rm) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); } - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i64Bit || - size == FEXCore::ARMEmitter::SubRegSize::i32Bit, "Only 32-bit and 64-bit subregsize supported"); + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i64Bit || + size == ARMEmitter::SubRegSize::i32Bit, "Only 32-bit and 64-bit subregsize supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10; - const FEXCore::ARMEmitter::SubRegSize ConvertedSize = + const ARMEmitter::SubRegSize ConvertedSize = size == ARMEmitter::SubRegSize::i64Bit ? ARMEmitter::SubRegSize::i16Bit : ARMEmitter::SubRegSize::i8Bit; @@ -2523,15 +2523,15 @@ public: ASIMD3Same(Op, 0, ConvertedSize, 0b11010, rd, rn, rm); } template - void fmulx(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, T rm) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); + void fmulx(ARMEmitter::SubRegSize size, T rd, T rn, T rm) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); } - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i64Bit || - size == FEXCore::ARMEmitter::SubRegSize::i32Bit, "Only 32-bit and 64-bit subregsize supported"); + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i64Bit || + size == ARMEmitter::SubRegSize::i32Bit, "Only 32-bit and 64-bit subregsize supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10; - const FEXCore::ARMEmitter::SubRegSize ConvertedSize = + const ARMEmitter::SubRegSize ConvertedSize = size == ARMEmitter::SubRegSize::i64Bit ? ARMEmitter::SubRegSize::i16Bit : ARMEmitter::SubRegSize::i8Bit; @@ -2539,15 +2539,15 @@ public: ASIMD3Same(Op, 0, ConvertedSize, 0b11011, rd, rn, rm); } template - void fcmeq(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, T rm) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); + void fcmeq(ARMEmitter::SubRegSize size, T rd, T rn, T rm) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); } - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i64Bit || - size == FEXCore::ARMEmitter::SubRegSize::i32Bit, "Only 32-bit and 64-bit subregsize supported"); + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i64Bit || + size == ARMEmitter::SubRegSize::i32Bit, "Only 32-bit and 64-bit subregsize supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10; - const FEXCore::ARMEmitter::SubRegSize ConvertedSize = + const ARMEmitter::SubRegSize ConvertedSize = size == ARMEmitter::SubRegSize::i64Bit ? ARMEmitter::SubRegSize::i16Bit : ARMEmitter::SubRegSize::i8Bit; @@ -2555,15 +2555,15 @@ public: ASIMD3Same(Op, 0, ConvertedSize, 0b11100, rd, rn, rm); } template - void fmax(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, T rm) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); + void fmax(ARMEmitter::SubRegSize size, T rd, T rn, T rm) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); } - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i64Bit || - size == FEXCore::ARMEmitter::SubRegSize::i32Bit, "Only 32-bit and 64-bit subregsize supported"); + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i64Bit || + size == ARMEmitter::SubRegSize::i32Bit, "Only 32-bit and 64-bit subregsize supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10; - const FEXCore::ARMEmitter::SubRegSize ConvertedSize = + const ARMEmitter::SubRegSize ConvertedSize = size == ARMEmitter::SubRegSize::i64Bit ? ARMEmitter::SubRegSize::i16Bit : ARMEmitter::SubRegSize::i8Bit; @@ -2571,15 +2571,15 @@ public: ASIMD3Same(Op, 0, ConvertedSize, 0b11110, rd, rn, rm); } template - void frecps(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, T rm) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); + void frecps(ARMEmitter::SubRegSize size, T rd, T rn, T rm) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); } - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i64Bit || - size == FEXCore::ARMEmitter::SubRegSize::i32Bit, "Only 32-bit and 64-bit subregsize supported"); + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i64Bit || + size == ARMEmitter::SubRegSize::i32Bit, "Only 32-bit and 64-bit subregsize supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10; - const FEXCore::ARMEmitter::SubRegSize ConvertedSize = + const ARMEmitter::SubRegSize ConvertedSize = size == ARMEmitter::SubRegSize::i64Bit ? ARMEmitter::SubRegSize::i16Bit : ARMEmitter::SubRegSize::i8Bit; @@ -2607,56 +2607,56 @@ public: ASIMD3Same(Op, 0, ARMEmitter::SubRegSize::i16Bit, 0b00011, rd, rn, rm); } template - void fminnm(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, T rm) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); + void fminnm(ARMEmitter::SubRegSize size, T rd, T rn, T rm) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); } - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i64Bit || - size == FEXCore::ARMEmitter::SubRegSize::i32Bit, "Only 32-bit and 64-bit subregsize supported"); + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i64Bit || + size == ARMEmitter::SubRegSize::i32Bit, "Only 32-bit and 64-bit subregsize supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10; ASIMD3Same(Op, 0, size, 0b11000, rd, rn, rm); } template - void fmls(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, T rm) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); + void fmls(ARMEmitter::SubRegSize size, T rd, T rn, T rm) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); } - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i64Bit || - size == FEXCore::ARMEmitter::SubRegSize::i32Bit, "Only 32-bit and 64-bit subregsize supported"); + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i64Bit || + size == ARMEmitter::SubRegSize::i32Bit, "Only 32-bit and 64-bit subregsize supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10; ASIMD3Same(Op, 0, size, 0b11001, rd, rn, rm); } template - void fsub(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, T rm) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); + void fsub(ARMEmitter::SubRegSize size, T rd, T rn, T rm) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); } - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i64Bit || - size == FEXCore::ARMEmitter::SubRegSize::i32Bit, "Only 32-bit and 64-bit subregsize supported"); + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i64Bit || + size == ARMEmitter::SubRegSize::i32Bit, "Only 32-bit and 64-bit subregsize supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10; ASIMD3Same(Op, 0, size, 0b11010, rd, rn, rm); } template - void fmin(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, T rm) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); + void fmin(ARMEmitter::SubRegSize size, T rd, T rn, T rm) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); } - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i64Bit || - size == FEXCore::ARMEmitter::SubRegSize::i32Bit, "Only 32-bit and 64-bit subregsize supported"); + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i64Bit || + size == ARMEmitter::SubRegSize::i32Bit, "Only 32-bit and 64-bit subregsize supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10; ASIMD3Same(Op, 0, size, 0b11110, rd, rn, rm); } template - void frsqrts(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, T rm) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); + void frsqrts(ARMEmitter::SubRegSize size, T rd, T rn, T rm) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); } - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i64Bit || - size == FEXCore::ARMEmitter::SubRegSize::i32Bit, "Only 32-bit and 64-bit subregsize supported"); + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i64Bit || + size == ARMEmitter::SubRegSize::i32Bit, "Only 32-bit and 64-bit subregsize supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10; ASIMD3Same(Op, 0, size, 0b11111, rd, rn, rm); @@ -2686,122 +2686,122 @@ public: ASIMD3Same(Op, 0, ARMEmitter::SubRegSize::i64Bit, 0b00011, rd, rn, rm); } template - void uhadd(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, T rm) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); + void uhadd(ARMEmitter::SubRegSize size, T rd, T rn, T rm) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10; ASIMD3Same(Op, 1, size, 0b00000, rd, rn, rm); } template - void uqadd(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, T rm) { + void uqadd(ARMEmitter::SubRegSize size, T rd, T rn, T rm) { constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10; ASIMD3Same(Op, 1, size, 0b00001, rd, rn, rm); } template - void urhadd(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, T rm) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); + void urhadd(ARMEmitter::SubRegSize size, T rd, T rn, T rm) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10; ASIMD3Same(Op, 1, size, 0b00010, rd, rn, rm); } template - void uhsub(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, T rm) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); + void uhsub(ARMEmitter::SubRegSize size, T rd, T rn, T rm) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10; ASIMD3Same(Op, 1, size, 0b00100, rd, rn, rm); } template - void uqsub(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, T rm) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); + void uqsub(ARMEmitter::SubRegSize size, T rd, T rn, T rm) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10; ASIMD3Same(Op, 1, size, 0b00101, rd, rn, rm); } template - void cmhi(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, T rm) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); + void cmhi(ARMEmitter::SubRegSize size, T rd, T rn, T rm) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); } constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10; ASIMD3Same(Op, 1, size, 0b00110, rd, rn, rm); } template - void cmhs(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, T rm) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); + void cmhs(ARMEmitter::SubRegSize size, T rd, T rn, T rm) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); } constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10; ASIMD3Same(Op, 1, size, 0b00111, rd, rn, rm); } template - void ushl(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, T rm) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); + void ushl(ARMEmitter::SubRegSize size, T rd, T rn, T rm) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); } constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10; ASIMD3Same(Op, 1, size, 0b01000, rd, rn, rm); } template - void uqshl(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, T rm) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); + void uqshl(ARMEmitter::SubRegSize size, T rd, T rn, T rm) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10; ASIMD3Same(Op, 1, size, 0b01001, rd, rn, rm); } template - void urshl(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, T rm) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); + void urshl(ARMEmitter::SubRegSize size, T rd, T rn, T rm) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); } constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10; ASIMD3Same(Op, 1, size, 0b01010, rd, rn, rm); } template - void uqrshl(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, T rm) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); + void uqrshl(ARMEmitter::SubRegSize size, T rd, T rn, T rm) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10; ASIMD3Same(Op, 1, size, 0b01011, rd, rn, rm); } template - void umax(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, T rm) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); + void umax(ARMEmitter::SubRegSize size, T rd, T rn, T rm) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10; ASIMD3Same(Op, 1, size, 0b01100, rd, rn, rm); } template - void umin(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, T rm) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); + void umin(ARMEmitter::SubRegSize size, T rd, T rn, T rm) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10; ASIMD3Same(Op, 1, size, 0b01101, rd, rn, rm); } template - void uabd(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, T rm) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); + void uabd(ARMEmitter::SubRegSize size, T rd, T rn, T rm) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10; ASIMD3Same(Op, 1, size, 0b01110, rd, rn, rm); } template - void uaba(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, T rm) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); + void uaba(ARMEmitter::SubRegSize size, T rd, T rn, T rm) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10; ASIMD3Same(Op, 1, size, 0b01111, rd, rn, rm); } template - void sub(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, T rm) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); + void sub(ARMEmitter::SubRegSize size, T rd, T rn, T rm) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); } constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10; ASIMD3Same(Op, 1, size, 0b10000, rd, rn, rm); } template - void cmeq(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, T rm) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); + void cmeq(ARMEmitter::SubRegSize size, T rd, T rn, T rm) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); } constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10; ASIMD3Same(Op, 1, size, 0b10001, rd, rn, rm); } template - void mls(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, T rm) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); + void mls(ARMEmitter::SubRegSize size, T rd, T rn, T rm) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10; ASIMD3Same(Op, 1, size, 0b10010, rd, rn, rm); } @@ -2811,33 +2811,33 @@ public: ASIMD3Same(Op, 1, ARMEmitter::SubRegSize::i8Bit, 0b10011, rd, rn, rm); } template - void umaxp(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, T rm) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); + void umaxp(ARMEmitter::SubRegSize size, T rd, T rn, T rm) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10; ASIMD3Same(Op, 1, size, 0b10100, rd, rn, rm); } template - void uminp(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, T rm) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); + void uminp(ARMEmitter::SubRegSize size, T rd, T rn, T rm) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10; ASIMD3Same(Op, 1, size, 0b10101, rd, rn, rm); } template - void sqrdmulh(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, T rm) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit && size != FEXCore::ARMEmitter::SubRegSize::i8Bit, "8/64-bit subregsize not supported"); + void sqrdmulh(ARMEmitter::SubRegSize size, T rd, T rn, T rm) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit && size != ARMEmitter::SubRegSize::i8Bit, "8/64-bit subregsize not supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10; ASIMD3Same(Op, 1, size, 0b10110, rd, rn, rm); } template - void fmaxnmp(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, T rm) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); + void fmaxnmp(ARMEmitter::SubRegSize size, T rd, T rn, T rm) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); } - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i64Bit || - size == FEXCore::ARMEmitter::SubRegSize::i32Bit, "Only 32-bit and 64-bit subregsize supported"); + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i64Bit || + size == ARMEmitter::SubRegSize::i32Bit, "Only 32-bit and 64-bit subregsize supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10; - const FEXCore::ARMEmitter::SubRegSize ConvertedSize = + const ARMEmitter::SubRegSize ConvertedSize = size == ARMEmitter::SubRegSize::i64Bit ? ARMEmitter::SubRegSize::i16Bit : ARMEmitter::SubRegSize::i8Bit; @@ -2845,15 +2845,15 @@ public: ASIMD3Same(Op, 1, ConvertedSize, 0b11000, rd, rn, rm); } template - void faddp(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, T rm) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); + void faddp(ARMEmitter::SubRegSize size, T rd, T rn, T rm) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); } - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i64Bit || - size == FEXCore::ARMEmitter::SubRegSize::i32Bit, "Only 32-bit and 64-bit subregsize supported"); + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i64Bit || + size == ARMEmitter::SubRegSize::i32Bit, "Only 32-bit and 64-bit subregsize supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10; - const FEXCore::ARMEmitter::SubRegSize ConvertedSize = + const ARMEmitter::SubRegSize ConvertedSize = size == ARMEmitter::SubRegSize::i64Bit ? ARMEmitter::SubRegSize::i16Bit : ARMEmitter::SubRegSize::i8Bit; @@ -2861,15 +2861,15 @@ public: ASIMD3Same(Op, 1, ConvertedSize, 0b11010, rd, rn, rm); } template - void fmul(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, T rm) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); + void fmul(ARMEmitter::SubRegSize size, T rd, T rn, T rm) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); } - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i64Bit || - size == FEXCore::ARMEmitter::SubRegSize::i32Bit, "Only 32-bit and 64-bit subregsize supported"); + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i64Bit || + size == ARMEmitter::SubRegSize::i32Bit, "Only 32-bit and 64-bit subregsize supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10; - const FEXCore::ARMEmitter::SubRegSize ConvertedSize = + const ARMEmitter::SubRegSize ConvertedSize = size == ARMEmitter::SubRegSize::i64Bit ? ARMEmitter::SubRegSize::i16Bit : ARMEmitter::SubRegSize::i8Bit; @@ -2877,15 +2877,15 @@ public: ASIMD3Same(Op, 1, ConvertedSize, 0b11011, rd, rn, rm); } template - void fcmge(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, T rm) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); + void fcmge(ARMEmitter::SubRegSize size, T rd, T rn, T rm) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); } - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i64Bit || - size == FEXCore::ARMEmitter::SubRegSize::i32Bit, "Only 32-bit and 64-bit subregsize supported"); + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i64Bit || + size == ARMEmitter::SubRegSize::i32Bit, "Only 32-bit and 64-bit subregsize supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10; - const FEXCore::ARMEmitter::SubRegSize ConvertedSize = + const ARMEmitter::SubRegSize ConvertedSize = size == ARMEmitter::SubRegSize::i64Bit ? ARMEmitter::SubRegSize::i16Bit : ARMEmitter::SubRegSize::i8Bit; @@ -2893,15 +2893,15 @@ public: ASIMD3Same(Op, 1, ConvertedSize, 0b11100, rd, rn, rm); } template - void facge(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, T rm) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); + void facge(ARMEmitter::SubRegSize size, T rd, T rn, T rm) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); } - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i64Bit || - size == FEXCore::ARMEmitter::SubRegSize::i32Bit, "Only 32-bit and 64-bit subregsize supported"); + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i64Bit || + size == ARMEmitter::SubRegSize::i32Bit, "Only 32-bit and 64-bit subregsize supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10; - const FEXCore::ARMEmitter::SubRegSize ConvertedSize = + const ARMEmitter::SubRegSize ConvertedSize = size == ARMEmitter::SubRegSize::i64Bit ? ARMEmitter::SubRegSize::i16Bit : ARMEmitter::SubRegSize::i8Bit; @@ -2909,15 +2909,15 @@ public: ASIMD3Same(Op, 1, ConvertedSize, 0b11101, rd, rn, rm); } template - void fmaxp(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, T rm) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); + void fmaxp(ARMEmitter::SubRegSize size, T rd, T rn, T rm) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); } - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i64Bit || - size == FEXCore::ARMEmitter::SubRegSize::i32Bit, "Only 32-bit and 64-bit subregsize supported"); + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i64Bit || + size == ARMEmitter::SubRegSize::i32Bit, "Only 32-bit and 64-bit subregsize supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10; - const FEXCore::ARMEmitter::SubRegSize ConvertedSize = + const ARMEmitter::SubRegSize ConvertedSize = size == ARMEmitter::SubRegSize::i64Bit ? ARMEmitter::SubRegSize::i16Bit : ARMEmitter::SubRegSize::i8Bit; @@ -2925,15 +2925,15 @@ public: ASIMD3Same(Op, 1, ConvertedSize, 0b11110, rd, rn, rm); } template - void fdiv(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, T rm) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); + void fdiv(ARMEmitter::SubRegSize size, T rd, T rn, T rm) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); } - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i64Bit || - size == FEXCore::ARMEmitter::SubRegSize::i32Bit, "Only 32-bit and 64-bit subregsize supported"); + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i64Bit || + size == ARMEmitter::SubRegSize::i32Bit, "Only 32-bit and 64-bit subregsize supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10; - const FEXCore::ARMEmitter::SubRegSize ConvertedSize = + const ARMEmitter::SubRegSize ConvertedSize = size == ARMEmitter::SubRegSize::i64Bit ? ARMEmitter::SubRegSize::i16Bit : ARMEmitter::SubRegSize::i8Bit; @@ -2951,56 +2951,56 @@ public: ASIMD3Same(Op, 1, ARMEmitter::SubRegSize::i16Bit, 0b00011, rd, rn, rm); } template - void fminnmp(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, T rm) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); + void fminnmp(ARMEmitter::SubRegSize size, T rd, T rn, T rm) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); } - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i64Bit || - size == FEXCore::ARMEmitter::SubRegSize::i32Bit, "Only 32-bit and 64-bit subregsize supported"); + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i64Bit || + size == ARMEmitter::SubRegSize::i32Bit, "Only 32-bit and 64-bit subregsize supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10; ASIMD3Same(Op, 1, size, 0b11000, rd, rn, rm); } template - void fabd(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, T rm) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); + void fabd(ARMEmitter::SubRegSize size, T rd, T rn, T rm) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); } - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i64Bit || - size == FEXCore::ARMEmitter::SubRegSize::i32Bit, "Only 32-bit and 64-bit subregsize supported"); + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i64Bit || + size == ARMEmitter::SubRegSize::i32Bit, "Only 32-bit and 64-bit subregsize supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10; ASIMD3Same(Op, 1, size, 0b11010, rd, rn, rm); } template - void fcmgt(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, T rm) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); + void fcmgt(ARMEmitter::SubRegSize size, T rd, T rn, T rm) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); } - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i64Bit || - size == FEXCore::ARMEmitter::SubRegSize::i32Bit, "Only 32-bit and 64-bit subregsize supported"); + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i64Bit || + size == ARMEmitter::SubRegSize::i32Bit, "Only 32-bit and 64-bit subregsize supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10; ASIMD3Same(Op, 1, size, 0b11100, rd, rn, rm); } template - void facgt(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, T rm) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); + void facgt(ARMEmitter::SubRegSize size, T rd, T rn, T rm) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); } - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i64Bit || - size == FEXCore::ARMEmitter::SubRegSize::i32Bit, "Only 32-bit and 64-bit subregsize supported"); + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i64Bit || + size == ARMEmitter::SubRegSize::i32Bit, "Only 32-bit and 64-bit subregsize supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10; ASIMD3Same(Op, 1, size, 0b11101, rd, rn, rm); } template - void fminp(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, T rm) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); + void fminp(ARMEmitter::SubRegSize size, T rd, T rn, T rm) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); } - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i64Bit || - size == FEXCore::ARMEmitter::SubRegSize::i32Bit, "Only 32-bit and 64-bit subregsize supported"); + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i64Bit || + size == ARMEmitter::SubRegSize::i32Bit, "Only 32-bit and 64-bit subregsize supported"); constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'01 << 10; ASIMD3Same(Op, 1, size, 0b11110, rd, rn, rm); @@ -3020,13 +3020,13 @@ public: // XXX: ORR - 32-bit/16-bit // XXX: MOVI - Shifting ones template - void fmov(FEXCore::ARMEmitter::SubRegSize size, T rd, float Value) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); + void fmov(ARMEmitter::SubRegSize size, T rd, float Value) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); } - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i16Bit || - size == FEXCore::ARMEmitter::SubRegSize::i32Bit || - size == FEXCore::ARMEmitter::SubRegSize::i64Bit, "Unsupported fmov size"); + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i16Bit || + size == ARMEmitter::SubRegSize::i32Bit || + size == ARMEmitter::SubRegSize::i64Bit, "Unsupported fmov size"); constexpr uint32_t Op = 0b0000'1111'0000'0000'0000'01 << 10; uint32_t op; @@ -3060,11 +3060,11 @@ public: //void ASIMDModifiedImm(uint32_t Op, uint32_t op, uint32_t cmode, uint32_t o2, uint32_t imm, T rd) { template - void movi(FEXCore::ARMEmitter::SubRegSize size, T rd, uint64_t Imm, uint16_t Shift = 0) { - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i8Bit || - size == FEXCore::ARMEmitter::SubRegSize::i16Bit || - size == FEXCore::ARMEmitter::SubRegSize::i32Bit || - size == FEXCore::ARMEmitter::SubRegSize::i64Bit, "Unsupported smov size"); + void movi(ARMEmitter::SubRegSize size, T rd, uint64_t Imm, uint16_t Shift = 0) { + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i8Bit || + size == ARMEmitter::SubRegSize::i16Bit || + size == ARMEmitter::SubRegSize::i32Bit || + size == ARMEmitter::SubRegSize::i64Bit, "Unsupported smov size"); constexpr uint32_t Op = 0b0000'1111'0000'0000'0000'01 << 10; uint32_t cmode; @@ -3116,9 +3116,9 @@ public: // Advanced SIMD shift by immediate template - void sshr(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, uint32_t Shift) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); + void sshr(ARMEmitter::SubRegSize size, T rd, T rn, uint32_t Shift) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); } constexpr uint32_t Op = 0b0000'1111'0000'0000'0000'01 << 10; const size_t SubregSizeInBits = SubRegSizeInBits(size); @@ -3132,9 +3132,9 @@ public: ASIMDShiftByImm(Op, 0, immh, immb, 0b00000, rn, rd); } template - void ssra(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, uint32_t Shift) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); + void ssra(ARMEmitter::SubRegSize size, T rd, T rn, uint32_t Shift) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); } constexpr uint32_t Op = 0b0000'1111'0000'0000'0000'01 << 10; const size_t SubregSizeInBits = SubRegSizeInBits(size); @@ -3148,9 +3148,9 @@ public: ASIMDShiftByImm(Op, 0, immh, immb, 0b00010, rn, rd); } template - void srshr(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, uint32_t Shift) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); + void srshr(ARMEmitter::SubRegSize size, T rd, T rn, uint32_t Shift) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); } constexpr uint32_t Op = 0b0000'1111'0000'0000'0000'01 << 10; const size_t SubregSizeInBits = SubRegSizeInBits(size); @@ -3164,9 +3164,9 @@ public: ASIMDShiftByImm(Op, 0, immh, immb, 0b00100, rn, rd); } template - void srsra(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, uint32_t Shift) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); + void srsra(ARMEmitter::SubRegSize size, T rd, T rn, uint32_t Shift) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); } constexpr uint32_t Op = 0b0000'1111'0000'0000'0000'01 << 10; const size_t SubregSizeInBits = SubRegSizeInBits(size); @@ -3180,9 +3180,9 @@ public: ASIMDShiftByImm(Op, 0, immh, immb, 0b00110, rn, rd); } template - void shl(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, uint32_t Shift) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); + void shl(ARMEmitter::SubRegSize size, T rd, T rn, uint32_t Shift) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); } constexpr uint32_t Op = 0b0000'1111'0000'0000'0000'01 << 10; const size_t SubregSizeInBits = SubRegSizeInBits(size); @@ -3196,9 +3196,9 @@ public: ASIMDShiftByImm(Op, 0, immh, immb, 0b01010, rn, rd); } template - void sqshl(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, uint32_t Shift) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); + void sqshl(ARMEmitter::SubRegSize size, T rd, T rn, uint32_t Shift) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); } constexpr uint32_t Op = 0b0000'1111'0000'0000'0000'01 << 10; const size_t SubregSizeInBits = SubRegSizeInBits(size); @@ -3212,8 +3212,8 @@ public: ASIMDShiftByImm(Op, 0, immh, immb, 0b01110, rn, rd); } ///< size is destination size - void shrn(FEXCore::ARMEmitter::SubRegSize size, FEXCore::ARMEmitter::DRegister rd, FEXCore::ARMEmitter::DRegister rn, uint32_t Shift) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); + void shrn(ARMEmitter::SubRegSize size, ARMEmitter::DRegister rd, ARMEmitter::DRegister rn, uint32_t Shift) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); constexpr uint32_t Op = 0b0000'1111'0000'0000'0000'01 << 10; const size_t SubregSizeInBits = SubRegSizeInBits(size); @@ -3226,8 +3226,8 @@ public: ASIMDShiftByImm(Op, 0, immh, immb, 0b10000, rn, rd); } ///< size is destination size - void shrn2(FEXCore::ARMEmitter::SubRegSize size, FEXCore::ARMEmitter::QRegister rd, FEXCore::ARMEmitter::QRegister rn, uint32_t Shift) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); + void shrn2(ARMEmitter::SubRegSize size, ARMEmitter::QRegister rd, ARMEmitter::QRegister rn, uint32_t Shift) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); constexpr uint32_t Op = 0b0000'1111'0000'0000'0000'01 << 10; const size_t SubregSizeInBits = SubRegSizeInBits(size); @@ -3240,8 +3240,8 @@ public: ASIMDShiftByImm(Op, 0, immh, immb, 0b10000, rn, rd); } ///< size is destination size - void rshrn(FEXCore::ARMEmitter::SubRegSize size, FEXCore::ARMEmitter::DRegister rd, FEXCore::ARMEmitter::DRegister rn, uint32_t Shift) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); + void rshrn(ARMEmitter::SubRegSize size, ARMEmitter::DRegister rd, ARMEmitter::DRegister rn, uint32_t Shift) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); constexpr uint32_t Op = 0b0000'1111'0000'0000'0000'01 << 10; const size_t SubregSizeInBits = SubRegSizeInBits(size); @@ -3254,8 +3254,8 @@ public: ASIMDShiftByImm(Op, 0, immh, immb, 0b10001, rn, rd); } ///< size is destination size - void rshrn2(FEXCore::ARMEmitter::SubRegSize size, FEXCore::ARMEmitter::QRegister rd, FEXCore::ARMEmitter::QRegister rn, uint32_t Shift) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); + void rshrn2(ARMEmitter::SubRegSize size, ARMEmitter::QRegister rd, ARMEmitter::QRegister rn, uint32_t Shift) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); constexpr uint32_t Op = 0b0000'1111'0000'0000'0000'01 << 10; const size_t SubregSizeInBits = SubRegSizeInBits(size); @@ -3268,8 +3268,8 @@ public: ASIMDShiftByImm(Op, 0, immh, immb, 0b10001, rn, rd); } ///< size is destination size - void sqshrn(FEXCore::ARMEmitter::SubRegSize size, FEXCore::ARMEmitter::DRegister rd, FEXCore::ARMEmitter::DRegister rn, uint32_t Shift) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); + void sqshrn(ARMEmitter::SubRegSize size, ARMEmitter::DRegister rd, ARMEmitter::DRegister rn, uint32_t Shift) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); constexpr uint32_t Op = 0b0000'1111'0000'0000'0000'01 << 10; const size_t SubregSizeInBits = SubRegSizeInBits(size); @@ -3282,8 +3282,8 @@ public: ASIMDShiftByImm(Op, 0, immh, immb, 0b10010, rn, rd); } ///< size is destination size - void sqshrn2(FEXCore::ARMEmitter::SubRegSize size, FEXCore::ARMEmitter::QRegister rd, FEXCore::ARMEmitter::QRegister rn, uint32_t Shift) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); + void sqshrn2(ARMEmitter::SubRegSize size, ARMEmitter::QRegister rd, ARMEmitter::QRegister rn, uint32_t Shift) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); constexpr uint32_t Op = 0b0000'1111'0000'0000'0000'01 << 10; const size_t SubregSizeInBits = SubRegSizeInBits(size); @@ -3296,8 +3296,8 @@ public: ASIMDShiftByImm(Op, 0, immh, immb, 0b10010, rn, rd); } ///< size is destination size - void sqrshrn(FEXCore::ARMEmitter::SubRegSize size, FEXCore::ARMEmitter::DRegister rd, FEXCore::ARMEmitter::DRegister rn, uint32_t Shift) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); + void sqrshrn(ARMEmitter::SubRegSize size, ARMEmitter::DRegister rd, ARMEmitter::DRegister rn, uint32_t Shift) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); constexpr uint32_t Op = 0b0000'1111'0000'0000'0000'01 << 10; const size_t SubregSizeInBits = SubRegSizeInBits(size); @@ -3310,8 +3310,8 @@ public: ASIMDShiftByImm(Op, 0, immh, immb, 0b10011, rn, rd); } ///< size is destination size - void sqrshrn2(FEXCore::ARMEmitter::SubRegSize size, FEXCore::ARMEmitter::QRegister rd, FEXCore::ARMEmitter::QRegister rn, uint32_t Shift) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); + void sqrshrn2(ARMEmitter::SubRegSize size, ARMEmitter::QRegister rd, ARMEmitter::QRegister rn, uint32_t Shift) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); constexpr uint32_t Op = 0b0000'1111'0000'0000'0000'01 << 10; const size_t SubregSizeInBits = SubRegSizeInBits(size); @@ -3324,9 +3324,9 @@ public: ASIMDShiftByImm(Op, 0, immh, immb, 0b10011, rn, rd); } ///< size is destination size - void sshll(FEXCore::ARMEmitter::SubRegSize size, FEXCore::ARMEmitter::DRegister rd, FEXCore::ARMEmitter::DRegister rn, uint32_t Shift) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i8Bit, "Invalid size"); - size = FEXCore::ARMEmitter::SubRegSize(FEXCore::ToUnderlying(size) - 1); + void sshll(ARMEmitter::SubRegSize size, ARMEmitter::DRegister rd, ARMEmitter::DRegister rn, uint32_t Shift) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i8Bit, "Invalid size"); + size = ARMEmitter::SubRegSize(FEXCore::ToUnderlying(size) - 1); constexpr uint32_t Op = 0b0000'1111'0000'0000'0000'01 << 10; const size_t SubregSizeInBits = SubRegSizeInBits(size); @@ -3342,9 +3342,9 @@ public: } ///< size is destination size - void sshll2(FEXCore::ARMEmitter::SubRegSize size, FEXCore::ARMEmitter::QRegister rd, FEXCore::ARMEmitter::QRegister rn, uint32_t Shift) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i8Bit, "Invalid size"); - size = FEXCore::ARMEmitter::SubRegSize(FEXCore::ToUnderlying(size) - 1); + void sshll2(ARMEmitter::SubRegSize size, ARMEmitter::QRegister rd, ARMEmitter::QRegister rn, uint32_t Shift) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i8Bit, "Invalid size"); + size = ARMEmitter::SubRegSize(FEXCore::ToUnderlying(size) - 1); constexpr uint32_t Op = 0b0000'1111'0000'0000'0000'01 << 10; const size_t SubregSizeInBits = SubRegSizeInBits(size); @@ -3359,19 +3359,19 @@ public: ASIMDShiftByImm(Op, 0, immh, immb, 0b10100, rn, rd); } ///< size is destination size - void sxtl(FEXCore::ARMEmitter::SubRegSize size, FEXCore::ARMEmitter::VRegister rd, FEXCore::ARMEmitter::VRegister rn) { + void sxtl(ARMEmitter::SubRegSize size, ARMEmitter::VRegister rd, ARMEmitter::VRegister rn) { sshll(size, rd.D(), rn.D(), 0); } ///< size is destination size - void sxtl2(FEXCore::ARMEmitter::SubRegSize size, FEXCore::ARMEmitter::VRegister rd, FEXCore::ARMEmitter::VRegister rn) { + void sxtl2(ARMEmitter::SubRegSize size, ARMEmitter::VRegister rd, ARMEmitter::VRegister rn) { sshll2(size, rd.Q(), rn.Q(), 0); } template - void scvtf(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, uint32_t FractionalBits) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i8Bit, "Invalid size"); - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); + void scvtf(ARMEmitter::SubRegSize size, T rd, T rn, uint32_t FractionalBits) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i8Bit, "Invalid size"); + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); } constexpr uint32_t Op = 0b0000'1111'0000'0000'0000'01 << 10; @@ -3388,10 +3388,10 @@ public: } template - void fcvtzs(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, uint32_t FractionalBits) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i8Bit, "Invalid size"); - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); + void fcvtzs(ARMEmitter::SubRegSize size, T rd, T rn, uint32_t FractionalBits) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i8Bit, "Invalid size"); + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); } constexpr uint32_t Op = 0b0000'1111'0000'0000'0000'01 << 10; @@ -3408,9 +3408,9 @@ public: } template - void ushr(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, uint32_t Shift) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); + void ushr(ARMEmitter::SubRegSize size, T rd, T rn, uint32_t Shift) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); } constexpr uint32_t Op = 0b0000'1111'0000'0000'0000'01 << 10; const size_t SubregSizeInBits = SubRegSizeInBits(size); @@ -3424,9 +3424,9 @@ public: ASIMDShiftByImm(Op, 1, immh, immb, 0b00000, rn, rd); } template - void usra(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, uint32_t Shift) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); + void usra(ARMEmitter::SubRegSize size, T rd, T rn, uint32_t Shift) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); } constexpr uint32_t Op = 0b0000'1111'0000'0000'0000'01 << 10; const size_t SubregSizeInBits = SubRegSizeInBits(size); @@ -3440,9 +3440,9 @@ public: ASIMDShiftByImm(Op, 1, immh, immb, 0b00010, rn, rd); } template - void urshr(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, uint32_t Shift) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); + void urshr(ARMEmitter::SubRegSize size, T rd, T rn, uint32_t Shift) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); } constexpr uint32_t Op = 0b0000'1111'0000'0000'0000'01 << 10; const size_t SubregSizeInBits = SubRegSizeInBits(size); @@ -3456,9 +3456,9 @@ public: ASIMDShiftByImm(Op, 1, immh, immb, 0b00100, rn, rd); } template - void ursra(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, uint32_t Shift) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); + void ursra(ARMEmitter::SubRegSize size, T rd, T rn, uint32_t Shift) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); } constexpr uint32_t Op = 0b0000'1111'0000'0000'0000'01 << 10; const size_t SubregSizeInBits = SubRegSizeInBits(size); @@ -3472,9 +3472,9 @@ public: ASIMDShiftByImm(Op, 1, immh, immb, 0b00110, rn, rd); } template - void sri(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, uint32_t Shift) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); + void sri(ARMEmitter::SubRegSize size, T rd, T rn, uint32_t Shift) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); } constexpr uint32_t Op = 0b0000'1111'0000'0000'0000'01 << 10; const size_t SubregSizeInBits = SubRegSizeInBits(size); @@ -3488,9 +3488,9 @@ public: ASIMDShiftByImm(Op, 1, immh, immb, 0b01000, rn, rd); } template - void sli(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, uint32_t Shift) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); + void sli(ARMEmitter::SubRegSize size, T rd, T rn, uint32_t Shift) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); } constexpr uint32_t Op = 0b0000'1111'0000'0000'0000'01 << 10; const size_t SubregSizeInBits = SubRegSizeInBits(size); @@ -3504,9 +3504,9 @@ public: ASIMDShiftByImm(Op, 1, immh, immb, 0b01010, rn, rd); } template - void sqshlu(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, uint32_t Shift) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); + void sqshlu(ARMEmitter::SubRegSize size, T rd, T rn, uint32_t Shift) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); } constexpr uint32_t Op = 0b0000'1111'0000'0000'0000'01 << 10; const size_t SubregSizeInBits = SubRegSizeInBits(size); @@ -3521,9 +3521,9 @@ public: } ///< size is destination size template - void uqshl(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, uint32_t Shift) { - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); + void uqshl(ARMEmitter::SubRegSize size, T rd, T rn, uint32_t Shift) { + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); } constexpr uint32_t Op = 0b0000'1111'0000'0000'0000'01 << 10; const size_t SubregSizeInBits = SubRegSizeInBits(size); @@ -3537,8 +3537,8 @@ public: ASIMDShiftByImm(Op, 1, immh, immb, 0b01110, rn, rd); } ///< size is destination size - void sqshrun(FEXCore::ARMEmitter::SubRegSize size, FEXCore::ARMEmitter::DRegister rd, FEXCore::ARMEmitter::DRegister rn, uint32_t Shift) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); + void sqshrun(ARMEmitter::SubRegSize size, ARMEmitter::DRegister rd, ARMEmitter::DRegister rn, uint32_t Shift) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); constexpr uint32_t Op = 0b0000'1111'0000'0000'0000'01 << 10; const size_t SubregSizeInBits = SubRegSizeInBits(size); @@ -3551,8 +3551,8 @@ public: ASIMDShiftByImm(Op, 1, immh, immb, 0b10000, rn, rd); } ///< size is destination size - void sqshrun2(FEXCore::ARMEmitter::SubRegSize size, FEXCore::ARMEmitter::QRegister rd, FEXCore::ARMEmitter::QRegister rn, uint32_t Shift) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); + void sqshrun2(ARMEmitter::SubRegSize size, ARMEmitter::QRegister rd, ARMEmitter::QRegister rn, uint32_t Shift) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); constexpr uint32_t Op = 0b0000'1111'0000'0000'0000'01 << 10; const size_t SubregSizeInBits = SubRegSizeInBits(size); @@ -3565,8 +3565,8 @@ public: ASIMDShiftByImm(Op, 1, immh, immb, 0b10000, rn, rd); } ///< size is destination size - void sqrshrun(FEXCore::ARMEmitter::SubRegSize size, FEXCore::ARMEmitter::DRegister rd, FEXCore::ARMEmitter::DRegister rn, uint32_t Shift) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); + void sqrshrun(ARMEmitter::SubRegSize size, ARMEmitter::DRegister rd, ARMEmitter::DRegister rn, uint32_t Shift) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); constexpr uint32_t Op = 0b0000'1111'0000'0000'0000'01 << 10; const size_t SubregSizeInBits = SubRegSizeInBits(size); @@ -3579,8 +3579,8 @@ public: ASIMDShiftByImm(Op, 1, immh, immb, 0b10001, rn, rd); } ///< size is destination size - void sqrshrun2(FEXCore::ARMEmitter::SubRegSize size, FEXCore::ARMEmitter::QRegister rd, FEXCore::ARMEmitter::QRegister rn, uint32_t Shift) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); + void sqrshrun2(ARMEmitter::SubRegSize size, ARMEmitter::QRegister rd, ARMEmitter::QRegister rn, uint32_t Shift) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); constexpr uint32_t Op = 0b0000'1111'0000'0000'0000'01 << 10; const size_t SubregSizeInBits = SubRegSizeInBits(size); @@ -3593,7 +3593,7 @@ public: ASIMDShiftByImm(Op, 1, immh, immb, 0b10001, rn, rd); } ///< size is destination size - void uqshrn(FEXCore::ARMEmitter::SubRegSize size, FEXCore::ARMEmitter::DRegister rd, FEXCore::ARMEmitter::DRegister rn, uint32_t Shift) { + void uqshrn(ARMEmitter::SubRegSize size, ARMEmitter::DRegister rd, ARMEmitter::DRegister rn, uint32_t Shift) { constexpr uint32_t Op = 0b0000'1111'0000'0000'0000'01 << 10; const size_t SubregSizeInBits = SubRegSizeInBits(size); @@ -3606,7 +3606,7 @@ public: ASIMDShiftByImm(Op, 1, immh, immb, 0b10010, rn, rd); } ///< size is destination size - void uqshrn2(FEXCore::ARMEmitter::SubRegSize size, FEXCore::ARMEmitter::QRegister rd, FEXCore::ARMEmitter::QRegister rn, uint32_t Shift) { + void uqshrn2(ARMEmitter::SubRegSize size, ARMEmitter::QRegister rd, ARMEmitter::QRegister rn, uint32_t Shift) { constexpr uint32_t Op = 0b0000'1111'0000'0000'0000'01 << 10; const size_t SubregSizeInBits = SubRegSizeInBits(size); @@ -3619,7 +3619,7 @@ public: ASIMDShiftByImm(Op, 1, immh, immb, 0b10010, rn, rd); } ///< size is destination size - void uqrshrn(FEXCore::ARMEmitter::SubRegSize size, FEXCore::ARMEmitter::DRegister rd, FEXCore::ARMEmitter::DRegister rn, uint32_t Shift) { + void uqrshrn(ARMEmitter::SubRegSize size, ARMEmitter::DRegister rd, ARMEmitter::DRegister rn, uint32_t Shift) { constexpr uint32_t Op = 0b0000'1111'0000'0000'0000'01 << 10; const size_t SubregSizeInBits = SubRegSizeInBits(size); @@ -3632,7 +3632,7 @@ public: ASIMDShiftByImm(Op, 1, immh, immb, 0b10011, rn, rd); } ///< size is destination size - void uqrshrn2(FEXCore::ARMEmitter::SubRegSize size, FEXCore::ARMEmitter::QRegister rd, FEXCore::ARMEmitter::QRegister rn, uint32_t Shift) { + void uqrshrn2(ARMEmitter::SubRegSize size, ARMEmitter::QRegister rd, ARMEmitter::QRegister rn, uint32_t Shift) { constexpr uint32_t Op = 0b0000'1111'0000'0000'0000'01 << 10; const size_t SubregSizeInBits = SubRegSizeInBits(size); @@ -3645,9 +3645,9 @@ public: ASIMDShiftByImm(Op, 1, immh, immb, 0b10011, rn, rd); } ///< size is destination size - void ushll(FEXCore::ARMEmitter::SubRegSize size, FEXCore::ARMEmitter::DRegister rd, FEXCore::ARMEmitter::DRegister rn, uint32_t Shift) { + void ushll(ARMEmitter::SubRegSize size, ARMEmitter::DRegister rd, ARMEmitter::DRegister rn, uint32_t Shift) { constexpr uint32_t Op = 0b0000'1111'0000'0000'0000'01 << 10; - size = FEXCore::ARMEmitter::SubRegSize(FEXCore::ToUnderlying(size) - 1); + size = ARMEmitter::SubRegSize(FEXCore::ToUnderlying(size) - 1); const size_t SubregSizeInBits = SubRegSizeInBits(size); // Shift encoded a bit weirdly. @@ -3659,9 +3659,9 @@ public: ASIMDShiftByImm(Op, 1, immh, immb, 0b10100, rn, rd); } ///< size is destination size - void ushll2(FEXCore::ARMEmitter::SubRegSize size, FEXCore::ARMEmitter::QRegister rd, FEXCore::ARMEmitter::QRegister rn, uint32_t Shift) { + void ushll2(ARMEmitter::SubRegSize size, ARMEmitter::QRegister rd, ARMEmitter::QRegister rn, uint32_t Shift) { constexpr uint32_t Op = 0b0000'1111'0000'0000'0000'01 << 10; - size = FEXCore::ARMEmitter::SubRegSize(FEXCore::ToUnderlying(size) - 1); + size = ARMEmitter::SubRegSize(FEXCore::ToUnderlying(size) - 1); const size_t SubregSizeInBits = SubRegSizeInBits(size); // Shift encoded a bit weirdly. @@ -3673,17 +3673,17 @@ public: ASIMDShiftByImm(Op, 1, immh, immb, 0b10100, rn, rd); } - void uxtl(FEXCore::ARMEmitter::SubRegSize size, FEXCore::ARMEmitter::DRegister rd, FEXCore::ARMEmitter::DRegister rn) { + void uxtl(ARMEmitter::SubRegSize size, ARMEmitter::DRegister rd, ARMEmitter::DRegister rn) { ushll(size, rd, rn, 0); } - void uxtl2(FEXCore::ARMEmitter::SubRegSize size, FEXCore::ARMEmitter::QRegister rd, FEXCore::ARMEmitter::QRegister rn) { + void uxtl2(ARMEmitter::SubRegSize size, ARMEmitter::QRegister rd, ARMEmitter::QRegister rn) { ushll2(size, rd, rn, 0); } template - void ucvtf(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, uint32_t FractionalBits) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i8Bit, "Invalid size"); - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); + void ucvtf(ARMEmitter::SubRegSize size, T rd, T rn, uint32_t FractionalBits) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i8Bit, "Invalid size"); + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); } constexpr uint32_t Op = 0b0000'1111'0000'0000'0000'01 << 10; @@ -3700,10 +3700,10 @@ public: } template - void fcvtzu(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, uint32_t FractionalBits) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i8Bit, "Invalid size"); - if constexpr (std::is_same_v) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); + void fcvtzu(ARMEmitter::SubRegSize size, T rd, T rn, uint32_t FractionalBits) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i8Bit, "Invalid size"); + if constexpr (std::is_same_v) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__); } constexpr uint32_t Op = 0b0000'1111'0000'0000'0000'01 << 10; @@ -3721,17 +3721,17 @@ public: // Advanced SIMD vector x indexed element ///< size is destination size - void smlal(FEXCore::ARMEmitter::SubRegSize size, FEXCore::ARMEmitter::VRegister rd, FEXCore::ARMEmitter::VRegister rn, FEXCore::ARMEmitter::VRegister rm, uint32_t Index) { - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i32Bit || size == FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid destination size"); + void smlal(ARMEmitter::SubRegSize size, ARMEmitter::VRegister rd, ARMEmitter::VRegister rn, ARMEmitter::VRegister rm, uint32_t Index) { + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i32Bit || size == ARMEmitter::SubRegSize::i64Bit, "Invalid destination size"); - if (size == FEXCore::ARMEmitter::SubRegSize::i32Bit) { + if (size == ARMEmitter::SubRegSize::i32Bit) { LOGMAN_THROW_A_FMT(rm.Idx() < 16, "Rm can't be v16-v31 with half source size"); } - const auto EncodedSubRegSize = FEXCore::ARMEmitter::SubRegSize(FEXCore::ToUnderlying(size) - 1); + const auto EncodedSubRegSize = ARMEmitter::SubRegSize(FEXCore::ToUnderlying(size) - 1); LOGMAN_THROW_A_FMT(Index < SubRegSizeInBits(EncodedSubRegSize), "Index must be less than the source register size"); uint32_t H, L, M; - if (size == FEXCore::ARMEmitter::SubRegSize::i32Bit) { + if (size == ARMEmitter::SubRegSize::i32Bit) { // Index encoded in H:L:M H = (Index >> 2) & 1; L = (Index >> 1) & 1; @@ -3747,17 +3747,17 @@ public: ASIMDVectorXIndexedElement(0b0, L, M, 0b0010, H, EncodedSubRegSize, rm.D(), rn.D(), rd.D()); } ///< size is destination size - void smlal2(FEXCore::ARMEmitter::SubRegSize size, FEXCore::ARMEmitter::VRegister rd, FEXCore::ARMEmitter::VRegister rn, FEXCore::ARMEmitter::VRegister rm, uint32_t Index) { - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i32Bit || size == FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid destination size"); + void smlal2(ARMEmitter::SubRegSize size, ARMEmitter::VRegister rd, ARMEmitter::VRegister rn, ARMEmitter::VRegister rm, uint32_t Index) { + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i32Bit || size == ARMEmitter::SubRegSize::i64Bit, "Invalid destination size"); - if (size == FEXCore::ARMEmitter::SubRegSize::i32Bit) { + if (size == ARMEmitter::SubRegSize::i32Bit) { LOGMAN_THROW_A_FMT(rm.Idx() < 16, "Rm can't be v16-v31 with half source size"); } - const auto EncodedSubRegSize = FEXCore::ARMEmitter::SubRegSize(FEXCore::ToUnderlying(size) - 1); + const auto EncodedSubRegSize = ARMEmitter::SubRegSize(FEXCore::ToUnderlying(size) - 1); LOGMAN_THROW_A_FMT(Index < SubRegSizeInBits(EncodedSubRegSize), "Index must be less than the source register size"); uint32_t H, L, M; - if (size == FEXCore::ARMEmitter::SubRegSize::i32Bit) { + if (size == ARMEmitter::SubRegSize::i32Bit) { // Index encoded in H:L:M H = (Index >> 2) & 1; L = (Index >> 1) & 1; @@ -3773,17 +3773,17 @@ public: ASIMDVectorXIndexedElement(0b0, L, M, 0b0010, H, EncodedSubRegSize, rm.Q(), rn.Q(), rd.Q()); } ///< size is destination size - void sqdmlal(FEXCore::ARMEmitter::SubRegSize size, FEXCore::ARMEmitter::VRegister rd, FEXCore::ARMEmitter::VRegister rn, FEXCore::ARMEmitter::VRegister rm, uint32_t Index) { - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i32Bit || size == FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid destination size"); + void sqdmlal(ARMEmitter::SubRegSize size, ARMEmitter::VRegister rd, ARMEmitter::VRegister rn, ARMEmitter::VRegister rm, uint32_t Index) { + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i32Bit || size == ARMEmitter::SubRegSize::i64Bit, "Invalid destination size"); - if (size == FEXCore::ARMEmitter::SubRegSize::i32Bit) { + if (size == ARMEmitter::SubRegSize::i32Bit) { LOGMAN_THROW_A_FMT(rm.Idx() < 16, "Rm can't be v16-v31 with half source size"); } - const auto EncodedSubRegSize = FEXCore::ARMEmitter::SubRegSize(FEXCore::ToUnderlying(size) - 1); + const auto EncodedSubRegSize = ARMEmitter::SubRegSize(FEXCore::ToUnderlying(size) - 1); LOGMAN_THROW_A_FMT(Index < SubRegSizeInBits(EncodedSubRegSize), "Index must be less than the source register size"); uint32_t H, L, M; - if (size == FEXCore::ARMEmitter::SubRegSize::i32Bit) { + if (size == ARMEmitter::SubRegSize::i32Bit) { // Index encoded in H:L:M H = (Index >> 2) & 1; L = (Index >> 1) & 1; @@ -3799,17 +3799,17 @@ public: ASIMDVectorXIndexedElement(0b0, L, M, 0b0011, H, EncodedSubRegSize, rm.D(), rn.D(), rd.D()); } ///< size is destination size - void sqdmlal2(FEXCore::ARMEmitter::SubRegSize size, FEXCore::ARMEmitter::VRegister rd, FEXCore::ARMEmitter::VRegister rn, FEXCore::ARMEmitter::VRegister rm, uint32_t Index) { - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i32Bit || size == FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid destination size"); + void sqdmlal2(ARMEmitter::SubRegSize size, ARMEmitter::VRegister rd, ARMEmitter::VRegister rn, ARMEmitter::VRegister rm, uint32_t Index) { + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i32Bit || size == ARMEmitter::SubRegSize::i64Bit, "Invalid destination size"); - if (size == FEXCore::ARMEmitter::SubRegSize::i32Bit) { + if (size == ARMEmitter::SubRegSize::i32Bit) { LOGMAN_THROW_A_FMT(rm.Idx() < 16, "Rm can't be v16-v31 with half source size"); } - const auto EncodedSubRegSize = FEXCore::ARMEmitter::SubRegSize(FEXCore::ToUnderlying(size) - 1); + const auto EncodedSubRegSize = ARMEmitter::SubRegSize(FEXCore::ToUnderlying(size) - 1); LOGMAN_THROW_A_FMT(Index < SubRegSizeInBits(EncodedSubRegSize), "Index must be less than the source register size"); uint32_t H, L, M; - if (size == FEXCore::ARMEmitter::SubRegSize::i32Bit) { + if (size == ARMEmitter::SubRegSize::i32Bit) { // Index encoded in H:L:M H = (Index >> 2) & 1; L = (Index >> 1) & 1; @@ -3825,17 +3825,17 @@ public: ASIMDVectorXIndexedElement(0b0, L, M, 0b0011, H, EncodedSubRegSize, rm.Q(), rn.Q(), rd.Q()); } ///< size is destination size - void smlsl(FEXCore::ARMEmitter::SubRegSize size, FEXCore::ARMEmitter::VRegister rd, FEXCore::ARMEmitter::VRegister rn, FEXCore::ARMEmitter::VRegister rm, uint32_t Index) { - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i32Bit || size == FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid destination size"); + void smlsl(ARMEmitter::SubRegSize size, ARMEmitter::VRegister rd, ARMEmitter::VRegister rn, ARMEmitter::VRegister rm, uint32_t Index) { + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i32Bit || size == ARMEmitter::SubRegSize::i64Bit, "Invalid destination size"); - if (size == FEXCore::ARMEmitter::SubRegSize::i32Bit) { + if (size == ARMEmitter::SubRegSize::i32Bit) { LOGMAN_THROW_A_FMT(rm.Idx() < 16, "Rm can't be v16-v31 with half source size"); } - const auto EncodedSubRegSize = FEXCore::ARMEmitter::SubRegSize(FEXCore::ToUnderlying(size) - 1); + const auto EncodedSubRegSize = ARMEmitter::SubRegSize(FEXCore::ToUnderlying(size) - 1); LOGMAN_THROW_A_FMT(Index < SubRegSizeInBits(EncodedSubRegSize), "Index must be less than the source register size"); uint32_t H, L, M; - if (size == FEXCore::ARMEmitter::SubRegSize::i32Bit) { + if (size == ARMEmitter::SubRegSize::i32Bit) { // Index encoded in H:L:M H = (Index >> 2) & 1; L = (Index >> 1) & 1; @@ -3851,17 +3851,17 @@ public: ASIMDVectorXIndexedElement(0b0, L, M, 0b0110, H, EncodedSubRegSize, rm.D(), rn.D(), rd.D()); } ///< size is destination size - void smlsl2(FEXCore::ARMEmitter::SubRegSize size, FEXCore::ARMEmitter::VRegister rd, FEXCore::ARMEmitter::VRegister rn, FEXCore::ARMEmitter::VRegister rm, uint32_t Index) { - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i32Bit || size == FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid destination size"); + void smlsl2(ARMEmitter::SubRegSize size, ARMEmitter::VRegister rd, ARMEmitter::VRegister rn, ARMEmitter::VRegister rm, uint32_t Index) { + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i32Bit || size == ARMEmitter::SubRegSize::i64Bit, "Invalid destination size"); - if (size == FEXCore::ARMEmitter::SubRegSize::i32Bit) { + if (size == ARMEmitter::SubRegSize::i32Bit) { LOGMAN_THROW_A_FMT(rm.Idx() < 16, "Rm can't be v16-v31 with half source size"); } - const auto EncodedSubRegSize = FEXCore::ARMEmitter::SubRegSize(FEXCore::ToUnderlying(size) - 1); + const auto EncodedSubRegSize = ARMEmitter::SubRegSize(FEXCore::ToUnderlying(size) - 1); LOGMAN_THROW_A_FMT(Index < SubRegSizeInBits(EncodedSubRegSize), "Index must be less than the source register size"); uint32_t H, L, M; - if (size == FEXCore::ARMEmitter::SubRegSize::i32Bit) { + if (size == ARMEmitter::SubRegSize::i32Bit) { // Index encoded in H:L:M H = (Index >> 2) & 1; L = (Index >> 1) & 1; @@ -3877,17 +3877,17 @@ public: ASIMDVectorXIndexedElement(0b0, L, M, 0b0110, H, EncodedSubRegSize, rm.Q(), rn.Q(), rd.Q()); } ///< size is destination size - void sqdmlsl(FEXCore::ARMEmitter::SubRegSize size, FEXCore::ARMEmitter::VRegister rd, FEXCore::ARMEmitter::VRegister rn, FEXCore::ARMEmitter::VRegister rm, uint32_t Index) { - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i32Bit || size == FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid destination size"); + void sqdmlsl(ARMEmitter::SubRegSize size, ARMEmitter::VRegister rd, ARMEmitter::VRegister rn, ARMEmitter::VRegister rm, uint32_t Index) { + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i32Bit || size == ARMEmitter::SubRegSize::i64Bit, "Invalid destination size"); - if (size == FEXCore::ARMEmitter::SubRegSize::i32Bit) { + if (size == ARMEmitter::SubRegSize::i32Bit) { LOGMAN_THROW_A_FMT(rm.Idx() < 16, "Rm can't be v16-v31 with half source size"); } - const auto EncodedSubRegSize = FEXCore::ARMEmitter::SubRegSize(FEXCore::ToUnderlying(size) - 1); + const auto EncodedSubRegSize = ARMEmitter::SubRegSize(FEXCore::ToUnderlying(size) - 1); LOGMAN_THROW_A_FMT(Index < SubRegSizeInBits(EncodedSubRegSize), "Index must be less than the source register size"); uint32_t H, L, M; - if (size == FEXCore::ARMEmitter::SubRegSize::i32Bit) { + if (size == ARMEmitter::SubRegSize::i32Bit) { // Index encoded in H:L:M H = (Index >> 2) & 1; L = (Index >> 1) & 1; @@ -3903,17 +3903,17 @@ public: ASIMDVectorXIndexedElement(0b0, L, M, 0b0111, H, EncodedSubRegSize, rm.D(), rn.D(), rd.D()); } ///< size is destination size - void sqdmlsl2(FEXCore::ARMEmitter::SubRegSize size, FEXCore::ARMEmitter::VRegister rd, FEXCore::ARMEmitter::VRegister rn, FEXCore::ARMEmitter::VRegister rm, uint32_t Index) { - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i32Bit || size == FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid destination size"); + void sqdmlsl2(ARMEmitter::SubRegSize size, ARMEmitter::VRegister rd, ARMEmitter::VRegister rn, ARMEmitter::VRegister rm, uint32_t Index) { + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i32Bit || size == ARMEmitter::SubRegSize::i64Bit, "Invalid destination size"); - if (size == FEXCore::ARMEmitter::SubRegSize::i32Bit) { + if (size == ARMEmitter::SubRegSize::i32Bit) { LOGMAN_THROW_A_FMT(rm.Idx() < 16, "Rm can't be v16-v31 with half source size"); } - const auto EncodedSubRegSize = FEXCore::ARMEmitter::SubRegSize(FEXCore::ToUnderlying(size) - 1); + const auto EncodedSubRegSize = ARMEmitter::SubRegSize(FEXCore::ToUnderlying(size) - 1); LOGMAN_THROW_A_FMT(Index < SubRegSizeInBits(EncodedSubRegSize), "Index must be less than the source register size"); uint32_t H, L, M; - if (size == FEXCore::ARMEmitter::SubRegSize::i32Bit) { + if (size == ARMEmitter::SubRegSize::i32Bit) { // Index encoded in H:L:M H = (Index >> 2) & 1; L = (Index >> 1) & 1; @@ -3929,17 +3929,17 @@ public: ASIMDVectorXIndexedElement(0b0, L, M, 0b0111, H, EncodedSubRegSize, rm.Q(), rn.Q(), rd.Q()); } template - requires(std::is_same_v || std::is_same_v) - void mul(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, T rm, uint32_t Index) { - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i16Bit || size == FEXCore::ARMEmitter::SubRegSize::i32Bit, "Invalid destination size"); + requires(std::is_same_v || std::is_same_v) + void mul(ARMEmitter::SubRegSize size, T rd, T rn, T rm, uint32_t Index) { + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i16Bit || size == ARMEmitter::SubRegSize::i32Bit, "Invalid destination size"); - if (size == FEXCore::ARMEmitter::SubRegSize::i16Bit) { + if (size == ARMEmitter::SubRegSize::i16Bit) { LOGMAN_THROW_A_FMT(rm.Idx() < 16, "Rm can't be v16-v31 with half source size"); } LOGMAN_THROW_A_FMT(Index < SubRegSizeInBits(size), "Index must be less than the source register size"); uint32_t H, L, M; - if (size == FEXCore::ARMEmitter::SubRegSize::i16Bit) { + if (size == ARMEmitter::SubRegSize::i16Bit) { // Index encoded in H:L:M H = (Index >> 2) & 1; L = (Index >> 1) & 1; @@ -3955,17 +3955,17 @@ public: ASIMDVectorXIndexedElement(0b0, L, M, 0b1000, H, size, rm, rn, rd); } ///< size is destination size - void smull(FEXCore::ARMEmitter::SubRegSize size, FEXCore::ARMEmitter::VRegister rd, FEXCore::ARMEmitter::VRegister rn, FEXCore::ARMEmitter::VRegister rm, uint32_t Index) { - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i32Bit || size == FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid destination size"); + void smull(ARMEmitter::SubRegSize size, ARMEmitter::VRegister rd, ARMEmitter::VRegister rn, ARMEmitter::VRegister rm, uint32_t Index) { + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i32Bit || size == ARMEmitter::SubRegSize::i64Bit, "Invalid destination size"); - if (size == FEXCore::ARMEmitter::SubRegSize::i32Bit) { + if (size == ARMEmitter::SubRegSize::i32Bit) { LOGMAN_THROW_A_FMT(rm.Idx() < 16, "Rm can't be v16-v31 with half source size"); } - const auto EncodedSubRegSize = FEXCore::ARMEmitter::SubRegSize(FEXCore::ToUnderlying(size) - 1); + const auto EncodedSubRegSize = ARMEmitter::SubRegSize(FEXCore::ToUnderlying(size) - 1); LOGMAN_THROW_A_FMT(Index < SubRegSizeInBits(EncodedSubRegSize), "Index must be less than the source register size"); uint32_t H, L, M; - if (size == FEXCore::ARMEmitter::SubRegSize::i32Bit) { + if (size == ARMEmitter::SubRegSize::i32Bit) { // Index encoded in H:L:M H = (Index >> 2) & 1; L = (Index >> 1) & 1; @@ -3981,17 +3981,17 @@ public: ASIMDVectorXIndexedElement(0b0, L, M, 0b1010, H, EncodedSubRegSize, rm.D(), rn.D(), rd.D()); } ///< size is destination size - void smull2(FEXCore::ARMEmitter::SubRegSize size, FEXCore::ARMEmitter::VRegister rd, FEXCore::ARMEmitter::VRegister rn, FEXCore::ARMEmitter::VRegister rm, uint32_t Index) { - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i32Bit || size == FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid destination size"); + void smull2(ARMEmitter::SubRegSize size, ARMEmitter::VRegister rd, ARMEmitter::VRegister rn, ARMEmitter::VRegister rm, uint32_t Index) { + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i32Bit || size == ARMEmitter::SubRegSize::i64Bit, "Invalid destination size"); - if (size == FEXCore::ARMEmitter::SubRegSize::i32Bit) { + if (size == ARMEmitter::SubRegSize::i32Bit) { LOGMAN_THROW_A_FMT(rm.Idx() < 16, "Rm can't be v16-v31 with half source size"); } - const auto EncodedSubRegSize = FEXCore::ARMEmitter::SubRegSize(FEXCore::ToUnderlying(size) - 1); + const auto EncodedSubRegSize = ARMEmitter::SubRegSize(FEXCore::ToUnderlying(size) - 1); LOGMAN_THROW_A_FMT(Index < SubRegSizeInBits(EncodedSubRegSize), "Index must be less than the source register size"); uint32_t H, L, M; - if (size == FEXCore::ARMEmitter::SubRegSize::i32Bit) { + if (size == ARMEmitter::SubRegSize::i32Bit) { // Index encoded in H:L:M H = (Index >> 2) & 1; L = (Index >> 1) & 1; @@ -4007,17 +4007,17 @@ public: ASIMDVectorXIndexedElement(0b0, L, M, 0b1010, H, EncodedSubRegSize, rm.Q(), rn.Q(), rd.Q()); } ///< size is destination size - void sqdmull(FEXCore::ARMEmitter::SubRegSize size, FEXCore::ARMEmitter::VRegister rd, FEXCore::ARMEmitter::VRegister rn, FEXCore::ARMEmitter::VRegister rm, uint32_t Index) { - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i32Bit || size == FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid destination size"); + void sqdmull(ARMEmitter::SubRegSize size, ARMEmitter::VRegister rd, ARMEmitter::VRegister rn, ARMEmitter::VRegister rm, uint32_t Index) { + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i32Bit || size == ARMEmitter::SubRegSize::i64Bit, "Invalid destination size"); - if (size == FEXCore::ARMEmitter::SubRegSize::i32Bit) { + if (size == ARMEmitter::SubRegSize::i32Bit) { LOGMAN_THROW_A_FMT(rm.Idx() < 16, "Rm can't be v16-v31 with half source size"); } - const auto EncodedSubRegSize = FEXCore::ARMEmitter::SubRegSize(FEXCore::ToUnderlying(size) - 1); + const auto EncodedSubRegSize = ARMEmitter::SubRegSize(FEXCore::ToUnderlying(size) - 1); LOGMAN_THROW_A_FMT(Index < SubRegSizeInBits(EncodedSubRegSize), "Index must be less than the source register size"); uint32_t H, L, M; - if (size == FEXCore::ARMEmitter::SubRegSize::i32Bit) { + if (size == ARMEmitter::SubRegSize::i32Bit) { // Index encoded in H:L:M H = (Index >> 2) & 1; L = (Index >> 1) & 1; @@ -4033,17 +4033,17 @@ public: ASIMDVectorXIndexedElement(0b0, L, M, 0b1011, H, EncodedSubRegSize, rm.D(), rn.D(), rd.D()); } ///< size is destination size - void sqdmull2(FEXCore::ARMEmitter::SubRegSize size, FEXCore::ARMEmitter::VRegister rd, FEXCore::ARMEmitter::VRegister rn, FEXCore::ARMEmitter::VRegister rm, uint32_t Index) { - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i32Bit || size == FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid destination size"); + void sqdmull2(ARMEmitter::SubRegSize size, ARMEmitter::VRegister rd, ARMEmitter::VRegister rn, ARMEmitter::VRegister rm, uint32_t Index) { + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i32Bit || size == ARMEmitter::SubRegSize::i64Bit, "Invalid destination size"); - if (size == FEXCore::ARMEmitter::SubRegSize::i32Bit) { + if (size == ARMEmitter::SubRegSize::i32Bit) { LOGMAN_THROW_A_FMT(rm.Idx() < 16, "Rm can't be v16-v31 with half source size"); } - const auto EncodedSubRegSize = FEXCore::ARMEmitter::SubRegSize(FEXCore::ToUnderlying(size) - 1); + const auto EncodedSubRegSize = ARMEmitter::SubRegSize(FEXCore::ToUnderlying(size) - 1); LOGMAN_THROW_A_FMT(Index < SubRegSizeInBits(EncodedSubRegSize), "Index must be less than the source register size"); uint32_t H, L, M; - if (size == FEXCore::ARMEmitter::SubRegSize::i32Bit) { + if (size == ARMEmitter::SubRegSize::i32Bit) { // Index encoded in H:L:M H = (Index >> 2) & 1; L = (Index >> 1) & 1; @@ -4059,17 +4059,17 @@ public: ASIMDVectorXIndexedElement(0b0, L, M, 0b1011, H, EncodedSubRegSize, rm.Q(), rn.Q(), rd.Q()); } template - requires(std::is_same_v || std::is_same_v) - void sqdmulh(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, T rm, uint32_t Index) { - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i16Bit || size == FEXCore::ARMEmitter::SubRegSize::i32Bit, "Invalid destination size"); + requires(std::is_same_v || std::is_same_v) + void sqdmulh(ARMEmitter::SubRegSize size, T rd, T rn, T rm, uint32_t Index) { + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i16Bit || size == ARMEmitter::SubRegSize::i32Bit, "Invalid destination size"); - if (size == FEXCore::ARMEmitter::SubRegSize::i16Bit) { + if (size == ARMEmitter::SubRegSize::i16Bit) { LOGMAN_THROW_A_FMT(rm.Idx() < 16, "Rm can't be v16-v31 with half source size"); } LOGMAN_THROW_A_FMT(Index < SubRegSizeInBits(size), "Index must be less than the source register size"); uint32_t H, L, M; - if (size == FEXCore::ARMEmitter::SubRegSize::i16Bit) { + if (size == ARMEmitter::SubRegSize::i16Bit) { // Index encoded in H:L:M H = (Index >> 2) & 1; L = (Index >> 1) & 1; @@ -4085,17 +4085,17 @@ public: ASIMDVectorXIndexedElement(0b0, L, M, 0b1100, H, size, rm, rn, rd); } template - requires(std::is_same_v || std::is_same_v) - void sqrdmulh(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, T rm, uint32_t Index) { - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i16Bit || size == FEXCore::ARMEmitter::SubRegSize::i32Bit, "Invalid destination size"); + requires(std::is_same_v || std::is_same_v) + void sqrdmulh(ARMEmitter::SubRegSize size, T rd, T rn, T rm, uint32_t Index) { + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i16Bit || size == ARMEmitter::SubRegSize::i32Bit, "Invalid destination size"); - if (size == FEXCore::ARMEmitter::SubRegSize::i16Bit) { + if (size == ARMEmitter::SubRegSize::i16Bit) { LOGMAN_THROW_A_FMT(rm.Idx() < 16, "Rm can't be v16-v31 with half source size"); } LOGMAN_THROW_A_FMT(Index < SubRegSizeInBits(size), "Index must be less than the source register size"); uint32_t H, L, M; - if (size == FEXCore::ARMEmitter::SubRegSize::i16Bit) { + if (size == ARMEmitter::SubRegSize::i16Bit) { // Index encoded in H:L:M H = (Index >> 2) & 1; L = (Index >> 1) & 1; @@ -4112,7 +4112,7 @@ public: } template - requires(std::is_same_v || std::is_same_v) + requires(std::is_same_v || std::is_same_v) void sdot(T rd, T rn, T rm, uint32_t Index) { LOGMAN_THROW_A_FMT(Index < 4, "Index must be less than the source register size"); @@ -4122,11 +4122,11 @@ public: H = (Index >> 1) & 1; L = (Index >> 0) & 1; M = 0; - ASIMDVectorXIndexedElement(0b0, L, M, 0b1110, H, FEXCore::ARMEmitter::SubRegSize::i32Bit, rm, rn, rd); + ASIMDVectorXIndexedElement(0b0, L, M, 0b1110, H, ARMEmitter::SubRegSize::i32Bit, rm, rn, rd); } template - requires(std::is_same_v || std::is_same_v) + requires(std::is_same_v || std::is_same_v) void sudot(T rd, T rn, T rm, uint32_t Index) { LOGMAN_THROW_A_FMT(Index < 4, "Index must be less than the source register size"); @@ -4136,11 +4136,11 @@ public: H = (Index >> 1) & 1; L = (Index >> 0) & 1; M = 0; - ASIMDVectorXIndexedElement(0b0, L, M, 0b1111, H, FEXCore::ARMEmitter::SubRegSize::i8Bit, rm, rn, rd); + ASIMDVectorXIndexedElement(0b0, L, M, 0b1111, H, ARMEmitter::SubRegSize::i8Bit, rm, rn, rd); } template - requires(std::is_same_v || std::is_same_v) + requires(std::is_same_v || std::is_same_v) void bfdot(T rd, T rn, T rm, uint32_t Index) { LOGMAN_THROW_A_FMT(Index < 4, "Index must be less than the source register size"); @@ -4150,36 +4150,36 @@ public: H = (Index >> 1) & 1; L = (Index >> 0) & 1; M = 0; - ASIMDVectorXIndexedElement(0b0, L, M, 0b1111, H, FEXCore::ARMEmitter::SubRegSize::i16Bit, rm, rn, rd); + ASIMDVectorXIndexedElement(0b0, L, M, 0b1111, H, ARMEmitter::SubRegSize::i16Bit, rm, rn, rd); } template - requires(std::is_same_v || std::is_same_v) - void fmla(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, T rm, uint32_t Index) { - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i16Bit || - size == FEXCore::ARMEmitter::SubRegSize::i32Bit || - size == FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid destination size"); + requires(std::is_same_v || std::is_same_v) + void fmla(ARMEmitter::SubRegSize size, T rd, T rn, T rm, uint32_t Index) { + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i16Bit || + size == ARMEmitter::SubRegSize::i32Bit || + size == ARMEmitter::SubRegSize::i64Bit, "Invalid destination size"); LOGMAN_THROW_A_FMT(Index < SubRegSizeInBits(size), "Index must be less than the source register size"); uint32_t H, L, M; auto EncodedSubRegSize = size; - if (size == FEXCore::ARMEmitter::SubRegSize::i16Bit) { + if (size == ARMEmitter::SubRegSize::i16Bit) { // Index encoded in H:L:M H = (Index >> 2) & 1; L = (Index >> 1) & 1; M = (Index >> 0) & 1; // ARM in their infinite wisdom decided to encode 16-bit as an 8-bit operation even though 16-bit was unallocated. - EncodedSubRegSize = FEXCore::ARMEmitter::SubRegSize::i8Bit; + EncodedSubRegSize = ARMEmitter::SubRegSize::i8Bit; } - else if (size == FEXCore::ARMEmitter::SubRegSize::i32Bit) { + else if (size == ARMEmitter::SubRegSize::i32Bit) { // Index encoded in H:L H = (Index >> 1) & 1; L = (Index >> 0) & 1; M = 0; } else { - LOGMAN_THROW_A_FMT(std::is_same_v, "Can't encode DRegister with i64Bit"); + LOGMAN_THROW_A_FMT(std::is_same_v, "Can't encode DRegister with i64Bit"); // Index encoded in H H = Index; L = 0; @@ -4189,32 +4189,32 @@ public: } template - requires(std::is_same_v || std::is_same_v) - void fmls(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, T rm, uint32_t Index) { - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i16Bit || - size == FEXCore::ARMEmitter::SubRegSize::i32Bit || - size == FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid destination size"); + requires(std::is_same_v || std::is_same_v) + void fmls(ARMEmitter::SubRegSize size, T rd, T rn, T rm, uint32_t Index) { + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i16Bit || + size == ARMEmitter::SubRegSize::i32Bit || + size == ARMEmitter::SubRegSize::i64Bit, "Invalid destination size"); LOGMAN_THROW_A_FMT(Index < SubRegSizeInBits(size), "Index must be less than the source register size"); uint32_t H, L, M; auto EncodedSubRegSize = size; - if (size == FEXCore::ARMEmitter::SubRegSize::i16Bit) { + if (size == ARMEmitter::SubRegSize::i16Bit) { // Index encoded in H:L:M H = (Index >> 2) & 1; L = (Index >> 1) & 1; M = (Index >> 0) & 1; // ARM in their infinite wisdom decided to encode 16-bit as an 8-bit operation even though 16-bit was unallocated. - EncodedSubRegSize = FEXCore::ARMEmitter::SubRegSize::i8Bit; + EncodedSubRegSize = ARMEmitter::SubRegSize::i8Bit; } - else if (size == FEXCore::ARMEmitter::SubRegSize::i32Bit) { + else if (size == ARMEmitter::SubRegSize::i32Bit) { // Index encoded in H:L H = (Index >> 1) & 1; L = (Index >> 0) & 1; M = 0; } else { - LOGMAN_THROW_A_FMT(std::is_same_v, "Can't encode DRegister with i64Bit"); + LOGMAN_THROW_A_FMT(std::is_same_v, "Can't encode DRegister with i64Bit"); // Index encoded in H H = Index; L = 0; @@ -4224,32 +4224,32 @@ public: } template - requires(std::is_same_v || std::is_same_v) - void fmul(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, T rm, uint32_t Index) { - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i16Bit || - size == FEXCore::ARMEmitter::SubRegSize::i32Bit || - size == FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid destination size"); + requires(std::is_same_v || std::is_same_v) + void fmul(ARMEmitter::SubRegSize size, T rd, T rn, T rm, uint32_t Index) { + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i16Bit || + size == ARMEmitter::SubRegSize::i32Bit || + size == ARMEmitter::SubRegSize::i64Bit, "Invalid destination size"); LOGMAN_THROW_A_FMT(Index < SubRegSizeInBits(size), "Index must be less than the source register size"); uint32_t H, L, M; auto EncodedSubRegSize = size; - if (size == FEXCore::ARMEmitter::SubRegSize::i16Bit) { + if (size == ARMEmitter::SubRegSize::i16Bit) { // Index encoded in H:L:M H = (Index >> 2) & 1; L = (Index >> 1) & 1; M = (Index >> 0) & 1; // ARM in their infinite wisdom decided to encode 16-bit as an 8-bit operation even though 16-bit was unallocated. - EncodedSubRegSize = FEXCore::ARMEmitter::SubRegSize::i8Bit; + EncodedSubRegSize = ARMEmitter::SubRegSize::i8Bit; } - else if (size == FEXCore::ARMEmitter::SubRegSize::i32Bit) { + else if (size == ARMEmitter::SubRegSize::i32Bit) { // Index encoded in H:L H = (Index >> 1) & 1; L = (Index >> 0) & 1; M = 0; } else { - LOGMAN_THROW_A_FMT(std::is_same_v, "Can't encode DRegister with i64Bit"); + LOGMAN_THROW_A_FMT(std::is_same_v, "Can't encode DRegister with i64Bit"); // Index encoded in H H = Index; L = 0; @@ -4259,7 +4259,7 @@ public: } template - requires(std::is_same_v || std::is_same_v) + requires(std::is_same_v || std::is_same_v) void fmlal(T rd, T rn, T rm, uint32_t Index) { LOGMAN_THROW_A_FMT(Index < 8, "Index must be less than the source register size"); @@ -4269,11 +4269,11 @@ public: H = (Index >> 2) & 1; L = (Index >> 1) & 1; M = (Index >> 0) & 1; - ASIMDVectorXIndexedElement(0b0, L, M, 0b0000, H, FEXCore::ARMEmitter::SubRegSize::i32Bit, rm, rn, rd); + ASIMDVectorXIndexedElement(0b0, L, M, 0b0000, H, ARMEmitter::SubRegSize::i32Bit, rm, rn, rd); } template - requires(std::is_same_v || std::is_same_v) + requires(std::is_same_v || std::is_same_v) void fmlal2(T rd, T rn, T rm, uint32_t Index) { LOGMAN_THROW_A_FMT(Index < 8, "Index must be less than the source register size"); @@ -4283,11 +4283,11 @@ public: H = (Index >> 2) & 1; L = (Index >> 1) & 1; M = (Index >> 0) & 1; - ASIMDVectorXIndexedElement(0b1, L, M, 0b1000, H, FEXCore::ARMEmitter::SubRegSize::i32Bit, rm, rn, rd); + ASIMDVectorXIndexedElement(0b1, L, M, 0b1000, H, ARMEmitter::SubRegSize::i32Bit, rm, rn, rd); } template - requires(std::is_same_v || std::is_same_v) + requires(std::is_same_v || std::is_same_v) void fmlsl(T rd, T rn, T rm, uint32_t Index) { LOGMAN_THROW_A_FMT(Index < 8, "Index must be less than the source register size"); @@ -4297,11 +4297,11 @@ public: H = (Index >> 2) & 1; L = (Index >> 1) & 1; M = (Index >> 0) & 1; - ASIMDVectorXIndexedElement(0b0, L, M, 0b0100, H, FEXCore::ARMEmitter::SubRegSize::i32Bit, rm, rn, rd); + ASIMDVectorXIndexedElement(0b0, L, M, 0b0100, H, ARMEmitter::SubRegSize::i32Bit, rm, rn, rd); } template - requires(std::is_same_v || std::is_same_v) + requires(std::is_same_v || std::is_same_v) void fmlsl2(T rd, T rn, T rm, uint32_t Index) { LOGMAN_THROW_A_FMT(Index < 8, "Index must be less than the source register size"); @@ -4311,11 +4311,11 @@ public: H = (Index >> 2) & 1; L = (Index >> 1) & 1; M = (Index >> 0) & 1; - ASIMDVectorXIndexedElement(0b1, L, M, 0b1100, H, FEXCore::ARMEmitter::SubRegSize::i32Bit, rm, rn, rd); + ASIMDVectorXIndexedElement(0b1, L, M, 0b1100, H, ARMEmitter::SubRegSize::i32Bit, rm, rn, rd); } template - requires(std::is_same_v || std::is_same_v) + requires(std::is_same_v || std::is_same_v) void usdot(T rd, T rn, T rm, uint32_t Index) { LOGMAN_THROW_A_FMT(Index < 4, "Index must be less than the source register size"); @@ -4325,10 +4325,10 @@ public: H = (Index >> 1) & 1; L = (Index >> 0) & 1; M = 0; - ASIMDVectorXIndexedElement(0b0, L, M, 0b1111, H, FEXCore::ARMEmitter::SubRegSize::i32Bit, rm, rn, rd); + ASIMDVectorXIndexedElement(0b0, L, M, 0b1111, H, ARMEmitter::SubRegSize::i32Bit, rm, rn, rd); } - void bfmlalb(FEXCore::ARMEmitter::VRegister rd, FEXCore::ARMEmitter::VRegister rn, FEXCore::ARMEmitter::VRegister rm, uint32_t Index) { + void bfmlalb(ARMEmitter::VRegister rd, ARMEmitter::VRegister rn, ARMEmitter::VRegister rm, uint32_t Index) { LOGMAN_THROW_A_FMT(rm.Idx() < 16, "Rm can't be v16-v31 with half source size"); LOGMAN_THROW_A_FMT(Index < 8, "Index must be less than the source register size"); @@ -4338,9 +4338,9 @@ public: H = (Index >> 2) & 1; L = (Index >> 1) & 1; M = (Index >> 0) & 1; - ASIMDVectorXIndexedElement(0b0, L, M, 0b1111, H, FEXCore::ARMEmitter::SubRegSize::i64Bit, rm.D(), rn.D(), rd.D()); + ASIMDVectorXIndexedElement(0b0, L, M, 0b1111, H, ARMEmitter::SubRegSize::i64Bit, rm.D(), rn.D(), rd.D()); } - void bfmlalt(FEXCore::ARMEmitter::VRegister rd, FEXCore::ARMEmitter::VRegister rn, FEXCore::ARMEmitter::VRegister rm, uint32_t Index) { + void bfmlalt(ARMEmitter::VRegister rd, ARMEmitter::VRegister rn, ARMEmitter::VRegister rm, uint32_t Index) { LOGMAN_THROW_A_FMT(rm.Idx() < 16, "Rm can't be v16-v31 with half source size"); LOGMAN_THROW_A_FMT(Index < 8, "Index must be less than the source register size"); @@ -4350,21 +4350,21 @@ public: H = (Index >> 2) & 1; L = (Index >> 1) & 1; M = (Index >> 0) & 1; - ASIMDVectorXIndexedElement(0b0, L, M, 0b1111, H, FEXCore::ARMEmitter::SubRegSize::i64Bit, rm.Q(), rn.Q(), rd.Q()); + ASIMDVectorXIndexedElement(0b0, L, M, 0b1111, H, ARMEmitter::SubRegSize::i64Bit, rm.Q(), rn.Q(), rd.Q()); } template - requires(std::is_same_v || std::is_same_v) - void mla(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, T rm, uint32_t Index) { - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i16Bit || size == FEXCore::ARMEmitter::SubRegSize::i32Bit, "Invalid destination size"); + requires(std::is_same_v || std::is_same_v) + void mla(ARMEmitter::SubRegSize size, T rd, T rn, T rm, uint32_t Index) { + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i16Bit || size == ARMEmitter::SubRegSize::i32Bit, "Invalid destination size"); - if (size == FEXCore::ARMEmitter::SubRegSize::i16Bit) { + if (size == ARMEmitter::SubRegSize::i16Bit) { LOGMAN_THROW_A_FMT(rm.Idx() < 16, "Rm can't be v16-v31 with half source size"); } LOGMAN_THROW_A_FMT(Index < SubRegSizeInBits(size), "Index must be less than the source register size"); uint32_t H, L, M; - if (size == FEXCore::ARMEmitter::SubRegSize::i16Bit) { + if (size == ARMEmitter::SubRegSize::i16Bit) { // Index encoded in H:L:M H = (Index >> 2) & 1; L = (Index >> 1) & 1; @@ -4381,17 +4381,17 @@ public: } ///< size is destination size - void umlal(FEXCore::ARMEmitter::SubRegSize size, FEXCore::ARMEmitter::VRegister rd, FEXCore::ARMEmitter::VRegister rn, FEXCore::ARMEmitter::VRegister rm, uint32_t Index) { - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i32Bit || size == FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid destination size"); + void umlal(ARMEmitter::SubRegSize size, ARMEmitter::VRegister rd, ARMEmitter::VRegister rn, ARMEmitter::VRegister rm, uint32_t Index) { + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i32Bit || size == ARMEmitter::SubRegSize::i64Bit, "Invalid destination size"); - if (size == FEXCore::ARMEmitter::SubRegSize::i32Bit) { + if (size == ARMEmitter::SubRegSize::i32Bit) { LOGMAN_THROW_A_FMT(rm.Idx() < 16, "Rm can't be v16-v31 with half source size"); } - const auto EncodedSubRegSize = FEXCore::ARMEmitter::SubRegSize(FEXCore::ToUnderlying(size) - 1); + const auto EncodedSubRegSize = ARMEmitter::SubRegSize(FEXCore::ToUnderlying(size) - 1); LOGMAN_THROW_A_FMT(Index < SubRegSizeInBits(EncodedSubRegSize), "Index must be less than the source register size"); uint32_t H, L, M; - if (size == FEXCore::ARMEmitter::SubRegSize::i32Bit) { + if (size == ARMEmitter::SubRegSize::i32Bit) { // Index encoded in H:L:M H = (Index >> 2) & 1; L = (Index >> 1) & 1; @@ -4407,17 +4407,17 @@ public: ASIMDVectorXIndexedElement(0b1, L, M, 0b0010, H, EncodedSubRegSize, rm.D(), rn.D(), rd.D()); } ///< size is destination size - void umlal2(FEXCore::ARMEmitter::SubRegSize size, FEXCore::ARMEmitter::VRegister rd, FEXCore::ARMEmitter::VRegister rn, FEXCore::ARMEmitter::VRegister rm, uint32_t Index) { - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i32Bit || size == FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid destination size"); + void umlal2(ARMEmitter::SubRegSize size, ARMEmitter::VRegister rd, ARMEmitter::VRegister rn, ARMEmitter::VRegister rm, uint32_t Index) { + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i32Bit || size == ARMEmitter::SubRegSize::i64Bit, "Invalid destination size"); - if (size == FEXCore::ARMEmitter::SubRegSize::i32Bit) { + if (size == ARMEmitter::SubRegSize::i32Bit) { LOGMAN_THROW_A_FMT(rm.Idx() < 16, "Rm can't be v16-v31 with half source size"); } - const auto EncodedSubRegSize = FEXCore::ARMEmitter::SubRegSize(FEXCore::ToUnderlying(size) - 1); + const auto EncodedSubRegSize = ARMEmitter::SubRegSize(FEXCore::ToUnderlying(size) - 1); LOGMAN_THROW_A_FMT(Index < SubRegSizeInBits(EncodedSubRegSize), "Index must be less than the source register size"); uint32_t H, L, M; - if (size == FEXCore::ARMEmitter::SubRegSize::i32Bit) { + if (size == ARMEmitter::SubRegSize::i32Bit) { // Index encoded in H:L:M H = (Index >> 2) & 1; L = (Index >> 1) & 1; @@ -4434,17 +4434,17 @@ public: } template - requires(std::is_same_v || std::is_same_v) - void mls(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, T rm, uint32_t Index) { - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i16Bit || size == FEXCore::ARMEmitter::SubRegSize::i32Bit, "Invalid destination size"); + requires(std::is_same_v || std::is_same_v) + void mls(ARMEmitter::SubRegSize size, T rd, T rn, T rm, uint32_t Index) { + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i16Bit || size == ARMEmitter::SubRegSize::i32Bit, "Invalid destination size"); - if (size == FEXCore::ARMEmitter::SubRegSize::i16Bit) { + if (size == ARMEmitter::SubRegSize::i16Bit) { LOGMAN_THROW_A_FMT(rm.Idx() < 16, "Rm can't be v16-v31 with half source size"); } LOGMAN_THROW_A_FMT(Index < SubRegSizeInBits(size), "Index must be less than the source register size"); uint32_t H, L, M; - if (size == FEXCore::ARMEmitter::SubRegSize::i16Bit) { + if (size == ARMEmitter::SubRegSize::i16Bit) { // Index encoded in H:L:M H = (Index >> 2) & 1; L = (Index >> 1) & 1; @@ -4461,17 +4461,17 @@ public: } ///< size is destination size - void umlsl(FEXCore::ARMEmitter::SubRegSize size, FEXCore::ARMEmitter::VRegister rd, FEXCore::ARMEmitter::VRegister rn, FEXCore::ARMEmitter::VRegister rm, uint32_t Index) { - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i32Bit || size == FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid destination size"); + void umlsl(ARMEmitter::SubRegSize size, ARMEmitter::VRegister rd, ARMEmitter::VRegister rn, ARMEmitter::VRegister rm, uint32_t Index) { + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i32Bit || size == ARMEmitter::SubRegSize::i64Bit, "Invalid destination size"); - if (size == FEXCore::ARMEmitter::SubRegSize::i32Bit) { + if (size == ARMEmitter::SubRegSize::i32Bit) { LOGMAN_THROW_A_FMT(rm.Idx() < 16, "Rm can't be v16-v31 with half source size"); } - const auto EncodedSubRegSize = FEXCore::ARMEmitter::SubRegSize(FEXCore::ToUnderlying(size) - 1); + const auto EncodedSubRegSize = ARMEmitter::SubRegSize(FEXCore::ToUnderlying(size) - 1); LOGMAN_THROW_A_FMT(Index < SubRegSizeInBits(EncodedSubRegSize), "Index must be less than the source register size"); uint32_t H, L, M; - if (size == FEXCore::ARMEmitter::SubRegSize::i32Bit) { + if (size == ARMEmitter::SubRegSize::i32Bit) { // Index encoded in H:L:M H = (Index >> 2) & 1; L = (Index >> 1) & 1; @@ -4487,17 +4487,17 @@ public: ASIMDVectorXIndexedElement(0b1, L, M, 0b0110, H, EncodedSubRegSize, rm.D(), rn.D(), rd.D()); } ///< size is destination size - void umlsl2(FEXCore::ARMEmitter::SubRegSize size, FEXCore::ARMEmitter::VRegister rd, FEXCore::ARMEmitter::VRegister rn, FEXCore::ARMEmitter::VRegister rm, uint32_t Index) { - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i32Bit || size == FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid destination size"); + void umlsl2(ARMEmitter::SubRegSize size, ARMEmitter::VRegister rd, ARMEmitter::VRegister rn, ARMEmitter::VRegister rm, uint32_t Index) { + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i32Bit || size == ARMEmitter::SubRegSize::i64Bit, "Invalid destination size"); - if (size == FEXCore::ARMEmitter::SubRegSize::i32Bit) { + if (size == ARMEmitter::SubRegSize::i32Bit) { LOGMAN_THROW_A_FMT(rm.Idx() < 16, "Rm can't be v16-v31 with half source size"); } - const auto EncodedSubRegSize = FEXCore::ARMEmitter::SubRegSize(FEXCore::ToUnderlying(size) - 1); + const auto EncodedSubRegSize = ARMEmitter::SubRegSize(FEXCore::ToUnderlying(size) - 1); LOGMAN_THROW_A_FMT(Index < SubRegSizeInBits(EncodedSubRegSize), "Index must be less than the source register size"); uint32_t H, L, M; - if (size == FEXCore::ARMEmitter::SubRegSize::i32Bit) { + if (size == ARMEmitter::SubRegSize::i32Bit) { // Index encoded in H:L:M H = (Index >> 2) & 1; L = (Index >> 1) & 1; @@ -4514,17 +4514,17 @@ public: } ///< size is destination size - void umull(FEXCore::ARMEmitter::SubRegSize size, FEXCore::ARMEmitter::VRegister rd, FEXCore::ARMEmitter::VRegister rn, FEXCore::ARMEmitter::VRegister rm, uint32_t Index) { - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i32Bit || size == FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid destination size"); + void umull(ARMEmitter::SubRegSize size, ARMEmitter::VRegister rd, ARMEmitter::VRegister rn, ARMEmitter::VRegister rm, uint32_t Index) { + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i32Bit || size == ARMEmitter::SubRegSize::i64Bit, "Invalid destination size"); - if (size == FEXCore::ARMEmitter::SubRegSize::i32Bit) { + if (size == ARMEmitter::SubRegSize::i32Bit) { LOGMAN_THROW_A_FMT(rm.Idx() < 16, "Rm can't be v16-v31 with half source size"); } - const auto EncodedSubRegSize = FEXCore::ARMEmitter::SubRegSize(FEXCore::ToUnderlying(size) - 1); + const auto EncodedSubRegSize = ARMEmitter::SubRegSize(FEXCore::ToUnderlying(size) - 1); LOGMAN_THROW_A_FMT(Index < SubRegSizeInBits(EncodedSubRegSize), "Index must be less than the source register size"); uint32_t H, L, M; - if (size == FEXCore::ARMEmitter::SubRegSize::i32Bit) { + if (size == ARMEmitter::SubRegSize::i32Bit) { // Index encoded in H:L:M H = (Index >> 2) & 1; L = (Index >> 1) & 1; @@ -4540,17 +4540,17 @@ public: ASIMDVectorXIndexedElement(0b1, L, M, 0b1010, H, EncodedSubRegSize, rm.D(), rn.D(), rd.D()); } ///< size is destination size - void umull2(FEXCore::ARMEmitter::SubRegSize size, FEXCore::ARMEmitter::VRegister rd, FEXCore::ARMEmitter::VRegister rn, FEXCore::ARMEmitter::VRegister rm, uint32_t Index) { - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i32Bit || size == FEXCore::ARMEmitter::SubRegSize::i64Bit, "Invalid destination size"); + void umull2(ARMEmitter::SubRegSize size, ARMEmitter::VRegister rd, ARMEmitter::VRegister rn, ARMEmitter::VRegister rm, uint32_t Index) { + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i32Bit || size == ARMEmitter::SubRegSize::i64Bit, "Invalid destination size"); - if (size == FEXCore::ARMEmitter::SubRegSize::i32Bit) { + if (size == ARMEmitter::SubRegSize::i32Bit) { LOGMAN_THROW_A_FMT(rm.Idx() < 16, "Rm can't be v16-v31 with half source size"); } - const auto EncodedSubRegSize = FEXCore::ARMEmitter::SubRegSize(FEXCore::ToUnderlying(size) - 1); + const auto EncodedSubRegSize = ARMEmitter::SubRegSize(FEXCore::ToUnderlying(size) - 1); LOGMAN_THROW_A_FMT(Index < SubRegSizeInBits(EncodedSubRegSize), "Index must be less than the source register size"); uint32_t H, L, M; - if (size == FEXCore::ARMEmitter::SubRegSize::i32Bit) { + if (size == ARMEmitter::SubRegSize::i32Bit) { // Index encoded in H:L:M H = (Index >> 2) & 1; L = (Index >> 1) & 1; @@ -4567,17 +4567,17 @@ public: } template - requires(std::is_same_v || std::is_same_v) - void sqrdmlah(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, T rm, uint32_t Index) { - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i16Bit || size == FEXCore::ARMEmitter::SubRegSize::i32Bit, "Invalid destination size"); + requires(std::is_same_v || std::is_same_v) + void sqrdmlah(ARMEmitter::SubRegSize size, T rd, T rn, T rm, uint32_t Index) { + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i16Bit || size == ARMEmitter::SubRegSize::i32Bit, "Invalid destination size"); - if (size == FEXCore::ARMEmitter::SubRegSize::i16Bit) { + if (size == ARMEmitter::SubRegSize::i16Bit) { LOGMAN_THROW_A_FMT(rm.Idx() < 16, "Rm can't be v16-v31 with half source size"); } LOGMAN_THROW_A_FMT(Index < SubRegSizeInBits(size), "Index must be less than the source register size"); uint32_t H, L, M; - if (size == FEXCore::ARMEmitter::SubRegSize::i16Bit) { + if (size == ARMEmitter::SubRegSize::i16Bit) { // Index encoded in H:L:M H = (Index >> 2) & 1; L = (Index >> 1) & 1; @@ -4593,7 +4593,7 @@ public: ASIMDVectorXIndexedElement(0b1, L, M, 0b1101, H, size, rm, rn, rd); } template - requires(std::is_same_v || std::is_same_v) + requires(std::is_same_v || std::is_same_v) void udot(T rd, T rn, T rm, uint32_t Index) { LOGMAN_THROW_A_FMT(Index < 4, "Index must be less than the source register size"); @@ -4603,21 +4603,21 @@ public: H = (Index >> 1) & 1; L = (Index >> 0) & 1; M = 0; - ASIMDVectorXIndexedElement(0b1, L, M, 0b1110, H, FEXCore::ARMEmitter::SubRegSize::i32Bit, rm, rn, rd); + ASIMDVectorXIndexedElement(0b1, L, M, 0b1110, H, ARMEmitter::SubRegSize::i32Bit, rm, rn, rd); } template - requires(std::is_same_v || std::is_same_v) - void sqrdmlsh(FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, T rm, uint32_t Index) { - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i16Bit || size == FEXCore::ARMEmitter::SubRegSize::i32Bit, "Invalid destination size"); + requires(std::is_same_v || std::is_same_v) + void sqrdmlsh(ARMEmitter::SubRegSize size, T rd, T rn, T rm, uint32_t Index) { + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i16Bit || size == ARMEmitter::SubRegSize::i32Bit, "Invalid destination size"); - if (size == FEXCore::ARMEmitter::SubRegSize::i16Bit) { + if (size == ARMEmitter::SubRegSize::i16Bit) { LOGMAN_THROW_A_FMT(rm.Idx() < 16, "Rm can't be v16-v31 with half source size"); } LOGMAN_THROW_A_FMT(Index < SubRegSizeInBits(size), "Index must be less than the source register size"); uint32_t H, L, M; - if (size == FEXCore::ARMEmitter::SubRegSize::i16Bit) { + if (size == ARMEmitter::SubRegSize::i16Bit) { // Index encoded in H:L:M H = (Index >> 2) & 1; L = (Index >> 1) & 1; @@ -4642,8 +4642,8 @@ public: // Cryptographic two-register SHA 512 // TODO // Conversion between floating-point and fixed-point - void scvtf(FEXCore::ARMEmitter::ScalarRegSize ScalarSize, FEXCore::ARMEmitter::VRegister rd, FEXCore::ARMEmitter::Size GPRSize, FEXCore::ARMEmitter::Register rn, uint32_t FractionalBits) { - LOGMAN_THROW_A_FMT(FractionalBits >= 1 && FractionalBits <= FEXCore::ARMEmitter::RegSizeInBits(GPRSize), "Fractional bits out of range"); + void scvtf(ARMEmitter::ScalarRegSize ScalarSize, ARMEmitter::VRegister rd, ARMEmitter::Size GPRSize, ARMEmitter::Register rn, uint32_t FractionalBits) { + LOGMAN_THROW_A_FMT(FractionalBits >= 1 && FractionalBits <= ARMEmitter::RegSizeInBits(GPRSize), "Fractional bits out of range"); uint32_t Scale = 64 - FractionalBits; const auto ConvertedSize = @@ -4654,8 +4654,8 @@ public: ScalarConvertBetweenFPAndFixed(0, 0b00, 0b010, Scale, GPRSize, ConvertedSize, rn, rd); } - void ucvtf(FEXCore::ARMEmitter::ScalarRegSize ScalarSize, FEXCore::ARMEmitter::VRegister rd, FEXCore::ARMEmitter::Size GPRSize, FEXCore::ARMEmitter::Register rn, uint32_t FractionalBits) { - LOGMAN_THROW_A_FMT(FractionalBits >= 1 && FractionalBits <= FEXCore::ARMEmitter::RegSizeInBits(GPRSize), "Fractional bits out of range"); + void ucvtf(ARMEmitter::ScalarRegSize ScalarSize, ARMEmitter::VRegister rd, ARMEmitter::Size GPRSize, ARMEmitter::Register rn, uint32_t FractionalBits) { + LOGMAN_THROW_A_FMT(FractionalBits >= 1 && FractionalBits <= ARMEmitter::RegSizeInBits(GPRSize), "Fractional bits out of range"); uint32_t Scale = 64 - FractionalBits; const auto ConvertedSize = @@ -4666,8 +4666,8 @@ public: ScalarConvertBetweenFPAndFixed(0, 0b00, 0b011, Scale, GPRSize, ConvertedSize, rn, rd); } - void fcvtzs(FEXCore::ARMEmitter::Size GPRSize, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::ScalarRegSize ScalarSize, FEXCore::ARMEmitter::VRegister rn, uint32_t FractionalBits) { - LOGMAN_THROW_A_FMT(FractionalBits >= 1 && FractionalBits <= FEXCore::ARMEmitter::RegSizeInBits(GPRSize), "Fractional bits out of range"); + void fcvtzs(ARMEmitter::Size GPRSize, ARMEmitter::Register rd, ARMEmitter::ScalarRegSize ScalarSize, ARMEmitter::VRegister rn, uint32_t FractionalBits) { + LOGMAN_THROW_A_FMT(FractionalBits >= 1 && FractionalBits <= ARMEmitter::RegSizeInBits(GPRSize), "Fractional bits out of range"); uint32_t Scale = 64 - FractionalBits; const auto ConvertedSize = @@ -4678,8 +4678,8 @@ public: ScalarConvertBetweenFPAndFixed(0, 0b11, 0b000, Scale, GPRSize, ConvertedSize, rn, rd); } - void fcvtzu(FEXCore::ARMEmitter::Size GPRSize, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::ScalarRegSize ScalarSize, FEXCore::ARMEmitter::VRegister rn, uint32_t FractionalBits) { - LOGMAN_THROW_A_FMT(FractionalBits >= 1 && FractionalBits <= FEXCore::ARMEmitter::RegSizeInBits(GPRSize), "Fractional bits out of range"); + void fcvtzu(ARMEmitter::Size GPRSize, ARMEmitter::Register rd, ARMEmitter::ScalarRegSize ScalarSize, ARMEmitter::VRegister rn, uint32_t FractionalBits) { + LOGMAN_THROW_A_FMT(FractionalBits >= 1 && FractionalBits <= ARMEmitter::RegSizeInBits(GPRSize), "Fractional bits out of range"); uint32_t Scale = 64 - FractionalBits; const auto ConvertedSize = @@ -4691,200 +4691,200 @@ public: } // Conversion between floating-point and integer - void fcvtns(FEXCore::ARMEmitter::Size size, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::HRegister rn) { + void fcvtns(ARMEmitter::Size size, ARMEmitter::Register rd, ARMEmitter::HRegister rn) { constexpr uint32_t Op = 0b0001'1110'001 << 21; - ASIMDFloatConvBetweenInt(Op, size, 0, 0b11, 0b00, 0b000, rd, FEXCore::ARMEmitter::ToReg(rn)); + ASIMDFloatConvBetweenInt(Op, size, 0, 0b11, 0b00, 0b000, rd, ARMEmitter::ToReg(rn)); } - void fcvtns(FEXCore::ARMEmitter::Size size, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::SRegister rn) { + void fcvtns(ARMEmitter::Size size, ARMEmitter::Register rd, ARMEmitter::SRegister rn) { constexpr uint32_t Op = 0b0001'1110'001 << 21; - ASIMDFloatConvBetweenInt(Op, size, 0, 0b00, 0b00, 0b000, rd, FEXCore::ARMEmitter::ToReg(rn)); + ASIMDFloatConvBetweenInt(Op, size, 0, 0b00, 0b00, 0b000, rd, ARMEmitter::ToReg(rn)); } - void fcvtns(FEXCore::ARMEmitter::Size size, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::DRegister rn) { + void fcvtns(ARMEmitter::Size size, ARMEmitter::Register rd, ARMEmitter::DRegister rn) { constexpr uint32_t Op = 0b0001'1110'001 << 21; - ASIMDFloatConvBetweenInt(Op, size, 0, 0b01, 0b00, 0b000, rd, FEXCore::ARMEmitter::ToReg(rn)); + ASIMDFloatConvBetweenInt(Op, size, 0, 0b01, 0b00, 0b000, rd, ARMEmitter::ToReg(rn)); } - void fcvtnu(FEXCore::ARMEmitter::Size size, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::HRegister rn) { + void fcvtnu(ARMEmitter::Size size, ARMEmitter::Register rd, ARMEmitter::HRegister rn) { constexpr uint32_t Op = 0b0001'1110'001 << 21; - ASIMDFloatConvBetweenInt(Op, size, 0, 0b11, 0b00, 0b001, rd, FEXCore::ARMEmitter::ToReg(rn)); + ASIMDFloatConvBetweenInt(Op, size, 0, 0b11, 0b00, 0b001, rd, ARMEmitter::ToReg(rn)); } - void fcvtnu(FEXCore::ARMEmitter::Size size, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::SRegister rn) { + void fcvtnu(ARMEmitter::Size size, ARMEmitter::Register rd, ARMEmitter::SRegister rn) { constexpr uint32_t Op = 0b0001'1110'001 << 21; - ASIMDFloatConvBetweenInt(Op, size, 0, 0b00, 0b00, 0b001, rd, FEXCore::ARMEmitter::ToReg(rn)); + ASIMDFloatConvBetweenInt(Op, size, 0, 0b00, 0b00, 0b001, rd, ARMEmitter::ToReg(rn)); } - void fcvtnu(FEXCore::ARMEmitter::Size size, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::DRegister rn) { + void fcvtnu(ARMEmitter::Size size, ARMEmitter::Register rd, ARMEmitter::DRegister rn) { constexpr uint32_t Op = 0b0001'1110'001 << 21; - ASIMDFloatConvBetweenInt(Op, size, 0, 0b01, 0b00, 0b001, rd, FEXCore::ARMEmitter::ToReg(rn)); + ASIMDFloatConvBetweenInt(Op, size, 0, 0b01, 0b00, 0b001, rd, ARMEmitter::ToReg(rn)); } - void scvtf(FEXCore::ARMEmitter::Size size, FEXCore::ARMEmitter::HRegister rd, FEXCore::ARMEmitter::Register rn) { + void scvtf(ARMEmitter::Size size, ARMEmitter::HRegister rd, ARMEmitter::Register rn) { constexpr uint32_t Op = 0b0001'1110'001 << 21; - ASIMDFloatConvBetweenInt(Op, size, 0, 0b11, 0b00, 0b010, FEXCore::ARMEmitter::ToReg(rd), rn); + ASIMDFloatConvBetweenInt(Op, size, 0, 0b11, 0b00, 0b010, ARMEmitter::ToReg(rd), rn); } - void scvtf(FEXCore::ARMEmitter::Size size, FEXCore::ARMEmitter::SRegister rd, FEXCore::ARMEmitter::Register rn) { + void scvtf(ARMEmitter::Size size, ARMEmitter::SRegister rd, ARMEmitter::Register rn) { constexpr uint32_t Op = 0b0001'1110'001 << 21; - ASIMDFloatConvBetweenInt(Op, size, 0, 0b00, 0b00, 0b010, FEXCore::ARMEmitter::ToReg(rd), rn); + ASIMDFloatConvBetweenInt(Op, size, 0, 0b00, 0b00, 0b010, ARMEmitter::ToReg(rd), rn); } - void scvtf(FEXCore::ARMEmitter::Size size, FEXCore::ARMEmitter::DRegister rd, FEXCore::ARMEmitter::Register rn) { + void scvtf(ARMEmitter::Size size, ARMEmitter::DRegister rd, ARMEmitter::Register rn) { constexpr uint32_t Op = 0b0001'1110'001 << 21; - ASIMDFloatConvBetweenInt(Op, size, 0, 0b01, 0b00, 0b010, FEXCore::ARMEmitter::ToReg(rd), rn); + ASIMDFloatConvBetweenInt(Op, size, 0, 0b01, 0b00, 0b010, ARMEmitter::ToReg(rd), rn); } - void ucvtf(FEXCore::ARMEmitter::Size size, FEXCore::ARMEmitter::HRegister rd, FEXCore::ARMEmitter::Register rn) { + void ucvtf(ARMEmitter::Size size, ARMEmitter::HRegister rd, ARMEmitter::Register rn) { constexpr uint32_t Op = 0b0001'1110'001 << 21; - ASIMDFloatConvBetweenInt(Op, size, 0, 0b11, 0b00, 0b011, FEXCore::ARMEmitter::ToReg(rd), rn); + ASIMDFloatConvBetweenInt(Op, size, 0, 0b11, 0b00, 0b011, ARMEmitter::ToReg(rd), rn); } - void ucvtf(FEXCore::ARMEmitter::Size size, FEXCore::ARMEmitter::SRegister rd, FEXCore::ARMEmitter::Register rn) { + void ucvtf(ARMEmitter::Size size, ARMEmitter::SRegister rd, ARMEmitter::Register rn) { constexpr uint32_t Op = 0b0001'1110'001 << 21; - ASIMDFloatConvBetweenInt(Op, size, 0, 0b00, 0b00, 0b011, FEXCore::ARMEmitter::ToReg(rd), rn); + ASIMDFloatConvBetweenInt(Op, size, 0, 0b00, 0b00, 0b011, ARMEmitter::ToReg(rd), rn); } - void ucvtf(FEXCore::ARMEmitter::Size size, FEXCore::ARMEmitter::DRegister rd, FEXCore::ARMEmitter::Register rn) { + void ucvtf(ARMEmitter::Size size, ARMEmitter::DRegister rd, ARMEmitter::Register rn) { constexpr uint32_t Op = 0b0001'1110'001 << 21; - ASIMDFloatConvBetweenInt(Op, size, 0, 0b01, 0b00, 0b011, FEXCore::ARMEmitter::ToReg(rd), rn); + ASIMDFloatConvBetweenInt(Op, size, 0, 0b01, 0b00, 0b011, ARMEmitter::ToReg(rd), rn); } - void fcvtas(FEXCore::ARMEmitter::Size size, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::HRegister rn) { + void fcvtas(ARMEmitter::Size size, ARMEmitter::Register rd, ARMEmitter::HRegister rn) { constexpr uint32_t Op = 0b0001'1110'001 << 21; - ASIMDFloatConvBetweenInt(Op, size, 0, 0b11, 0b00, 0b100, rd, FEXCore::ARMEmitter::ToReg(rn)); + ASIMDFloatConvBetweenInt(Op, size, 0, 0b11, 0b00, 0b100, rd, ARMEmitter::ToReg(rn)); } - void fcvtas(FEXCore::ARMEmitter::Size size, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::SRegister rn) { + void fcvtas(ARMEmitter::Size size, ARMEmitter::Register rd, ARMEmitter::SRegister rn) { constexpr uint32_t Op = 0b0001'1110'001 << 21; - ASIMDFloatConvBetweenInt(Op, size, 0, 0b00, 0b00, 0b100, rd, FEXCore::ARMEmitter::ToReg(rn)); + ASIMDFloatConvBetweenInt(Op, size, 0, 0b00, 0b00, 0b100, rd, ARMEmitter::ToReg(rn)); } - void fcvtas(FEXCore::ARMEmitter::Size size, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::DRegister rn) { + void fcvtas(ARMEmitter::Size size, ARMEmitter::Register rd, ARMEmitter::DRegister rn) { constexpr uint32_t Op = 0b0001'1110'001 << 21; - ASIMDFloatConvBetweenInt(Op, size, 0, 0b01, 0b00, 0b100, rd, FEXCore::ARMEmitter::ToReg(rn)); + ASIMDFloatConvBetweenInt(Op, size, 0, 0b01, 0b00, 0b100, rd, ARMEmitter::ToReg(rn)); } - void fcvtau(FEXCore::ARMEmitter::Size size, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::HRegister rn) { + void fcvtau(ARMEmitter::Size size, ARMEmitter::Register rd, ARMEmitter::HRegister rn) { constexpr uint32_t Op = 0b0001'1110'001 << 21; - ASIMDFloatConvBetweenInt(Op, size, 0, 0b11, 0b00, 0b101, rd, FEXCore::ARMEmitter::ToReg(rn)); + ASIMDFloatConvBetweenInt(Op, size, 0, 0b11, 0b00, 0b101, rd, ARMEmitter::ToReg(rn)); } - void fcvtau(FEXCore::ARMEmitter::Size size, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::SRegister rn) { + void fcvtau(ARMEmitter::Size size, ARMEmitter::Register rd, ARMEmitter::SRegister rn) { constexpr uint32_t Op = 0b0001'1110'001 << 21; - ASIMDFloatConvBetweenInt(Op, size, 0, 0b00, 0b00, 0b101, rd, FEXCore::ARMEmitter::ToReg(rn)); + ASIMDFloatConvBetweenInt(Op, size, 0, 0b00, 0b00, 0b101, rd, ARMEmitter::ToReg(rn)); } - void fcvtau(FEXCore::ARMEmitter::Size size, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::DRegister rn) { + void fcvtau(ARMEmitter::Size size, ARMEmitter::Register rd, ARMEmitter::DRegister rn) { constexpr uint32_t Op = 0b0001'1110'001 << 21; - ASIMDFloatConvBetweenInt(Op, size, 0, 0b01, 0b00, 0b101, rd, FEXCore::ARMEmitter::ToReg(rn)); + ASIMDFloatConvBetweenInt(Op, size, 0, 0b01, 0b00, 0b101, rd, ARMEmitter::ToReg(rn)); } - void fmov(FEXCore::ARMEmitter::Size size, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::HRegister rn) { + void fmov(ARMEmitter::Size size, ARMEmitter::Register rd, ARMEmitter::HRegister rn) { constexpr uint32_t Op = 0b0001'1110'001 << 21; - ASIMDFloatConvBetweenInt(Op, size, 0, 0b11, 0b00, 0b110, rd, FEXCore::ARMEmitter::ToReg(rn)); + ASIMDFloatConvBetweenInt(Op, size, 0, 0b11, 0b00, 0b110, rd, ARMEmitter::ToReg(rn)); } - void fmov(FEXCore::ARMEmitter::Size size, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::SRegister rn) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::Size::i64Bit, "Can't move SReg to 64-bit"); + void fmov(ARMEmitter::Size size, ARMEmitter::Register rd, ARMEmitter::SRegister rn) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::Size::i64Bit, "Can't move SReg to 64-bit"); constexpr uint32_t Op = 0b0001'1110'001 << 21; - ASIMDFloatConvBetweenInt(Op, size, 0, 0b00, 0b00, 0b110, rd, FEXCore::ARMEmitter::ToReg(rn)); + ASIMDFloatConvBetweenInt(Op, size, 0, 0b00, 0b00, 0b110, rd, ARMEmitter::ToReg(rn)); } - void fmov(FEXCore::ARMEmitter::Size size, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::DRegister rn) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::Size::i32Bit, "Can't move DReg to 32-bit"); + void fmov(ARMEmitter::Size size, ARMEmitter::Register rd, ARMEmitter::DRegister rn) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::Size::i32Bit, "Can't move DReg to 32-bit"); constexpr uint32_t Op = 0b0001'1110'001 << 21; - ASIMDFloatConvBetweenInt(Op, size, 0, 0b01, 0b00, 0b110, rd, FEXCore::ARMEmitter::ToReg(rn)); + ASIMDFloatConvBetweenInt(Op, size, 0, 0b01, 0b00, 0b110, rd, ARMEmitter::ToReg(rn)); } - void fmov(FEXCore::ARMEmitter::Size size, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::VRegister rn, bool Upper) { + void fmov(ARMEmitter::Size size, ARMEmitter::Register rd, ARMEmitter::VRegister rn, bool Upper) { if (Upper) { - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::Size::i64Bit, "Can only move upper with 64-bit elements"); + LOGMAN_THROW_AA_FMT(size == ARMEmitter::Size::i64Bit, "Can only move upper with 64-bit elements"); } constexpr uint32_t Op = 0b0001'1110'001 << 21; - ASIMDFloatConvBetweenInt(Op, size, 0, Upper ? 0b10 : 0b01, Upper ? 0b01 : 0b00, 0b110, rd, FEXCore::ARMEmitter::ToReg(rn)); + ASIMDFloatConvBetweenInt(Op, size, 0, Upper ? 0b10 : 0b01, Upper ? 0b01 : 0b00, 0b110, rd, ARMEmitter::ToReg(rn)); } - void fmov(FEXCore::ARMEmitter::Size size, FEXCore::ARMEmitter::HRegister rd, FEXCore::ARMEmitter::Register rn) { + void fmov(ARMEmitter::Size size, ARMEmitter::HRegister rd, ARMEmitter::Register rn) { constexpr uint32_t Op = 0b0001'1110'001 << 21; - ASIMDFloatConvBetweenInt(Op, size, 0, 0b11, 0b00, 0b111, FEXCore::ARMEmitter::ToReg(rd), rn); + ASIMDFloatConvBetweenInt(Op, size, 0, 0b11, 0b00, 0b111, ARMEmitter::ToReg(rd), rn); } - void fmov(FEXCore::ARMEmitter::Size size, FEXCore::ARMEmitter::SRegister rd, FEXCore::ARMEmitter::Register rn) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::Size::i64Bit, "Can't move SReg to 64-bit"); + void fmov(ARMEmitter::Size size, ARMEmitter::SRegister rd, ARMEmitter::Register rn) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::Size::i64Bit, "Can't move SReg to 64-bit"); constexpr uint32_t Op = 0b0001'1110'001 << 21; - ASIMDFloatConvBetweenInt(Op, size, 0, 0b00, 0b00, 0b111, FEXCore::ARMEmitter::ToReg(rd), rn); + ASIMDFloatConvBetweenInt(Op, size, 0, 0b00, 0b00, 0b111, ARMEmitter::ToReg(rd), rn); } - void fmov(FEXCore::ARMEmitter::Size size, FEXCore::ARMEmitter::DRegister rd, FEXCore::ARMEmitter::Register rn) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::Size::i32Bit, "Can't move DReg to 32-bit"); + void fmov(ARMEmitter::Size size, ARMEmitter::DRegister rd, ARMEmitter::Register rn) { + LOGMAN_THROW_AA_FMT(size != ARMEmitter::Size::i32Bit, "Can't move DReg to 32-bit"); constexpr uint32_t Op = 0b0001'1110'001 << 21; - ASIMDFloatConvBetweenInt(Op, size, 0, 0b01, 0b00, 0b111, FEXCore::ARMEmitter::ToReg(rd), rn); + ASIMDFloatConvBetweenInt(Op, size, 0, 0b01, 0b00, 0b111, ARMEmitter::ToReg(rd), rn); } - void fmov(FEXCore::ARMEmitter::Size size, FEXCore::ARMEmitter::VRegister rd, FEXCore::ARMEmitter::Register rn, bool Upper) { + void fmov(ARMEmitter::Size size, ARMEmitter::VRegister rd, ARMEmitter::Register rn, bool Upper) { if (Upper) { - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::Size::i64Bit, "Can only move upper with 64-bit elements"); + LOGMAN_THROW_AA_FMT(size == ARMEmitter::Size::i64Bit, "Can only move upper with 64-bit elements"); } constexpr uint32_t Op = 0b0001'1110'001 << 21; - ASIMDFloatConvBetweenInt(Op, size, 0, Upper ? 0b10 : 0b01, Upper ? 0b01 : 0b00, 0b111, FEXCore::ARMEmitter::ToReg(rd), rn); + ASIMDFloatConvBetweenInt(Op, size, 0, Upper ? 0b10 : 0b01, Upper ? 0b01 : 0b00, 0b111, ARMEmitter::ToReg(rd), rn); } - void fcvtps(FEXCore::ARMEmitter::Size size, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::HRegister rn) { + void fcvtps(ARMEmitter::Size size, ARMEmitter::Register rd, ARMEmitter::HRegister rn) { constexpr uint32_t Op = 0b0001'1110'001 << 21; - ASIMDFloatConvBetweenInt(Op, size, 0, 0b11, 0b01, 0b000, rd, FEXCore::ARMEmitter::ToReg(rn)); + ASIMDFloatConvBetweenInt(Op, size, 0, 0b11, 0b01, 0b000, rd, ARMEmitter::ToReg(rn)); } - void fcvtps(FEXCore::ARMEmitter::Size size, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::SRegister rn) { + void fcvtps(ARMEmitter::Size size, ARMEmitter::Register rd, ARMEmitter::SRegister rn) { constexpr uint32_t Op = 0b0001'1110'001 << 21; - ASIMDFloatConvBetweenInt(Op, size, 0, 0b00, 0b01, 0b000, rd, FEXCore::ARMEmitter::ToReg(rn)); + ASIMDFloatConvBetweenInt(Op, size, 0, 0b00, 0b01, 0b000, rd, ARMEmitter::ToReg(rn)); } - void fcvtps(FEXCore::ARMEmitter::Size size, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::DRegister rn) { + void fcvtps(ARMEmitter::Size size, ARMEmitter::Register rd, ARMEmitter::DRegister rn) { constexpr uint32_t Op = 0b0001'1110'001 << 21; - ASIMDFloatConvBetweenInt(Op, size, 0, 0b01, 0b01, 0b000, rd, FEXCore::ARMEmitter::ToReg(rn)); + ASIMDFloatConvBetweenInt(Op, size, 0, 0b01, 0b01, 0b000, rd, ARMEmitter::ToReg(rn)); } - void fcvtpu(FEXCore::ARMEmitter::Size size, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::HRegister rn) { + void fcvtpu(ARMEmitter::Size size, ARMEmitter::Register rd, ARMEmitter::HRegister rn) { constexpr uint32_t Op = 0b0001'1110'001 << 21; - ASIMDFloatConvBetweenInt(Op, size, 0, 0b11, 0b01, 0b001, rd, FEXCore::ARMEmitter::ToReg(rn)); + ASIMDFloatConvBetweenInt(Op, size, 0, 0b11, 0b01, 0b001, rd, ARMEmitter::ToReg(rn)); } - void fcvtpu(FEXCore::ARMEmitter::Size size, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::SRegister rn) { + void fcvtpu(ARMEmitter::Size size, ARMEmitter::Register rd, ARMEmitter::SRegister rn) { constexpr uint32_t Op = 0b0001'1110'001 << 21; - ASIMDFloatConvBetweenInt(Op, size, 0, 0b00, 0b01, 0b001, rd, FEXCore::ARMEmitter::ToReg(rn)); + ASIMDFloatConvBetweenInt(Op, size, 0, 0b00, 0b01, 0b001, rd, ARMEmitter::ToReg(rn)); } - void fcvtpu(FEXCore::ARMEmitter::Size size, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::DRegister rn) { + void fcvtpu(ARMEmitter::Size size, ARMEmitter::Register rd, ARMEmitter::DRegister rn) { constexpr uint32_t Op = 0b0001'1110'001 << 21; - ASIMDFloatConvBetweenInt(Op, size, 0, 0b01, 0b01, 0b001, rd, FEXCore::ARMEmitter::ToReg(rn)); + ASIMDFloatConvBetweenInt(Op, size, 0, 0b01, 0b01, 0b001, rd, ARMEmitter::ToReg(rn)); } - void fcvtms(FEXCore::ARMEmitter::Size size, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::HRegister rn) { + void fcvtms(ARMEmitter::Size size, ARMEmitter::Register rd, ARMEmitter::HRegister rn) { constexpr uint32_t Op = 0b0001'1110'001 << 21; - ASIMDFloatConvBetweenInt(Op, size, 0, 0b11, 0b10, 0b000, rd, FEXCore::ARMEmitter::ToReg(rn)); + ASIMDFloatConvBetweenInt(Op, size, 0, 0b11, 0b10, 0b000, rd, ARMEmitter::ToReg(rn)); } - void fcvtms(FEXCore::ARMEmitter::Size size, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::SRegister rn) { + void fcvtms(ARMEmitter::Size size, ARMEmitter::Register rd, ARMEmitter::SRegister rn) { constexpr uint32_t Op = 0b0001'1110'001 << 21; - ASIMDFloatConvBetweenInt(Op, size, 0, 0b00, 0b10, 0b000, rd, FEXCore::ARMEmitter::ToReg(rn)); + ASIMDFloatConvBetweenInt(Op, size, 0, 0b00, 0b10, 0b000, rd, ARMEmitter::ToReg(rn)); } - void fcvtms(FEXCore::ARMEmitter::Size size, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::DRegister rn) { + void fcvtms(ARMEmitter::Size size, ARMEmitter::Register rd, ARMEmitter::DRegister rn) { constexpr uint32_t Op = 0b0001'1110'001 << 21; - ASIMDFloatConvBetweenInt(Op, size, 0, 0b01, 0b10, 0b000, rd, FEXCore::ARMEmitter::ToReg(rn)); + ASIMDFloatConvBetweenInt(Op, size, 0, 0b01, 0b10, 0b000, rd, ARMEmitter::ToReg(rn)); } - void fcvtmu(FEXCore::ARMEmitter::Size size, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::HRegister rn) { + void fcvtmu(ARMEmitter::Size size, ARMEmitter::Register rd, ARMEmitter::HRegister rn) { constexpr uint32_t Op = 0b0001'1110'001 << 21; - ASIMDFloatConvBetweenInt(Op, size, 0, 0b11, 0b10, 0b001, rd, FEXCore::ARMEmitter::ToReg(rn)); + ASIMDFloatConvBetweenInt(Op, size, 0, 0b11, 0b10, 0b001, rd, ARMEmitter::ToReg(rn)); } - void fcvtmu(FEXCore::ARMEmitter::Size size, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::SRegister rn) { + void fcvtmu(ARMEmitter::Size size, ARMEmitter::Register rd, ARMEmitter::SRegister rn) { constexpr uint32_t Op = 0b0001'1110'001 << 21; - ASIMDFloatConvBetweenInt(Op, size, 0, 0b00, 0b10, 0b001, rd, FEXCore::ARMEmitter::ToReg(rn)); + ASIMDFloatConvBetweenInt(Op, size, 0, 0b00, 0b10, 0b001, rd, ARMEmitter::ToReg(rn)); } - void fcvtmu(FEXCore::ARMEmitter::Size size, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::DRegister rn) { + void fcvtmu(ARMEmitter::Size size, ARMEmitter::Register rd, ARMEmitter::DRegister rn) { constexpr uint32_t Op = 0b0001'1110'001 << 21; - ASIMDFloatConvBetweenInt(Op, size, 0, 0b01, 0b10, 0b001, rd, FEXCore::ARMEmitter::ToReg(rn)); + ASIMDFloatConvBetweenInt(Op, size, 0, 0b01, 0b10, 0b001, rd, ARMEmitter::ToReg(rn)); } - void fcvtzs(FEXCore::ARMEmitter::Size size, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::HRegister rn) { + void fcvtzs(ARMEmitter::Size size, ARMEmitter::Register rd, ARMEmitter::HRegister rn) { constexpr uint32_t Op = 0b0001'1110'001 << 21; - ASIMDFloatConvBetweenInt(Op, size, 0, 0b11, 0b11, 0b000, rd, FEXCore::ARMEmitter::ToReg(rn)); + ASIMDFloatConvBetweenInt(Op, size, 0, 0b11, 0b11, 0b000, rd, ARMEmitter::ToReg(rn)); } - void fcvtzs(FEXCore::ARMEmitter::Size size, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::SRegister rn) { + void fcvtzs(ARMEmitter::Size size, ARMEmitter::Register rd, ARMEmitter::SRegister rn) { constexpr uint32_t Op = 0b0001'1110'001 << 21; - ASIMDFloatConvBetweenInt(Op, size, 0, 0b00, 0b11, 0b000, rd, FEXCore::ARMEmitter::ToReg(rn)); + ASIMDFloatConvBetweenInt(Op, size, 0, 0b00, 0b11, 0b000, rd, ARMEmitter::ToReg(rn)); } - void fcvtzs(FEXCore::ARMEmitter::Size size, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::DRegister rn) { + void fcvtzs(ARMEmitter::Size size, ARMEmitter::Register rd, ARMEmitter::DRegister rn) { constexpr uint32_t Op = 0b0001'1110'001 << 21; - ASIMDFloatConvBetweenInt(Op, size, 0, 0b01, 0b11, 0b000, rd, FEXCore::ARMEmitter::ToReg(rn)); + ASIMDFloatConvBetweenInt(Op, size, 0, 0b01, 0b11, 0b000, rd, ARMEmitter::ToReg(rn)); } - void fcvtzs(FEXCore::ARMEmitter::Size size, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::VRegister rn) { + void fcvtzs(ARMEmitter::Size size, ARMEmitter::Register rd, ARMEmitter::VRegister rn) { constexpr uint32_t Op = 0b0001'1110'001 << 21; - ASIMDFloatConvBetweenInt(Op, size, 0, 0b01, 0b11, 0b000, rd, FEXCore::ARMEmitter::ToReg(rn)); + ASIMDFloatConvBetweenInt(Op, size, 0, 0b01, 0b11, 0b000, rd, ARMEmitter::ToReg(rn)); } - void fcvtzu(FEXCore::ARMEmitter::Size size, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::HRegister rn) { + void fcvtzu(ARMEmitter::Size size, ARMEmitter::Register rd, ARMEmitter::HRegister rn) { constexpr uint32_t Op = 0b0001'1110'001 << 21; - ASIMDFloatConvBetweenInt(Op, size, 0, 0b11, 0b11, 0b001, rd, FEXCore::ARMEmitter::ToReg(rn)); + ASIMDFloatConvBetweenInt(Op, size, 0, 0b11, 0b11, 0b001, rd, ARMEmitter::ToReg(rn)); } - void fcvtzu(FEXCore::ARMEmitter::Size size, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::SRegister rn) { + void fcvtzu(ARMEmitter::Size size, ARMEmitter::Register rd, ARMEmitter::SRegister rn) { constexpr uint32_t Op = 0b0001'1110'001 << 21; - ASIMDFloatConvBetweenInt(Op, size, 0, 0b00, 0b11, 0b001, rd, FEXCore::ARMEmitter::ToReg(rn)); + ASIMDFloatConvBetweenInt(Op, size, 0, 0b00, 0b11, 0b001, rd, ARMEmitter::ToReg(rn)); } - void fcvtzu(FEXCore::ARMEmitter::Size size, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::DRegister rn) { + void fcvtzu(ARMEmitter::Size size, ARMEmitter::Register rd, ARMEmitter::DRegister rn) { constexpr uint32_t Op = 0b0001'1110'001 << 21; - ASIMDFloatConvBetweenInt(Op, size, 0, 0b01, 0b11, 0b001, rd, FEXCore::ARMEmitter::ToReg(rn)); + ASIMDFloatConvBetweenInt(Op, size, 0, 0b01, 0b11, 0b001, rd, ARMEmitter::ToReg(rn)); } private: // Cryptographic AES - void CryptoAES(uint32_t Op, uint32_t opcode, FEXCore::ARMEmitter::VRegister rd, FEXCore::ARMEmitter::VRegister rn) { + void CryptoAES(uint32_t Op, uint32_t opcode, ARMEmitter::VRegister rd, ARMEmitter::VRegister rn) { uint32_t Instr = Op; Instr |= opcode << 12; @@ -4894,7 +4894,7 @@ private: } // Cryptographic three-register SHA - void Crypto3RegSHA(uint32_t Op, uint32_t opcode, FEXCore::ARMEmitter::VRegister rd, FEXCore::ARMEmitter::VRegister rn, FEXCore::ARMEmitter::VRegister rm) { + void Crypto3RegSHA(uint32_t Op, uint32_t opcode, ARMEmitter::VRegister rd, ARMEmitter::VRegister rn, ARMEmitter::VRegister rm) { uint32_t Instr = Op; Instr |= Encode_rm(rm); @@ -4905,7 +4905,7 @@ private: } // Cryptographic two-register SHA - void Crypto2RegSHA(uint32_t Op, uint32_t opcode, FEXCore::ARMEmitter::VRegister rd, FEXCore::ARMEmitter::VRegister rn) { + void Crypto2RegSHA(uint32_t Op, uint32_t opcode, ARMEmitter::VRegister rd, ARMEmitter::VRegister rn) { uint32_t Instr = Op; Instr |= opcode << 12; @@ -4915,7 +4915,7 @@ private: } // Advanced SIMD table lookup - void ASIMDTable(uint32_t Op, uint32_t Q, uint32_t op2, uint32_t len, uint32_t op, FEXCore::ARMEmitter::VRegister rd, FEXCore::ARMEmitter::VRegister rn, FEXCore::ARMEmitter::VRegister rm) { + void ASIMDTable(uint32_t Op, uint32_t Q, uint32_t op2, uint32_t len, uint32_t op, ARMEmitter::VRegister rd, ARMEmitter::VRegister rn, ARMEmitter::VRegister rm) { uint32_t Instr = Op; Instr |= Q << 30; @@ -4929,7 +4929,7 @@ private: } // Advanced SIMD permute - void ASIMDPermute(uint32_t Op, uint32_t Q, FEXCore::ARMEmitter::SubRegSize size, uint32_t opcode, FEXCore::ARMEmitter::VRegister rd, FEXCore::ARMEmitter::VRegister rn, FEXCore::ARMEmitter::VRegister rm) { + void ASIMDPermute(uint32_t Op, uint32_t Q, ARMEmitter::SubRegSize size, uint32_t opcode, ARMEmitter::VRegister rd, ARMEmitter::VRegister rn, ARMEmitter::VRegister rm) { uint32_t Instr = Op; Instr |= Q << 30; @@ -4942,7 +4942,7 @@ private: } // Advanced SIMD extract - void ASIMDExtract(uint32_t Op, uint32_t Q, uint32_t op2, uint32_t imm4, FEXCore::ARMEmitter::VRegister rd, FEXCore::ARMEmitter::VRegister rn, FEXCore::ARMEmitter::VRegister rm) { + void ASIMDExtract(uint32_t Op, uint32_t Q, uint32_t op2, uint32_t imm4, ARMEmitter::VRegister rd, ARMEmitter::VRegister rn, ARMEmitter::VRegister rm) { uint32_t Instr = Op; Instr |= Q << 30; @@ -4956,9 +4956,9 @@ private: // Advanced SIMD two-register miscellaneous template - requires(std::is_same_v || std::is_same_v) - void ASIMD2RegMisc(uint32_t Op, uint32_t U, FEXCore::ARMEmitter::SubRegSize size, uint32_t opcode, T rd, T rn) { - constexpr uint32_t Q = std::is_same_v ? 1U << 30 : 0; + requires(std::is_same_v || std::is_same_v) + void ASIMD2RegMisc(uint32_t Op, uint32_t U, ARMEmitter::SubRegSize size, uint32_t opcode, T rd, T rn) { + constexpr uint32_t Q = std::is_same_v ? 1U << 30 : 0; uint32_t Instr = Op; Instr |= Q; @@ -4972,9 +4972,9 @@ private: // Advanced SIMD across lanes template - requires(std::is_same_v || std::is_same_v) - void ASIMDAcrossLanes(uint32_t Op, uint32_t U, FEXCore::ARMEmitter::SubRegSize size, uint32_t opcode, T rd, T rn) { - constexpr uint32_t Q = std::is_same_v ? 1U << 30 : 0; + requires(std::is_same_v || std::is_same_v) + void ASIMDAcrossLanes(uint32_t Op, uint32_t U, ARMEmitter::SubRegSize size, uint32_t opcode, T rd, T rn) { + constexpr uint32_t Q = std::is_same_v ? 1U << 30 : 0; uint32_t Instr = Op; Instr |= Q; @@ -4988,9 +4988,9 @@ private: // Advanced SIMD three different template - requires(std::is_same_v || std::is_same_v) - void ASIMD3Different(uint32_t Op, uint32_t U, uint32_t opcode, FEXCore::ARMEmitter::SubRegSize size, T rd, T rn, T rm) { - constexpr uint32_t Q = std::is_same_v ? 1U << 30 : 0; + requires(std::is_same_v || std::is_same_v) + void ASIMD3Different(uint32_t Op, uint32_t U, uint32_t opcode, ARMEmitter::SubRegSize size, T rd, T rn, T rm) { + constexpr uint32_t Q = std::is_same_v ? 1U << 30 : 0; uint32_t Instr = Op; Instr |= Q; @@ -5005,9 +5005,9 @@ private: // Advanced SIMD three same template - requires(std::is_same_v || std::is_same_v) - void ASIMD3Same(uint32_t Op, uint32_t U, FEXCore::ARMEmitter::SubRegSize size, uint32_t opcode, T rd, T rn, T rm) { - constexpr uint32_t Q = std::is_same_v ? 1U << 30 : 0; + requires(std::is_same_v || std::is_same_v) + void ASIMD3Same(uint32_t Op, uint32_t U, ARMEmitter::SubRegSize size, uint32_t opcode, T rd, T rn, T rm) { + constexpr uint32_t Q = std::is_same_v ? 1U << 30 : 0; uint32_t Instr = Op; Instr |= Q; @@ -5022,9 +5022,9 @@ private: // Advanced SIMD modified immediate template - requires(std::is_same_v || std::is_same_v) + requires(std::is_same_v || std::is_same_v) void ASIMDModifiedImm(uint32_t Op, uint32_t op, uint32_t cmode, uint32_t o2, uint32_t imm, T rd) { - constexpr uint32_t Q = std::is_same_v ? 1U << 30 : 0; + constexpr uint32_t Q = std::is_same_v ? 1U << 30 : 0; uint32_t Instr = Op; Instr |= Q; @@ -5046,9 +5046,9 @@ private: // Advanced SIMD shift by immediate template - requires(std::is_same_v || std::is_same_v) + requires(std::is_same_v || std::is_same_v) void ASIMDShiftByImm(uint32_t Op, uint32_t U, uint32_t immh, uint32_t immb, uint32_t opcode, T rn, T rd) { - constexpr uint32_t Q = std::is_same_v ? 1U << 30 : 0; + constexpr uint32_t Q = std::is_same_v ? 1U << 30 : 0; LOGMAN_THROW_A_FMT(immh != 0, "ImmH needs to not be zero"); uint32_t Instr = Op; @@ -5065,10 +5065,10 @@ private: // Advanced SIMD vector x indexed element template - requires(std::is_same_v || std::is_same_v) - void ASIMDVectorXIndexedElement(uint32_t U, uint32_t L, uint32_t M, uint32_t opcode, uint32_t H, FEXCore::ARMEmitter::SubRegSize size, T rm, T rn, T rd) { + requires(std::is_same_v || std::is_same_v) + void ASIMDVectorXIndexedElement(uint32_t U, uint32_t L, uint32_t M, uint32_t opcode, uint32_t H, ARMEmitter::SubRegSize size, T rm, T rn, T rd) { constexpr uint32_t Op = 0b0000'1111'0000'0000'0000'00 << 10; - constexpr uint32_t Q = std::is_same_v ? 1U << 30 : 0; + constexpr uint32_t Q = std::is_same_v ? 1U << 30 : 0; uint32_t Instr = Op; @@ -5090,10 +5090,10 @@ private: // Conversion between floating-point and fixed-point template void ScalarConvertBetweenFPAndFixed(uint32_t S, uint32_t rmode, uint32_t opcode, uint32_t scale, - FEXCore::ARMEmitter::Size GPRSize, uint32_t ScalarSize, + ARMEmitter::Size GPRSize, uint32_t ScalarSize, T rn, T2 rd) { constexpr uint32_t Op = 0b0001'1110'000 << 21; - const uint32_t SF = GPRSize == FEXCore::ARMEmitter::Size::i64Bit ? (1U << 31) : 0; + const uint32_t SF = GPRSize == ARMEmitter::Size::i64Bit ? (1U << 31) : 0; uint32_t Instr = Op; Instr |= SF; @@ -5108,8 +5108,8 @@ private: } // Conversion between floating-point and integer - void ASIMDFloatConvBetweenInt(uint32_t Op, FEXCore::ARMEmitter::Size s, uint32_t S, uint32_t ptype, uint32_t rmode, uint32_t opcode, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn) { - const uint32_t SF = s == FEXCore::ARMEmitter::Size::i64Bit ? (1U << 31) : 0; + void ASIMDFloatConvBetweenInt(uint32_t Op, ARMEmitter::Size s, uint32_t S, uint32_t ptype, uint32_t rmode, uint32_t opcode, ARMEmitter::Register rd, ARMEmitter::Register rn) { + const uint32_t SF = s == ARMEmitter::Size::i64Bit ? (1U << 31) : 0; uint32_t Instr = Op; @@ -5123,10 +5123,10 @@ private: dc32(Instr); } - template - requires(std::is_same_v || std::is_same_v) - void ASIMDLoadStoreMultipleStructure(uint32_t Op, uint32_t opcode, T rt, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm) { - constexpr uint32_t Q = std::is_same_v ? 1U << 30 : 0; + template + requires(std::is_same_v || std::is_same_v) + void ASIMDLoadStoreMultipleStructure(uint32_t Op, uint32_t opcode, T rt, ARMEmitter::Register rn, ARMEmitter::Register rm) { + constexpr uint32_t Q = std::is_same_v ? 1U << 30 : 0; uint32_t Instr = Op; @@ -5139,8 +5139,8 @@ private: Instr |= Encode_rt(rt); dc32(Instr); } - template - void ASIMDSTLD(uint32_t Op, uint32_t Opcode, FEXCore::ARMEmitter::VRegister rt, uint32_t Index, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm) { + template + void ASIMDSTLD(uint32_t Op, uint32_t Opcode, ARMEmitter::VRegister rt, uint32_t Index, ARMEmitter::Register rn, ARMEmitter::Register rm) { LOGMAN_THROW_A_FMT( (size == SubRegSize::i8Bit && Index < 16) || (size == SubRegSize::i16Bit && Index < 8) || @@ -5202,9 +5202,9 @@ private: ASIMDLoadStore(Op | Q, Load, selem & 1, opcode, S, Size, rt, rn, rm); } - template - void ASIMDSTLD(uint32_t Op, uint32_t Opcode, T rt, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm) { - constexpr uint32_t Q = std::is_same_v ? 1U << 30 : 0; + template + void ASIMDSTLD(uint32_t Op, uint32_t Opcode, T rt, ARMEmitter::Register rn, ARMEmitter::Register rm) { + constexpr uint32_t Q = std::is_same_v ? 1U << 30 : 0; constexpr uint32_t S = 0; // selem is for determining if we are doing 1-3 loadstore single structure operations @@ -5232,7 +5232,7 @@ private: ASIMDLoadStore(Op | Q, Load, selem & 1, opcode, S, FEXCore::ToUnderlying(size), rt, rn, rm); } - void ASIMDLoadStore(uint32_t Op, uint32_t L, uint32_t R, uint32_t opcode, uint32_t S, uint32_t size, FEXCore::ARMEmitter::VRegister rt, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm) { + void ASIMDLoadStore(uint32_t Op, uint32_t L, uint32_t R, uint32_t opcode, uint32_t S, uint32_t size, ARMEmitter::VRegister rt, ARMEmitter::Register rn, ARMEmitter::Register rm) { uint32_t Instr = Op; Instr |= L << 22; diff --git a/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/BranchOps.inl b/CodeEmitter/CodeEmitter/BranchOps.inl similarity index 79% rename from FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/BranchOps.inl rename to CodeEmitter/CodeEmitter/BranchOps.inl index abe01ddfa..bbc0179c3 100644 --- a/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/BranchOps.inl +++ b/CodeEmitter/CodeEmitter/BranchOps.inl @@ -8,11 +8,11 @@ public: public: // Conditional branch immediate ///< Branch conditional - void b(FEXCore::ARMEmitter::Condition Cond, uint32_t Imm) { + void b(ARMEmitter::Condition Cond, uint32_t Imm) { constexpr uint32_t Op = 0b0101'010 << 25; Branch_Conditional(Op, 0, 0, Cond, Imm); } - void b(FEXCore::ARMEmitter::Condition Cond, BackwardLabel const* Label) { + void b(ARMEmitter::Condition Cond, BackwardLabel const* Label) { int32_t Imm = static_cast(Label->Location - GetCursorAddress()); LOGMAN_THROW_A_FMT(Imm >= -1048576 && Imm <= 1048575 && ((Imm & 0b11) == 0), "Unscaled offset too large"); constexpr uint32_t Op = 0b0101'010 << 25; @@ -20,13 +20,13 @@ public: } template requires (std::is_same_v || std::is_same_v) - void b(FEXCore::ARMEmitter::Condition Cond, LabelType *Label) { + void b(ARMEmitter::Condition Cond, LabelType *Label) { AddLocationToLabel(Label, SingleUseForwardLabel{ .Location = GetCursorAddress(), .Type = SingleUseForwardLabel::InstType::BC }); constexpr uint32_t Op = 0b0101'010 << 25; Branch_Conditional(Op, 0, 0, Cond, 0); } - void b(FEXCore::ARMEmitter::Condition Cond, BiDirectionalLabel *Label) { + void b(ARMEmitter::Condition Cond, BiDirectionalLabel *Label) { if (Label->Backward.Location) { b(Cond, &Label->Backward); } @@ -36,11 +36,11 @@ public: } ///< Branch consistent conditional - void bc(FEXCore::ARMEmitter::Condition Cond, uint32_t Imm) { + void bc(ARMEmitter::Condition Cond, uint32_t Imm) { constexpr uint32_t Op = 0b0101'010 << 25; Branch_Conditional(Op, 0, 1, Cond, Imm); } - void bc(FEXCore::ARMEmitter::Condition Cond, BackwardLabel const* Label) { + void bc(ARMEmitter::Condition Cond, BackwardLabel const* Label) { int32_t Imm = static_cast(Label->Location - GetCursorAddress()); LOGMAN_THROW_A_FMT(Imm >= -1048576 && Imm <= 1048575 && ((Imm & 0b11) == 0), "Unscaled offset too large"); constexpr uint32_t Op = 0b0101'010 << 25; @@ -49,13 +49,13 @@ public: template requires (std::is_same_v || std::is_same_v) - void bc(FEXCore::ARMEmitter::Condition Cond, LabelType *Label) { + void bc(ARMEmitter::Condition Cond, LabelType *Label) { AddLocationToLabel(Label, SingleUseForwardLabel{ .Location = GetCursorAddress(), .Type = SingleUseForwardLabel::InstType::BC }); constexpr uint32_t Op = 0b0101'010 << 25; Branch_Conditional(Op, 0, 1, Cond, 0); } - void bc(FEXCore::ARMEmitter::Condition Cond, BiDirectionalLabel *Label) { + void bc(ARMEmitter::Condition Cond, BiDirectionalLabel *Label) { if (Label->Backward.Location) { bc(Cond, &Label->Backward); } @@ -65,7 +65,7 @@ public: } // Unconditional branch register - void br(FEXCore::ARMEmitter::Register rn) { + void br(ARMEmitter::Register rn) { constexpr uint32_t Op = 0b1101011 << 25 | 0b0'000 << 21 | // opc 0b1'1111 << 16 | // op2 @@ -74,7 +74,7 @@ public: UnconditionalBranch(Op, rn); } - void blr(FEXCore::ARMEmitter::Register rn) { + void blr(ARMEmitter::Register rn) { constexpr uint32_t Op = 0b1101011 << 25 | 0b0'001 << 21 | // opc 0b1'1111 << 16 | // op2 @@ -83,7 +83,7 @@ public: UnconditionalBranch(Op, rn); } - void ret(FEXCore::ARMEmitter::Register rn = FEXCore::ARMEmitter::Reg::r30) { + void ret(ARMEmitter::Register rn = ARMEmitter::Reg::r30) { constexpr uint32_t Op = 0b1101011 << 25 | 0b0'010 << 21 | // opc 0b1'1111 << 16 | // op2 @@ -156,13 +156,13 @@ public: } // Compare and branch - void cbz(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rt, uint32_t Imm) { + void cbz(ARMEmitter::Size s, ARMEmitter::Register rt, uint32_t Imm) { constexpr uint32_t Op = 0b0011'0100 << 24; CompareAndBranch(Op, s, rt, Imm); } - void cbz(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rt, BackwardLabel const* Label) { + void cbz(ARMEmitter::Size s, ARMEmitter::Register rt, BackwardLabel const* Label) { int32_t Imm = static_cast(Label->Location - GetCursorAddress()); LOGMAN_THROW_A_FMT(Imm >= -1048576 && Imm <= 1048575 && ((Imm & 0b11) == 0), "Unscaled offset too large"); @@ -173,7 +173,7 @@ public: template requires (std::is_same_v || std::is_same_v) - void cbz(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rt, LabelType *Label) { + void cbz(ARMEmitter::Size s, ARMEmitter::Register rt, LabelType *Label) { AddLocationToLabel(Label, SingleUseForwardLabel{ .Location = GetCursorAddress(), .Type = SingleUseForwardLabel::InstType::BC }); constexpr uint32_t Op = 0b0011'0100 << 24; @@ -181,7 +181,7 @@ public: CompareAndBranch(Op, s, rt, 0); } - void cbz(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rt, BiDirectionalLabel *Label) { + void cbz(ARMEmitter::Size s, ARMEmitter::Register rt, BiDirectionalLabel *Label) { if (Label->Backward.Location) { cbz(s, rt, &Label->Backward); } @@ -190,13 +190,13 @@ public: } } - void cbnz(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rt, uint32_t Imm) { + void cbnz(ARMEmitter::Size s, ARMEmitter::Register rt, uint32_t Imm) { constexpr uint32_t Op = 0b0011'0101 << 24; CompareAndBranch(Op, s, rt, Imm); } - void cbnz(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rt, BackwardLabel const* Label) { + void cbnz(ARMEmitter::Size s, ARMEmitter::Register rt, BackwardLabel const* Label) { int32_t Imm = static_cast(Label->Location - GetCursorAddress()); LOGMAN_THROW_A_FMT(Imm >= -1048576 && Imm <= 1048575 && ((Imm & 0b11) == 0), "Unscaled offset too large"); @@ -207,7 +207,7 @@ public: template requires (std::is_same_v || std::is_same_v) - void cbnz(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rt, LabelType *Label) { + void cbnz(ARMEmitter::Size s, ARMEmitter::Register rt, LabelType *Label) { AddLocationToLabel(Label, SingleUseForwardLabel{ .Location = GetCursorAddress(), .Type = SingleUseForwardLabel::InstType::BC }); constexpr uint32_t Op = 0b0011'0101 << 24; @@ -215,7 +215,7 @@ public: CompareAndBranch(Op, s, rt, 0); } - void cbnz(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rt, BiDirectionalLabel *Label) { + void cbnz(ARMEmitter::Size s, ARMEmitter::Register rt, BiDirectionalLabel *Label) { if (Label->Backward.Location) { cbnz(s, rt, &Label->Backward); } @@ -225,12 +225,12 @@ public: } // Test and branch immediate - void tbz(FEXCore::ARMEmitter::Register rt, uint32_t Bit, uint32_t Imm) { + void tbz(ARMEmitter::Register rt, uint32_t Bit, uint32_t Imm) { constexpr uint32_t Op = 0b0011'0110 << 24; TestAndBranch(Op, rt, Bit, Imm); } - void tbz(FEXCore::ARMEmitter::Register rt, uint32_t Bit, BackwardLabel const* Label) { + void tbz(ARMEmitter::Register rt, uint32_t Bit, BackwardLabel const* Label) { int32_t Imm = static_cast(Label->Location - GetCursorAddress()); LOGMAN_THROW_A_FMT(Imm >= -32768 && Imm <= 32764 && ((Imm & 0b11) == 0), "Unscaled offset too large"); @@ -241,7 +241,7 @@ public: template requires (std::is_same_v || std::is_same_v) - void tbz(FEXCore::ARMEmitter::Register rt, uint32_t Bit, LabelType *Label) { + void tbz(ARMEmitter::Register rt, uint32_t Bit, LabelType *Label) { AddLocationToLabel(Label, SingleUseForwardLabel{ .Location = GetCursorAddress(), .Type = SingleUseForwardLabel::InstType::TEST_BRANCH }); constexpr uint32_t Op = 0b0011'0110 << 24; @@ -249,7 +249,7 @@ public: TestAndBranch(Op, rt, Bit, 0); } - void tbz(FEXCore::ARMEmitter::Register rt, uint32_t Bit, BiDirectionalLabel *Label) { + void tbz(ARMEmitter::Register rt, uint32_t Bit, BiDirectionalLabel *Label) { if (Label->Backward.Location) { tbz(rt, Bit, &Label->Backward); } @@ -258,12 +258,12 @@ public: } } - void tbnz(FEXCore::ARMEmitter::Register rt, uint32_t Bit, uint32_t Imm) { + void tbnz(ARMEmitter::Register rt, uint32_t Bit, uint32_t Imm) { constexpr uint32_t Op = 0b0011'0111 << 24; TestAndBranch(Op, rt, Bit, Imm); } - void tbnz(FEXCore::ARMEmitter::Register rt, uint32_t Bit, BackwardLabel const* Label) { + void tbnz(ARMEmitter::Register rt, uint32_t Bit, BackwardLabel const* Label) { int32_t Imm = static_cast(Label->Location - GetCursorAddress()); LOGMAN_THROW_A_FMT(Imm >= -32768 && Imm <= 32764 && ((Imm & 0b11) == 0), "Unscaled offset too large"); @@ -274,14 +274,14 @@ public: template requires (std::is_same_v || std::is_same_v) - void tbnz(FEXCore::ARMEmitter::Register rt, uint32_t Bit, LabelType *Label) { + void tbnz(ARMEmitter::Register rt, uint32_t Bit, LabelType *Label) { AddLocationToLabel(Label, SingleUseForwardLabel{ .Location = GetCursorAddress(), .Type = SingleUseForwardLabel::InstType::TEST_BRANCH }); constexpr uint32_t Op = 0b0011'0111 << 24; TestAndBranch(Op, rt, Bit, 0); } - void tbnz(FEXCore::ARMEmitter::Register rt, uint32_t Bit, BiDirectionalLabel *Label) { + void tbnz(ARMEmitter::Register rt, uint32_t Bit, BiDirectionalLabel *Label) { if (Label->Backward.Location) { tbnz(rt, Bit, &Label->Backward); } @@ -292,7 +292,7 @@ public: private: // Conditional branch immediate - void Branch_Conditional(uint32_t Op, uint32_t Op1, uint32_t Op0, FEXCore::ARMEmitter::Condition Cond, uint32_t Imm) { + void Branch_Conditional(uint32_t Op, uint32_t Op1, uint32_t Op0, ARMEmitter::Condition Cond, uint32_t Imm) { uint32_t Instr = Op; Instr |= Op1 << 24; @@ -304,7 +304,7 @@ private: } // Unconditional branch register - void UnconditionalBranch(uint32_t Op, FEXCore::ARMEmitter::Register rn) { + void UnconditionalBranch(uint32_t Op, ARMEmitter::Register rn) { uint32_t Instr = Op; Instr |= Encode_rn(rn); dc32(Instr); @@ -318,8 +318,8 @@ private: } // Compare and branch - void CompareAndBranch(uint32_t Op, FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rt, uint32_t Imm) { - const uint32_t SF = s == FEXCore::ARMEmitter::Size::i64Bit ? (1U << 31) : 0; + void CompareAndBranch(uint32_t Op, ARMEmitter::Size s, ARMEmitter::Register rt, uint32_t Imm) { + const uint32_t SF = s == ARMEmitter::Size::i64Bit ? (1U << 31) : 0; uint32_t Instr = Op; @@ -330,7 +330,7 @@ private: } // Test and branch - immediate - void TestAndBranch(uint32_t Op, FEXCore::ARMEmitter::Register rt, uint32_t Bit, uint32_t Imm) { + void TestAndBranch(uint32_t Op, ARMEmitter::Register rt, uint32_t Bit, uint32_t Imm) { uint32_t Instr = Op; Instr |= (Bit >> 5) << 31; diff --git a/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/Buffer.h b/CodeEmitter/CodeEmitter/Buffer.h similarity index 97% rename from FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/Buffer.h rename to CodeEmitter/CodeEmitter/Buffer.h index c04c15b38..f42b712be 100644 --- a/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/Buffer.h +++ b/CodeEmitter/CodeEmitter/Buffer.h @@ -4,7 +4,7 @@ #include #include -namespace FEXCore::ARMEmitter { +namespace ARMEmitter { class Buffer { public: Buffer() { @@ -103,4 +103,4 @@ protected: uint8_t* CurrentOffset; uint64_t Size; }; -} // namespace FEXCore::ARMEmitter +} // namespace ARMEmitter diff --git a/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/Emitter.h b/CodeEmitter/CodeEmitter/Emitter.h similarity index 97% rename from FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/Emitter.h rename to CodeEmitter/CodeEmitter/Emitter.h index 50307c18e..50a203933 100644 --- a/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/Emitter.h +++ b/CodeEmitter/CodeEmitter/Emitter.h @@ -1,9 +1,6 @@ // SPDX-License-Identifier: MIT #pragma once -#include "Interface/Core/ArchHelpers/CodeEmitter/Buffer.h" -#include "Interface/Core/ArchHelpers/CodeEmitter/Registers.h" - #include #include #include @@ -11,6 +8,8 @@ #include #include +#include +#include #include #include @@ -54,7 +53,7 @@ * it easier to select the correct load-store instruction. Mostly because these are a nightmare selecting * the right instruction. */ -namespace FEXCore::ARMEmitter { +namespace ARMEmitter { /* * This `Size` enum is used for most ALU operations. * These follow the AArch64 encoding style in most cases. @@ -609,7 +608,7 @@ constexpr bool AreVectorsSequential(T first, const Args&... args) { // Choices: // - Size of ops passed as an argument rather than template to let the compiler use csel instead of branching. // - Registers are unsized so they can be passed in a GPR and not need conversion operations -class Emitter : public FEXCore::ARMEmitter::Buffer { +class Emitter : public ARMEmitter::Buffer { public: Emitter() = default; @@ -804,7 +803,7 @@ public: } } - uint8_t ToImm8() { + uint8_t ToImm8() const { // ARM imm8 float encoding // Bit[7] - Sign // Bit[6] - Exponent @@ -831,17 +830,17 @@ public: } }; -#include "Interface/Core/ArchHelpers/CodeEmitter/VixlUtils.inl" +#include public: // TODO: Implement SME when it matters. -#include "Interface/Core/ArchHelpers/CodeEmitter/ALUOps.inl" -#include "Interface/Core/ArchHelpers/CodeEmitter/BranchOps.inl" -#include "Interface/Core/ArchHelpers/CodeEmitter/LoadstoreOps.inl" -#include "Interface/Core/ArchHelpers/CodeEmitter/SystemOps.inl" -#include "Interface/Core/ArchHelpers/CodeEmitter/ScalarOps.inl" -#include "Interface/Core/ArchHelpers/CodeEmitter/ASIMDOps.inl" -#include "Interface/Core/ArchHelpers/CodeEmitter/SVEOps.inl" +#include +#include +#include +#include +#include +#include +#include private: template @@ -903,4 +902,4 @@ private: return FEXCore::ToUnderlying(Reg); } }; -} // namespace FEXCore::ARMEmitter +} // namespace ARMEmitter diff --git a/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/LoadstoreOps.inl b/CodeEmitter/CodeEmitter/LoadstoreOps.inl similarity index 76% rename from FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/LoadstoreOps.inl rename to CodeEmitter/CodeEmitter/LoadstoreOps.inl index ab2a9ac69..e470c299d 100644 --- a/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/LoadstoreOps.inl +++ b/CodeEmitter/CodeEmitter/LoadstoreOps.inl @@ -12,29 +12,29 @@ */ public: // Compare and swap pair - void casp(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rs, FEXCore::ARMEmitter::Register rs2, FEXCore::ARMEmitter::Register rt, FEXCore::ARMEmitter::Register rt2, FEXCore::ARMEmitter::Register rn) { + void casp(ARMEmitter::Size s, ARMEmitter::Register rs, ARMEmitter::Register rs2, ARMEmitter::Register rt, ARMEmitter::Register rt2, ARMEmitter::Register rn) { LOGMAN_THROW_A_FMT((rs.Idx() + 1) == rs2.Idx(), "These must be sequential"); LOGMAN_THROW_A_FMT((rt.Idx() + 1) == rt2.Idx(), "These must be sequential"); constexpr uint32_t Op = 0b0000'1000'001 << 21; - AtomicOp(Op, s, 0, 0, rs, rt, FEXCore::ARMEmitter::Reg::r31, rn); + AtomicOp(Op, s, 0, 0, rs, rt, ARMEmitter::Reg::r31, rn); } - void caspa(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rs, FEXCore::ARMEmitter::Register rs2, FEXCore::ARMEmitter::Register rt, FEXCore::ARMEmitter::Register rt2, FEXCore::ARMEmitter::Register rn) { + void caspa(ARMEmitter::Size s, ARMEmitter::Register rs, ARMEmitter::Register rs2, ARMEmitter::Register rt, ARMEmitter::Register rt2, ARMEmitter::Register rn) { LOGMAN_THROW_A_FMT((rs.Idx() + 1) == rs2.Idx(), "These must be sequential"); LOGMAN_THROW_A_FMT((rt.Idx() + 1) == rt2.Idx(), "These must be sequential"); constexpr uint32_t Op = 0b0000'1000'001 << 21; - AtomicOp(Op, s, 1, 0, rs, rt, FEXCore::ARMEmitter::Reg::r31, rn); + AtomicOp(Op, s, 1, 0, rs, rt, ARMEmitter::Reg::r31, rn); } - void caspl(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rs, FEXCore::ARMEmitter::Register rs2, FEXCore::ARMEmitter::Register rt, FEXCore::ARMEmitter::Register rt2, FEXCore::ARMEmitter::Register rn) { + void caspl(ARMEmitter::Size s, ARMEmitter::Register rs, ARMEmitter::Register rs2, ARMEmitter::Register rt, ARMEmitter::Register rt2, ARMEmitter::Register rn) { LOGMAN_THROW_A_FMT((rs.Idx() + 1) == rs2.Idx(), "These must be sequential"); LOGMAN_THROW_A_FMT((rt.Idx() + 1) == rt2.Idx(), "These must be sequential"); constexpr uint32_t Op = 0b0000'1000'001 << 21; - AtomicOp(Op, s, 0, 1, rs, rt, FEXCore::ARMEmitter::Reg::r31, rn); + AtomicOp(Op, s, 0, 1, rs, rt, ARMEmitter::Reg::r31, rn); } - void caspal(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rs, FEXCore::ARMEmitter::Register rs2, FEXCore::ARMEmitter::Register rt, FEXCore::ARMEmitter::Register rt2, FEXCore::ARMEmitter::Register rn) { + void caspal(ARMEmitter::Size s, ARMEmitter::Register rs, ARMEmitter::Register rs2, ARMEmitter::Register rt, ARMEmitter::Register rt2, ARMEmitter::Register rn) { LOGMAN_THROW_A_FMT((rs.Idx() + 1) == rs2.Idx(), "These must be sequential"); LOGMAN_THROW_A_FMT((rt.Idx() + 1) == rt2.Idx(), "These must be sequential"); constexpr uint32_t Op = 0b0000'1000'001 << 21; - AtomicOp(Op, s, 1, 1, rs, rt, FEXCore::ARMEmitter::Reg::r31, rn); + AtomicOp(Op, s, 1, 1, rs, rt, ARMEmitter::Reg::r31, rn); } // Advanced SIMD load/store multiple structures @@ -804,7 +804,7 @@ public: // Advanced SIMD load/store single structure (post-indexed) template - void st1(FEXCore::ARMEmitter::SubRegSize size, T rt, uint32_t Index, FEXCore::ARMEmitter::Register rn, uint32_t PostOffset) { + void st1(ARMEmitter::SubRegSize size, T rt, uint32_t Index, ARMEmitter::Register rn, uint32_t PostOffset) { LOGMAN_THROW_AA_FMT(size == SubRegSize::i8Bit || size == SubRegSize::i16Bit || size == SubRegSize::i32Bit || size == SubRegSize::i64Bit, "Incorrect size"); constexpr uint32_t Op = 0b0000'1101'1 << 23; uint32_t Q; @@ -845,10 +845,10 @@ public: FEX_UNREACHABLE; } - ASIMDLoadStoreSinglePost(Op, Q, 0, R, opcode, S, Size, FEXCore::ARMEmitter::Reg::r31, rn, rt.Q()); + ASIMDLoadStoreSinglePost(Op, Q, 0, R, opcode, S, Size, ARMEmitter::Reg::r31, rn, rt.Q()); } template - void ld1(FEXCore::ARMEmitter::SubRegSize size, T rt, uint32_t Index, FEXCore::ARMEmitter::Register rn, uint32_t PostOffset) { + void ld1(ARMEmitter::SubRegSize size, T rt, uint32_t Index, ARMEmitter::Register rn, uint32_t PostOffset) { LOGMAN_THROW_AA_FMT(size == SubRegSize::i8Bit || size == SubRegSize::i16Bit || size == SubRegSize::i32Bit || size == SubRegSize::i64Bit, "Incorrect size"); constexpr uint32_t Op = 0b0000'1101'1 << 23; uint32_t Q; @@ -889,18 +889,18 @@ public: FEX_UNREACHABLE; } - ASIMDLoadStoreSinglePost(Op, Q, 1, R, opcode, S, Size, FEXCore::ARMEmitter::Reg::r31, rn, rt.Q()); + ASIMDLoadStoreSinglePost(Op, Q, 1, R, opcode, S, Size, ARMEmitter::Reg::r31, rn, rt.Q()); } template - void ld1r(FEXCore::ARMEmitter::SubRegSize size, T rt, FEXCore::ARMEmitter::Register rn, uint32_t PostOffset) { + void ld1r(ARMEmitter::SubRegSize size, T rt, ARMEmitter::Register rn, uint32_t PostOffset) { LOGMAN_THROW_AA_FMT(PostOffset == 1 || PostOffset == 2 || PostOffset == 4 || PostOffset == 8, "Index too large"); constexpr uint32_t Op = 0b0000'1101'1 << 23; - constexpr uint32_t Q = std::is_same_v ? 1 : 0; + constexpr uint32_t Q = std::is_same_v ? 1 : 0; uint32_t R = 0; uint32_t opcode = 0b110; uint32_t S = 0; uint32_t Size = FEXCore::ToUnderlying(size); - ASIMDLoadStoreSinglePost(Op, Q, 1, R, opcode, S, Size, FEXCore::ARMEmitter::Reg::r31, rn, rt); + ASIMDLoadStoreSinglePost(Op, Q, 1, R, opcode, S, Size, ARMEmitter::Reg::r31, rn, rt); } template @@ -1219,7 +1219,7 @@ public: } template - void st1(FEXCore::ARMEmitter::SubRegSize size, T rt, uint32_t Index, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm) { + void st1(ARMEmitter::SubRegSize size, T rt, uint32_t Index, ARMEmitter::Register rn, ARMEmitter::Register rm) { LOGMAN_THROW_AA_FMT(size == SubRegSize::i8Bit || size == SubRegSize::i16Bit || size == SubRegSize::i32Bit || size == SubRegSize::i64Bit, "Incorrect size"); constexpr uint32_t Op = 0b0000'1101'1 << 23; uint32_t Q; @@ -1263,7 +1263,7 @@ public: ASIMDLoadStoreSinglePost(Op, Q, 0, R, opcode, S, Size, rm, rn, rt.Q()); } template - void ld1(FEXCore::ARMEmitter::SubRegSize size, T rt, uint32_t Index, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm) { + void ld1(ARMEmitter::SubRegSize size, T rt, uint32_t Index, ARMEmitter::Register rn, ARMEmitter::Register rm) { LOGMAN_THROW_AA_FMT(size == SubRegSize::i8Bit || size == SubRegSize::i16Bit || size == SubRegSize::i32Bit || size == SubRegSize::i64Bit, "Incorrect size"); constexpr uint32_t Op = 0b0000'1101'1 << 23; uint32_t Q; @@ -1629,109 +1629,109 @@ public: ASIMDLoadStoreSinglePost(Op, Q, 1, R, opcode, S, Size, rm, rn, rt.Q()); } - template - void st1(T rt, uint32_t Index, FEXCore::ARMEmitter::Register rn, uint32_t PostOffset) { + template + void st1(T rt, uint32_t Index, ARMEmitter::Register rn, uint32_t PostOffset) { st1(size, rt, Index, rn, PostOffset); } - template - void ld1(T rt, uint32_t Index, FEXCore::ARMEmitter::Register rn, uint32_t PostOffset) { + template + void ld1(T rt, uint32_t Index, ARMEmitter::Register rn, uint32_t PostOffset) { ld1(size, rt, Index, rn, PostOffset); } - template - void ld1r(T rt, FEXCore::ARMEmitter::Register rn, uint32_t PostOffset) { + template + void ld1r(T rt, ARMEmitter::Register rn, uint32_t PostOffset) { ld1r(size, rt, rn, PostOffset); } - template - void ld2r(T rt, T rt2, FEXCore::ARMEmitter::Register rn, uint32_t PostOffset) { + template + void ld2r(T rt, T rt2, ARMEmitter::Register rn, uint32_t PostOffset) { ld2r(size, rt, rt2, rn, PostOffset); } - template - void ld3r(T rt, T rt2, T rt3, FEXCore::ARMEmitter::Register rn, uint32_t PostOffset) { + template + void ld3r(T rt, T rt2, T rt3, ARMEmitter::Register rn, uint32_t PostOffset) { ld3r(size, rt, rt2, rt3, rn, PostOffset); } - template - void ld4r(T rt, T rt2, T rt3, T rt4, FEXCore::ARMEmitter::Register rn, uint32_t PostOffset) { + template + void ld4r(T rt, T rt2, T rt3, T rt4, ARMEmitter::Register rn, uint32_t PostOffset) { ld4r(size, rt, rt2, rt3, rt4, rn, PostOffset); } - template - void st2(T rt, T rt2, uint32_t Index, FEXCore::ARMEmitter::Register rn, uint32_t PostOffset) { + template + void st2(T rt, T rt2, uint32_t Index, ARMEmitter::Register rn, uint32_t PostOffset) { st2(size, rt, rt2, Index, rn, PostOffset); } - template - void ld2(T rt, T rt2, uint32_t Index, FEXCore::ARMEmitter::Register rn, uint32_t PostOffset) { + template + void ld2(T rt, T rt2, uint32_t Index, ARMEmitter::Register rn, uint32_t PostOffset) { ld2(size, rt, rt2, Index, rn, PostOffset); } - template - void st3(T rt, T rt2, T rt3, uint32_t Index, FEXCore::ARMEmitter::Register rn, uint32_t PostOffset) { + template + void st3(T rt, T rt2, T rt3, uint32_t Index, ARMEmitter::Register rn, uint32_t PostOffset) { st3(size, rt, rt2, rt3, Index, rn, PostOffset); } - template - void ld3(T rt, T rt2, T rt3, uint32_t Index, FEXCore::ARMEmitter::Register rn, uint32_t PostOffset) { + template + void ld3(T rt, T rt2, T rt3, uint32_t Index, ARMEmitter::Register rn, uint32_t PostOffset) { ld3(size, rt, rt2, rt3, Index, rn, PostOffset); } - template - void st4(T rt, T rt2, T rt3, T rt4, uint32_t Index, FEXCore::ARMEmitter::Register rn, uint32_t PostOffset) { + template + void st4(T rt, T rt2, T rt3, T rt4, uint32_t Index, ARMEmitter::Register rn, uint32_t PostOffset) { st4(size, rt, rt2, rt3, rt4, Index, rn, PostOffset); } - template - void ld4(T rt, T rt2, T rt3, T rt4, uint32_t Index, FEXCore::ARMEmitter::Register rn, uint32_t PostOffset) { + template + void ld4(T rt, T rt2, T rt3, T rt4, uint32_t Index, ARMEmitter::Register rn, uint32_t PostOffset) { ld4(size, rt, rt2, rt3, rt4, Index, rn, PostOffset); } - template - void st1(T rt, uint32_t Index, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm) { + template + void st1(T rt, uint32_t Index, ARMEmitter::Register rn, ARMEmitter::Register rm) { st1(size, rt, Index, rn, rm); } - template - void ld1(T rt, uint32_t Index, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm) { + template + void ld1(T rt, uint32_t Index, ARMEmitter::Register rn, ARMEmitter::Register rm) { ld1(size, rt, Index, rn, rm); } - template - void ld1r(T rt, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm) { + template + void ld1r(T rt, ARMEmitter::Register rn, ARMEmitter::Register rm) { ld1r(size, rt, rn, rm); } - template - void ld2r(T rt, T rt2, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm) { + template + void ld2r(T rt, T rt2, ARMEmitter::Register rn, ARMEmitter::Register rm) { ld2r(size, rt, rt2, rn, rm); } - template - void ld3r(T rt, T rt2, T rt3, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm) { + template + void ld3r(T rt, T rt2, T rt3, ARMEmitter::Register rn, ARMEmitter::Register rm) { ld3r(size, rt, rt2, rt3, rn, rm); } - template - void ld4r(T rt, T rt2, T rt3, T rt4, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm) { + template + void ld4r(T rt, T rt2, T rt3, T rt4, ARMEmitter::Register rn, ARMEmitter::Register rm) { ld4r(size, rt, rt2, rt3, rt4, rn, rm); } - template - void st2(T rt, T rt2, uint32_t Index, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm) { + template + void st2(T rt, T rt2, uint32_t Index, ARMEmitter::Register rn, ARMEmitter::Register rm) { st2(size, rt, rt2, Index, rn, rm); } - template - void ld2(T rt, T rt2, uint32_t Index, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm) { + template + void ld2(T rt, T rt2, uint32_t Index, ARMEmitter::Register rn, ARMEmitter::Register rm) { ld2(size, rt, rt2, Index, rn, rm); } - template - void st3(T rt, T rt2, T rt3, uint32_t Index, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm) { + template + void st3(T rt, T rt2, T rt3, uint32_t Index, ARMEmitter::Register rn, ARMEmitter::Register rm) { st3(size, rt, rt2, rt3, Index, rn, rm); } - template - void ld3(T rt, T rt2, T rt3, uint32_t Index, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm) { + template + void ld3(T rt, T rt2, T rt3, uint32_t Index, ARMEmitter::Register rn, ARMEmitter::Register rm) { ld3(size, rt, rt2, rt3, Index, rn, rm); } - template - void st4(T rt, T rt2, T rt3, T rt4, uint32_t Index, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm) { + template + void st4(T rt, T rt2, T rt3, T rt4, uint32_t Index, ARMEmitter::Register rn, ARMEmitter::Register rm) { st4(size, rt, rt2, rt3, rt4, Index, rn, rm); } - template - void ld4(T rt, T rt2, T rt3, T rt4, uint32_t Index, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm) { + template + void ld4(T rt, T rt2, T rt3, T rt4, uint32_t Index, ARMEmitter::Register rn, ARMEmitter::Register rm) { ld4(size, rt, rt2, rt3, rt4, Index, rn, rm); } template - void ASIMDLoadStoreSinglePost(uint32_t Op, uint32_t Q, uint32_t L, uint32_t R, uint32_t opcode, uint32_t S, uint32_t size, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::Register rn, T rt) { - LOGMAN_THROW_A_FMT(std::is_same_v || std::is_same_v, "Only supports 128-bit and 64-bit vector registers."); + void ASIMDLoadStoreSinglePost(uint32_t Op, uint32_t Q, uint32_t L, uint32_t R, uint32_t opcode, uint32_t S, uint32_t size, ARMEmitter::Register rm, ARMEmitter::Register rn, T rt) { + LOGMAN_THROW_A_FMT(std::is_same_v || std::is_same_v, "Only supports 128-bit and 64-bit vector registers."); uint32_t Instr = Op; Instr |= Q << 30; @@ -1746,375 +1746,375 @@ public: dc32(Instr); } // Loadstore exclusive pair - void stxp(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rs, FEXCore::ARMEmitter::Register rt, FEXCore::ARMEmitter::Register rt2, FEXCore::ARMEmitter::Register rn) { + void stxp(ARMEmitter::Size s, ARMEmitter::Register rs, ARMEmitter::Register rt, ARMEmitter::Register rt2, ARMEmitter::Register rn) { constexpr uint32_t Op = 0b1000'1000'001 << 21; AtomicOp(Op, s, 0, 0, rs, rt, rt2, rn); } - void stlxp(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rs, FEXCore::ARMEmitter::Register rt, FEXCore::ARMEmitter::Register rt2, FEXCore::ARMEmitter::Register rn) { + void stlxp(ARMEmitter::Size s, ARMEmitter::Register rs, ARMEmitter::Register rt, ARMEmitter::Register rt2, ARMEmitter::Register rn) { constexpr uint32_t Op = 0b1000'1000'001 << 21; AtomicOp(Op, s, 0, 1, rs, rt, rt2, rn); } - void ldxp(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rt, FEXCore::ARMEmitter::Register rt2, FEXCore::ARMEmitter::Register rn) { + void ldxp(ARMEmitter::Size s, ARMEmitter::Register rt, ARMEmitter::Register rt2, ARMEmitter::Register rn) { constexpr uint32_t Op = 0b1000'1000'001 << 21; - AtomicOp(Op, s, 1, 0, FEXCore::ARMEmitter::Reg::r31, rt, rt2, rn); + AtomicOp(Op, s, 1, 0, ARMEmitter::Reg::r31, rt, rt2, rn); } - void ldaxp(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rt, FEXCore::ARMEmitter::Register rt2, FEXCore::ARMEmitter::Register rn) { + void ldaxp(ARMEmitter::Size s, ARMEmitter::Register rt, ARMEmitter::Register rt2, ARMEmitter::Register rn) { constexpr uint32_t Op = 0b1000'1000'001 << 21; - AtomicOp(Op, s, 1, 1, FEXCore::ARMEmitter::Reg::r31, rt, rt2, rn); + AtomicOp(Op, s, 1, 1, ARMEmitter::Reg::r31, rt, rt2, rn); } // Loadstore exclusive register - void stxrb(FEXCore::ARMEmitter::Register rs, FEXCore::ARMEmitter::Register rt, FEXCore::ARMEmitter::Register rn) { + void stxrb(ARMEmitter::Register rs, ARMEmitter::Register rt, ARMEmitter::Register rn) { constexpr uint32_t Op = 0b0000'1000'000 << 21; - SubAtomicOp(Op, FEXCore::ARMEmitter::SubRegSize::i8Bit, 0, 0, rs, rt, FEXCore::ARMEmitter::Reg::r31, rn); + SubAtomicOp(Op, ARMEmitter::SubRegSize::i8Bit, 0, 0, rs, rt, ARMEmitter::Reg::r31, rn); } - void stlxrb(FEXCore::ARMEmitter::Register rs, FEXCore::ARMEmitter::Register rt, FEXCore::ARMEmitter::Register rn) { + void stlxrb(ARMEmitter::Register rs, ARMEmitter::Register rt, ARMEmitter::Register rn) { constexpr uint32_t Op = 0b0000'1000'000 << 21; - SubAtomicOp(Op, FEXCore::ARMEmitter::SubRegSize::i8Bit, 0, 1, rs, rt, FEXCore::ARMEmitter::Reg::r31, rn); + SubAtomicOp(Op, ARMEmitter::SubRegSize::i8Bit, 0, 1, rs, rt, ARMEmitter::Reg::r31, rn); } - void ldxrb(FEXCore::ARMEmitter::Register rt, FEXCore::ARMEmitter::Register rn) { + void ldxrb(ARMEmitter::Register rt, ARMEmitter::Register rn) { constexpr uint32_t Op = 0b0000'1000'000 << 21; - SubAtomicOp(Op, FEXCore::ARMEmitter::SubRegSize::i8Bit, 1, 0, FEXCore::ARMEmitter::Reg::r31, rt, FEXCore::ARMEmitter::Reg::r31, rn); + SubAtomicOp(Op, ARMEmitter::SubRegSize::i8Bit, 1, 0, ARMEmitter::Reg::r31, rt, ARMEmitter::Reg::r31, rn); } - void ldaxrb(FEXCore::ARMEmitter::Register rt, FEXCore::ARMEmitter::Register rn) { + void ldaxrb(ARMEmitter::Register rt, ARMEmitter::Register rn) { constexpr uint32_t Op = 0b0000'1000'000 << 21; - SubAtomicOp(Op, FEXCore::ARMEmitter::SubRegSize::i8Bit, 1, 1, FEXCore::ARMEmitter::Reg::r31, rt, FEXCore::ARMEmitter::Reg::r31, rn); + SubAtomicOp(Op, ARMEmitter::SubRegSize::i8Bit, 1, 1, ARMEmitter::Reg::r31, rt, ARMEmitter::Reg::r31, rn); } - void stxrh(FEXCore::ARMEmitter::Register rs, FEXCore::ARMEmitter::Register rt, FEXCore::ARMEmitter::Register rn) { + void stxrh(ARMEmitter::Register rs, ARMEmitter::Register rt, ARMEmitter::Register rn) { constexpr uint32_t Op = 0b0000'1000'000 << 21; - SubAtomicOp(Op, FEXCore::ARMEmitter::SubRegSize::i16Bit, 0, 0, rs, rt, FEXCore::ARMEmitter::Reg::r31, rn); + SubAtomicOp(Op, ARMEmitter::SubRegSize::i16Bit, 0, 0, rs, rt, ARMEmitter::Reg::r31, rn); } - void stlxrh(FEXCore::ARMEmitter::Register rs, FEXCore::ARMEmitter::Register rt, FEXCore::ARMEmitter::Register rn) { + void stlxrh(ARMEmitter::Register rs, ARMEmitter::Register rt, ARMEmitter::Register rn) { constexpr uint32_t Op = 0b0000'1000'000 << 21; - SubAtomicOp(Op, FEXCore::ARMEmitter::SubRegSize::i16Bit, 0, 1, rs, rt, FEXCore::ARMEmitter::Reg::r31, rn); + SubAtomicOp(Op, ARMEmitter::SubRegSize::i16Bit, 0, 1, rs, rt, ARMEmitter::Reg::r31, rn); } - void ldxrh(FEXCore::ARMEmitter::Register rt, FEXCore::ARMEmitter::Register rn) { + void ldxrh(ARMEmitter::Register rt, ARMEmitter::Register rn) { constexpr uint32_t Op = 0b0000'1000'000 << 21; - SubAtomicOp(Op, FEXCore::ARMEmitter::SubRegSize::i16Bit, 1, 0, FEXCore::ARMEmitter::Reg::r31, rt, FEXCore::ARMEmitter::Reg::r31, rn); + SubAtomicOp(Op, ARMEmitter::SubRegSize::i16Bit, 1, 0, ARMEmitter::Reg::r31, rt, ARMEmitter::Reg::r31, rn); } - void ldaxrh(FEXCore::ARMEmitter::Register rt, FEXCore::ARMEmitter::Register rn) { + void ldaxrh(ARMEmitter::Register rt, ARMEmitter::Register rn) { constexpr uint32_t Op = 0b0000'1000'000 << 21; - SubAtomicOp(Op, FEXCore::ARMEmitter::SubRegSize::i16Bit, 1, 1, FEXCore::ARMEmitter::Reg::r31, rt, FEXCore::ARMEmitter::Reg::r31, rn); + SubAtomicOp(Op, ARMEmitter::SubRegSize::i16Bit, 1, 1, ARMEmitter::Reg::r31, rt, ARMEmitter::Reg::r31, rn); } - void stxr(FEXCore::ARMEmitter::WRegister rs, FEXCore::ARMEmitter::WRegister rt, FEXCore::ARMEmitter::Register rn) { + void stxr(ARMEmitter::WRegister rs, ARMEmitter::WRegister rt, ARMEmitter::Register rn) { constexpr uint32_t Op = 0b0000'1000'000 << 21; - SubAtomicOp(Op, FEXCore::ARMEmitter::SubRegSize::i32Bit, 0, 0, rs, rt, FEXCore::ARMEmitter::WReg::w31, rn); + SubAtomicOp(Op, ARMEmitter::SubRegSize::i32Bit, 0, 0, rs, rt, ARMEmitter::WReg::w31, rn); } - void stlxr(FEXCore::ARMEmitter::WRegister rs, FEXCore::ARMEmitter::WRegister rt, FEXCore::ARMEmitter::Register rn) { + void stlxr(ARMEmitter::WRegister rs, ARMEmitter::WRegister rt, ARMEmitter::Register rn) { constexpr uint32_t Op = 0b0000'1000'000 << 21; - SubAtomicOp(Op, FEXCore::ARMEmitter::SubRegSize::i32Bit, 0, 1, rs, rt, FEXCore::ARMEmitter::WReg::w31, rn); + SubAtomicOp(Op, ARMEmitter::SubRegSize::i32Bit, 0, 1, rs, rt, ARMEmitter::WReg::w31, rn); } - void ldxr(FEXCore::ARMEmitter::WRegister rt, FEXCore::ARMEmitter::Register rn) { + void ldxr(ARMEmitter::WRegister rt, ARMEmitter::Register rn) { constexpr uint32_t Op = 0b0000'1000'000 << 21; - SubAtomicOp(Op, FEXCore::ARMEmitter::SubRegSize::i32Bit, 1, 0, FEXCore::ARMEmitter::WReg::w31, rt, FEXCore::ARMEmitter::WReg::w31, rn); + SubAtomicOp(Op, ARMEmitter::SubRegSize::i32Bit, 1, 0, ARMEmitter::WReg::w31, rt, ARMEmitter::WReg::w31, rn); } - void ldaxr(FEXCore::ARMEmitter::WRegister rt, FEXCore::ARMEmitter::Register rn) { + void ldaxr(ARMEmitter::WRegister rt, ARMEmitter::Register rn) { constexpr uint32_t Op = 0b0000'1000'000 << 21; - SubAtomicOp(Op, FEXCore::ARMEmitter::SubRegSize::i32Bit, 1, 1, FEXCore::ARMEmitter::WReg::w31, rt, FEXCore::ARMEmitter::WReg::w31, rn); + SubAtomicOp(Op, ARMEmitter::SubRegSize::i32Bit, 1, 1, ARMEmitter::WReg::w31, rt, ARMEmitter::WReg::w31, rn); } - void stxr(FEXCore::ARMEmitter::XRegister rs, FEXCore::ARMEmitter::XRegister rt, FEXCore::ARMEmitter::Register rn) { + void stxr(ARMEmitter::XRegister rs, ARMEmitter::XRegister rt, ARMEmitter::Register rn) { constexpr uint32_t Op = 0b0000'1000'000 << 21; - SubAtomicOp(Op, FEXCore::ARMEmitter::SubRegSize::i64Bit, 0, 0, rs, rt, FEXCore::ARMEmitter::XReg::x31, rn); + SubAtomicOp(Op, ARMEmitter::SubRegSize::i64Bit, 0, 0, rs, rt, ARMEmitter::XReg::x31, rn); } - void stlxr(FEXCore::ARMEmitter::WRegister rs, FEXCore::ARMEmitter::XRegister rt, FEXCore::ARMEmitter::Register rn) { + void stlxr(ARMEmitter::WRegister rs, ARMEmitter::XRegister rt, ARMEmitter::Register rn) { constexpr uint32_t Op = 0b0000'1000'000 << 21; - SubAtomicOp(Op, FEXCore::ARMEmitter::SubRegSize::i64Bit, 0, 1, rs.R(), rt.R(), FEXCore::ARMEmitter::Reg::r31, rn); + SubAtomicOp(Op, ARMEmitter::SubRegSize::i64Bit, 0, 1, rs.R(), rt.R(), ARMEmitter::Reg::r31, rn); } - void ldxr(FEXCore::ARMEmitter::XRegister rt, FEXCore::ARMEmitter::Register rn) { + void ldxr(ARMEmitter::XRegister rt, ARMEmitter::Register rn) { constexpr uint32_t Op = 0b0000'1000'000 << 21; - SubAtomicOp(Op, FEXCore::ARMEmitter::SubRegSize::i64Bit, 1, 0, FEXCore::ARMEmitter::XReg::x31, rt, FEXCore::ARMEmitter::XReg::x31, rn); + SubAtomicOp(Op, ARMEmitter::SubRegSize::i64Bit, 1, 0, ARMEmitter::XReg::x31, rt, ARMEmitter::XReg::x31, rn); } - void ldaxr(FEXCore::ARMEmitter::XRegister rt, FEXCore::ARMEmitter::Register rn) { + void ldaxr(ARMEmitter::XRegister rt, ARMEmitter::Register rn) { constexpr uint32_t Op = 0b0000'1000'000 << 21; - SubAtomicOp(Op, FEXCore::ARMEmitter::SubRegSize::i64Bit, 1, 1, FEXCore::ARMEmitter::XReg::x31, rt, FEXCore::ARMEmitter::XReg::x31, rn); + SubAtomicOp(Op, ARMEmitter::SubRegSize::i64Bit, 1, 1, ARMEmitter::XReg::x31, rt, ARMEmitter::XReg::x31, rn); } - void stxr(ARMEmitter::SubRegSize size, FEXCore::ARMEmitter::Register rs, FEXCore::ARMEmitter::Register rt, FEXCore::ARMEmitter::Register rn) { + void stxr(ARMEmitter::SubRegSize size, ARMEmitter::Register rs, ARMEmitter::Register rt, ARMEmitter::Register rn) { constexpr uint32_t Op = 0b0000'1000'000 << 21; - SubAtomicOp(Op, size, 0, 0, rs, rt, FEXCore::ARMEmitter::Reg::r31, rn); + SubAtomicOp(Op, size, 0, 0, rs, rt, ARMEmitter::Reg::r31, rn); } - void stlxr(ARMEmitter::SubRegSize size, FEXCore::ARMEmitter::Register rs, FEXCore::ARMEmitter::Register rt, FEXCore::ARMEmitter::Register rn) { + void stlxr(ARMEmitter::SubRegSize size, ARMEmitter::Register rs, ARMEmitter::Register rt, ARMEmitter::Register rn) { constexpr uint32_t Op = 0b0000'1000'000 << 21; - SubAtomicOp(Op, size, 0, 1, rs, rt, FEXCore::ARMEmitter::Reg::r31, rn); + SubAtomicOp(Op, size, 0, 1, rs, rt, ARMEmitter::Reg::r31, rn); } - void ldxr(ARMEmitter::SubRegSize size, FEXCore::ARMEmitter::Register rt, FEXCore::ARMEmitter::Register rn) { + void ldxr(ARMEmitter::SubRegSize size, ARMEmitter::Register rt, ARMEmitter::Register rn) { constexpr uint32_t Op = 0b0000'1000'000 << 21; - SubAtomicOp(Op, size, 1, 0, FEXCore::ARMEmitter::Reg::r31, rt, FEXCore::ARMEmitter::Reg::r31, rn); + SubAtomicOp(Op, size, 1, 0, ARMEmitter::Reg::r31, rt, ARMEmitter::Reg::r31, rn); } - void ldaxr(ARMEmitter::SubRegSize size, FEXCore::ARMEmitter::Register rt, FEXCore::ARMEmitter::Register rn) { + void ldaxr(ARMEmitter::SubRegSize size, ARMEmitter::Register rt, ARMEmitter::Register rn) { constexpr uint32_t Op = 0b0000'1000'000 << 21; - SubAtomicOp(Op, size, 1, 1, FEXCore::ARMEmitter::Reg::r31, rt, FEXCore::ARMEmitter::Reg::r31, rn); + SubAtomicOp(Op, size, 1, 1, ARMEmitter::Reg::r31, rt, ARMEmitter::Reg::r31, rn); } // Load/store ordered static constexpr uint32_t LoadStoreOrdered_Op = 0b0000'1000'100 << 21; - void stllrb(FEXCore::ARMEmitter::Register rt, FEXCore::ARMEmitter::Register rn) { - SubAtomicOp(LoadStoreOrdered_Op, FEXCore::ARMEmitter::SubRegSize::i8Bit, 0, 0, FEXCore::ARMEmitter::Reg::r31, rt, FEXCore::ARMEmitter::Reg::r31, rn); + void stllrb(ARMEmitter::Register rt, ARMEmitter::Register rn) { + SubAtomicOp(LoadStoreOrdered_Op, ARMEmitter::SubRegSize::i8Bit, 0, 0, ARMEmitter::Reg::r31, rt, ARMEmitter::Reg::r31, rn); } - void stlrb(FEXCore::ARMEmitter::Register rt, FEXCore::ARMEmitter::Register rn) { - SubAtomicOp(LoadStoreOrdered_Op, FEXCore::ARMEmitter::SubRegSize::i8Bit, 0, 1, FEXCore::ARMEmitter::Reg::r31, rt, FEXCore::ARMEmitter::Reg::r31, rn); + void stlrb(ARMEmitter::Register rt, ARMEmitter::Register rn) { + SubAtomicOp(LoadStoreOrdered_Op, ARMEmitter::SubRegSize::i8Bit, 0, 1, ARMEmitter::Reg::r31, rt, ARMEmitter::Reg::r31, rn); } - void ldlarb(FEXCore::ARMEmitter::Register rt, FEXCore::ARMEmitter::Register rn) { - SubAtomicOp(LoadStoreOrdered_Op, FEXCore::ARMEmitter::SubRegSize::i8Bit, 1, 0, FEXCore::ARMEmitter::Reg::r31, rt, FEXCore::ARMEmitter::Reg::r31, rn); + void ldlarb(ARMEmitter::Register rt, ARMEmitter::Register rn) { + SubAtomicOp(LoadStoreOrdered_Op, ARMEmitter::SubRegSize::i8Bit, 1, 0, ARMEmitter::Reg::r31, rt, ARMEmitter::Reg::r31, rn); } - void ldarb(FEXCore::ARMEmitter::Register rt, FEXCore::ARMEmitter::Register rn) { - SubAtomicOp(LoadStoreOrdered_Op, FEXCore::ARMEmitter::SubRegSize::i8Bit, 1, 1, FEXCore::ARMEmitter::Reg::r31, rt, FEXCore::ARMEmitter::Reg::r31, rn); + void ldarb(ARMEmitter::Register rt, ARMEmitter::Register rn) { + SubAtomicOp(LoadStoreOrdered_Op, ARMEmitter::SubRegSize::i8Bit, 1, 1, ARMEmitter::Reg::r31, rt, ARMEmitter::Reg::r31, rn); } - void stllrh(FEXCore::ARMEmitter::Register rt, FEXCore::ARMEmitter::Register rn) { - SubAtomicOp(LoadStoreOrdered_Op, FEXCore::ARMEmitter::SubRegSize::i16Bit, 0, 0, FEXCore::ARMEmitter::Reg::r31, rt, FEXCore::ARMEmitter::Reg::r31, rn); + void stllrh(ARMEmitter::Register rt, ARMEmitter::Register rn) { + SubAtomicOp(LoadStoreOrdered_Op, ARMEmitter::SubRegSize::i16Bit, 0, 0, ARMEmitter::Reg::r31, rt, ARMEmitter::Reg::r31, rn); } - void stlrh(FEXCore::ARMEmitter::Register rt, FEXCore::ARMEmitter::Register rn) { - SubAtomicOp(LoadStoreOrdered_Op, FEXCore::ARMEmitter::SubRegSize::i16Bit, 0, 1, FEXCore::ARMEmitter::Reg::r31, rt, FEXCore::ARMEmitter::Reg::r31, rn); + void stlrh(ARMEmitter::Register rt, ARMEmitter::Register rn) { + SubAtomicOp(LoadStoreOrdered_Op, ARMEmitter::SubRegSize::i16Bit, 0, 1, ARMEmitter::Reg::r31, rt, ARMEmitter::Reg::r31, rn); } - void ldlarh(FEXCore::ARMEmitter::Register rt, FEXCore::ARMEmitter::Register rn) { - SubAtomicOp(LoadStoreOrdered_Op, FEXCore::ARMEmitter::SubRegSize::i16Bit, 1, 0, FEXCore::ARMEmitter::Reg::r31, rt, FEXCore::ARMEmitter::Reg::r31, rn); + void ldlarh(ARMEmitter::Register rt, ARMEmitter::Register rn) { + SubAtomicOp(LoadStoreOrdered_Op, ARMEmitter::SubRegSize::i16Bit, 1, 0, ARMEmitter::Reg::r31, rt, ARMEmitter::Reg::r31, rn); } - void ldarh(FEXCore::ARMEmitter::Register rt, FEXCore::ARMEmitter::Register rn) { - SubAtomicOp(LoadStoreOrdered_Op, FEXCore::ARMEmitter::SubRegSize::i16Bit, 1, 1, FEXCore::ARMEmitter::Reg::r31, rt, FEXCore::ARMEmitter::Reg::r31, rn); + void ldarh(ARMEmitter::Register rt, ARMEmitter::Register rn) { + SubAtomicOp(LoadStoreOrdered_Op, ARMEmitter::SubRegSize::i16Bit, 1, 1, ARMEmitter::Reg::r31, rt, ARMEmitter::Reg::r31, rn); } - void stllr(FEXCore::ARMEmitter::WRegister rt, FEXCore::ARMEmitter::Register rn) { - SubAtomicOp(LoadStoreOrdered_Op, FEXCore::ARMEmitter::SubRegSize::i32Bit, 0, 0, FEXCore::ARMEmitter::WReg::w31, rt, FEXCore::ARMEmitter::WReg::w31, rn); + void stllr(ARMEmitter::WRegister rt, ARMEmitter::Register rn) { + SubAtomicOp(LoadStoreOrdered_Op, ARMEmitter::SubRegSize::i32Bit, 0, 0, ARMEmitter::WReg::w31, rt, ARMEmitter::WReg::w31, rn); } - void stlr(FEXCore::ARMEmitter::WRegister rt, FEXCore::ARMEmitter::Register rn) { - SubAtomicOp(LoadStoreOrdered_Op, FEXCore::ARMEmitter::SubRegSize::i32Bit, 0, 1, FEXCore::ARMEmitter::WReg::w31, rt, FEXCore::ARMEmitter::WReg::w31, rn); + void stlr(ARMEmitter::WRegister rt, ARMEmitter::Register rn) { + SubAtomicOp(LoadStoreOrdered_Op, ARMEmitter::SubRegSize::i32Bit, 0, 1, ARMEmitter::WReg::w31, rt, ARMEmitter::WReg::w31, rn); } - void ldlar(FEXCore::ARMEmitter::WRegister rt, FEXCore::ARMEmitter::Register rn) { - SubAtomicOp(LoadStoreOrdered_Op, FEXCore::ARMEmitter::SubRegSize::i32Bit, 1, 0, FEXCore::ARMEmitter::WReg::w31, rt, FEXCore::ARMEmitter::WReg::w31, rn); + void ldlar(ARMEmitter::WRegister rt, ARMEmitter::Register rn) { + SubAtomicOp(LoadStoreOrdered_Op, ARMEmitter::SubRegSize::i32Bit, 1, 0, ARMEmitter::WReg::w31, rt, ARMEmitter::WReg::w31, rn); } - void ldar(FEXCore::ARMEmitter::WRegister rt, FEXCore::ARMEmitter::Register rn) { - SubAtomicOp(LoadStoreOrdered_Op, FEXCore::ARMEmitter::SubRegSize::i32Bit, 1, 1, FEXCore::ARMEmitter::WReg::w31, rt, FEXCore::ARMEmitter::WReg::w31, rn); + void ldar(ARMEmitter::WRegister rt, ARMEmitter::Register rn) { + SubAtomicOp(LoadStoreOrdered_Op, ARMEmitter::SubRegSize::i32Bit, 1, 1, ARMEmitter::WReg::w31, rt, ARMEmitter::WReg::w31, rn); } - void stllr(FEXCore::ARMEmitter::XRegister rt, FEXCore::ARMEmitter::Register rn) { - SubAtomicOp(LoadStoreOrdered_Op, FEXCore::ARMEmitter::SubRegSize::i64Bit, 0, 0, FEXCore::ARMEmitter::XReg::x31, rt, FEXCore::ARMEmitter::XReg::x31, rn); + void stllr(ARMEmitter::XRegister rt, ARMEmitter::Register rn) { + SubAtomicOp(LoadStoreOrdered_Op, ARMEmitter::SubRegSize::i64Bit, 0, 0, ARMEmitter::XReg::x31, rt, ARMEmitter::XReg::x31, rn); } - void stlr(FEXCore::ARMEmitter::XRegister rt, FEXCore::ARMEmitter::Register rn) { - SubAtomicOp(LoadStoreOrdered_Op, FEXCore::ARMEmitter::SubRegSize::i64Bit, 0, 1, FEXCore::ARMEmitter::XReg::x31, rt, FEXCore::ARMEmitter::XReg::x31, rn); + void stlr(ARMEmitter::XRegister rt, ARMEmitter::Register rn) { + SubAtomicOp(LoadStoreOrdered_Op, ARMEmitter::SubRegSize::i64Bit, 0, 1, ARMEmitter::XReg::x31, rt, ARMEmitter::XReg::x31, rn); } - void ldlar(FEXCore::ARMEmitter::XRegister rt, FEXCore::ARMEmitter::Register rn) { - SubAtomicOp(LoadStoreOrdered_Op, FEXCore::ARMEmitter::SubRegSize::i64Bit, 1, 0, FEXCore::ARMEmitter::XReg::x31, rt, FEXCore::ARMEmitter::XReg::x31, rn); + void ldlar(ARMEmitter::XRegister rt, ARMEmitter::Register rn) { + SubAtomicOp(LoadStoreOrdered_Op, ARMEmitter::SubRegSize::i64Bit, 1, 0, ARMEmitter::XReg::x31, rt, ARMEmitter::XReg::x31, rn); } - void ldar(FEXCore::ARMEmitter::XRegister rt, FEXCore::ARMEmitter::Register rn) { - SubAtomicOp(LoadStoreOrdered_Op, FEXCore::ARMEmitter::SubRegSize::i64Bit, 1, 1, FEXCore::ARMEmitter::XReg::x31, rt, FEXCore::ARMEmitter::XReg::x31, rn); + void ldar(ARMEmitter::XRegister rt, ARMEmitter::Register rn) { + SubAtomicOp(LoadStoreOrdered_Op, ARMEmitter::SubRegSize::i64Bit, 1, 1, ARMEmitter::XReg::x31, rt, ARMEmitter::XReg::x31, rn); } // Compare and swap - void casb(FEXCore::ARMEmitter::Register rs, FEXCore::ARMEmitter::Register rt, FEXCore::ARMEmitter::Register rn) { + void casb(ARMEmitter::Register rs, ARMEmitter::Register rt, ARMEmitter::Register rn) { constexpr uint32_t Op = 0b0000'1000'101 << 21; - SubAtomicOp(Op, FEXCore::ARMEmitter::SubRegSize::i8Bit, 0, 0, rs, rt, FEXCore::ARMEmitter::Reg::r31, rn); + SubAtomicOp(Op, ARMEmitter::SubRegSize::i8Bit, 0, 0, rs, rt, ARMEmitter::Reg::r31, rn); } - void caslb(FEXCore::ARMEmitter::Register rs, FEXCore::ARMEmitter::Register rt, FEXCore::ARMEmitter::Register rn) { + void caslb(ARMEmitter::Register rs, ARMEmitter::Register rt, ARMEmitter::Register rn) { constexpr uint32_t Op = 0b0000'1000'101 << 21; - SubAtomicOp(Op, FEXCore::ARMEmitter::SubRegSize::i8Bit, 0, 1, rs, rt, FEXCore::ARMEmitter::Reg::r31, rn); + SubAtomicOp(Op, ARMEmitter::SubRegSize::i8Bit, 0, 1, rs, rt, ARMEmitter::Reg::r31, rn); } - void casab(FEXCore::ARMEmitter::Register rs, FEXCore::ARMEmitter::Register rt, FEXCore::ARMEmitter::Register rn) { + void casab(ARMEmitter::Register rs, ARMEmitter::Register rt, ARMEmitter::Register rn) { constexpr uint32_t Op = 0b0000'1000'101 << 21; - SubAtomicOp(Op, FEXCore::ARMEmitter::SubRegSize::i8Bit, 1, 0, rs, rt, FEXCore::ARMEmitter::Reg::r31, rn); + SubAtomicOp(Op, ARMEmitter::SubRegSize::i8Bit, 1, 0, rs, rt, ARMEmitter::Reg::r31, rn); } - void casalb(FEXCore::ARMEmitter::Register rs, FEXCore::ARMEmitter::Register rt, FEXCore::ARMEmitter::Register rn) { + void casalb(ARMEmitter::Register rs, ARMEmitter::Register rt, ARMEmitter::Register rn) { constexpr uint32_t Op = 0b0000'1000'101 << 21; - SubAtomicOp(Op, FEXCore::ARMEmitter::SubRegSize::i8Bit, 1, 1, rs, rt, FEXCore::ARMEmitter::Reg::r31, rn); + SubAtomicOp(Op, ARMEmitter::SubRegSize::i8Bit, 1, 1, rs, rt, ARMEmitter::Reg::r31, rn); } - void cash(FEXCore::ARMEmitter::Register rs, FEXCore::ARMEmitter::Register rt, FEXCore::ARMEmitter::Register rn) { + void cash(ARMEmitter::Register rs, ARMEmitter::Register rt, ARMEmitter::Register rn) { constexpr uint32_t Op = 0b0000'1000'101 << 21; - SubAtomicOp(Op, FEXCore::ARMEmitter::SubRegSize::i16Bit, 0, 0, rs, rt, FEXCore::ARMEmitter::Reg::r31, rn); + SubAtomicOp(Op, ARMEmitter::SubRegSize::i16Bit, 0, 0, rs, rt, ARMEmitter::Reg::r31, rn); } - void caslh(FEXCore::ARMEmitter::Register rs, FEXCore::ARMEmitter::Register rt, FEXCore::ARMEmitter::Register rn) { + void caslh(ARMEmitter::Register rs, ARMEmitter::Register rt, ARMEmitter::Register rn) { constexpr uint32_t Op = 0b0000'1000'101 << 21; - SubAtomicOp(Op, FEXCore::ARMEmitter::SubRegSize::i16Bit, 0, 1, rs, rt, FEXCore::ARMEmitter::Reg::r31, rn); + SubAtomicOp(Op, ARMEmitter::SubRegSize::i16Bit, 0, 1, rs, rt, ARMEmitter::Reg::r31, rn); } - void casah(FEXCore::ARMEmitter::Register rs, FEXCore::ARMEmitter::Register rt, FEXCore::ARMEmitter::Register rn) { + void casah(ARMEmitter::Register rs, ARMEmitter::Register rt, ARMEmitter::Register rn) { constexpr uint32_t Op = 0b0000'1000'101 << 21; - SubAtomicOp(Op, FEXCore::ARMEmitter::SubRegSize::i16Bit, 1, 0, rs, rt, FEXCore::ARMEmitter::Reg::r31, rn); + SubAtomicOp(Op, ARMEmitter::SubRegSize::i16Bit, 1, 0, rs, rt, ARMEmitter::Reg::r31, rn); } - void casalh(FEXCore::ARMEmitter::Register rs, FEXCore::ARMEmitter::Register rt, FEXCore::ARMEmitter::Register rn) { + void casalh(ARMEmitter::Register rs, ARMEmitter::Register rt, ARMEmitter::Register rn) { constexpr uint32_t Op = 0b0000'1000'101 << 21; - SubAtomicOp(Op, FEXCore::ARMEmitter::SubRegSize::i16Bit, 1, 1, rs, rt, FEXCore::ARMEmitter::Reg::r31, rn); + SubAtomicOp(Op, ARMEmitter::SubRegSize::i16Bit, 1, 1, rs, rt, ARMEmitter::Reg::r31, rn); } - void cas(FEXCore::ARMEmitter::WRegister rs, FEXCore::ARMEmitter::WRegister rt, FEXCore::ARMEmitter::Register rn) { + void cas(ARMEmitter::WRegister rs, ARMEmitter::WRegister rt, ARMEmitter::Register rn) { constexpr uint32_t Op = 0b0000'1000'101 << 21; - SubAtomicOp(Op, FEXCore::ARMEmitter::SubRegSize::i32Bit, 0, 0, rs.R(), rt.R(), FEXCore::ARMEmitter::Reg::r31, rn); + SubAtomicOp(Op, ARMEmitter::SubRegSize::i32Bit, 0, 0, rs.R(), rt.R(), ARMEmitter::Reg::r31, rn); } - void casl(FEXCore::ARMEmitter::WRegister rs, FEXCore::ARMEmitter::WRegister rt, FEXCore::ARMEmitter::Register rn) { + void casl(ARMEmitter::WRegister rs, ARMEmitter::WRegister rt, ARMEmitter::Register rn) { constexpr uint32_t Op = 0b0000'1000'101 << 21; - SubAtomicOp(Op, FEXCore::ARMEmitter::SubRegSize::i32Bit, 0, 1, rs.R(), rt.R(), FEXCore::ARMEmitter::Reg::r31, rn); + SubAtomicOp(Op, ARMEmitter::SubRegSize::i32Bit, 0, 1, rs.R(), rt.R(), ARMEmitter::Reg::r31, rn); } - void casa(FEXCore::ARMEmitter::WRegister rs, FEXCore::ARMEmitter::WRegister rt, FEXCore::ARMEmitter::Register rn) { + void casa(ARMEmitter::WRegister rs, ARMEmitter::WRegister rt, ARMEmitter::Register rn) { constexpr uint32_t Op = 0b0000'1000'101 << 21; - SubAtomicOp(Op, FEXCore::ARMEmitter::SubRegSize::i32Bit, 1, 0, rs.R(), rt.R(), FEXCore::ARMEmitter::Reg::r31, rn); + SubAtomicOp(Op, ARMEmitter::SubRegSize::i32Bit, 1, 0, rs.R(), rt.R(), ARMEmitter::Reg::r31, rn); } - void casal(FEXCore::ARMEmitter::WRegister rs, FEXCore::ARMEmitter::WRegister rt, FEXCore::ARMEmitter::Register rn) { + void casal(ARMEmitter::WRegister rs, ARMEmitter::WRegister rt, ARMEmitter::Register rn) { constexpr uint32_t Op = 0b0000'1000'101 << 21; - SubAtomicOp(Op, FEXCore::ARMEmitter::SubRegSize::i32Bit, 1, 1, rs.R(), rt.R(), FEXCore::ARMEmitter::Reg::r31, rn); + SubAtomicOp(Op, ARMEmitter::SubRegSize::i32Bit, 1, 1, rs.R(), rt.R(), ARMEmitter::Reg::r31, rn); } - void cas(FEXCore::ARMEmitter::XRegister rs, FEXCore::ARMEmitter::XRegister rt, FEXCore::ARMEmitter::Register rn) { + void cas(ARMEmitter::XRegister rs, ARMEmitter::XRegister rt, ARMEmitter::Register rn) { constexpr uint32_t Op = 0b0000'1000'101 << 21; - SubAtomicOp(Op, FEXCore::ARMEmitter::SubRegSize::i64Bit, 0, 0, rs.R(), rt.R(), FEXCore::ARMEmitter::Reg::r31, rn); + SubAtomicOp(Op, ARMEmitter::SubRegSize::i64Bit, 0, 0, rs.R(), rt.R(), ARMEmitter::Reg::r31, rn); } - void casl(FEXCore::ARMEmitter::XRegister rs, FEXCore::ARMEmitter::XRegister rt, FEXCore::ARMEmitter::Register rn) { + void casl(ARMEmitter::XRegister rs, ARMEmitter::XRegister rt, ARMEmitter::Register rn) { constexpr uint32_t Op = 0b0000'1000'101 << 21; - SubAtomicOp(Op, FEXCore::ARMEmitter::SubRegSize::i64Bit, 0, 1, rs.R(), rt.R(), FEXCore::ARMEmitter::Reg::r31, rn); + SubAtomicOp(Op, ARMEmitter::SubRegSize::i64Bit, 0, 1, rs.R(), rt.R(), ARMEmitter::Reg::r31, rn); } - void casa(FEXCore::ARMEmitter::XRegister rs, FEXCore::ARMEmitter::XRegister rt, FEXCore::ARMEmitter::Register rn) { + void casa(ARMEmitter::XRegister rs, ARMEmitter::XRegister rt, ARMEmitter::Register rn) { constexpr uint32_t Op = 0b0000'1000'101 << 21; - SubAtomicOp(Op, FEXCore::ARMEmitter::SubRegSize::i64Bit, 1, 0, rs.R(), rt.R(), FEXCore::ARMEmitter::Reg::r31, rn); + SubAtomicOp(Op, ARMEmitter::SubRegSize::i64Bit, 1, 0, rs.R(), rt.R(), ARMEmitter::Reg::r31, rn); } - void casal(FEXCore::ARMEmitter::XRegister rs, FEXCore::ARMEmitter::XRegister rt, FEXCore::ARMEmitter::Register rn) { + void casal(ARMEmitter::XRegister rs, ARMEmitter::XRegister rt, ARMEmitter::Register rn) { constexpr uint32_t Op = 0b0000'1000'101 << 21; - SubAtomicOp(Op, FEXCore::ARMEmitter::SubRegSize::i64Bit, 1, 1, rs.R(), rt.R(), FEXCore::ARMEmitter::Reg::r31, rn); + SubAtomicOp(Op, ARMEmitter::SubRegSize::i64Bit, 1, 1, rs.R(), rt.R(), ARMEmitter::Reg::r31, rn); } - void cas(FEXCore::ARMEmitter::SubRegSize size, FEXCore::ARMEmitter::Register rs, FEXCore::ARMEmitter::Register rt, FEXCore::ARMEmitter::Register rn) { + void cas(ARMEmitter::SubRegSize size, ARMEmitter::Register rs, ARMEmitter::Register rt, ARMEmitter::Register rn) { constexpr uint32_t Op = 0b0000'1000'101 << 21; - SubAtomicOp(Op, size, 0, 0, rs, rt, FEXCore::ARMEmitter::Reg::r31, rn); + SubAtomicOp(Op, size, 0, 0, rs, rt, ARMEmitter::Reg::r31, rn); } - void casl(FEXCore::ARMEmitter::SubRegSize size, FEXCore::ARMEmitter::Register rs, FEXCore::ARMEmitter::Register rt, FEXCore::ARMEmitter::Register rn) { + void casl(ARMEmitter::SubRegSize size, ARMEmitter::Register rs, ARMEmitter::Register rt, ARMEmitter::Register rn) { constexpr uint32_t Op = 0b0000'1000'101 << 21; - SubAtomicOp(Op, size, 0, 1, rs, rt, FEXCore::ARMEmitter::Reg::r31, rn); + SubAtomicOp(Op, size, 0, 1, rs, rt, ARMEmitter::Reg::r31, rn); } - void casa(FEXCore::ARMEmitter::SubRegSize size, FEXCore::ARMEmitter::Register rs, FEXCore::ARMEmitter::Register rt, FEXCore::ARMEmitter::Register rn) { + void casa(ARMEmitter::SubRegSize size, ARMEmitter::Register rs, ARMEmitter::Register rt, ARMEmitter::Register rn) { constexpr uint32_t Op = 0b0000'1000'101 << 21; - SubAtomicOp(Op, size, 1, 0, rs, rt, FEXCore::ARMEmitter::Reg::r31, rn); + SubAtomicOp(Op, size, 1, 0, rs, rt, ARMEmitter::Reg::r31, rn); } - void casal(FEXCore::ARMEmitter::SubRegSize size, FEXCore::ARMEmitter::Register rs, FEXCore::ARMEmitter::Register rt, FEXCore::ARMEmitter::Register rn) { + void casal(ARMEmitter::SubRegSize size, ARMEmitter::Register rs, ARMEmitter::Register rt, ARMEmitter::Register rn) { constexpr uint32_t Op = 0b0000'1000'101 << 21; - SubAtomicOp(Op, size, 1, 1, rs, rt, FEXCore::ARMEmitter::Reg::r31, rn); + SubAtomicOp(Op, size, 1, 1, rs, rt, ARMEmitter::Reg::r31, rn); } // LDAPR/STLR unscaled immediate - void stlurb(FEXCore::ARMEmitter::Register rt, FEXCore::ARMEmitter::Register rn, int32_t Imm) { + void stlurb(ARMEmitter::Register rt, ARMEmitter::Register rn, int32_t Imm) { LOGMAN_THROW_A_FMT(Imm >= -256 && Imm <= 255, "Unscaled offset too large"); constexpr uint32_t Op = 0b0001'1001'000 << 21; - SubAtomicImm(Op, FEXCore::ARMEmitter::SubRegSize::i8Bit, 0b00, rt, rn, static_cast(Imm) & 0x1'FF); + SubAtomicImm(Op, ARMEmitter::SubRegSize::i8Bit, 0b00, rt, rn, static_cast(Imm) & 0x1'FF); } - void ldapurb(FEXCore::ARMEmitter::Register rt, FEXCore::ARMEmitter::Register rn, int32_t Imm) { + void ldapurb(ARMEmitter::Register rt, ARMEmitter::Register rn, int32_t Imm) { LOGMAN_THROW_A_FMT(Imm >= -256 && Imm <= 255, "Unscaled offset too large"); constexpr uint32_t Op = 0b0001'1001'000 << 21; - SubAtomicImm(Op, FEXCore::ARMEmitter::SubRegSize::i8Bit, 0b01, rt, rn, static_cast(Imm) & 0x1'FF); + SubAtomicImm(Op, ARMEmitter::SubRegSize::i8Bit, 0b01, rt, rn, static_cast(Imm) & 0x1'FF); } - void ldapursb(FEXCore::ARMEmitter::WRegister rt, FEXCore::ARMEmitter::Register rn, int32_t Imm) { + void ldapursb(ARMEmitter::WRegister rt, ARMEmitter::Register rn, int32_t Imm) { LOGMAN_THROW_A_FMT(Imm >= -256 && Imm <= 255, "Unscaled offset too large"); constexpr uint32_t Op = 0b0001'1001'000 << 21; - SubAtomicImm(Op, FEXCore::ARMEmitter::SubRegSize::i8Bit, 0b11, rt, rn, static_cast(Imm) & 0x1'FF); + SubAtomicImm(Op, ARMEmitter::SubRegSize::i8Bit, 0b11, rt, rn, static_cast(Imm) & 0x1'FF); } - void ldapursb(FEXCore::ARMEmitter::XRegister rt, FEXCore::ARMEmitter::Register rn, int32_t Imm) { + void ldapursb(ARMEmitter::XRegister rt, ARMEmitter::Register rn, int32_t Imm) { LOGMAN_THROW_A_FMT(Imm >= -256 && Imm <= 255, "Unscaled offset too large"); constexpr uint32_t Op = 0b0001'1001'000 << 21; - SubAtomicImm(Op, FEXCore::ARMEmitter::SubRegSize::i8Bit, 0b10, rt, rn, static_cast(Imm) & 0x1'FF); + SubAtomicImm(Op, ARMEmitter::SubRegSize::i8Bit, 0b10, rt, rn, static_cast(Imm) & 0x1'FF); } - void stlurh(FEXCore::ARMEmitter::Register rt, FEXCore::ARMEmitter::Register rn, int32_t Imm) { + void stlurh(ARMEmitter::Register rt, ARMEmitter::Register rn, int32_t Imm) { LOGMAN_THROW_A_FMT(Imm >= -256 && Imm <= 255, "Unscaled offset too large"); constexpr uint32_t Op = 0b0001'1001'000 << 21; - SubAtomicImm(Op, FEXCore::ARMEmitter::SubRegSize::i16Bit, 0b00, rt, rn, static_cast(Imm) & 0x1'FF); + SubAtomicImm(Op, ARMEmitter::SubRegSize::i16Bit, 0b00, rt, rn, static_cast(Imm) & 0x1'FF); } - void ldapurh(FEXCore::ARMEmitter::Register rt, FEXCore::ARMEmitter::Register rn, int32_t Imm) { + void ldapurh(ARMEmitter::Register rt, ARMEmitter::Register rn, int32_t Imm) { LOGMAN_THROW_A_FMT(Imm >= -256 && Imm <= 255, "Unscaled offset too large"); constexpr uint32_t Op = 0b0001'1001'000 << 21; - SubAtomicImm(Op, FEXCore::ARMEmitter::SubRegSize::i16Bit, 0b01, rt, rn, static_cast(Imm) & 0x1'FF); + SubAtomicImm(Op, ARMEmitter::SubRegSize::i16Bit, 0b01, rt, rn, static_cast(Imm) & 0x1'FF); } - void ldapursh(FEXCore::ARMEmitter::WRegister rt, FEXCore::ARMEmitter::Register rn, int32_t Imm) { + void ldapursh(ARMEmitter::WRegister rt, ARMEmitter::Register rn, int32_t Imm) { LOGMAN_THROW_A_FMT(Imm >= -256 && Imm <= 255, "Unscaled offset too large"); constexpr uint32_t Op = 0b0001'1001'000 << 21; - SubAtomicImm(Op, FEXCore::ARMEmitter::SubRegSize::i16Bit, 0b11, rt, rn, static_cast(Imm) & 0x1'FF); + SubAtomicImm(Op, ARMEmitter::SubRegSize::i16Bit, 0b11, rt, rn, static_cast(Imm) & 0x1'FF); } - void ldapursh(FEXCore::ARMEmitter::XRegister rt, FEXCore::ARMEmitter::Register rn, int32_t Imm) { + void ldapursh(ARMEmitter::XRegister rt, ARMEmitter::Register rn, int32_t Imm) { LOGMAN_THROW_A_FMT(Imm >= -256 && Imm <= 255, "Unscaled offset too large"); constexpr uint32_t Op = 0b0001'1001'000 << 21; - SubAtomicImm(Op, FEXCore::ARMEmitter::SubRegSize::i16Bit, 0b10, rt, rn, static_cast(Imm) & 0x1'FF); + SubAtomicImm(Op, ARMEmitter::SubRegSize::i16Bit, 0b10, rt, rn, static_cast(Imm) & 0x1'FF); } - void stlur(FEXCore::ARMEmitter::WRegister rt, FEXCore::ARMEmitter::Register rn, int32_t Imm) { + void stlur(ARMEmitter::WRegister rt, ARMEmitter::Register rn, int32_t Imm) { LOGMAN_THROW_A_FMT(Imm >= -256 && Imm <= 255, "Unscaled offset too large"); constexpr uint32_t Op = 0b0001'1001'000 << 21; - SubAtomicImm(Op, FEXCore::ARMEmitter::SubRegSize::i32Bit, 0b00, rt, rn, static_cast(Imm) & 0x1'FF); + SubAtomicImm(Op, ARMEmitter::SubRegSize::i32Bit, 0b00, rt, rn, static_cast(Imm) & 0x1'FF); } - void ldapur(FEXCore::ARMEmitter::WRegister rt, FEXCore::ARMEmitter::Register rn, int32_t Imm) { + void ldapur(ARMEmitter::WRegister rt, ARMEmitter::Register rn, int32_t Imm) { LOGMAN_THROW_A_FMT(Imm >= -256 && Imm <= 255, "Unscaled offset too large"); constexpr uint32_t Op = 0b0001'1001'000 << 21; - SubAtomicImm(Op, FEXCore::ARMEmitter::SubRegSize::i32Bit, 0b01, rt, rn, static_cast(Imm) & 0x1'FF); + SubAtomicImm(Op, ARMEmitter::SubRegSize::i32Bit, 0b01, rt, rn, static_cast(Imm) & 0x1'FF); } - void ldapursw(FEXCore::ARMEmitter::XRegister rt, FEXCore::ARMEmitter::Register rn, int32_t Imm) { + void ldapursw(ARMEmitter::XRegister rt, ARMEmitter::Register rn, int32_t Imm) { LOGMAN_THROW_A_FMT(Imm >= -256 && Imm <= 255, "Unscaled offset too large"); constexpr uint32_t Op = 0b0001'1001'000 << 21; - SubAtomicImm(Op, FEXCore::ARMEmitter::SubRegSize::i32Bit, 0b10, rt, rn, static_cast(Imm) & 0x1'FF); + SubAtomicImm(Op, ARMEmitter::SubRegSize::i32Bit, 0b10, rt, rn, static_cast(Imm) & 0x1'FF); } - void stlur(FEXCore::ARMEmitter::XRegister rt, FEXCore::ARMEmitter::Register rn, int32_t Imm) { + void stlur(ARMEmitter::XRegister rt, ARMEmitter::Register rn, int32_t Imm) { LOGMAN_THROW_A_FMT(Imm >= -256 && Imm <= 255, "Unscaled offset too large"); constexpr uint32_t Op = 0b0001'1001'000 << 21; - SubAtomicImm(Op, FEXCore::ARMEmitter::SubRegSize::i64Bit, 0b00, rt, rn, static_cast(Imm) & 0x1'FF); + SubAtomicImm(Op, ARMEmitter::SubRegSize::i64Bit, 0b00, rt, rn, static_cast(Imm) & 0x1'FF); } - void ldapur(FEXCore::ARMEmitter::XRegister rt, FEXCore::ARMEmitter::Register rn, int32_t Imm) { + void ldapur(ARMEmitter::XRegister rt, ARMEmitter::Register rn, int32_t Imm) { LOGMAN_THROW_A_FMT(Imm >= -256 && Imm <= 255, "Unscaled offset too large"); constexpr uint32_t Op = 0b0001'1001'000 << 21; - SubAtomicImm(Op, FEXCore::ARMEmitter::SubRegSize::i64Bit, 0b01, rt, rn, static_cast(Imm) & 0x1'FF); + SubAtomicImm(Op, ARMEmitter::SubRegSize::i64Bit, 0b01, rt, rn, static_cast(Imm) & 0x1'FF); } // Load register literal - void ldr(FEXCore::ARMEmitter::WRegister rt, int32_t Imm) { + void ldr(ARMEmitter::WRegister rt, int32_t Imm) { LOGMAN_THROW_A_FMT(Imm >= -1048576 && Imm <= 1048575 && ((Imm & 0b11) == 0), "Unscaled offset too large"); constexpr uint32_t Op = 0b0001'1000 << 24; LoadStoreLiteral(Op, rt, static_cast(Imm >> 2) & 0x7'FFFF); } - void ldr(FEXCore::ARMEmitter::SRegister rt, int32_t Imm) { + void ldr(ARMEmitter::SRegister rt, int32_t Imm) { LOGMAN_THROW_A_FMT(Imm >= -1048576 && Imm <= 1048575 && ((Imm & 0b11) == 0), "Unscaled offset too large"); constexpr uint32_t Op = 0b0001'1100 << 24; LoadStoreLiteral(Op, rt, static_cast(Imm >> 2) & 0x7'FFFF); } - void ldr(FEXCore::ARMEmitter::XRegister rt, int32_t Imm) { + void ldr(ARMEmitter::XRegister rt, int32_t Imm) { LOGMAN_THROW_A_FMT(Imm >= -1048576 && Imm <= 1048575 && ((Imm & 0b11) == 0), "Unscaled offset too large"); constexpr uint32_t Op = 0b0101'1000 << 24; LoadStoreLiteral(Op, rt, static_cast(Imm >> 2) & 0x7'FFFF); } - void ldr(FEXCore::ARMEmitter::DRegister rt, int32_t Imm) { + void ldr(ARMEmitter::DRegister rt, int32_t Imm) { LOGMAN_THROW_A_FMT(Imm >= -1048576 && Imm <= 1048575 && ((Imm & 0b11) == 0), "Unscaled offset too large"); constexpr uint32_t Op = 0b0101'1100 << 24; LoadStoreLiteral(Op, rt, static_cast(Imm >> 2) & 0x7'FFFF); } - void ldrs(FEXCore::ARMEmitter::WRegister rt, int32_t Imm) { + void ldrs(ARMEmitter::WRegister rt, int32_t Imm) { LOGMAN_THROW_A_FMT(Imm >= -1048576 && Imm <= 1048575 && ((Imm & 0b11) == 0), "Unscaled offset too large"); constexpr uint32_t Op = 0b1001'1000 << 24; LoadStoreLiteral(Op, rt, static_cast(Imm >> 2) & 0x7'FFFF); } - void ldr(FEXCore::ARMEmitter::QRegister rt, int32_t Imm) { + void ldr(ARMEmitter::QRegister rt, int32_t Imm) { LOGMAN_THROW_A_FMT(Imm >= -1048576 && Imm <= 1048575 && ((Imm & 0b11) == 0), "Unscaled offset too large"); constexpr uint32_t Op = 0b1001'1100 << 24; LoadStoreLiteral(Op, rt, static_cast(Imm >> 2) & 0x7'FFFF); } - void prfm(FEXCore::ARMEmitter::Prefetch prfop, int32_t Imm) { + void prfm(ARMEmitter::Prefetch prfop, int32_t Imm) { LOGMAN_THROW_A_FMT(Imm >= -1048576 && Imm <= 1048575 && ((Imm & 0b11) == 0), "Unscaled offset too large"); constexpr uint32_t Op = 0b1101'1000 << 24; LoadStoreLiteral(Op, prfop, static_cast(Imm >> 2) & 0x7'FFFF); } - void ldr(FEXCore::ARMEmitter::WRegister rt, BackwardLabel const* Label) { + void ldr(ARMEmitter::WRegister rt, BackwardLabel const* Label) { int32_t Imm = static_cast(Label->Location - GetCursorAddress()); LOGMAN_THROW_A_FMT(Imm >= -1048576 && Imm <= 1048575 && ((Imm & 0b11) == 0), "Unscaled offset too large"); constexpr uint32_t Op = 0b0001'1000 << 24; LoadStoreLiteral(Op, rt, static_cast(Imm >> 2) & 0x7'FFFF); } - void ldr(FEXCore::ARMEmitter::SRegister rt, BackwardLabel const* Label) { + void ldr(ARMEmitter::SRegister rt, BackwardLabel const* Label) { int32_t Imm = static_cast(Label->Location - GetCursorAddress()); LOGMAN_THROW_A_FMT(Imm >= -1048576 && Imm <= 1048575 && ((Imm & 0b11) == 0), "Unscaled offset too large"); constexpr uint32_t Op = 0b0001'1100 << 24; LoadStoreLiteral(Op, rt, static_cast(Imm >> 2) & 0x7'FFFF); } - void ldr(FEXCore::ARMEmitter::XRegister rt, BackwardLabel const* Label) { + void ldr(ARMEmitter::XRegister rt, BackwardLabel const* Label) { int32_t Imm = static_cast(Label->Location - GetCursorAddress()); LOGMAN_THROW_A_FMT(Imm >= -1048576 && Imm <= 1048575 && ((Imm & 0b11) == 0), "Unscaled offset too large"); constexpr uint32_t Op = 0b0101'1000 << 24; LoadStoreLiteral(Op, rt, static_cast(Imm >> 2) & 0x7'FFFF); } - void ldr(FEXCore::ARMEmitter::DRegister rt, BackwardLabel const* Label) { + void ldr(ARMEmitter::DRegister rt, BackwardLabel const* Label) { int32_t Imm = static_cast(Label->Location - GetCursorAddress()); LOGMAN_THROW_A_FMT(Imm >= -1048576 && Imm <= 1048575 && ((Imm & 0b11) == 0), "Unscaled offset too large"); constexpr uint32_t Op = 0b0101'1100 << 24; LoadStoreLiteral(Op, rt, static_cast(Imm >> 2) & 0x7'FFFF); } - void ldrsw(FEXCore::ARMEmitter::XRegister rt, BackwardLabel const* Label) { + void ldrsw(ARMEmitter::XRegister rt, BackwardLabel const* Label) { int32_t Imm = static_cast(Label->Location - GetCursorAddress()); LOGMAN_THROW_A_FMT(Imm >= -1048576 && Imm <= 1048575 && ((Imm & 0b11) == 0), "Unscaled offset too large"); constexpr uint32_t Op = 0b1001'1000 << 24; LoadStoreLiteral(Op, rt, static_cast(Imm >> 2) & 0x7'FFFF); } - void ldr(FEXCore::ARMEmitter::QRegister rt, BackwardLabel const* Label) { + void ldr(ARMEmitter::QRegister rt, BackwardLabel const* Label) { int32_t Imm = static_cast(Label->Location - GetCursorAddress()); LOGMAN_THROW_A_FMT(Imm >= -1048576 && Imm <= 1048575 && ((Imm & 0b11) == 0), "Unscaled offset too large"); constexpr uint32_t Op = 0b1001'1100 << 24; LoadStoreLiteral(Op, rt, static_cast(Imm >> 2) & 0x7'FFFF); } - void prfm(FEXCore::ARMEmitter::Prefetch prfop, BackwardLabel const* Label) { + void prfm(ARMEmitter::Prefetch prfop, BackwardLabel const* Label) { int32_t Imm = static_cast(Label->Location - GetCursorAddress()); LOGMAN_THROW_A_FMT(Imm >= -1048576 && Imm <= 1048575 && ((Imm & 0b11) == 0), "Unscaled offset too large"); constexpr uint32_t Op = 0b1101'1000 << 24; @@ -2123,7 +2123,7 @@ public: template requires (std::is_same_v || std::is_same_v) - void ldr(FEXCore::ARMEmitter::WRegister rt, LabelType *Label) { + void ldr(ARMEmitter::WRegister rt, LabelType *Label) { AddLocationToLabel(Label, SingleUseForwardLabel{ .Location = GetCursorAddress(), .Type = SingleUseForwardLabel::InstType::RELATIVE_LOAD }); constexpr uint32_t Op = 0b0001'1000 << 24; LoadStoreLiteral(Op, rt, 0); @@ -2131,7 +2131,7 @@ public: template requires (std::is_same_v || std::is_same_v) - void ldr(FEXCore::ARMEmitter::SRegister rt, LabelType *Label) { + void ldr(ARMEmitter::SRegister rt, LabelType *Label) { AddLocationToLabel(Label, SingleUseForwardLabel{ .Location = GetCursorAddress(), .Type = SingleUseForwardLabel::InstType::RELATIVE_LOAD }); constexpr uint32_t Op = 0b0001'1100 << 24; LoadStoreLiteral(Op, rt, 0); @@ -2139,7 +2139,7 @@ public: template requires (std::is_same_v || std::is_same_v) - void ldr(FEXCore::ARMEmitter::XRegister rt, LabelType *Label) { + void ldr(ARMEmitter::XRegister rt, LabelType *Label) { AddLocationToLabel(Label, SingleUseForwardLabel{ .Location = GetCursorAddress(), .Type = SingleUseForwardLabel::InstType::RELATIVE_LOAD }); constexpr uint32_t Op = 0b0101'1000 << 24; LoadStoreLiteral(Op, rt, 0); @@ -2147,7 +2147,7 @@ public: template requires (std::is_same_v || std::is_same_v) - void ldr(FEXCore::ARMEmitter::DRegister rt, LabelType *Label) { + void ldr(ARMEmitter::DRegister rt, LabelType *Label) { AddLocationToLabel(Label, SingleUseForwardLabel{ .Location = GetCursorAddress(), .Type = SingleUseForwardLabel::InstType::RELATIVE_LOAD }); constexpr uint32_t Op = 0b0101'1100 << 24; LoadStoreLiteral(Op, rt, 0); @@ -2155,7 +2155,7 @@ public: template requires (std::is_same_v || std::is_same_v) - void ldrsw(FEXCore::ARMEmitter::XRegister rt, LabelType *Label) { + void ldrsw(ARMEmitter::XRegister rt, LabelType *Label) { AddLocationToLabel(Label, SingleUseForwardLabel{ .Location = GetCursorAddress(), .Type = SingleUseForwardLabel::InstType::RELATIVE_LOAD }); constexpr uint32_t Op = 0b1001'1000 << 24; LoadStoreLiteral(Op, rt, 0); @@ -2163,7 +2163,7 @@ public: template requires (std::is_same_v || std::is_same_v) - void ldr(FEXCore::ARMEmitter::QRegister rt, LabelType *Label) { + void ldr(ARMEmitter::QRegister rt, LabelType *Label) { AddLocationToLabel(Label, SingleUseForwardLabel{ .Location = GetCursorAddress(), .Type = SingleUseForwardLabel::InstType::RELATIVE_LOAD }); constexpr uint32_t Op = 0b1001'1100 << 24; LoadStoreLiteral(Op, rt, 0); @@ -2171,13 +2171,13 @@ public: template requires (std::is_same_v || std::is_same_v) - void prfm(FEXCore::ARMEmitter::Prefetch prfop, LabelType *Label) { + void prfm(ARMEmitter::Prefetch prfop, LabelType *Label) { AddLocationToLabel(Label, SingleUseForwardLabel{ .Location = GetCursorAddress(), .Type = SingleUseForwardLabel::InstType::RELATIVE_LOAD }); constexpr uint32_t Op = 0b1101'1000 << 24; LoadStoreLiteral(Op, prfop, 0); } - void ldr(FEXCore::ARMEmitter::WRegister rt, BiDirectionalLabel *Label) { + void ldr(ARMEmitter::WRegister rt, BiDirectionalLabel *Label) { if (Label->Backward.Location) { ldr(rt, &Label->Backward); } @@ -2185,7 +2185,7 @@ public: ldr(rt, &Label->Forward); } } - void ldr(FEXCore::ARMEmitter::SRegister rt, BiDirectionalLabel *Label) { + void ldr(ARMEmitter::SRegister rt, BiDirectionalLabel *Label) { if (Label->Backward.Location) { ldr(rt, &Label->Backward); } @@ -2193,7 +2193,7 @@ public: ldr(rt, &Label->Forward); } } - void ldr(FEXCore::ARMEmitter::XRegister rt, BiDirectionalLabel *Label) { + void ldr(ARMEmitter::XRegister rt, BiDirectionalLabel *Label) { if (Label->Backward.Location) { ldr(rt, &Label->Backward); } @@ -2201,7 +2201,7 @@ public: ldr(rt, &Label->Forward); } } - void ldr(FEXCore::ARMEmitter::DRegister rt, BiDirectionalLabel *Label) { + void ldr(ARMEmitter::DRegister rt, BiDirectionalLabel *Label) { if (Label->Backward.Location) { ldr(rt, &Label->Backward); } @@ -2209,7 +2209,7 @@ public: ldr(rt, &Label->Forward); } } - void ldrs(FEXCore::ARMEmitter::WRegister rt, BiDirectionalLabel *Label) { + void ldrs(ARMEmitter::WRegister rt, BiDirectionalLabel *Label) { if (Label->Backward.Location) { ldr(rt, &Label->Backward); } @@ -2217,7 +2217,7 @@ public: ldr(rt, &Label->Forward); } } - void ldr(FEXCore::ARMEmitter::QRegister rt, BiDirectionalLabel *Label) { + void ldr(ARMEmitter::QRegister rt, BiDirectionalLabel *Label) { if (Label->Backward.Location) { ldr(rt, &Label->Backward); } @@ -2225,7 +2225,7 @@ public: ldr(rt, &Label->Forward); } } - void prfm(FEXCore::ARMEmitter::Prefetch prfop, BiDirectionalLabel *Label) { + void prfm(ARMEmitter::Prefetch prfop, BiDirectionalLabel *Label) { if (Label->Backward.Location) { prfm(prfop, &Label->Backward); } @@ -2237,52 +2237,52 @@ public: // Memory copy/set // TODO // Loadstore no-allocate pair - void stnp(FEXCore::ARMEmitter::WRegister rt, FEXCore::ARMEmitter::WRegister rt2, FEXCore::ARMEmitter::Register rn, int32_t Imm) { + void stnp(ARMEmitter::WRegister rt, ARMEmitter::WRegister rt2, ARMEmitter::Register rn, int32_t Imm) { LOGMAN_THROW_A_FMT(Imm >= -256 && Imm <= 252 && ((Imm & 0b11) == 0), "Unscaled offset too large"); constexpr uint32_t Op = 0b0010'1000'00 << 22; LoadStoreNoAllocate(Op, rt, rt2, rn, static_cast(Imm >> 2) & 0b111'1111); } - void ldnp(FEXCore::ARMEmitter::WRegister rt, FEXCore::ARMEmitter::WRegister rt2, FEXCore::ARMEmitter::Register rn, int32_t Imm) { + void ldnp(ARMEmitter::WRegister rt, ARMEmitter::WRegister rt2, ARMEmitter::Register rn, int32_t Imm) { LOGMAN_THROW_A_FMT(Imm >= -256 && Imm <= 252 && ((Imm & 0b11) == 0), "Unscaled offset too large"); constexpr uint32_t Op = 0b0010'1000'01 << 22; LoadStoreNoAllocate(Op, rt, rt2, rn, static_cast(Imm >> 2) & 0b111'1111); } - void stnp(FEXCore::ARMEmitter::SRegister rt, FEXCore::ARMEmitter::SRegister rt2, FEXCore::ARMEmitter::Register rn, int32_t Imm) { + void stnp(ARMEmitter::SRegister rt, ARMEmitter::SRegister rt2, ARMEmitter::Register rn, int32_t Imm) { LOGMAN_THROW_A_FMT(Imm >= -256 && Imm <= 252 && ((Imm & 0b11) == 0), "Unscaled offset too large"); constexpr uint32_t Op = 0b0010'1100'00 << 22; LoadStoreNoAllocate(Op, rt, rt2, rn, static_cast(Imm >> 2) & 0b111'1111); } - void ldnp(FEXCore::ARMEmitter::SRegister rt, FEXCore::ARMEmitter::SRegister rt2, FEXCore::ARMEmitter::Register rn, int32_t Imm) { + void ldnp(ARMEmitter::SRegister rt, ARMEmitter::SRegister rt2, ARMEmitter::Register rn, int32_t Imm) { LOGMAN_THROW_A_FMT(Imm >= -256 && Imm <= 252 && ((Imm & 0b11) == 0), "Unscaled offset too large"); constexpr uint32_t Op = 0b0010'1100'01 << 22; LoadStoreNoAllocate(Op, rt, rt2, rn, static_cast(Imm >> 2) & 0b111'1111); } - void stnp(FEXCore::ARMEmitter::XRegister rt, FEXCore::ARMEmitter::XRegister rt2, FEXCore::ARMEmitter::Register rn, int32_t Imm) { + void stnp(ARMEmitter::XRegister rt, ARMEmitter::XRegister rt2, ARMEmitter::Register rn, int32_t Imm) { LOGMAN_THROW_A_FMT(Imm >= -512 && Imm <= 504 && ((Imm & 0b111) == 0), "Unscaled offset too large"); constexpr uint32_t Op = 0b1010'1000'00 << 22; LoadStoreNoAllocate(Op, rt, rt2, rn, static_cast(Imm >> 3) & 0b111'1111); } - void ldnp(FEXCore::ARMEmitter::XRegister rt, FEXCore::ARMEmitter::XRegister rt2, FEXCore::ARMEmitter::Register rn, int32_t Imm) { + void ldnp(ARMEmitter::XRegister rt, ARMEmitter::XRegister rt2, ARMEmitter::Register rn, int32_t Imm) { LOGMAN_THROW_A_FMT(Imm >= -512 && Imm <= 504 && ((Imm & 0b111) == 0), "Unscaled offset too large"); constexpr uint32_t Op = 0b1010'1000'01 << 22; LoadStoreNoAllocate(Op, rt, rt2, rn, static_cast(Imm >> 3) & 0b111'1111); } - void stnp(FEXCore::ARMEmitter::DRegister rt, FEXCore::ARMEmitter::DRegister rt2, FEXCore::ARMEmitter::Register rn, int32_t Imm) { + void stnp(ARMEmitter::DRegister rt, ARMEmitter::DRegister rt2, ARMEmitter::Register rn, int32_t Imm) { LOGMAN_THROW_A_FMT(Imm >= -512 && Imm <= 504 && ((Imm & 0b111) == 0), "Unscaled offset too large"); constexpr uint32_t Op = 0b0110'1100'00 << 22; LoadStoreNoAllocate(Op, rt, rt2, rn, static_cast(Imm >> 3) & 0b111'1111); } - void ldnp(FEXCore::ARMEmitter::DRegister rt, FEXCore::ARMEmitter::DRegister rt2, FEXCore::ARMEmitter::Register rn, int32_t Imm) { + void ldnp(ARMEmitter::DRegister rt, ARMEmitter::DRegister rt2, ARMEmitter::Register rn, int32_t Imm) { LOGMAN_THROW_A_FMT(Imm >= -512 && Imm <= 504 && ((Imm & 0b111) == 0), "Unscaled offset too large"); constexpr uint32_t Op = 0b0110'1100'01 << 22; LoadStoreNoAllocate(Op, rt, rt2, rn, static_cast(Imm >> 3) & 0b111'1111); } - void stnp(FEXCore::ARMEmitter::QRegister rt, FEXCore::ARMEmitter::QRegister rt2, FEXCore::ARMEmitter::Register rn, int32_t Imm) { + void stnp(ARMEmitter::QRegister rt, ARMEmitter::QRegister rt2, ARMEmitter::Register rn, int32_t Imm) { LOGMAN_THROW_A_FMT(Imm >= -1024 && Imm <= 1008 && ((Imm & 0b1111) == 0), "Unscaled offset too large"); constexpr uint32_t Op = 0b1010'1100'00 << 22; LoadStoreNoAllocate(Op, rt, rt2, rn, static_cast(Imm >> 4) & 0b111'1111); } - void ldnp(FEXCore::ARMEmitter::QRegister rt, FEXCore::ARMEmitter::QRegister rt2, FEXCore::ARMEmitter::Register rn, int32_t Imm) { + void ldnp(ARMEmitter::QRegister rt, ARMEmitter::QRegister rt2, ARMEmitter::Register rn, int32_t Imm) { LOGMAN_THROW_A_FMT(Imm >= -1024 && Imm <= 1008 && ((Imm & 0b1111) == 0), "Unscaled offset too large"); constexpr uint32_t Op = 0b1010'1100'01 << 22; LoadStoreNoAllocate(Op, rt, rt2, rn, static_cast(Imm >> 4) & 0b111'1111); @@ -2291,7 +2291,7 @@ public: // Loadstore register pair offset // Loadstore register pair pre-indexed template - void stp(FEXCore::ARMEmitter::WRegister rt, FEXCore::ARMEmitter::WRegister rt2, FEXCore::ARMEmitter::Register rn, int32_t Imm = 0) { + void stp(ARMEmitter::WRegister rt, ARMEmitter::WRegister rt2, ARMEmitter::Register rn, int32_t Imm = 0) { LOGMAN_THROW_A_FMT(Imm >= -256 && Imm <= 252 && ((Imm & 0b11) == 0), "Unscaled offset too large"); constexpr uint32_t Op = (0b0010'1000'00 << 22) | ( @@ -2303,7 +2303,7 @@ public: LoadStorePair(Op, rt, rt2, rn, (Imm >> 2) & 0b111'1111); } template - void ldp(FEXCore::ARMEmitter::WRegister rt, FEXCore::ARMEmitter::WRegister rt2, FEXCore::ARMEmitter::Register rn, int32_t Imm = 0) { + void ldp(ARMEmitter::WRegister rt, ARMEmitter::WRegister rt2, ARMEmitter::Register rn, int32_t Imm = 0) { LOGMAN_THROW_A_FMT(Imm >= -256 && Imm <= 252 && ((Imm & 0b11) == 0), "Unscaled offset too large"); constexpr uint32_t Op = (0b0010'1000'01 << 22) | ( @@ -2315,7 +2315,7 @@ public: LoadStorePair(Op, rt, rt2, rn, (Imm >> 2) & 0b111'1111); } template - void ldpsw(FEXCore::ARMEmitter::XRegister rt, FEXCore::ARMEmitter::XRegister rt2, FEXCore::ARMEmitter::Register rn, int32_t Imm = 0) { + void ldpsw(ARMEmitter::XRegister rt, ARMEmitter::XRegister rt2, ARMEmitter::Register rn, int32_t Imm = 0) { LOGMAN_THROW_A_FMT(Imm >= -256 && Imm <= 252 && ((Imm & 0b11) == 0), "Unscaled offset too large"); constexpr uint32_t Op = (0b0110'1000'01 << 22) | ( @@ -2326,7 +2326,7 @@ public: LoadStorePair(Op, rt, rt2, rn, (Imm >> 2) & 0b111'1111); } template - void stp(FEXCore::ARMEmitter::XRegister rt, FEXCore::ARMEmitter::XRegister rt2, FEXCore::ARMEmitter::Register rn, int32_t Imm = 0) { + void stp(ARMEmitter::XRegister rt, ARMEmitter::XRegister rt2, ARMEmitter::Register rn, int32_t Imm = 0) { LOGMAN_THROW_A_FMT(Imm >= -512 && Imm <= 504 && ((Imm & 0b111) == 0), "Unscaled offset too large"); constexpr uint32_t Op = (0b1010'1000'00 << 22) | ( @@ -2338,7 +2338,7 @@ public: LoadStorePair(Op, rt, rt2, rn, (Imm >> 3) & 0b111'1111); } template - void ldp(FEXCore::ARMEmitter::XRegister rt, FEXCore::ARMEmitter::XRegister rt2, FEXCore::ARMEmitter::Register rn, int32_t Imm = 0) { + void ldp(ARMEmitter::XRegister rt, ARMEmitter::XRegister rt2, ARMEmitter::Register rn, int32_t Imm = 0) { LOGMAN_THROW_A_FMT(Imm >= -512 && Imm <= 504 && ((Imm & 0b111) == 0), "Unscaled offset too large"); constexpr uint32_t Op = (0b1010'1000'01 << 22) | ( @@ -2350,102 +2350,102 @@ public: LoadStorePair(Op, rt, rt2, rn, (Imm >> 3) & 0b111'1111); } template - void stp(FEXCore::ARMEmitter::SRegister rt, FEXCore::ARMEmitter::SRegister rt2, FEXCore::ARMEmitter::Register rn, int32_t Imm = 0) { + void stp(ARMEmitter::SRegister rt, ARMEmitter::SRegister rt2, ARMEmitter::Register rn, int32_t Imm = 0) { stp_w(rt.V(), rt2.V(), rn, Imm); } template - void ldp(FEXCore::ARMEmitter::SRegister rt, FEXCore::ARMEmitter::SRegister rt2, FEXCore::ARMEmitter::Register rn, int32_t Imm = 0) { + void ldp(ARMEmitter::SRegister rt, ARMEmitter::SRegister rt2, ARMEmitter::Register rn, int32_t Imm = 0) { ldp_w(rt.V(), rt2.V(), rn, Imm); } template - void stp(FEXCore::ARMEmitter::DRegister rt, FEXCore::ARMEmitter::DRegister rt2, FEXCore::ARMEmitter::Register rn, int32_t Imm = 0) { + void stp(ARMEmitter::DRegister rt, ARMEmitter::DRegister rt2, ARMEmitter::Register rn, int32_t Imm = 0) { stp_x(rt.V(), rt2.V(), rn, Imm); } template - void ldp(FEXCore::ARMEmitter::DRegister rt, FEXCore::ARMEmitter::DRegister rt2, FEXCore::ARMEmitter::Register rn, int32_t Imm = 0) { + void ldp(ARMEmitter::DRegister rt, ARMEmitter::DRegister rt2, ARMEmitter::Register rn, int32_t Imm = 0) { ldp_x(rt.V(), rt2.V(), rn, Imm); } template - void stp(FEXCore::ARMEmitter::QRegister rt, FEXCore::ARMEmitter::QRegister rt2, FEXCore::ARMEmitter::Register rn, int32_t Imm = 0) { + void stp(ARMEmitter::QRegister rt, ARMEmitter::QRegister rt2, ARMEmitter::Register rn, int32_t Imm = 0) { stp_q(rt.V(), rt2.V(), rn, Imm); } template - void ldp(FEXCore::ARMEmitter::QRegister rt, FEXCore::ARMEmitter::QRegister rt2, FEXCore::ARMEmitter::Register rn, int32_t Imm = 0) { + void ldp(ARMEmitter::QRegister rt, ARMEmitter::QRegister rt2, ARMEmitter::Register rn, int32_t Imm = 0) { ldp_q(rt.V(), rt2.V(), rn, Imm); } // Loadstore register unscaled immediate - void sturb(FEXCore::ARMEmitter::Register rt, FEXCore::ARMEmitter::Register rn, int32_t Imm = 0) { + void sturb(ARMEmitter::Register rt, ARMEmitter::Register rn, int32_t Imm = 0) { stXrb(rt, rn, Imm); } - void ldurb(FEXCore::ARMEmitter::Register rt, FEXCore::ARMEmitter::Register rn, int32_t Imm = 0) { + void ldurb(ARMEmitter::Register rt, ARMEmitter::Register rn, int32_t Imm = 0) { ldXrb(rt, rn, Imm); } - void sturb(FEXCore::ARMEmitter::VRegister rt, FEXCore::ARMEmitter::Register rn, int32_t Imm = 0) { + void sturb(ARMEmitter::VRegister rt, ARMEmitter::Register rn, int32_t Imm = 0) { stXrb(rt, rn, Imm); } - void ldurb(FEXCore::ARMEmitter::VRegister rt, FEXCore::ARMEmitter::Register rn, int32_t Imm = 0) { + void ldurb(ARMEmitter::VRegister rt, ARMEmitter::Register rn, int32_t Imm = 0) { ldXrb(rt, rn, Imm); } - void ldursb(FEXCore::ARMEmitter::XRegister rt, FEXCore::ARMEmitter::Register rn, int32_t Imm = 0) { + void ldursb(ARMEmitter::XRegister rt, ARMEmitter::Register rn, int32_t Imm = 0) { ldXrsb(rt, rn, Imm); } - void ldursb(FEXCore::ARMEmitter::WRegister rt, FEXCore::ARMEmitter::Register rn, int32_t Imm = 0) { + void ldursb(ARMEmitter::WRegister rt, ARMEmitter::Register rn, int32_t Imm = 0) { ldXrsb(rt, rn, Imm); } - void sturh(FEXCore::ARMEmitter::Register rt, FEXCore::ARMEmitter::Register rn, int32_t Imm = 0) { + void sturh(ARMEmitter::Register rt, ARMEmitter::Register rn, int32_t Imm = 0) { stXrh(rt, rn, Imm); } - void ldurh(FEXCore::ARMEmitter::Register rt, FEXCore::ARMEmitter::Register rn, int32_t Imm = 0) { + void ldurh(ARMEmitter::Register rt, ARMEmitter::Register rn, int32_t Imm = 0) { ldXrh(rt, rn, Imm); } - void sturh(FEXCore::ARMEmitter::VRegister rt, FEXCore::ARMEmitter::Register rn, int32_t Imm = 0) { + void sturh(ARMEmitter::VRegister rt, ARMEmitter::Register rn, int32_t Imm = 0) { stXrh(rt, rn, Imm); } - void ldurh(FEXCore::ARMEmitter::VRegister rt, FEXCore::ARMEmitter::Register rn, int32_t Imm = 0) { + void ldurh(ARMEmitter::VRegister rt, ARMEmitter::Register rn, int32_t Imm = 0) { ldXrh(rt, rn, Imm); } - void ldursh(FEXCore::ARMEmitter::XRegister rt, FEXCore::ARMEmitter::Register rn, int32_t Imm = 0) { + void ldursh(ARMEmitter::XRegister rt, ARMEmitter::Register rn, int32_t Imm = 0) { ldXrsh(rt, rn, Imm); } - void ldursh(FEXCore::ARMEmitter::WRegister rt, FEXCore::ARMEmitter::Register rn, int32_t Imm = 0) { + void ldursh(ARMEmitter::WRegister rt, ARMEmitter::Register rn, int32_t Imm = 0) { ldXrsh(rt, rn, Imm); } - void stur(FEXCore::ARMEmitter::WRegister rt, FEXCore::ARMEmitter::Register rn, int32_t Imm = 0) { + void stur(ARMEmitter::WRegister rt, ARMEmitter::Register rn, int32_t Imm = 0) { stXr(rt, rn, Imm); } - void ldur(FEXCore::ARMEmitter::WRegister rt, FEXCore::ARMEmitter::Register rn, int32_t Imm = 0) { + void ldur(ARMEmitter::WRegister rt, ARMEmitter::Register rn, int32_t Imm = 0) { ldXr(rt, rn, Imm); } - void stur(FEXCore::ARMEmitter::SRegister rt, FEXCore::ARMEmitter::Register rn, int32_t Imm = 0) { + void stur(ARMEmitter::SRegister rt, ARMEmitter::Register rn, int32_t Imm = 0) { stXr(rt, rn, Imm); } - void ldur(FEXCore::ARMEmitter::SRegister rt, FEXCore::ARMEmitter::Register rn, int32_t Imm = 0) { + void ldur(ARMEmitter::SRegister rt, ARMEmitter::Register rn, int32_t Imm = 0) { ldXr(rt, rn, Imm); } - void ldursw(FEXCore::ARMEmitter::XRegister rt, FEXCore::ARMEmitter::Register rn, int32_t Imm = 0) { + void ldursw(ARMEmitter::XRegister rt, ARMEmitter::Register rn, int32_t Imm = 0) { ldXrsw(rt, rn, Imm); } - void stur(FEXCore::ARMEmitter::XRegister rt, FEXCore::ARMEmitter::Register rn, int32_t Imm = 0) { + void stur(ARMEmitter::XRegister rt, ARMEmitter::Register rn, int32_t Imm = 0) { stXr(rt, rn, Imm); } - void ldur(FEXCore::ARMEmitter::XRegister rt, FEXCore::ARMEmitter::Register rn, int32_t Imm = 0) { + void ldur(ARMEmitter::XRegister rt, ARMEmitter::Register rn, int32_t Imm = 0) { ldXr(rt, rn, Imm); } - void stur(FEXCore::ARMEmitter::DRegister rt, FEXCore::ARMEmitter::Register rn, int32_t Imm = 0) { + void stur(ARMEmitter::DRegister rt, ARMEmitter::Register rn, int32_t Imm = 0) { stXr(rt, rn, Imm); } - void ldur(FEXCore::ARMEmitter::DRegister rt, FEXCore::ARMEmitter::Register rn, int32_t Imm = 0) { + void ldur(ARMEmitter::DRegister rt, ARMEmitter::Register rn, int32_t Imm = 0) { ldXr(rt, rn, Imm); } - void stur(FEXCore::ARMEmitter::QRegister rt, FEXCore::ARMEmitter::Register rn, int32_t Imm = 0) { + void stur(ARMEmitter::QRegister rt, ARMEmitter::Register rn, int32_t Imm = 0) { stXr(rt, rn, Imm); } - void ldur(FEXCore::ARMEmitter::QRegister rt, FEXCore::ARMEmitter::Register rn, int32_t Imm = 0) { + void ldur(ARMEmitter::QRegister rt, ARMEmitter::Register rn, int32_t Imm = 0) { ldXr(rt, rn, Imm); } template - void prfum(FEXCore::ARMEmitter::Prefetch prfop, FEXCore::ARMEmitter::Register rn, int32_t Imm = 0) { + void prfum(ARMEmitter::Prefetch prfop, ARMEmitter::Register rn, int32_t Imm = 0) { LOGMAN_THROW_A_FMT(Imm >= -256 && Imm <= 255, "Unscaled offset too large"); static_assert(Index == IndexType::OFFSET, "Doesn't support another index type"); @@ -2459,158 +2459,158 @@ public: // Loadstore register immediate pre-indexed template requires(Index == IndexType::POST || Index == IndexType::PRE) - void strb(FEXCore::ARMEmitter::Register rt, FEXCore::ARMEmitter::Register rn, int32_t Imm = 0) { + void strb(ARMEmitter::Register rt, ARMEmitter::Register rn, int32_t Imm = 0) { stXrb(rt, rn, Imm); } template requires(Index == IndexType::POST || Index == IndexType::PRE) - void ldrb(FEXCore::ARMEmitter::Register rt, FEXCore::ARMEmitter::Register rn, int32_t Imm = 0) { + void ldrb(ARMEmitter::Register rt, ARMEmitter::Register rn, int32_t Imm = 0) { ldXrb(rt, rn, Imm); } template requires(Index == IndexType::POST || Index == IndexType::PRE) - void strb(FEXCore::ARMEmitter::VRegister rt, FEXCore::ARMEmitter::Register rn, int32_t Imm = 0) { + void strb(ARMEmitter::VRegister rt, ARMEmitter::Register rn, int32_t Imm = 0) { stXrb(rt, rn, Imm); } template requires(Index == IndexType::POST || Index == IndexType::PRE) - void ldrb(FEXCore::ARMEmitter::VRegister rt, FEXCore::ARMEmitter::Register rn, int32_t Imm = 0) { + void ldrb(ARMEmitter::VRegister rt, ARMEmitter::Register rn, int32_t Imm = 0) { ldXrb(rt, rn, Imm); } template requires(Index == IndexType::POST || Index == IndexType::PRE) - void ldrsb(FEXCore::ARMEmitter::XRegister rt, FEXCore::ARMEmitter::Register rn, int32_t Imm = 0) { + void ldrsb(ARMEmitter::XRegister rt, ARMEmitter::Register rn, int32_t Imm = 0) { ldXrsb(rt, rn, Imm); } template requires(Index == IndexType::POST || Index == IndexType::PRE) - void ldrsb(FEXCore::ARMEmitter::WRegister rt, FEXCore::ARMEmitter::Register rn, int32_t Imm = 0) { + void ldrsb(ARMEmitter::WRegister rt, ARMEmitter::Register rn, int32_t Imm = 0) { ldXrsb(rt, rn, Imm); } template requires(Index == IndexType::POST || Index == IndexType::PRE) - void strh(FEXCore::ARMEmitter::Register rt, FEXCore::ARMEmitter::Register rn, int32_t Imm = 0) { + void strh(ARMEmitter::Register rt, ARMEmitter::Register rn, int32_t Imm = 0) { stXrh(rt, rn, Imm); } template requires(Index == IndexType::POST || Index == IndexType::PRE) - void ldrh(FEXCore::ARMEmitter::Register rt, FEXCore::ARMEmitter::Register rn, int32_t Imm = 0) { + void ldrh(ARMEmitter::Register rt, ARMEmitter::Register rn, int32_t Imm = 0) { ldXrh(rt, rn, Imm); } template requires(Index == IndexType::POST || Index == IndexType::PRE) - void strh(FEXCore::ARMEmitter::VRegister rt, FEXCore::ARMEmitter::Register rn, int32_t Imm = 0) { + void strh(ARMEmitter::VRegister rt, ARMEmitter::Register rn, int32_t Imm = 0) { stXrh(rt, rn, Imm); } template requires(Index == IndexType::POST || Index == IndexType::PRE) - void ldrh(FEXCore::ARMEmitter::VRegister rt, FEXCore::ARMEmitter::Register rn, int32_t Imm = 0) { + void ldrh(ARMEmitter::VRegister rt, ARMEmitter::Register rn, int32_t Imm = 0) { ldXrh(rt, rn, Imm); } template requires(Index == IndexType::POST || Index == IndexType::PRE) - void ldrsh(FEXCore::ARMEmitter::XRegister rt, FEXCore::ARMEmitter::Register rn, int32_t Imm = 0) { + void ldrsh(ARMEmitter::XRegister rt, ARMEmitter::Register rn, int32_t Imm = 0) { ldXrsh(rt, rn, Imm); } template requires(Index == IndexType::POST || Index == IndexType::PRE) - void ldrsh(FEXCore::ARMEmitter::WRegister rt, FEXCore::ARMEmitter::Register rn, int32_t Imm = 0) { + void ldrsh(ARMEmitter::WRegister rt, ARMEmitter::Register rn, int32_t Imm = 0) { ldXrsh(rt, rn, Imm); } template requires(Index == IndexType::POST || Index == IndexType::PRE) - void str(FEXCore::ARMEmitter::WRegister rt, FEXCore::ARMEmitter::Register rn, int32_t Imm = 0) { + void str(ARMEmitter::WRegister rt, ARMEmitter::Register rn, int32_t Imm = 0) { stXr(rt, rn, Imm); } template requires(Index == IndexType::POST || Index == IndexType::PRE) - void ldr(FEXCore::ARMEmitter::WRegister rt, FEXCore::ARMEmitter::Register rn, int32_t Imm = 0) { + void ldr(ARMEmitter::WRegister rt, ARMEmitter::Register rn, int32_t Imm = 0) { ldXr(rt, rn, Imm); } template requires(Index == IndexType::POST || Index == IndexType::PRE) - void str(FEXCore::ARMEmitter::SRegister rt, FEXCore::ARMEmitter::Register rn, int32_t Imm = 0) { + void str(ARMEmitter::SRegister rt, ARMEmitter::Register rn, int32_t Imm = 0) { stXr(rt, rn, Imm); } template requires(Index == IndexType::POST || Index == IndexType::PRE) - void ldr(FEXCore::ARMEmitter::SRegister rt, FEXCore::ARMEmitter::Register rn, int32_t Imm = 0) { + void ldr(ARMEmitter::SRegister rt, ARMEmitter::Register rn, int32_t Imm = 0) { ldXr(rt, rn, Imm); } template requires(Index == IndexType::POST || Index == IndexType::PRE) - void ldrsw(FEXCore::ARMEmitter::XRegister rt, FEXCore::ARMEmitter::Register rn, int32_t Imm = 0) { + void ldrsw(ARMEmitter::XRegister rt, ARMEmitter::Register rn, int32_t Imm = 0) { ldXrsw(rt, rn, Imm); } template requires(Index == IndexType::POST || Index == IndexType::PRE) - void str(FEXCore::ARMEmitter::XRegister rt, FEXCore::ARMEmitter::Register rn, int32_t Imm = 0) { + void str(ARMEmitter::XRegister rt, ARMEmitter::Register rn, int32_t Imm = 0) { stXr(rt, rn, Imm); } template requires(Index == IndexType::POST || Index == IndexType::PRE) - void ldr(FEXCore::ARMEmitter::XRegister rt, FEXCore::ARMEmitter::Register rn, int32_t Imm = 0) { + void ldr(ARMEmitter::XRegister rt, ARMEmitter::Register rn, int32_t Imm = 0) { ldXr(rt, rn, Imm); } template requires(Index == IndexType::POST || Index == IndexType::PRE) - void str(FEXCore::ARMEmitter::DRegister rt, FEXCore::ARMEmitter::Register rn, int32_t Imm = 0) { + void str(ARMEmitter::DRegister rt, ARMEmitter::Register rn, int32_t Imm = 0) { stXr(rt, rn, Imm); } template requires(Index == IndexType::POST || Index == IndexType::PRE) - void ldr(FEXCore::ARMEmitter::DRegister rt, FEXCore::ARMEmitter::Register rn, int32_t Imm = 0) { + void ldr(ARMEmitter::DRegister rt, ARMEmitter::Register rn, int32_t Imm = 0) { ldXr(rt, rn, Imm); } template requires(Index == IndexType::POST || Index == IndexType::PRE) - void str(FEXCore::ARMEmitter::QRegister rt, FEXCore::ARMEmitter::Register rn, int32_t Imm = 0) { + void str(ARMEmitter::QRegister rt, ARMEmitter::Register rn, int32_t Imm = 0) { stXr(rt, rn, Imm); } template requires(Index == IndexType::POST || Index == IndexType::PRE) - void ldr(FEXCore::ARMEmitter::QRegister rt, FEXCore::ARMEmitter::Register rn, int32_t Imm = 0) { + void ldr(ARMEmitter::QRegister rt, ARMEmitter::Register rn, int32_t Imm = 0) { ldXr(rt, rn, Imm); } // Loadstore register unprivileged - void sttrb(FEXCore::ARMEmitter::Register rt, FEXCore::ARMEmitter::Register rn, int32_t Imm = 0) { + void sttrb(ARMEmitter::Register rt, ARMEmitter::Register rn, int32_t Imm = 0) { stXrb(rt, rn, Imm); } - void ldtrb(FEXCore::ARMEmitter::Register rt, FEXCore::ARMEmitter::Register rn, int32_t Imm = 0) { + void ldtrb(ARMEmitter::Register rt, ARMEmitter::Register rn, int32_t Imm = 0) { ldXrb(rt, rn, Imm); } - void ldtrsb(FEXCore::ARMEmitter::XRegister rt, FEXCore::ARMEmitter::Register rn, int32_t Imm = 0) { + void ldtrsb(ARMEmitter::XRegister rt, ARMEmitter::Register rn, int32_t Imm = 0) { ldXrsb(rt, rn, Imm); } - void ldtrsb(FEXCore::ARMEmitter::WRegister rt, FEXCore::ARMEmitter::Register rn, int32_t Imm = 0) { + void ldtrsb(ARMEmitter::WRegister rt, ARMEmitter::Register rn, int32_t Imm = 0) { ldXrsb(rt, rn, Imm); } - void sttrh(FEXCore::ARMEmitter::Register rt, FEXCore::ARMEmitter::Register rn, int32_t Imm = 0) { + void sttrh(ARMEmitter::Register rt, ARMEmitter::Register rn, int32_t Imm = 0) { stXrh(rt, rn, Imm); } - void ldtrh(FEXCore::ARMEmitter::Register rt, FEXCore::ARMEmitter::Register rn, int32_t Imm = 0) { + void ldtrh(ARMEmitter::Register rt, ARMEmitter::Register rn, int32_t Imm = 0) { ldXrh(rt, rn, Imm); } - void ldtrsh(FEXCore::ARMEmitter::XRegister rt, FEXCore::ARMEmitter::Register rn, int32_t Imm = 0) { + void ldtrsh(ARMEmitter::XRegister rt, ARMEmitter::Register rn, int32_t Imm = 0) { ldXrsh(rt, rn, Imm); } - void ldtrsh(FEXCore::ARMEmitter::WRegister rt, FEXCore::ARMEmitter::Register rn, int32_t Imm = 0) { + void ldtrsh(ARMEmitter::WRegister rt, ARMEmitter::Register rn, int32_t Imm = 0) { ldXrsh(rt, rn, Imm); } - void sttr(FEXCore::ARMEmitter::WRegister rt, FEXCore::ARMEmitter::Register rn, int32_t Imm = 0) { + void sttr(ARMEmitter::WRegister rt, ARMEmitter::Register rn, int32_t Imm = 0) { stXr(rt, rn, Imm); } - void ldtr(FEXCore::ARMEmitter::WRegister rt, FEXCore::ARMEmitter::Register rn, int32_t Imm = 0) { + void ldtr(ARMEmitter::WRegister rt, ARMEmitter::Register rn, int32_t Imm = 0) { ldXr(rt, rn, Imm); } - void ldtrsw(FEXCore::ARMEmitter::XRegister rt, FEXCore::ARMEmitter::Register rn, int32_t Imm = 0) { + void ldtrsw(ARMEmitter::XRegister rt, ARMEmitter::Register rn, int32_t Imm = 0) { ldXrsw(rt, rn, Imm); } - void sttr(FEXCore::ARMEmitter::XRegister rt, FEXCore::ARMEmitter::Register rn, int32_t Imm = 0) { + void sttr(ARMEmitter::XRegister rt, ARMEmitter::Register rn, int32_t Imm = 0) { stXr(rt, rn, Imm); } - void ldtr(FEXCore::ARMEmitter::XRegister rt, FEXCore::ARMEmitter::Register rn, int32_t Imm = 0) { + void ldtr(ARMEmitter::XRegister rt, ARMEmitter::Register rn, int32_t Imm = 0) { ldXr(rt, rn, Imm); } // Atomic memory operations @@ -3236,151 +3236,151 @@ public: } // Loadstore register-register offset - void strb(FEXCore::ARMEmitter::Register rt, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::ExtendedType Option, bool Shift = false) { + void strb(ARMEmitter::Register rt, ARMEmitter::Register rn, ARMEmitter::Register rm, ARMEmitter::ExtendedType Option, bool Shift = false) { LOGMAN_THROW_A_FMT((FEXCore::ToUnderlying(Option) & 0b010) == 0b010, "Unsupported Extendtype"); constexpr uint32_t Op = 0b0011'1000'001 << 21 | (0b10 << 10); LoadStoreRegisterOffset(Op, 0b00, rt, rn, rm, Option, Shift ? 1 : 0); } - void ldrb(FEXCore::ARMEmitter::Register rt, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::ExtendedType Option, bool Shift = false) { + void ldrb(ARMEmitter::Register rt, ARMEmitter::Register rn, ARMEmitter::Register rm, ARMEmitter::ExtendedType Option, bool Shift = false) { LOGMAN_THROW_A_FMT((FEXCore::ToUnderlying(Option) & 0b010) == 0b010, "Unsupported Extendtype"); constexpr uint32_t Op = 0b0011'1000'001 << 21 | (0b10 << 10); LoadStoreRegisterOffset(Op, 0b01, rt, rn, rm, Option, Shift ? 1 : 0); } - void ldrsb(FEXCore::ARMEmitter::XRegister rt, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::ExtendedType Option, bool Shift = false) { + void ldrsb(ARMEmitter::XRegister rt, ARMEmitter::Register rn, ARMEmitter::Register rm, ARMEmitter::ExtendedType Option, bool Shift = false) { LOGMAN_THROW_A_FMT((FEXCore::ToUnderlying(Option) & 0b010) == 0b010, "Unsupported Extendtype"); constexpr uint32_t Op = 0b0011'1000'001 << 21 | (0b10 << 10); LoadStoreRegisterOffset(Op, 0b10, rt, rn, rm, Option, Shift ? 1 : 0); } - void ldrsb(FEXCore::ARMEmitter::WRegister rt, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::ExtendedType Option, bool Shift = false) { + void ldrsb(ARMEmitter::WRegister rt, ARMEmitter::Register rn, ARMEmitter::Register rm, ARMEmitter::ExtendedType Option, bool Shift = false) { LOGMAN_THROW_A_FMT((FEXCore::ToUnderlying(Option) & 0b010) == 0b010, "Unsupported Extendtype"); constexpr uint32_t Op = 0b0011'1000'001 << 21 | (0b10 << 10); LoadStoreRegisterOffset(Op, 0b11, rt, rn, rm, Option, Shift ? 1 : 0); } - void strh(FEXCore::ARMEmitter::Register rt, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::ExtendedType Option, uint32_t Shift) { + void strh(ARMEmitter::Register rt, ARMEmitter::Register rn, ARMEmitter::Register rm, ARMEmitter::ExtendedType Option, uint32_t Shift) { LOGMAN_THROW_A_FMT((FEXCore::ToUnderlying(Option) & 0b010) == 0b010, "Unsupported Extendtype"); LOGMAN_THROW_A_FMT(Shift == 0 || Shift == 1, "Unsupported shift amount"); constexpr uint32_t Op = 0b0111'1000'001 << 21 | (0b10 << 10); LoadStoreRegisterOffset(Op, 0b00, rt, rn, rm, Option, Shift ? 1 : 0); } - void ldrh(FEXCore::ARMEmitter::Register rt, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::ExtendedType Option, uint32_t Shift) { + void ldrh(ARMEmitter::Register rt, ARMEmitter::Register rn, ARMEmitter::Register rm, ARMEmitter::ExtendedType Option, uint32_t Shift) { LOGMAN_THROW_A_FMT((FEXCore::ToUnderlying(Option) & 0b010) == 0b010, "Unsupported Extendtype"); LOGMAN_THROW_A_FMT(Shift == 0 || Shift == 1, "Unsupported shift amount"); constexpr uint32_t Op = 0b0111'1000'001 << 21 | (0b10 << 10); LoadStoreRegisterOffset(Op, 0b01, rt, rn, rm, Option, Shift ? 1 : 0); } - void ldrsh(FEXCore::ARMEmitter::XRegister rt, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::ExtendedType Option, uint32_t Shift) { + void ldrsh(ARMEmitter::XRegister rt, ARMEmitter::Register rn, ARMEmitter::Register rm, ARMEmitter::ExtendedType Option, uint32_t Shift) { LOGMAN_THROW_A_FMT((FEXCore::ToUnderlying(Option) & 0b010) == 0b010, "Unsupported Extendtype"); LOGMAN_THROW_A_FMT(Shift == 0 || Shift == 1, "Unsupported shift amount"); constexpr uint32_t Op = 0b0111'1000'001 << 21 | (0b10 << 10); LoadStoreRegisterOffset(Op, 0b10, rt, rn, rm, Option, Shift ? 1 : 0); } - void ldrsh(FEXCore::ARMEmitter::WRegister rt, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::ExtendedType Option, uint32_t Shift) { + void ldrsh(ARMEmitter::WRegister rt, ARMEmitter::Register rn, ARMEmitter::Register rm, ARMEmitter::ExtendedType Option, uint32_t Shift) { LOGMAN_THROW_A_FMT((FEXCore::ToUnderlying(Option) & 0b010) == 0b010, "Unsupported Extendtype"); LOGMAN_THROW_A_FMT(Shift == 0 || Shift == 1, "Unsupported shift amount"); constexpr uint32_t Op = 0b0111'1000'001 << 21 | (0b10 << 10); LoadStoreRegisterOffset(Op, 0b11, rt, rn, rm, Option, Shift ? 1 : 0); } - void str(FEXCore::ARMEmitter::WRegister rt, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::ExtendedType Option, uint32_t Shift) { + void str(ARMEmitter::WRegister rt, ARMEmitter::Register rn, ARMEmitter::Register rm, ARMEmitter::ExtendedType Option, uint32_t Shift) { LOGMAN_THROW_A_FMT((FEXCore::ToUnderlying(Option) & 0b010) == 0b010, "Unsupported Extendtype"); LOGMAN_THROW_A_FMT(Shift == 0 || Shift == 2, "Unsupported shift amount"); constexpr uint32_t Op = 0b1011'1000'001 << 21 | (0b10 << 10); LoadStoreRegisterOffset(Op, 0b00, rt, rn, rm, Option, Shift ? 1 : 0); } - void ldr(FEXCore::ARMEmitter::WRegister rt, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::ExtendedType Option, uint32_t Shift) { + void ldr(ARMEmitter::WRegister rt, ARMEmitter::Register rn, ARMEmitter::Register rm, ARMEmitter::ExtendedType Option, uint32_t Shift) { LOGMAN_THROW_A_FMT((FEXCore::ToUnderlying(Option) & 0b010) == 0b010, "Unsupported Extendtype"); LOGMAN_THROW_A_FMT(Shift == 0 || Shift == 2, "Unsupported shift amount: {}", Shift); constexpr uint32_t Op = 0b1011'1000'001 << 21 | (0b10 << 10); LoadStoreRegisterOffset(Op, 0b01, rt, rn, rm, Option, Shift ? 1 : 0); } - void ldrsw(FEXCore::ARMEmitter::XRegister rt, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::ExtendedType Option, uint32_t Shift) { + void ldrsw(ARMEmitter::XRegister rt, ARMEmitter::Register rn, ARMEmitter::Register rm, ARMEmitter::ExtendedType Option, uint32_t Shift) { LOGMAN_THROW_A_FMT((FEXCore::ToUnderlying(Option) & 0b010) == 0b010, "Unsupported Extendtype"); LOGMAN_THROW_A_FMT(Shift == 0 || Shift == 2, "Unsupported shift amount"); constexpr uint32_t Op = 0b1011'1000'001 << 21 | (0b10 << 10); LoadStoreRegisterOffset(Op, 0b10, rt, rn, rm, Option, Shift ? 1 : 0); } - void str(FEXCore::ARMEmitter::XRegister rt, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::ExtendedType Option, uint32_t Shift) { + void str(ARMEmitter::XRegister rt, ARMEmitter::Register rn, ARMEmitter::Register rm, ARMEmitter::ExtendedType Option, uint32_t Shift) { LOGMAN_THROW_A_FMT((FEXCore::ToUnderlying(Option) & 0b010) == 0b010, "Unsupported Extendtype"); LOGMAN_THROW_A_FMT(Shift == 0 || Shift == 3, "Unsupported shift amount"); constexpr uint32_t Op = 0b1111'1000'001 << 21 | (0b10 << 10); LoadStoreRegisterOffset(Op, 0b00, rt, rn, rm, Option, Shift ? 1 : 0); } - void ldr(FEXCore::ARMEmitter::XRegister rt, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::ExtendedType Option, uint32_t Shift) { + void ldr(ARMEmitter::XRegister rt, ARMEmitter::Register rn, ARMEmitter::Register rm, ARMEmitter::ExtendedType Option, uint32_t Shift) { LOGMAN_THROW_A_FMT((FEXCore::ToUnderlying(Option) & 0b010) == 0b010, "Unsupported Extendtype"); LOGMAN_THROW_A_FMT(Shift == 0 || Shift == 3, "Unsupported shift amount"); constexpr uint32_t Op = 0b1111'1000'001 << 21 | (0b10 << 10); LoadStoreRegisterOffset(Op, 0b01, rt, rn, rm, Option, Shift ? 1 : 0); } - void prfm(FEXCore::ARMEmitter::Prefetch prfop, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::ExtendedType Option, uint32_t Shift) { + void prfm(ARMEmitter::Prefetch prfop, ARMEmitter::Register rn, ARMEmitter::Register rm, ARMEmitter::ExtendedType Option, uint32_t Shift) { LOGMAN_THROW_A_FMT((FEXCore::ToUnderlying(Option) & 0b010) == 0b010, "Unsupported Extendtype"); LOGMAN_THROW_A_FMT(Shift == 0 || Shift == 3, "Unsupported shift amount"); constexpr uint32_t Op = 0b1111'1000'001 << 21 | (0b10 << 10); LoadStoreRegisterOffset(Op, 0b10, prfop, rn, rm, Option, Shift ? 1 : 0); } - void strb(FEXCore::ARMEmitter::VRegister rt, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::ExtendedType Option) { + void strb(ARMEmitter::VRegister rt, ARMEmitter::Register rn, ARMEmitter::Register rm, ARMEmitter::ExtendedType Option) { LOGMAN_THROW_A_FMT((FEXCore::ToUnderlying(Option) & 0b010) == 0b010, "Unsupported Extendtype"); constexpr uint32_t Op = 0b0011'1100'001 << 21 | (0b10 << 10); LoadStoreRegisterOffset(Op, 0b00, rt, rn, rm, Option, 0); } - void ldrb(FEXCore::ARMEmitter::VRegister rt, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::ExtendedType Option) { + void ldrb(ARMEmitter::VRegister rt, ARMEmitter::Register rn, ARMEmitter::Register rm, ARMEmitter::ExtendedType Option) { LOGMAN_THROW_A_FMT((FEXCore::ToUnderlying(Option) & 0b010) == 0b010, "Unsupported Extendtype"); constexpr uint32_t Op = 0b0011'1100'001 << 21 | (0b10 << 10); LoadStoreRegisterOffset(Op, 0b01, rt, rn, rm, Option, 0); } - void strh(FEXCore::ARMEmitter::VRegister rt, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::ExtendedType Option, uint32_t Shift) { + void strh(ARMEmitter::VRegister rt, ARMEmitter::Register rn, ARMEmitter::Register rm, ARMEmitter::ExtendedType Option, uint32_t Shift) { LOGMAN_THROW_A_FMT((FEXCore::ToUnderlying(Option) & 0b010) == 0b010, "Unsupported Extendtype"); LOGMAN_THROW_A_FMT(Shift == 0 || Shift == 1, "Unsupported shift amount"); constexpr uint32_t Op = 0b0111'1100'001 << 21 | (0b10 << 10); LoadStoreRegisterOffset(Op, 0b00, rt, rn, rm, Option, Shift ? 1 : 0); } - void ldrh(FEXCore::ARMEmitter::VRegister rt, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::ExtendedType Option, uint32_t Shift) { + void ldrh(ARMEmitter::VRegister rt, ARMEmitter::Register rn, ARMEmitter::Register rm, ARMEmitter::ExtendedType Option, uint32_t Shift) { LOGMAN_THROW_A_FMT((FEXCore::ToUnderlying(Option) & 0b010) == 0b010, "Unsupported Extendtype"); LOGMAN_THROW_A_FMT(Shift == 0 || Shift == 1, "Unsupported shift amount"); constexpr uint32_t Op = 0b0111'1100'001 << 21 | (0b10 << 10); LoadStoreRegisterOffset(Op, 0b01, rt, rn, rm, Option, Shift ? 1 : 0); } - void str(FEXCore::ARMEmitter::SRegister rt, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::ExtendedType Option, uint32_t Shift) { + void str(ARMEmitter::SRegister rt, ARMEmitter::Register rn, ARMEmitter::Register rm, ARMEmitter::ExtendedType Option, uint32_t Shift) { LOGMAN_THROW_A_FMT((FEXCore::ToUnderlying(Option) & 0b010) == 0b010, "Unsupported Extendtype"); LOGMAN_THROW_A_FMT(Shift == 0 || Shift == 2, "Unsupported shift amount"); constexpr uint32_t Op = 0b1011'1100'001 << 21 | (0b10 << 10); LoadStoreRegisterOffset(Op, 0b00, rt, rn, rm, Option, Shift ? 1 : 0); } - void ldr(FEXCore::ARMEmitter::SRegister rt, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::ExtendedType Option, uint32_t Shift) { + void ldr(ARMEmitter::SRegister rt, ARMEmitter::Register rn, ARMEmitter::Register rm, ARMEmitter::ExtendedType Option, uint32_t Shift) { LOGMAN_THROW_A_FMT((FEXCore::ToUnderlying(Option) & 0b010) == 0b010, "Unsupported Extendtype"); LOGMAN_THROW_A_FMT(Shift == 0 || Shift == 2, "Unsupported shift amount"); constexpr uint32_t Op = 0b1011'1100'001 << 21 | (0b10 << 10); LoadStoreRegisterOffset(Op, 0b01, rt, rn, rm, Option, Shift ? 1 : 0); } - void str(FEXCore::ARMEmitter::DRegister rt, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::ExtendedType Option, uint32_t Shift) { + void str(ARMEmitter::DRegister rt, ARMEmitter::Register rn, ARMEmitter::Register rm, ARMEmitter::ExtendedType Option, uint32_t Shift) { LOGMAN_THROW_A_FMT((FEXCore::ToUnderlying(Option) & 0b010) == 0b010, "Unsupported Extendtype"); LOGMAN_THROW_A_FMT(Shift == 0 || Shift == 3, "Unsupported shift amount"); constexpr uint32_t Op = 0b1111'1100'001 << 21 | (0b10 << 10); LoadStoreRegisterOffset(Op, 0b00, rt, rn, rm, Option, Shift ? 1 : 0); } - void ldr(FEXCore::ARMEmitter::DRegister rt, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::ExtendedType Option, uint32_t Shift) { + void ldr(ARMEmitter::DRegister rt, ARMEmitter::Register rn, ARMEmitter::Register rm, ARMEmitter::ExtendedType Option, uint32_t Shift) { LOGMAN_THROW_A_FMT((FEXCore::ToUnderlying(Option) & 0b010) == 0b010, "Unsupported Extendtype"); LOGMAN_THROW_A_FMT(Shift == 0 || Shift == 3, "Unsupported shift amount"); constexpr uint32_t Op = 0b1111'1100'001 << 21 | (0b10 << 10); LoadStoreRegisterOffset(Op, 0b01, rt, rn, rm, Option, Shift ? 1 : 0); } - void str(FEXCore::ARMEmitter::QRegister rt, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::ExtendedType Option, uint32_t Shift) { + void str(ARMEmitter::QRegister rt, ARMEmitter::Register rn, ARMEmitter::Register rm, ARMEmitter::ExtendedType Option, uint32_t Shift) { LOGMAN_THROW_A_FMT((FEXCore::ToUnderlying(Option) & 0b010) == 0b010, "Unsupported Extendtype"); LOGMAN_THROW_A_FMT(Shift == 0 || Shift == 4, "Unsupported shift amount"); constexpr uint32_t Op = 0b0011'1100'001 << 21 | (0b10 << 10); LoadStoreRegisterOffset(Op, 0b10, rt, rn, rm, Option, Shift ? 1 : 0); } - void ldr(FEXCore::ARMEmitter::QRegister rt, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::ExtendedType Option, uint32_t Shift) { + void ldr(ARMEmitter::QRegister rt, ARMEmitter::Register rn, ARMEmitter::Register rm, ARMEmitter::ExtendedType Option, uint32_t Shift) { LOGMAN_THROW_A_FMT((FEXCore::ToUnderlying(Option) & 0b010) == 0b010, "Unsupported Extendtype"); LOGMAN_THROW_A_FMT(Shift == 0 || Shift == 4, "Unsupported shift amount"); constexpr uint32_t Op = 0b0011'1100'001 << 21 | (0b10 << 10); LoadStoreRegisterOffset(Op, 0b11, rt, rn, rm, Option, Shift ? 1 : 0); } - void strb(FEXCore::ARMEmitter::Register rt, FEXCore::ARMEmitter::ExtendedMemOperand MemSrc) { - if (MemSrc.MetaType.Header.MemType == FEXCore::ARMEmitter::ExtendedMemOperand::Type::TYPE_EXTENDED && - MemSrc.MetaType.ExtendedType.rm.Idx() != FEXCore::ARMEmitter::Reg::r31.Idx()) { + void strb(ARMEmitter::Register rt, ARMEmitter::ExtendedMemOperand MemSrc) { + if (MemSrc.MetaType.Header.MemType == ARMEmitter::ExtendedMemOperand::Type::TYPE_EXTENDED && + MemSrc.MetaType.ExtendedType.rm.Idx() != ARMEmitter::Reg::r31.Idx()) { strb(rt, MemSrc.rn, MemSrc.MetaType.ExtendedType.rm, MemSrc.MetaType.ExtendedType.Option, MemSrc.MetaType.ExtendedType.Shift); } - else if (MemSrc.MetaType.Header.MemType == FEXCore::ARMEmitter::ExtendedMemOperand::Type::TYPE_EXTENDED) { + else if (MemSrc.MetaType.Header.MemType == ARMEmitter::ExtendedMemOperand::Type::TYPE_EXTENDED) { strb(rt, MemSrc.rn); } else { @@ -3404,12 +3404,12 @@ public: } } } - void ldrb(FEXCore::ARMEmitter::Register rt, FEXCore::ARMEmitter::ExtendedMemOperand MemSrc) { - if (MemSrc.MetaType.Header.MemType == FEXCore::ARMEmitter::ExtendedMemOperand::Type::TYPE_EXTENDED && - MemSrc.MetaType.ExtendedType.rm.Idx() != FEXCore::ARMEmitter::Reg::r31.Idx()) { + void ldrb(ARMEmitter::Register rt, ARMEmitter::ExtendedMemOperand MemSrc) { + if (MemSrc.MetaType.Header.MemType == ARMEmitter::ExtendedMemOperand::Type::TYPE_EXTENDED && + MemSrc.MetaType.ExtendedType.rm.Idx() != ARMEmitter::Reg::r31.Idx()) { ldrb(rt, MemSrc.rn, MemSrc.MetaType.ExtendedType.rm, MemSrc.MetaType.ExtendedType.Option, MemSrc.MetaType.ExtendedType.Shift); } - else if (MemSrc.MetaType.Header.MemType == FEXCore::ARMEmitter::ExtendedMemOperand::Type::TYPE_EXTENDED) { + else if (MemSrc.MetaType.Header.MemType == ARMEmitter::ExtendedMemOperand::Type::TYPE_EXTENDED) { ldrb(rt, MemSrc.rn); } else { @@ -3433,12 +3433,12 @@ public: } } } - void ldrsb(FEXCore::ARMEmitter::XRegister rt, FEXCore::ARMEmitter::ExtendedMemOperand MemSrc) { - if (MemSrc.MetaType.Header.MemType == FEXCore::ARMEmitter::ExtendedMemOperand::Type::TYPE_EXTENDED && - MemSrc.MetaType.ExtendedType.rm.Idx() != FEXCore::ARMEmitter::Reg::r31.Idx()) { + void ldrsb(ARMEmitter::XRegister rt, ARMEmitter::ExtendedMemOperand MemSrc) { + if (MemSrc.MetaType.Header.MemType == ARMEmitter::ExtendedMemOperand::Type::TYPE_EXTENDED && + MemSrc.MetaType.ExtendedType.rm.Idx() != ARMEmitter::Reg::r31.Idx()) { ldrsb(rt, MemSrc.rn, MemSrc.MetaType.ExtendedType.rm, MemSrc.MetaType.ExtendedType.Option, MemSrc.MetaType.ExtendedType.Shift); } - else if (MemSrc.MetaType.Header.MemType == FEXCore::ARMEmitter::ExtendedMemOperand::Type::TYPE_EXTENDED) { + else if (MemSrc.MetaType.Header.MemType == ARMEmitter::ExtendedMemOperand::Type::TYPE_EXTENDED) { ldrsb(rt, MemSrc.rn); } else { @@ -3462,12 +3462,12 @@ public: } } } - void ldrsb(FEXCore::ARMEmitter::WRegister rt, FEXCore::ARMEmitter::ExtendedMemOperand MemSrc) { - if (MemSrc.MetaType.Header.MemType == FEXCore::ARMEmitter::ExtendedMemOperand::Type::TYPE_EXTENDED && - MemSrc.MetaType.ExtendedType.rm.Idx() != FEXCore::ARMEmitter::Reg::r31.Idx()) { + void ldrsb(ARMEmitter::WRegister rt, ARMEmitter::ExtendedMemOperand MemSrc) { + if (MemSrc.MetaType.Header.MemType == ARMEmitter::ExtendedMemOperand::Type::TYPE_EXTENDED && + MemSrc.MetaType.ExtendedType.rm.Idx() != ARMEmitter::Reg::r31.Idx()) { ldrsb(rt, MemSrc.rn, MemSrc.MetaType.ExtendedType.rm, MemSrc.MetaType.ExtendedType.Option, MemSrc.MetaType.ExtendedType.Shift); } - else if (MemSrc.MetaType.Header.MemType == FEXCore::ARMEmitter::ExtendedMemOperand::Type::TYPE_EXTENDED) { + else if (MemSrc.MetaType.Header.MemType == ARMEmitter::ExtendedMemOperand::Type::TYPE_EXTENDED) { ldrsb(rt, MemSrc.rn); } else { @@ -3491,12 +3491,12 @@ public: } } } - void strh(FEXCore::ARMEmitter::Register rt, FEXCore::ARMEmitter::ExtendedMemOperand MemSrc) { - if (MemSrc.MetaType.Header.MemType == FEXCore::ARMEmitter::ExtendedMemOperand::Type::TYPE_EXTENDED && - MemSrc.MetaType.ExtendedType.rm.Idx() != FEXCore::ARMEmitter::Reg::r31.Idx()) { + void strh(ARMEmitter::Register rt, ARMEmitter::ExtendedMemOperand MemSrc) { + if (MemSrc.MetaType.Header.MemType == ARMEmitter::ExtendedMemOperand::Type::TYPE_EXTENDED && + MemSrc.MetaType.ExtendedType.rm.Idx() != ARMEmitter::Reg::r31.Idx()) { strh(rt, MemSrc.rn, MemSrc.MetaType.ExtendedType.rm, MemSrc.MetaType.ExtendedType.Option, MemSrc.MetaType.ExtendedType.Shift); } - else if (MemSrc.MetaType.Header.MemType == FEXCore::ARMEmitter::ExtendedMemOperand::Type::TYPE_EXTENDED) { + else if (MemSrc.MetaType.Header.MemType == ARMEmitter::ExtendedMemOperand::Type::TYPE_EXTENDED) { strh(rt, MemSrc.rn); } else { @@ -3520,12 +3520,12 @@ public: } } } - void ldrh(FEXCore::ARMEmitter::Register rt, FEXCore::ARMEmitter::ExtendedMemOperand MemSrc) { - if (MemSrc.MetaType.Header.MemType == FEXCore::ARMEmitter::ExtendedMemOperand::Type::TYPE_EXTENDED && - MemSrc.MetaType.ExtendedType.rm.Idx() != FEXCore::ARMEmitter::Reg::r31.Idx()) { + void ldrh(ARMEmitter::Register rt, ARMEmitter::ExtendedMemOperand MemSrc) { + if (MemSrc.MetaType.Header.MemType == ARMEmitter::ExtendedMemOperand::Type::TYPE_EXTENDED && + MemSrc.MetaType.ExtendedType.rm.Idx() != ARMEmitter::Reg::r31.Idx()) { ldrh(rt, MemSrc.rn, MemSrc.MetaType.ExtendedType.rm, MemSrc.MetaType.ExtendedType.Option, MemSrc.MetaType.ExtendedType.Shift); } - else if (MemSrc.MetaType.Header.MemType == FEXCore::ARMEmitter::ExtendedMemOperand::Type::TYPE_EXTENDED) { + else if (MemSrc.MetaType.Header.MemType == ARMEmitter::ExtendedMemOperand::Type::TYPE_EXTENDED) { ldrh(rt, MemSrc.rn); } else { @@ -3549,12 +3549,12 @@ public: } } } - void ldrsh(FEXCore::ARMEmitter::XRegister rt, FEXCore::ARMEmitter::ExtendedMemOperand MemSrc) { - if (MemSrc.MetaType.Header.MemType == FEXCore::ARMEmitter::ExtendedMemOperand::Type::TYPE_EXTENDED && - MemSrc.MetaType.ExtendedType.rm.Idx() != FEXCore::ARMEmitter::Reg::r31.Idx()) { + void ldrsh(ARMEmitter::XRegister rt, ARMEmitter::ExtendedMemOperand MemSrc) { + if (MemSrc.MetaType.Header.MemType == ARMEmitter::ExtendedMemOperand::Type::TYPE_EXTENDED && + MemSrc.MetaType.ExtendedType.rm.Idx() != ARMEmitter::Reg::r31.Idx()) { ldrsh(rt, MemSrc.rn, MemSrc.MetaType.ExtendedType.rm, MemSrc.MetaType.ExtendedType.Option, MemSrc.MetaType.ExtendedType.Shift); } - else if (MemSrc.MetaType.Header.MemType == FEXCore::ARMEmitter::ExtendedMemOperand::Type::TYPE_EXTENDED) { + else if (MemSrc.MetaType.Header.MemType == ARMEmitter::ExtendedMemOperand::Type::TYPE_EXTENDED) { ldrsh(rt, MemSrc.rn); } else { @@ -3578,12 +3578,12 @@ public: } } } - void ldrsh(FEXCore::ARMEmitter::WRegister rt, FEXCore::ARMEmitter::ExtendedMemOperand MemSrc) { - if (MemSrc.MetaType.Header.MemType == FEXCore::ARMEmitter::ExtendedMemOperand::Type::TYPE_EXTENDED && - MemSrc.MetaType.ExtendedType.rm.Idx() != FEXCore::ARMEmitter::Reg::r31.Idx()) { + void ldrsh(ARMEmitter::WRegister rt, ARMEmitter::ExtendedMemOperand MemSrc) { + if (MemSrc.MetaType.Header.MemType == ARMEmitter::ExtendedMemOperand::Type::TYPE_EXTENDED && + MemSrc.MetaType.ExtendedType.rm.Idx() != ARMEmitter::Reg::r31.Idx()) { ldrsh(rt, MemSrc.rn, MemSrc.MetaType.ExtendedType.rm, MemSrc.MetaType.ExtendedType.Option, MemSrc.MetaType.ExtendedType.Shift); } - else if (MemSrc.MetaType.Header.MemType == FEXCore::ARMEmitter::ExtendedMemOperand::Type::TYPE_EXTENDED) { + else if (MemSrc.MetaType.Header.MemType == ARMEmitter::ExtendedMemOperand::Type::TYPE_EXTENDED) { ldrsh(rt, MemSrc.rn); } else { @@ -3607,12 +3607,12 @@ public: } } } - void str(FEXCore::ARMEmitter::WRegister rt, FEXCore::ARMEmitter::ExtendedMemOperand MemSrc) { - if (MemSrc.MetaType.Header.MemType == FEXCore::ARMEmitter::ExtendedMemOperand::Type::TYPE_EXTENDED && - MemSrc.MetaType.ExtendedType.rm.Idx() != FEXCore::ARMEmitter::Reg::r31.Idx()) { + void str(ARMEmitter::WRegister rt, ARMEmitter::ExtendedMemOperand MemSrc) { + if (MemSrc.MetaType.Header.MemType == ARMEmitter::ExtendedMemOperand::Type::TYPE_EXTENDED && + MemSrc.MetaType.ExtendedType.rm.Idx() != ARMEmitter::Reg::r31.Idx()) { str(rt, MemSrc.rn, MemSrc.MetaType.ExtendedType.rm, MemSrc.MetaType.ExtendedType.Option, MemSrc.MetaType.ExtendedType.Shift); } - else if (MemSrc.MetaType.Header.MemType == FEXCore::ARMEmitter::ExtendedMemOperand::Type::TYPE_EXTENDED) { + else if (MemSrc.MetaType.Header.MemType == ARMEmitter::ExtendedMemOperand::Type::TYPE_EXTENDED) { str(rt, MemSrc.rn); } else { @@ -3636,12 +3636,12 @@ public: } } } - void ldr(FEXCore::ARMEmitter::WRegister rt, FEXCore::ARMEmitter::ExtendedMemOperand MemSrc) { - if (MemSrc.MetaType.Header.MemType == FEXCore::ARMEmitter::ExtendedMemOperand::Type::TYPE_EXTENDED && - MemSrc.MetaType.ExtendedType.rm.Idx() != FEXCore::ARMEmitter::Reg::r31.Idx()) { + void ldr(ARMEmitter::WRegister rt, ARMEmitter::ExtendedMemOperand MemSrc) { + if (MemSrc.MetaType.Header.MemType == ARMEmitter::ExtendedMemOperand::Type::TYPE_EXTENDED && + MemSrc.MetaType.ExtendedType.rm.Idx() != ARMEmitter::Reg::r31.Idx()) { ldr(rt, MemSrc.rn, MemSrc.MetaType.ExtendedType.rm, MemSrc.MetaType.ExtendedType.Option, MemSrc.MetaType.ExtendedType.Shift); } - else if (MemSrc.MetaType.Header.MemType == FEXCore::ARMEmitter::ExtendedMemOperand::Type::TYPE_EXTENDED) { + else if (MemSrc.MetaType.Header.MemType == ARMEmitter::ExtendedMemOperand::Type::TYPE_EXTENDED) { ldr(rt, MemSrc.rn); } else { @@ -3665,12 +3665,12 @@ public: } } } - void ldrsw(FEXCore::ARMEmitter::XRegister rt, FEXCore::ARMEmitter::ExtendedMemOperand MemSrc) { - if (MemSrc.MetaType.Header.MemType == FEXCore::ARMEmitter::ExtendedMemOperand::Type::TYPE_EXTENDED && - MemSrc.MetaType.ExtendedType.rm.Idx() != FEXCore::ARMEmitter::Reg::r31.Idx()) { + void ldrsw(ARMEmitter::XRegister rt, ARMEmitter::ExtendedMemOperand MemSrc) { + if (MemSrc.MetaType.Header.MemType == ARMEmitter::ExtendedMemOperand::Type::TYPE_EXTENDED && + MemSrc.MetaType.ExtendedType.rm.Idx() != ARMEmitter::Reg::r31.Idx()) { ldrsw(rt, MemSrc.rn, MemSrc.MetaType.ExtendedType.rm, MemSrc.MetaType.ExtendedType.Option, MemSrc.MetaType.ExtendedType.Shift); } - else if (MemSrc.MetaType.Header.MemType == FEXCore::ARMEmitter::ExtendedMemOperand::Type::TYPE_EXTENDED) { + else if (MemSrc.MetaType.Header.MemType == ARMEmitter::ExtendedMemOperand::Type::TYPE_EXTENDED) { ldrsw(rt, MemSrc.rn); } else { @@ -3694,12 +3694,12 @@ public: } } } - void str(FEXCore::ARMEmitter::XRegister rt, FEXCore::ARMEmitter::ExtendedMemOperand MemSrc) { - if (MemSrc.MetaType.Header.MemType == FEXCore::ARMEmitter::ExtendedMemOperand::Type::TYPE_EXTENDED && - MemSrc.MetaType.ExtendedType.rm.Idx() != FEXCore::ARMEmitter::Reg::r31.Idx()) { + void str(ARMEmitter::XRegister rt, ARMEmitter::ExtendedMemOperand MemSrc) { + if (MemSrc.MetaType.Header.MemType == ARMEmitter::ExtendedMemOperand::Type::TYPE_EXTENDED && + MemSrc.MetaType.ExtendedType.rm.Idx() != ARMEmitter::Reg::r31.Idx()) { str(rt, MemSrc.rn, MemSrc.MetaType.ExtendedType.rm, MemSrc.MetaType.ExtendedType.Option, MemSrc.MetaType.ExtendedType.Shift); } - else if (MemSrc.MetaType.Header.MemType == FEXCore::ARMEmitter::ExtendedMemOperand::Type::TYPE_EXTENDED) { + else if (MemSrc.MetaType.Header.MemType == ARMEmitter::ExtendedMemOperand::Type::TYPE_EXTENDED) { str(rt, MemSrc.rn); } else { @@ -3723,12 +3723,12 @@ public: } } } - void ldr(FEXCore::ARMEmitter::XRegister rt, FEXCore::ARMEmitter::ExtendedMemOperand MemSrc) { - if (MemSrc.MetaType.Header.MemType == FEXCore::ARMEmitter::ExtendedMemOperand::Type::TYPE_EXTENDED && - MemSrc.MetaType.ExtendedType.rm.Idx() != FEXCore::ARMEmitter::Reg::r31.Idx()) { + void ldr(ARMEmitter::XRegister rt, ARMEmitter::ExtendedMemOperand MemSrc) { + if (MemSrc.MetaType.Header.MemType == ARMEmitter::ExtendedMemOperand::Type::TYPE_EXTENDED && + MemSrc.MetaType.ExtendedType.rm.Idx() != ARMEmitter::Reg::r31.Idx()) { ldr(rt, MemSrc.rn, MemSrc.MetaType.ExtendedType.rm, MemSrc.MetaType.ExtendedType.Option, MemSrc.MetaType.ExtendedType.Shift); } - else if (MemSrc.MetaType.Header.MemType == FEXCore::ARMEmitter::ExtendedMemOperand::Type::TYPE_EXTENDED) { + else if (MemSrc.MetaType.Header.MemType == ARMEmitter::ExtendedMemOperand::Type::TYPE_EXTENDED) { ldr(rt, MemSrc.rn); } else { @@ -3752,12 +3752,12 @@ public: } } } - void prfm(FEXCore::ARMEmitter::Prefetch prfop, FEXCore::ARMEmitter::ExtendedMemOperand MemSrc) { - if (MemSrc.MetaType.Header.MemType == FEXCore::ARMEmitter::ExtendedMemOperand::Type::TYPE_EXTENDED && - MemSrc.MetaType.ExtendedType.rm.Idx() != FEXCore::ARMEmitter::Reg::r31.Idx()) { + void prfm(ARMEmitter::Prefetch prfop, ARMEmitter::ExtendedMemOperand MemSrc) { + if (MemSrc.MetaType.Header.MemType == ARMEmitter::ExtendedMemOperand::Type::TYPE_EXTENDED && + MemSrc.MetaType.ExtendedType.rm.Idx() != ARMEmitter::Reg::r31.Idx()) { prfm(prfop, MemSrc.rn, MemSrc.MetaType.ExtendedType.rm, MemSrc.MetaType.ExtendedType.Option, MemSrc.MetaType.ExtendedType.Shift); } - else if (MemSrc.MetaType.Header.MemType == FEXCore::ARMEmitter::ExtendedMemOperand::Type::TYPE_EXTENDED) { + else if (MemSrc.MetaType.Header.MemType == ARMEmitter::ExtendedMemOperand::Type::TYPE_EXTENDED) { prfm(prfop, MemSrc.rn); } else { @@ -3776,14 +3776,14 @@ public: } } - void strb(FEXCore::ARMEmitter::VRegister rt, FEXCore::ARMEmitter::ExtendedMemOperand MemSrc) { - if (MemSrc.MetaType.Header.MemType == FEXCore::ARMEmitter::ExtendedMemOperand::Type::TYPE_EXTENDED && - MemSrc.MetaType.ExtendedType.rm.Idx() != FEXCore::ARMEmitter::Reg::r31.Idx()) { + void strb(ARMEmitter::VRegister rt, ARMEmitter::ExtendedMemOperand MemSrc) { + if (MemSrc.MetaType.Header.MemType == ARMEmitter::ExtendedMemOperand::Type::TYPE_EXTENDED && + MemSrc.MetaType.ExtendedType.rm.Idx() != ARMEmitter::Reg::r31.Idx()) { LOGMAN_THROW_AA_FMT(MemSrc.MetaType.ExtendedType.Shift == false, "Can't shift byte"); LOGMAN_MSG_A_FMT("Nope"); // XXX: Implement // strb(rt, MemSrc.rn, MemSrc.MetaType.ExtendedType.rm, MemSrc.MetaType.ExtendedType.Option); } - else if (MemSrc.MetaType.Header.MemType == FEXCore::ARMEmitter::ExtendedMemOperand::Type::TYPE_EXTENDED) { + else if (MemSrc.MetaType.Header.MemType == ARMEmitter::ExtendedMemOperand::Type::TYPE_EXTENDED) { strb(rt, MemSrc.rn); } else { @@ -3807,14 +3807,14 @@ public: } } } - void ldrb(FEXCore::ARMEmitter::VRegister rt, FEXCore::ARMEmitter::ExtendedMemOperand MemSrc) { - if (MemSrc.MetaType.Header.MemType == FEXCore::ARMEmitter::ExtendedMemOperand::Type::TYPE_EXTENDED && - MemSrc.MetaType.ExtendedType.rm.Idx() != FEXCore::ARMEmitter::Reg::r31.Idx()) { + void ldrb(ARMEmitter::VRegister rt, ARMEmitter::ExtendedMemOperand MemSrc) { + if (MemSrc.MetaType.Header.MemType == ARMEmitter::ExtendedMemOperand::Type::TYPE_EXTENDED && + MemSrc.MetaType.ExtendedType.rm.Idx() != ARMEmitter::Reg::r31.Idx()) { LOGMAN_THROW_AA_FMT(MemSrc.MetaType.ExtendedType.Shift == false, "Can't shift byte"); LOGMAN_MSG_A_FMT("Nope"); // XXX: Implement // ldrb(rt, MemSrc.rn, MemSrc.MetaType.ExtendedType.rm, MemSrc.MetaType.ExtendedType.Option); } - else if (MemSrc.MetaType.Header.MemType == FEXCore::ARMEmitter::ExtendedMemOperand::Type::TYPE_EXTENDED) { + else if (MemSrc.MetaType.Header.MemType == ARMEmitter::ExtendedMemOperand::Type::TYPE_EXTENDED) { ldrb(rt, MemSrc.rn); } else { @@ -3838,14 +3838,14 @@ public: } } } - void strh(FEXCore::ARMEmitter::VRegister rt, FEXCore::ARMEmitter::ExtendedMemOperand MemSrc) { - if (MemSrc.MetaType.Header.MemType == FEXCore::ARMEmitter::ExtendedMemOperand::Type::TYPE_EXTENDED && - MemSrc.MetaType.ExtendedType.rm.Idx() != FEXCore::ARMEmitter::Reg::r31.Idx()) { + void strh(ARMEmitter::VRegister rt, ARMEmitter::ExtendedMemOperand MemSrc) { + if (MemSrc.MetaType.Header.MemType == ARMEmitter::ExtendedMemOperand::Type::TYPE_EXTENDED && + MemSrc.MetaType.ExtendedType.rm.Idx() != ARMEmitter::Reg::r31.Idx()) { LOGMAN_THROW_AA_FMT(MemSrc.MetaType.ExtendedType.Shift == false, "Can't shift byte"); LOGMAN_MSG_A_FMT("Nope"); // XXX: Implement // strh(rt, MemSrc.rn, MemSrc.MetaType.ExtendedType.rm, MemSrc.MetaType.ExtendedType.Option); } - else if (MemSrc.MetaType.Header.MemType == FEXCore::ARMEmitter::ExtendedMemOperand::Type::TYPE_EXTENDED) { + else if (MemSrc.MetaType.Header.MemType == ARMEmitter::ExtendedMemOperand::Type::TYPE_EXTENDED) { strh(rt, MemSrc.rn); } else { @@ -3869,14 +3869,14 @@ public: } } } - void ldrh(FEXCore::ARMEmitter::VRegister rt, FEXCore::ARMEmitter::ExtendedMemOperand MemSrc) { - if (MemSrc.MetaType.Header.MemType == FEXCore::ARMEmitter::ExtendedMemOperand::Type::TYPE_EXTENDED && - MemSrc.MetaType.ExtendedType.rm.Idx() != FEXCore::ARMEmitter::Reg::r31.Idx()) { + void ldrh(ARMEmitter::VRegister rt, ARMEmitter::ExtendedMemOperand MemSrc) { + if (MemSrc.MetaType.Header.MemType == ARMEmitter::ExtendedMemOperand::Type::TYPE_EXTENDED && + MemSrc.MetaType.ExtendedType.rm.Idx() != ARMEmitter::Reg::r31.Idx()) { LOGMAN_THROW_AA_FMT(MemSrc.MetaType.ExtendedType.Shift == false, "Can't shift byte"); LOGMAN_MSG_A_FMT("Nope"); // XXX: Implement // ldrh(rt, MemSrc.rn, MemSrc.MetaType.ExtendedType.rm, MemSrc.MetaType.ExtendedType.Option); } - else if (MemSrc.MetaType.Header.MemType == FEXCore::ARMEmitter::ExtendedMemOperand::Type::TYPE_EXTENDED) { + else if (MemSrc.MetaType.Header.MemType == ARMEmitter::ExtendedMemOperand::Type::TYPE_EXTENDED) { ldrh(rt, MemSrc.rn); } else { @@ -3900,12 +3900,12 @@ public: } } } - void str(FEXCore::ARMEmitter::SRegister rt, FEXCore::ARMEmitter::ExtendedMemOperand MemSrc) { - if (MemSrc.MetaType.Header.MemType == FEXCore::ARMEmitter::ExtendedMemOperand::Type::TYPE_EXTENDED && - MemSrc.MetaType.ExtendedType.rm.Idx() != FEXCore::ARMEmitter::Reg::r31.Idx()) { + void str(ARMEmitter::SRegister rt, ARMEmitter::ExtendedMemOperand MemSrc) { + if (MemSrc.MetaType.Header.MemType == ARMEmitter::ExtendedMemOperand::Type::TYPE_EXTENDED && + MemSrc.MetaType.ExtendedType.rm.Idx() != ARMEmitter::Reg::r31.Idx()) { str(rt, MemSrc.rn, MemSrc.MetaType.ExtendedType.rm, MemSrc.MetaType.ExtendedType.Option, MemSrc.MetaType.ExtendedType.Shift); } - else if (MemSrc.MetaType.Header.MemType == FEXCore::ARMEmitter::ExtendedMemOperand::Type::TYPE_EXTENDED) { + else if (MemSrc.MetaType.Header.MemType == ARMEmitter::ExtendedMemOperand::Type::TYPE_EXTENDED) { str(rt, MemSrc.rn); } else { @@ -3929,12 +3929,12 @@ public: } } } - void ldr(FEXCore::ARMEmitter::SRegister rt, FEXCore::ARMEmitter::ExtendedMemOperand MemSrc) { - if (MemSrc.MetaType.Header.MemType == FEXCore::ARMEmitter::ExtendedMemOperand::Type::TYPE_EXTENDED && - MemSrc.MetaType.ExtendedType.rm.Idx() != FEXCore::ARMEmitter::Reg::r31.Idx()) { + void ldr(ARMEmitter::SRegister rt, ARMEmitter::ExtendedMemOperand MemSrc) { + if (MemSrc.MetaType.Header.MemType == ARMEmitter::ExtendedMemOperand::Type::TYPE_EXTENDED && + MemSrc.MetaType.ExtendedType.rm.Idx() != ARMEmitter::Reg::r31.Idx()) { ldr(rt, MemSrc.rn, MemSrc.MetaType.ExtendedType.rm, MemSrc.MetaType.ExtendedType.Option, MemSrc.MetaType.ExtendedType.Shift); } - else if (MemSrc.MetaType.Header.MemType == FEXCore::ARMEmitter::ExtendedMemOperand::Type::TYPE_EXTENDED) { + else if (MemSrc.MetaType.Header.MemType == ARMEmitter::ExtendedMemOperand::Type::TYPE_EXTENDED) { ldr(rt, MemSrc.rn); } else { @@ -3958,12 +3958,12 @@ public: } } } - void str(FEXCore::ARMEmitter::DRegister rt, FEXCore::ARMEmitter::ExtendedMemOperand MemSrc) { - if (MemSrc.MetaType.Header.MemType == FEXCore::ARMEmitter::ExtendedMemOperand::Type::TYPE_EXTENDED && - MemSrc.MetaType.ExtendedType.rm.Idx() != FEXCore::ARMEmitter::Reg::r31.Idx()) { + void str(ARMEmitter::DRegister rt, ARMEmitter::ExtendedMemOperand MemSrc) { + if (MemSrc.MetaType.Header.MemType == ARMEmitter::ExtendedMemOperand::Type::TYPE_EXTENDED && + MemSrc.MetaType.ExtendedType.rm.Idx() != ARMEmitter::Reg::r31.Idx()) { str(rt, MemSrc.rn, MemSrc.MetaType.ExtendedType.rm, MemSrc.MetaType.ExtendedType.Option, MemSrc.MetaType.ExtendedType.Shift); } - else if (MemSrc.MetaType.Header.MemType == FEXCore::ARMEmitter::ExtendedMemOperand::Type::TYPE_EXTENDED) { + else if (MemSrc.MetaType.Header.MemType == ARMEmitter::ExtendedMemOperand::Type::TYPE_EXTENDED) { str(rt, MemSrc.rn); } else { @@ -3987,12 +3987,12 @@ public: } } } - void ldr(FEXCore::ARMEmitter::DRegister rt, FEXCore::ARMEmitter::ExtendedMemOperand MemSrc) { - if (MemSrc.MetaType.Header.MemType == FEXCore::ARMEmitter::ExtendedMemOperand::Type::TYPE_EXTENDED && - MemSrc.MetaType.ExtendedType.rm.Idx() != FEXCore::ARMEmitter::Reg::r31.Idx()) { + void ldr(ARMEmitter::DRegister rt, ARMEmitter::ExtendedMemOperand MemSrc) { + if (MemSrc.MetaType.Header.MemType == ARMEmitter::ExtendedMemOperand::Type::TYPE_EXTENDED && + MemSrc.MetaType.ExtendedType.rm.Idx() != ARMEmitter::Reg::r31.Idx()) { ldr(rt, MemSrc.rn, MemSrc.MetaType.ExtendedType.rm, MemSrc.MetaType.ExtendedType.Option, MemSrc.MetaType.ExtendedType.Shift); } - else if (MemSrc.MetaType.Header.MemType == FEXCore::ARMEmitter::ExtendedMemOperand::Type::TYPE_EXTENDED) { + else if (MemSrc.MetaType.Header.MemType == ARMEmitter::ExtendedMemOperand::Type::TYPE_EXTENDED) { ldr(rt, MemSrc.rn); } else { @@ -4016,12 +4016,12 @@ public: } } } - void str(FEXCore::ARMEmitter::QRegister rt, FEXCore::ARMEmitter::ExtendedMemOperand MemSrc) { - if (MemSrc.MetaType.Header.MemType == FEXCore::ARMEmitter::ExtendedMemOperand::Type::TYPE_EXTENDED && - MemSrc.MetaType.ExtendedType.rm.Idx() != FEXCore::ARMEmitter::Reg::r31.Idx()) { + void str(ARMEmitter::QRegister rt, ARMEmitter::ExtendedMemOperand MemSrc) { + if (MemSrc.MetaType.Header.MemType == ARMEmitter::ExtendedMemOperand::Type::TYPE_EXTENDED && + MemSrc.MetaType.ExtendedType.rm.Idx() != ARMEmitter::Reg::r31.Idx()) { str(rt, MemSrc.rn, MemSrc.MetaType.ExtendedType.rm, MemSrc.MetaType.ExtendedType.Option, MemSrc.MetaType.ExtendedType.Shift); } - else if (MemSrc.MetaType.Header.MemType == FEXCore::ARMEmitter::ExtendedMemOperand::Type::TYPE_EXTENDED) { + else if (MemSrc.MetaType.Header.MemType == ARMEmitter::ExtendedMemOperand::Type::TYPE_EXTENDED) { str(rt, MemSrc.rn); } else { @@ -4045,12 +4045,12 @@ public: } } } - void ldr(FEXCore::ARMEmitter::QRegister rt, FEXCore::ARMEmitter::ExtendedMemOperand MemSrc) { - if (MemSrc.MetaType.Header.MemType == FEXCore::ARMEmitter::ExtendedMemOperand::Type::TYPE_EXTENDED && - MemSrc.MetaType.ExtendedType.rm.Idx() != FEXCore::ARMEmitter::Reg::r31.Idx()) { + void ldr(ARMEmitter::QRegister rt, ARMEmitter::ExtendedMemOperand MemSrc) { + if (MemSrc.MetaType.Header.MemType == ARMEmitter::ExtendedMemOperand::Type::TYPE_EXTENDED && + MemSrc.MetaType.ExtendedType.rm.Idx() != ARMEmitter::Reg::r31.Idx()) { ldr(rt, MemSrc.rn, MemSrc.MetaType.ExtendedType.rm, MemSrc.MetaType.ExtendedType.Option, MemSrc.MetaType.ExtendedType.Shift); } - else if (MemSrc.MetaType.Header.MemType == FEXCore::ARMEmitter::ExtendedMemOperand::Type::TYPE_EXTENDED) { + else if (MemSrc.MetaType.Header.MemType == ARMEmitter::ExtendedMemOperand::Type::TYPE_EXTENDED) { ldr(rt, MemSrc.rn); } else { @@ -4170,8 +4170,8 @@ public: } private: - void AtomicOp(uint32_t Op, FEXCore::ARMEmitter::Size s, uint32_t L, uint32_t o0, FEXCore::ARMEmitter::Register rs, FEXCore::ARMEmitter::Register rt, FEXCore::ARMEmitter::Register rt2, FEXCore::ARMEmitter::Register rn) { - const uint32_t sz = s == FEXCore::ARMEmitter::Size::i64Bit ? (1U << 30) : 0; + void AtomicOp(uint32_t Op, ARMEmitter::Size s, uint32_t L, uint32_t o0, ARMEmitter::Register rs, ARMEmitter::Register rt, ARMEmitter::Register rt2, ARMEmitter::Register rn) { + const uint32_t sz = s == ARMEmitter::Size::i64Bit ? (1U << 30) : 0; uint32_t Instr = Op; Instr |= sz; @@ -4186,7 +4186,7 @@ private: } template - void SubAtomicOp(uint32_t Op, FEXCore::ARMEmitter::SubRegSize s, uint32_t L, uint32_t o0, T rs, T rt, T rt2, FEXCore::ARMEmitter::Register rn) { + void SubAtomicOp(uint32_t Op, ARMEmitter::SubRegSize s, uint32_t L, uint32_t o0, T rs, T rt, T rt2, ARMEmitter::Register rn) { const uint32_t sz = FEXCore::ToUnderlying(s) << 30; uint32_t Instr = Op; @@ -4202,7 +4202,7 @@ private: } template - void SubAtomicImm(uint32_t Op, FEXCore::ARMEmitter::SubRegSize s, uint32_t opc, T rt, FEXCore::ARMEmitter::Register rn, uint32_t Imm) { + void SubAtomicImm(uint32_t Op, ARMEmitter::SubRegSize s, uint32_t opc, T rt, ARMEmitter::Register rn, uint32_t Imm) { const uint32_t sz = FEXCore::ToUnderlying(s) << 30; uint32_t Instr = Op; @@ -4226,7 +4226,7 @@ private: // Loadstore no-allocate pair template - void LoadStoreNoAllocate(uint32_t Op, T rt, T rt2, FEXCore::ARMEmitter::Register rn, uint32_t Imm) { + void LoadStoreNoAllocate(uint32_t Op, T rt, T rt2, ARMEmitter::Register rn, uint32_t Imm) { uint32_t Instr = Op; Instr |= Imm << 15; @@ -4237,7 +4237,7 @@ private: } // Loadstore register pair post-indexed template - void LoadStorePair(uint32_t Op, T rt, T rt2, FEXCore::ARMEmitter::Register rn, uint32_t Imm) { + void LoadStorePair(uint32_t Op, T rt, T rt2, ARMEmitter::Register rn, uint32_t Imm) { uint32_t Instr = Op; Instr |= Imm << 15; Instr |= Encode_rt2(rt2); @@ -4251,7 +4251,7 @@ private: // Loadstore register unprivileged // Loadstore register immediate pre-indexed template - void LoadStoreImm(uint32_t Op, uint32_t o2, T rt, FEXCore::ARMEmitter::Register rn, uint32_t Imm) { + void LoadStoreImm(uint32_t Op, uint32_t o2, T rt, ARMEmitter::Register rn, uint32_t Imm) { uint32_t Instr = Op; Instr |= Imm << 12; @@ -4278,7 +4278,7 @@ private: // Loadstore register-register offset template - void LoadStoreRegisterOffset(uint32_t Op, uint32_t opc, T rt, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::ExtendedType Option, uint32_t Shift) { + void LoadStoreRegisterOffset(uint32_t Op, uint32_t opc, T rt, ARMEmitter::Register rn, ARMEmitter::Register rm, ARMEmitter::ExtendedType Option, uint32_t Shift) { uint32_t Instr = Op; Instr |= opc << 22; @@ -4321,7 +4321,7 @@ private: } template - void ldp_w(FEXCore::ARMEmitter::VRegister rt, FEXCore::ARMEmitter::VRegister rt2, FEXCore::ARMEmitter::Register rn, int32_t Imm) { + void ldp_w(ARMEmitter::VRegister rt, ARMEmitter::VRegister rt2, ARMEmitter::Register rn, int32_t Imm) { LOGMAN_THROW_A_FMT(Imm >= -256 && Imm <= 252 && ((Imm & 0b11) == 0), "Unscaled offset too large"); constexpr uint32_t Op = (0b0010'1100'01 << 22) | ( @@ -4333,7 +4333,7 @@ private: LoadStorePair(Op, rt, rt2, rn, (Imm >> 2) & 0b111'1111); } template - void ldp_x(FEXCore::ARMEmitter::VRegister rt, FEXCore::ARMEmitter::VRegister rt2, FEXCore::ARMEmitter::Register rn, int32_t Imm) { + void ldp_x(ARMEmitter::VRegister rt, ARMEmitter::VRegister rt2, ARMEmitter::Register rn, int32_t Imm) { LOGMAN_THROW_A_FMT(Imm >= -512 && Imm <= 504 && ((Imm & 0b111) == 0), "Unscaled offset too large"); constexpr uint32_t Op = (0b0110'1100'01 << 22) | ( @@ -4345,7 +4345,7 @@ private: LoadStorePair(Op, rt, rt2, rn, (Imm >> 3) & 0b111'1111); } template - void stp_w(FEXCore::ARMEmitter::VRegister rt, FEXCore::ARMEmitter::VRegister rt2, FEXCore::ARMEmitter::Register rn, int32_t Imm) { + void stp_w(ARMEmitter::VRegister rt, ARMEmitter::VRegister rt2, ARMEmitter::Register rn, int32_t Imm) { LOGMAN_THROW_A_FMT(Imm >= -256 && Imm <= 252 && ((Imm & 0b11) == 0), "Unscaled offset too large"); constexpr uint32_t Op = (0b0010'1100'00 << 22) | ( @@ -4357,7 +4357,7 @@ private: LoadStorePair(Op, rt, rt2, rn, (Imm >> 2) & 0b111'1111); } template - void stp_x(FEXCore::ARMEmitter::VRegister rt, FEXCore::ARMEmitter::VRegister rt2, FEXCore::ARMEmitter::Register rn, int32_t Imm) { + void stp_x(ARMEmitter::VRegister rt, ARMEmitter::VRegister rt2, ARMEmitter::Register rn, int32_t Imm) { LOGMAN_THROW_A_FMT(Imm >= -512 && Imm <= 504 && ((Imm & 0b111) == 0), "Unscaled offset too large"); constexpr uint32_t Op = (0b0110'1100'00 << 22) | ( @@ -4369,7 +4369,7 @@ private: LoadStorePair(Op, rt, rt2, rn, (Imm >> 3) & 0b111'1111); } template - void ldp_q(FEXCore::ARMEmitter::VRegister rt, FEXCore::ARMEmitter::VRegister rt2, FEXCore::ARMEmitter::Register rn, int32_t Imm) { + void ldp_q(ARMEmitter::VRegister rt, ARMEmitter::VRegister rt2, ARMEmitter::Register rn, int32_t Imm) { LOGMAN_THROW_A_FMT(Imm >= -1024 && Imm <= 1008 && ((Imm & 0b1111) == 0), "Unscaled offset too large"); constexpr uint32_t Op = (0b1010'1100'01 << 22) | ( @@ -4381,7 +4381,7 @@ private: LoadStorePair(Op, rt, rt2, rn, (Imm >> 4) & 0b111'1111); } template - void stp_q(FEXCore::ARMEmitter::VRegister rt, FEXCore::ARMEmitter::VRegister rt2, FEXCore::ARMEmitter::Register rn, int32_t Imm) { + void stp_q(ARMEmitter::VRegister rt, ARMEmitter::VRegister rt2, ARMEmitter::Register rn, int32_t Imm) { LOGMAN_THROW_A_FMT(Imm >= -1024 && Imm <= 1008 && ((Imm & 0b1111) == 0), "Unscaled offset too large"); constexpr uint32_t Op = (0b1010'1100'00 << 22) | ( @@ -4394,7 +4394,7 @@ private: } template - void stXrb(FEXCore::ARMEmitter::Register rt, FEXCore::ARMEmitter::Register rn, int32_t Imm) { + void stXrb(ARMEmitter::Register rt, ARMEmitter::Register rn, int32_t Imm) { LOGMAN_THROW_A_FMT(Imm >= -256 && Imm <= 255, "Unscaled offset too large"); constexpr uint32_t Op = 0b0011'1000'00 << 22; @@ -4407,7 +4407,7 @@ private: LoadStoreImm(Op, o2, rt, rn, Imm & 0b1'1111'1111); } template - void ldXrb(FEXCore::ARMEmitter::Register rt, FEXCore::ARMEmitter::Register rn, int32_t Imm) { + void ldXrb(ARMEmitter::Register rt, ARMEmitter::Register rn, int32_t Imm) { LOGMAN_THROW_A_FMT(Imm >= -256 && Imm <= 255, "Unscaled offset too large"); constexpr uint32_t Op = 0b0011'1000'01 << 22; @@ -4420,7 +4420,7 @@ private: LoadStoreImm(Op, o2, rt, rn, Imm & 0b1'1111'1111); } template - void stXrb(FEXCore::ARMEmitter::VRegister rt, FEXCore::ARMEmitter::Register rn, int32_t Imm) { + void stXrb(ARMEmitter::VRegister rt, ARMEmitter::Register rn, int32_t Imm) { LOGMAN_THROW_A_FMT(Imm >= -256 && Imm <= 255, "Unscaled offset too large"); constexpr uint32_t Op = 0b0011'1100'00 << 22; @@ -4433,7 +4433,7 @@ private: LoadStoreImm(Op, o2, rt, rn, Imm & 0b1'1111'1111); } template - void ldXrb(FEXCore::ARMEmitter::VRegister rt, FEXCore::ARMEmitter::Register rn, int32_t Imm) { + void ldXrb(ARMEmitter::VRegister rt, ARMEmitter::Register rn, int32_t Imm) { LOGMAN_THROW_A_FMT(Imm >= -256 && Imm <= 255, "Unscaled offset too large"); constexpr uint32_t Op = 0b0011'1100'01 << 22; @@ -4446,7 +4446,7 @@ private: LoadStoreImm(Op, o2, rt, rn, Imm & 0b1'1111'1111); } template - void ldXrsb(FEXCore::ARMEmitter::XRegister rt, FEXCore::ARMEmitter::Register rn, int32_t Imm) { + void ldXrsb(ARMEmitter::XRegister rt, ARMEmitter::Register rn, int32_t Imm) { LOGMAN_THROW_A_FMT(Imm >= -256 && Imm <= 255, "Unscaled offset too large"); constexpr uint32_t Op = 0b0011'1000'10 << 22; @@ -4459,7 +4459,7 @@ private: LoadStoreImm(Op, o2, rt, rn, Imm & 0b1'1111'1111); } template - void ldXrsb(FEXCore::ARMEmitter::WRegister rt, FEXCore::ARMEmitter::Register rn, int32_t Imm) { + void ldXrsb(ARMEmitter::WRegister rt, ARMEmitter::Register rn, int32_t Imm) { LOGMAN_THROW_A_FMT(Imm >= -256 && Imm <= 255, "Unscaled offset too large"); constexpr uint32_t Op = 0b0011'1000'11 << 22; @@ -4472,7 +4472,7 @@ private: LoadStoreImm(Op, o2, rt, rn, Imm & 0b1'1111'1111); } template - void stXrh(FEXCore::ARMEmitter::Register rt, FEXCore::ARMEmitter::Register rn, int32_t Imm) { + void stXrh(ARMEmitter::Register rt, ARMEmitter::Register rn, int32_t Imm) { LOGMAN_THROW_A_FMT(Imm >= -256 && Imm <= 255, "Unscaled offset too large"); constexpr uint32_t Op = 0b0111'1000'00 << 22; @@ -4485,7 +4485,7 @@ private: LoadStoreImm(Op, o2, rt, rn, Imm & 0b1'1111'1111); } template - void ldXrh(FEXCore::ARMEmitter::Register rt, FEXCore::ARMEmitter::Register rn, int32_t Imm) { + void ldXrh(ARMEmitter::Register rt, ARMEmitter::Register rn, int32_t Imm) { LOGMAN_THROW_A_FMT(Imm >= -256 && Imm <= 255, "Unscaled offset too large"); constexpr uint32_t Op = 0b0111'1000'01 << 22; @@ -4498,7 +4498,7 @@ private: LoadStoreImm(Op, o2, rt, rn, Imm & 0b1'1111'1111); } template - void stXrh(FEXCore::ARMEmitter::VRegister rt, FEXCore::ARMEmitter::Register rn, int32_t Imm) { + void stXrh(ARMEmitter::VRegister rt, ARMEmitter::Register rn, int32_t Imm) { LOGMAN_THROW_A_FMT(Imm >= -256 && Imm <= 255, "Unscaled offset too large"); constexpr uint32_t Op = 0b0111'1100'00 << 22; @@ -4511,7 +4511,7 @@ private: LoadStoreImm(Op, o2, rt, rn, Imm & 0b1'1111'1111); } template - void ldXrh(FEXCore::ARMEmitter::VRegister rt, FEXCore::ARMEmitter::Register rn, int32_t Imm) { + void ldXrh(ARMEmitter::VRegister rt, ARMEmitter::Register rn, int32_t Imm) { LOGMAN_THROW_A_FMT(Imm >= -256 && Imm <= 255, "Unscaled offset too large"); constexpr uint32_t Op = 0b0111'1100'01 << 22; @@ -4524,7 +4524,7 @@ private: LoadStoreImm(Op, o2, rt, rn, Imm & 0b1'1111'1111); } template - void ldXrsh(FEXCore::ARMEmitter::XRegister rt, FEXCore::ARMEmitter::Register rn, int32_t Imm) { + void ldXrsh(ARMEmitter::XRegister rt, ARMEmitter::Register rn, int32_t Imm) { LOGMAN_THROW_A_FMT(Imm >= -256 && Imm <= 255, "Unscaled offset too large"); constexpr uint32_t Op = 0b0111'1000'10 << 22; @@ -4537,7 +4537,7 @@ private: LoadStoreImm(Op, o2, rt, rn, Imm & 0b1'1111'1111); } template - void ldXrsh(FEXCore::ARMEmitter::WRegister rt, FEXCore::ARMEmitter::Register rn, int32_t Imm) { + void ldXrsh(ARMEmitter::WRegister rt, ARMEmitter::Register rn, int32_t Imm) { LOGMAN_THROW_A_FMT(Imm >= -256 && Imm <= 255, "Unscaled offset too large"); constexpr uint32_t Op = 0b0111'1000'11 << 22; @@ -4550,7 +4550,7 @@ private: LoadStoreImm(Op, o2, rt, rn, Imm & 0b1'1111'1111); } template - void stXr(FEXCore::ARMEmitter::WRegister rt, FEXCore::ARMEmitter::Register rn, int32_t Imm) { + void stXr(ARMEmitter::WRegister rt, ARMEmitter::Register rn, int32_t Imm) { LOGMAN_THROW_A_FMT(Imm >= -256 && Imm <= 255, "Unscaled offset too large"); constexpr uint32_t Op = 0b1011'1000'00 << 22; @@ -4563,7 +4563,7 @@ private: LoadStoreImm(Op, o2, rt, rn, Imm & 0b1'1111'1111); } template - void ldXr(FEXCore::ARMEmitter::WRegister rt, FEXCore::ARMEmitter::Register rn, int32_t Imm) { + void ldXr(ARMEmitter::WRegister rt, ARMEmitter::Register rn, int32_t Imm) { LOGMAN_THROW_A_FMT(Imm >= -256 && Imm <= 255, "Unscaled offset too large"); constexpr uint32_t Op = 0b1011'1000'01 << 22; @@ -4576,7 +4576,7 @@ private: LoadStoreImm(Op, o2, rt, rn, Imm & 0b1'1111'1111); } template - void stXr(FEXCore::ARMEmitter::SRegister rt, FEXCore::ARMEmitter::Register rn, int32_t Imm) { + void stXr(ARMEmitter::SRegister rt, ARMEmitter::Register rn, int32_t Imm) { LOGMAN_THROW_A_FMT(Imm >= -256 && Imm <= 255, "Unscaled offset too large"); constexpr uint32_t Op = 0b1011'1100'00 << 22; @@ -4589,7 +4589,7 @@ private: LoadStoreImm(Op, o2, rt, rn, Imm & 0b1'1111'1111); } template - void ldXr(FEXCore::ARMEmitter::SRegister rt, FEXCore::ARMEmitter::Register rn, int32_t Imm) { + void ldXr(ARMEmitter::SRegister rt, ARMEmitter::Register rn, int32_t Imm) { LOGMAN_THROW_A_FMT(Imm >= -256 && Imm <= 255, "Unscaled offset too large"); constexpr uint32_t Op = 0b1011'1100'01 << 22; @@ -4602,7 +4602,7 @@ private: LoadStoreImm(Op, o2, rt, rn, Imm & 0b1'1111'1111); } template - void ldXrsw(FEXCore::ARMEmitter::XRegister rt, FEXCore::ARMEmitter::Register rn, int32_t Imm) { + void ldXrsw(ARMEmitter::XRegister rt, ARMEmitter::Register rn, int32_t Imm) { LOGMAN_THROW_A_FMT(Imm >= -256 && Imm <= 255, "Unscaled offset too large"); constexpr uint32_t Op = 0b1011'1000'10 << 22; @@ -4615,7 +4615,7 @@ private: LoadStoreImm(Op, o2, rt, rn, Imm & 0b1'1111'1111); } template - void stXr(FEXCore::ARMEmitter::XRegister rt, FEXCore::ARMEmitter::Register rn, int32_t Imm) { + void stXr(ARMEmitter::XRegister rt, ARMEmitter::Register rn, int32_t Imm) { LOGMAN_THROW_A_FMT(Imm >= -256 && Imm <= 255, "Unscaled offset too large"); constexpr uint32_t Op = 0b1111'1000'00 << 22; @@ -4628,7 +4628,7 @@ private: LoadStoreImm(Op, o2, rt, rn, Imm & 0b1'1111'1111); } template - void ldXr(FEXCore::ARMEmitter::XRegister rt, FEXCore::ARMEmitter::Register rn, int32_t Imm) { + void ldXr(ARMEmitter::XRegister rt, ARMEmitter::Register rn, int32_t Imm) { LOGMAN_THROW_A_FMT(Imm >= -256 && Imm <= 255, "Unscaled offset too large"); constexpr uint32_t Op = 0b1111'1000'01 << 22; @@ -4641,7 +4641,7 @@ private: LoadStoreImm(Op, o2, rt, rn, Imm & 0b1'1111'1111); } template - void stXr(FEXCore::ARMEmitter::DRegister rt, FEXCore::ARMEmitter::Register rn, int32_t Imm) { + void stXr(ARMEmitter::DRegister rt, ARMEmitter::Register rn, int32_t Imm) { LOGMAN_THROW_A_FMT(Imm >= -256 && Imm <= 255, "Unscaled offset too large"); constexpr uint32_t Op = 0b1111'1100'00 << 22; @@ -4654,7 +4654,7 @@ private: LoadStoreImm(Op, o2, rt, rn, Imm & 0b1'1111'1111); } template - void ldXr(FEXCore::ARMEmitter::DRegister rt, FEXCore::ARMEmitter::Register rn, int32_t Imm) { + void ldXr(ARMEmitter::DRegister rt, ARMEmitter::Register rn, int32_t Imm) { LOGMAN_THROW_A_FMT(Imm >= -256 && Imm <= 255, "Unscaled offset too large"); constexpr uint32_t Op = 0b1111'1100'01 << 22; @@ -4667,7 +4667,7 @@ private: LoadStoreImm(Op, o2, rt, rn, Imm & 0b1'1111'1111); } template - void stXr(FEXCore::ARMEmitter::QRegister rt, FEXCore::ARMEmitter::Register rn, int32_t Imm) { + void stXr(ARMEmitter::QRegister rt, ARMEmitter::Register rn, int32_t Imm) { LOGMAN_THROW_A_FMT(Imm >= -256 && Imm <= 255, "Unscaled offset too large"); constexpr uint32_t Op = 0b0011'1100'10 << 22; @@ -4680,7 +4680,7 @@ private: LoadStoreImm(Op, o2, rt, rn, Imm & 0b1'1111'1111); } template - void ldXr(FEXCore::ARMEmitter::QRegister rt, FEXCore::ARMEmitter::Register rn, int32_t Imm) { + void ldXr(ARMEmitter::QRegister rt, ARMEmitter::Register rn, int32_t Imm) { LOGMAN_THROW_A_FMT(Imm >= -256 && Imm <= 255, "Unscaled offset too large"); constexpr uint32_t Op = 0b0011'1100'11 << 22; diff --git a/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/Registers.h b/CodeEmitter/CodeEmitter/Registers.h similarity index 99% rename from FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/Registers.h rename to CodeEmitter/CodeEmitter/Registers.h index 5d3f9abc3..c75af47cf 100644 --- a/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/Registers.h +++ b/CodeEmitter/CodeEmitter/Registers.h @@ -6,7 +6,7 @@ #include #include -namespace FEXCore::ARMEmitter { +namespace ARMEmitter { class WRegister; class XRegister; @@ -1024,4 +1024,4 @@ enum class OpType : uint32_t { Destructive = 0, Constructive, }; -} // namespace FEXCore::ARMEmitter +} // namespace ARMEmitter diff --git a/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/SVEOps.inl b/CodeEmitter/CodeEmitter/SVEOps.inl similarity index 99% rename from FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/SVEOps.inl rename to CodeEmitter/CodeEmitter/SVEOps.inl index 782cc9094..064e12d63 100644 --- a/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/SVEOps.inl +++ b/CodeEmitter/CodeEmitter/SVEOps.inl @@ -1506,10 +1506,10 @@ public: } // SVE broadcast floating-point immediate (unpredicated) - void fdup(FEXCore::ARMEmitter::SubRegSize size, FEXCore::ARMEmitter::ZRegister zd, float Value) { - LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i16Bit || - size == FEXCore::ARMEmitter::SubRegSize::i32Bit || - size == FEXCore::ARMEmitter::SubRegSize::i64Bit, "Unsupported fmov size"); + void fdup(ARMEmitter::SubRegSize size, ARMEmitter::ZRegister zd, float Value) { + LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i16Bit || + size == ARMEmitter::SubRegSize::i32Bit || + size == ARMEmitter::SubRegSize::i64Bit, "Unsupported fmov size"); uint32_t Imm{}; if (size == SubRegSize::i16Bit) { Imm = FP16ToImm8(Float16(Value)); @@ -1521,7 +1521,7 @@ public: SVEBroadcastFloatImmUnpredicated(0b00, 0, Imm, size, zd); } - void fmov(FEXCore::ARMEmitter::SubRegSize size, FEXCore::ARMEmitter::ZRegister zd, float Value) { + void fmov(ARMEmitter::SubRegSize size, ARMEmitter::ZRegister zd, float Value) { fdup(size, zd, Value); } @@ -3717,7 +3717,7 @@ private: // SVE bitwise logical operations (predicated) void SVEBitwiseLogicalPredicated(uint32_t opc, SubRegSize size, PRegister pg, ZRegister zdn, ZRegister zm, ZRegister zd) { - LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i128Bit, "Can't use 128-bit size"); + LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i128Bit, "Can't use 128-bit size"); LOGMAN_THROW_A_FMT(zd == zdn, "zd needs to equal zdn"); LOGMAN_THROW_A_FMT(pg <= PReg::p7, "Can only use p0-p7 as a governing predicate"); @@ -4743,7 +4743,7 @@ private: dc32(Instr); } - void SVEPermuteVector(uint32_t op0, FEXCore::ARMEmitter::ZRegister zd, FEXCore::ARMEmitter::ZRegister zm, uint32_t Imm) { + void SVEPermuteVector(uint32_t op0, ARMEmitter::ZRegister zd, ARMEmitter::ZRegister zm, uint32_t Imm) { constexpr uint32_t Op = 0b0000'0101'0010'0000'000 << 13; uint32_t Instr = Op; diff --git a/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/ScalarOps.inl b/CodeEmitter/CodeEmitter/ScalarOps.inl similarity index 99% rename from FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/ScalarOps.inl rename to CodeEmitter/CodeEmitter/ScalarOps.inl index 4c32e61c4..1dacd1f9d 100644 --- a/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/ScalarOps.inl +++ b/CodeEmitter/CodeEmitter/ScalarOps.inl @@ -33,7 +33,7 @@ public: ASIMDScalarCopy(Op, 1, imm5, 0b0000, rd, rn); } - void mov(FEXCore::ARMEmitter::ScalarRegSize size, FEXCore::ARMEmitter::VRegister rd, FEXCore::ARMEmitter::VRegister rn, uint32_t Index) { + void mov(ARMEmitter::ScalarRegSize size, ARMEmitter::VRegister rd, ARMEmitter::VRegister rn, uint32_t Index) { dup(size, rd, rn, Index); } @@ -1052,21 +1052,21 @@ public: } // Floating-point immediate - void fmov(FEXCore::ARMEmitter::ScalarRegSize size, FEXCore::ARMEmitter::VRegister rd, float Value) { + void fmov(ARMEmitter::ScalarRegSize size, ARMEmitter::VRegister rd, float Value) { uint32_t M = 0; uint32_t S = 0; uint32_t ptype; uint32_t imm8; uint32_t imm5 = 0b0'0000; - if (size == FEXCore::ARMEmitter::ScalarRegSize::i16Bit) { + if (size == ARMEmitter::ScalarRegSize::i16Bit) { ptype = 0b11; imm8 = FP16ToImm8(Float16(Value)); } - else if (size == FEXCore::ARMEmitter::ScalarRegSize::i32Bit) { + else if (size == ARMEmitter::ScalarRegSize::i32Bit) { ptype = 0b00; imm8 = FP32ToImm8(Value); } - else if (size == FEXCore::ARMEmitter::ScalarRegSize::i64Bit) { + else if (size == ARMEmitter::ScalarRegSize::i64Bit) { ptype = 0b01; imm8 = FP64ToImm8(Value); } @@ -1077,7 +1077,7 @@ public: FloatScalarImmediate(M, S, ptype, imm8, imm5, rd); } - void FloatScalarImmediate(uint32_t M, uint32_t S, uint32_t ptype, uint32_t imm8, uint32_t imm5, FEXCore::ARMEmitter::VRegister rd) { + void FloatScalarImmediate(uint32_t M, uint32_t S, uint32_t ptype, uint32_t imm8, uint32_t imm5, ARMEmitter::VRegister rd) { constexpr uint32_t Op = 0b0001'1110'0010'0000'0001'00 << 10; uint32_t Instr = Op; @@ -1286,7 +1286,7 @@ public: private: // Advanced SIMD scalar copy - void ASIMDScalarCopy(uint32_t Op, uint32_t Q, uint32_t imm5, uint32_t imm4, FEXCore::ARMEmitter::VRegister rd, FEXCore::ARMEmitter::VRegister rn) { + void ASIMDScalarCopy(uint32_t Op, uint32_t Q, uint32_t imm5, uint32_t imm4, ARMEmitter::VRegister rd, ARMEmitter::VRegister rn) { uint32_t Instr = Op; Instr |= Q << 30; diff --git a/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/SystemOps.inl b/CodeEmitter/CodeEmitter/SystemOps.inl similarity index 65% rename from FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/SystemOps.inl rename to CodeEmitter/CodeEmitter/SystemOps.inl index 5aeaefa13..13242123f 100644 --- a/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/SystemOps.inl +++ b/CodeEmitter/CodeEmitter/SystemOps.inl @@ -11,7 +11,7 @@ public: // TODO: AT // TODO: CFP // TODO: CPP - void dc(FEXCore::ARMEmitter::DataCacheOperation DCOp, FEXCore::ARMEmitter::Register rt) { + void dc(ARMEmitter::DataCacheOperation DCOp, ARMEmitter::Register rt) { constexpr uint32_t Op = 0b1101'0101'0000'1000'0111 << 12; SystemInstruction(Op, 0, FEXCore::ToUnderlying(DCOp), rt); } @@ -48,67 +48,67 @@ public: ExceptionGeneration(0b101, 0b000, 0b11, Imm); } // System instructions with register argument - void wfet(FEXCore::ARMEmitter::Register rt) { + void wfet(ARMEmitter::Register rt) { SystemInstructionWithReg(0b0000, 0b000, rt); } - void wfit(FEXCore::ARMEmitter::Register rt) { + void wfit(ARMEmitter::Register rt) { SystemInstructionWithReg(0b0000, 0b001, rt); } // Hints void nop() { - Hint(FEXCore::ARMEmitter::HintRegister::NOP); + Hint(ARMEmitter::HintRegister::NOP); } void yield() { - Hint(FEXCore::ARMEmitter::HintRegister::YIELD); + Hint(ARMEmitter::HintRegister::YIELD); } void wfe() { - Hint(FEXCore::ARMEmitter::HintRegister::WFE); + Hint(ARMEmitter::HintRegister::WFE); } void wfi() { - Hint(FEXCore::ARMEmitter::HintRegister::WFI); + Hint(ARMEmitter::HintRegister::WFI); } void sev() { - Hint(FEXCore::ARMEmitter::HintRegister::SEV); + Hint(ARMEmitter::HintRegister::SEV); } void sevl() { - Hint(FEXCore::ARMEmitter::HintRegister::SEVL); + Hint(ARMEmitter::HintRegister::SEVL); } void dgh() { - Hint(FEXCore::ARMEmitter::HintRegister::DGH); + Hint(ARMEmitter::HintRegister::DGH); } void csdb() { - Hint(FEXCore::ARMEmitter::HintRegister::CSDB); + Hint(ARMEmitter::HintRegister::CSDB); } // Barriers void clrex(uint32_t imm = 15) { LOGMAN_THROW_AA_FMT(imm < 16, "Immediate out of range"); - Barrier(FEXCore::ARMEmitter::BarrierRegister::CLREX, imm); + Barrier(ARMEmitter::BarrierRegister::CLREX, imm); } - void dsb(FEXCore::ARMEmitter::BarrierScope Scope) { - Barrier(FEXCore::ARMEmitter::BarrierRegister::DSB, FEXCore::ToUnderlying(Scope)); + void dsb(ARMEmitter::BarrierScope Scope) { + Barrier(ARMEmitter::BarrierRegister::DSB, FEXCore::ToUnderlying(Scope)); } - void dmb(FEXCore::ARMEmitter::BarrierScope Scope) { - Barrier(FEXCore::ARMEmitter::BarrierRegister::DMB, FEXCore::ToUnderlying(Scope)); + void dmb(ARMEmitter::BarrierScope Scope) { + Barrier(ARMEmitter::BarrierRegister::DMB, FEXCore::ToUnderlying(Scope)); } void isb() { - Barrier(FEXCore::ARMEmitter::BarrierRegister::ISB, FEXCore::ToUnderlying(FEXCore::ARMEmitter::BarrierScope::SY)); + Barrier(ARMEmitter::BarrierRegister::ISB, FEXCore::ToUnderlying(ARMEmitter::BarrierScope::SY)); } void sb() { - Barrier(FEXCore::ARMEmitter::BarrierRegister::SB, 0); + Barrier(ARMEmitter::BarrierRegister::SB, 0); } void tcommit() { - Barrier(FEXCore::ARMEmitter::BarrierRegister::TCOMMIT, 0); + Barrier(ARMEmitter::BarrierRegister::TCOMMIT, 0); } // System register move - void msr(FEXCore::ARMEmitter::SystemRegister reg, FEXCore::ARMEmitter::Register rt) { + void msr(ARMEmitter::SystemRegister reg, ARMEmitter::Register rt) { constexpr uint32_t Op = 0b1101'0101'0001 << 20; SystemRegisterMove(Op, rt, reg); } - void mrs(FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::SystemRegister reg) { + void mrs(ARMEmitter::Register rd, ARMEmitter::SystemRegister reg) { constexpr uint32_t Op = 0b1101'0101'0011 << 20; SystemRegisterMove(Op, rd, reg); } @@ -130,7 +130,7 @@ private: } // System instructions with register argument - void SystemInstructionWithReg(uint32_t CRm, uint32_t op2, FEXCore::ARMEmitter::Register rt) { + void SystemInstructionWithReg(uint32_t CRm, uint32_t op2, ARMEmitter::Register rt) { uint32_t Instr = 0b1101'0101'0000'0011'0001 << 12; Instr |= CRm << 8; @@ -140,13 +140,13 @@ private: } // Hints - void Hint(FEXCore::ARMEmitter::HintRegister Reg) { + void Hint(ARMEmitter::HintRegister Reg) { uint32_t Instr = 0b1101'0101'0000'0011'0010'0000'0001'1111U; Instr |= FEXCore::ToUnderlying(Reg); dc32(Instr); } // Barriers - void Barrier(FEXCore::ARMEmitter::BarrierRegister Reg, uint32_t CRm) { + void Barrier(ARMEmitter::BarrierRegister Reg, uint32_t CRm) { uint32_t Instr = 0b1101'0101'0000'0011'0011'0000'0001'1111U; Instr |= CRm << 8; Instr |= FEXCore::ToUnderlying(Reg); @@ -154,7 +154,7 @@ private: } // System Instruction - void SystemInstruction(uint32_t Op, uint32_t L, uint32_t SubOp, FEXCore::ARMEmitter::Register rt) { + void SystemInstruction(uint32_t Op, uint32_t L, uint32_t SubOp, ARMEmitter::Register rt) { uint32_t Instr = Op; Instr |= L << 21; @@ -165,7 +165,7 @@ private: } // System register move - void SystemRegisterMove(uint32_t Op, FEXCore::ARMEmitter::Register rt, FEXCore::ARMEmitter::SystemRegister reg) { + void SystemRegisterMove(uint32_t Op, ARMEmitter::Register rt, ARMEmitter::SystemRegister reg) { uint32_t Instr = Op; Instr |= FEXCore::ToUnderlying(reg); diff --git a/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/VixlUtils.inl b/CodeEmitter/CodeEmitter/VixlUtils.inl similarity index 100% rename from FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/VixlUtils.inl rename to CodeEmitter/CodeEmitter/VixlUtils.inl diff --git a/FEXCore/Source/CMakeLists.txt b/FEXCore/Source/CMakeLists.txt index 514bd96b5..ce4b17b25 100644 --- a/FEXCore/Source/CMakeLists.txt +++ b/FEXCore/Source/CMakeLists.txt @@ -193,7 +193,7 @@ endif() # Some defines for the softfloat library list(APPEND DEFINES "-DSOFTFLOAT_BUILTIN_CLZ") -set (LIBS fmt::fmt vixl xxHash::xxhash FEXHeaderUtils) +set (LIBS fmt::fmt vixl xxHash::xxhash FEXHeaderUtils CodeEmitter) if (NOT MINGW_BUILD) list (APPEND LIBS dl) diff --git a/FEXCore/Source/Interface/Core/ArchHelpers/Arm64Emitter.cpp b/FEXCore/Source/Interface/Core/ArchHelpers/Arm64Emitter.cpp index c62318726..2b50b2dd6 100644 --- a/FEXCore/Source/Interface/Core/ArchHelpers/Arm64Emitter.cpp +++ b/FEXCore/Source/Interface/Core/ArchHelpers/Arm64Emitter.cpp @@ -2,8 +2,6 @@ #include "Interface/Core/ArchHelpers/Arm64Emitter.h" #include "FEXCore/Core/X86Enums.h" #include "FEXCore/Utils/AllocatorHooks.h" -#include "Interface/Core/ArchHelpers/CodeEmitter/Emitter.h" -#include "Interface/Core/ArchHelpers/CodeEmitter/Registers.h" #include "Interface/Core/Dispatcher/Dispatcher.h" #include "Interface/Context/Context.h" #include "Interface/HLE/Thunks/Thunks.h" @@ -13,6 +11,8 @@ #include #include +#include +#include #include #include @@ -31,110 +31,108 @@ namespace FEXCore::CPU { namespace x64 { #ifndef _M_ARM_64EC // All but x19 and x29 are caller saved - constexpr std::array SRA = { - FEXCore::ARMEmitter::Reg::r4, - FEXCore::ARMEmitter::Reg::r5, - FEXCore::ARMEmitter::Reg::r6, - FEXCore::ARMEmitter::Reg::r7, - FEXCore::ARMEmitter::Reg::r8, - FEXCore::ARMEmitter::Reg::r9, - FEXCore::ARMEmitter::Reg::r10, - FEXCore::ARMEmitter::Reg::r11, - FEXCore::ARMEmitter::Reg::r12, - FEXCore::ARMEmitter::Reg::r13, - FEXCore::ARMEmitter::Reg::r14, - FEXCore::ARMEmitter::Reg::r15, - FEXCore::ARMEmitter::Reg::r16, - FEXCore::ARMEmitter::Reg::r17, - FEXCore::ARMEmitter::Reg::r19, - FEXCore::ARMEmitter::Reg::r29, + constexpr std::array SRA = { + ARMEmitter::Reg::r4, + ARMEmitter::Reg::r5, + ARMEmitter::Reg::r6, + ARMEmitter::Reg::r7, + ARMEmitter::Reg::r8, + ARMEmitter::Reg::r9, + ARMEmitter::Reg::r10, + ARMEmitter::Reg::r11, + ARMEmitter::Reg::r12, + ARMEmitter::Reg::r13, + ARMEmitter::Reg::r14, + ARMEmitter::Reg::r15, + ARMEmitter::Reg::r16, + ARMEmitter::Reg::r17, + ARMEmitter::Reg::r19, + ARMEmitter::Reg::r29, // PF/AF must be last. REG_PF, REG_AF, }; - constexpr std::array RA = { + constexpr std::array RA = { // All these callee saved - FEXCore::ARMEmitter::Reg::r20, FEXCore::ARMEmitter::Reg::r21, FEXCore::ARMEmitter::Reg::r22, FEXCore::ARMEmitter::Reg::r23, - FEXCore::ARMEmitter::Reg::r24, FEXCore::ARMEmitter::Reg::r25, FEXCore::ARMEmitter::Reg::r30, + ARMEmitter::Reg::r20, ARMEmitter::Reg::r21, ARMEmitter::Reg::r22, ARMEmitter::Reg::r23, + ARMEmitter::Reg::r24, ARMEmitter::Reg::r25, ARMEmitter::Reg::r30, }; - constexpr std::array, 3> RAPair = {{ - {FEXCore::ARMEmitter::Reg::r20, FEXCore::ARMEmitter::Reg::r21}, - {FEXCore::ARMEmitter::Reg::r22, FEXCore::ARMEmitter::Reg::r23}, - {FEXCore::ARMEmitter::Reg::r24, FEXCore::ARMEmitter::Reg::r25}, + constexpr std::array, 3> RAPair = {{ + {ARMEmitter::Reg::r20, ARMEmitter::Reg::r21}, + {ARMEmitter::Reg::r22, ARMEmitter::Reg::r23}, + {ARMEmitter::Reg::r24, ARMEmitter::Reg::r25}, }}; // All are caller saved - constexpr std::array SRAFPR = { - FEXCore::ARMEmitter::VReg::v16, FEXCore::ARMEmitter::VReg::v17, FEXCore::ARMEmitter::VReg::v18, FEXCore::ARMEmitter::VReg::v19, - FEXCore::ARMEmitter::VReg::v20, FEXCore::ARMEmitter::VReg::v21, FEXCore::ARMEmitter::VReg::v22, FEXCore::ARMEmitter::VReg::v23, - FEXCore::ARMEmitter::VReg::v24, FEXCore::ARMEmitter::VReg::v25, FEXCore::ARMEmitter::VReg::v26, FEXCore::ARMEmitter::VReg::v27, - FEXCore::ARMEmitter::VReg::v28, FEXCore::ARMEmitter::VReg::v29, FEXCore::ARMEmitter::VReg::v30, FEXCore::ARMEmitter::VReg::v31}; + constexpr std::array SRAFPR = { + ARMEmitter::VReg::v16, ARMEmitter::VReg::v17, ARMEmitter::VReg::v18, ARMEmitter::VReg::v19, + ARMEmitter::VReg::v20, ARMEmitter::VReg::v21, ARMEmitter::VReg::v22, ARMEmitter::VReg::v23, + ARMEmitter::VReg::v24, ARMEmitter::VReg::v25, ARMEmitter::VReg::v26, ARMEmitter::VReg::v27, + ARMEmitter::VReg::v28, ARMEmitter::VReg::v29, ARMEmitter::VReg::v30, ARMEmitter::VReg::v31}; // v8..v15 = (lower 64bits) Callee saved - constexpr std::array RAFPR = { + constexpr std::array RAFPR = { // v0 ~ v1 are used as temps. - // FEXCore::ARMEmitter::VReg::v0, FEXCore::ARMEmitter::VReg::v1, + // ARMEmitter::VReg::v0, ARMEmitter::VReg::v1, - FEXCore::ARMEmitter::VReg::v2, FEXCore::ARMEmitter::VReg::v3, FEXCore::ARMEmitter::VReg::v4, FEXCore::ARMEmitter::VReg::v5, - FEXCore::ARMEmitter::VReg::v6, FEXCore::ARMEmitter::VReg::v7, FEXCore::ARMEmitter::VReg::v8, FEXCore::ARMEmitter::VReg::v9, - FEXCore::ARMEmitter::VReg::v10, FEXCore::ARMEmitter::VReg::v11, FEXCore::ARMEmitter::VReg::v12, FEXCore::ARMEmitter::VReg::v13, - FEXCore::ARMEmitter::VReg::v14, FEXCore::ARMEmitter::VReg::v15, + ARMEmitter::VReg::v2, ARMEmitter::VReg::v3, ARMEmitter::VReg::v4, ARMEmitter::VReg::v5, ARMEmitter::VReg::v6, + ARMEmitter::VReg::v7, ARMEmitter::VReg::v8, ARMEmitter::VReg::v9, ARMEmitter::VReg::v10, ARMEmitter::VReg::v11, + ARMEmitter::VReg::v12, ARMEmitter::VReg::v13, ARMEmitter::VReg::v14, ARMEmitter::VReg::v15, }; #else - constexpr std::array SRA = { - FEXCore::ARMEmitter::Reg::r8, - FEXCore::ARMEmitter::Reg::r0, - FEXCore::ARMEmitter::Reg::r1, - FEXCore::ARMEmitter::Reg::r27, + constexpr std::array SRA = { + ARMEmitter::Reg::r8, + ARMEmitter::Reg::r0, + ARMEmitter::Reg::r1, + ARMEmitter::Reg::r27, // SP's register location isn't specified by the ARM64EC ABI, we choose to use r23 - FEXCore::ARMEmitter::Reg::r23, - FEXCore::ARMEmitter::Reg::r29, - FEXCore::ARMEmitter::Reg::r25, - FEXCore::ARMEmitter::Reg::r26, - FEXCore::ARMEmitter::Reg::r2, - FEXCore::ARMEmitter::Reg::r3, - FEXCore::ARMEmitter::Reg::r4, - FEXCore::ARMEmitter::Reg::r5, - FEXCore::ARMEmitter::Reg::r19, - FEXCore::ARMEmitter::Reg::r20, - FEXCore::ARMEmitter::Reg::r21, - FEXCore::ARMEmitter::Reg::r22, + ARMEmitter::Reg::r23, + ARMEmitter::Reg::r29, + ARMEmitter::Reg::r25, + ARMEmitter::Reg::r26, + ARMEmitter::Reg::r2, + ARMEmitter::Reg::r3, + ARMEmitter::Reg::r4, + ARMEmitter::Reg::r5, + ARMEmitter::Reg::r19, + ARMEmitter::Reg::r20, + ARMEmitter::Reg::r21, + ARMEmitter::Reg::r22, REG_PF, REG_AF, }; - constexpr std::array RA = { - FEXCore::ARMEmitter::Reg::r6, FEXCore::ARMEmitter::Reg::r7, FEXCore::ARMEmitter::Reg::r14, FEXCore::ARMEmitter::Reg::r15, - FEXCore::ARMEmitter::Reg::r16, FEXCore::ARMEmitter::Reg::r17, FEXCore::ARMEmitter::Reg::r30, + constexpr std::array RA = { + ARMEmitter::Reg::r6, ARMEmitter::Reg::r7, ARMEmitter::Reg::r14, ARMEmitter::Reg::r15, + ARMEmitter::Reg::r16, ARMEmitter::Reg::r17, ARMEmitter::Reg::r30, }; - constexpr std::array, 3> RAPair = {{ - {FEXCore::ARMEmitter::Reg::r6, FEXCore::ARMEmitter::Reg::r7}, - {FEXCore::ARMEmitter::Reg::r14, FEXCore::ARMEmitter::Reg::r15}, - {FEXCore::ARMEmitter::Reg::r16, FEXCore::ARMEmitter::Reg::r17}, + constexpr std::array, 3> RAPair = {{ + {ARMEmitter::Reg::r6, ARMEmitter::Reg::r7}, + {ARMEmitter::Reg::r14, ARMEmitter::Reg::r15}, + {ARMEmitter::Reg::r16, ARMEmitter::Reg::r17}, }}; - constexpr std::array SRAFPR = { - FEXCore::ARMEmitter::VReg::v0, FEXCore::ARMEmitter::VReg::v1, FEXCore::ARMEmitter::VReg::v2, FEXCore::ARMEmitter::VReg::v3, - FEXCore::ARMEmitter::VReg::v4, FEXCore::ARMEmitter::VReg::v5, FEXCore::ARMEmitter::VReg::v6, FEXCore::ARMEmitter::VReg::v7, - FEXCore::ARMEmitter::VReg::v8, FEXCore::ARMEmitter::VReg::v9, FEXCore::ARMEmitter::VReg::v10, FEXCore::ARMEmitter::VReg::v11, - FEXCore::ARMEmitter::VReg::v12, FEXCore::ARMEmitter::VReg::v13, FEXCore::ARMEmitter::VReg::v14, FEXCore::ARMEmitter::VReg::v15, + constexpr std::array SRAFPR = { + ARMEmitter::VReg::v0, ARMEmitter::VReg::v1, ARMEmitter::VReg::v2, ARMEmitter::VReg::v3, + ARMEmitter::VReg::v4, ARMEmitter::VReg::v5, ARMEmitter::VReg::v6, ARMEmitter::VReg::v7, + ARMEmitter::VReg::v8, ARMEmitter::VReg::v9, ARMEmitter::VReg::v10, ARMEmitter::VReg::v11, + ARMEmitter::VReg::v12, ARMEmitter::VReg::v13, ARMEmitter::VReg::v14, ARMEmitter::VReg::v15, }; - constexpr std::array RAFPR = { - FEXCore::ARMEmitter::VReg::v18, FEXCore::ARMEmitter::VReg::v19, FEXCore::ARMEmitter::VReg::v20, FEXCore::ARMEmitter::VReg::v21, - FEXCore::ARMEmitter::VReg::v22, FEXCore::ARMEmitter::VReg::v23, FEXCore::ARMEmitter::VReg::v24, FEXCore::ARMEmitter::VReg::v25, - FEXCore::ARMEmitter::VReg::v26, FEXCore::ARMEmitter::VReg::v27, FEXCore::ARMEmitter::VReg::v28, FEXCore::ARMEmitter::VReg::v29, - FEXCore::ARMEmitter::VReg::v30, FEXCore::ARMEmitter::VReg::v31}; + constexpr std::array RAFPR = { + ARMEmitter::VReg::v18, ARMEmitter::VReg::v19, ARMEmitter::VReg::v20, ARMEmitter::VReg::v21, ARMEmitter::VReg::v22, + ARMEmitter::VReg::v23, ARMEmitter::VReg::v24, ARMEmitter::VReg::v25, ARMEmitter::VReg::v26, ARMEmitter::VReg::v27, + ARMEmitter::VReg::v28, ARMEmitter::VReg::v29, ARMEmitter::VReg::v30, ARMEmitter::VReg::v31}; #endif // I wish this could get constexpr generated from SRA's definition but impossible until libstdc++12, libc++15. // SRA GPRs that need to be spilled when calling a function with `preserve_all` ABI. - constexpr std::array PreserveAll_SRA = { - FEXCore::ARMEmitter::Reg::r4, FEXCore::ARMEmitter::Reg::r5, FEXCore::ARMEmitter::Reg::r6, FEXCore::ARMEmitter::Reg::r7, - FEXCore::ARMEmitter::Reg::r8, FEXCore::ARMEmitter::Reg::r16, FEXCore::ARMEmitter::Reg::r17, + constexpr std::array PreserveAll_SRA = { + ARMEmitter::Reg::r4, ARMEmitter::Reg::r5, ARMEmitter::Reg::r6, ARMEmitter::Reg::r7, + ARMEmitter::Reg::r8, ARMEmitter::Reg::r16, ARMEmitter::Reg::r17, }; constexpr uint32_t PreserveAll_SRAMask = {[]() -> uint32_t { @@ -160,12 +158,12 @@ namespace x64 { }()}; // Dynamic GPRs - constexpr std::array PreserveAll_Dynamic = { + constexpr std::array PreserveAll_Dynamic = { // Only LR needs to get saved. - FEXCore::ARMEmitter::Reg::r30}; + ARMEmitter::Reg::r30}; // SRA FPRs that need to be spilled when calling a function with `preserve_all` ABI. - constexpr std::array PreserveAll_SRAFPR = { + constexpr std::array PreserveAll_SRAFPR = { // None. }; @@ -179,15 +177,14 @@ namespace x64 { // Dynamic FPRs // - v0-v7 - constexpr std::array PreserveAll_DynamicFPR = { + constexpr std::array PreserveAll_DynamicFPR = { // v0 ~ v1 are temps - FEXCore::ARMEmitter::VReg::v2, FEXCore::ARMEmitter::VReg::v3, FEXCore::ARMEmitter::VReg::v4, - FEXCore::ARMEmitter::VReg::v5, FEXCore::ARMEmitter::VReg::v6, FEXCore::ARMEmitter::VReg::v7, + ARMEmitter::VReg::v2, ARMEmitter::VReg::v3, ARMEmitter::VReg::v4, ARMEmitter::VReg::v5, ARMEmitter::VReg::v6, ARMEmitter::VReg::v7, }; // SRA FPRs that need to be spilled when the host supports SVE-256bit with `preserve_all` ABI. // This is /all/ of the SRA registers - constexpr std::array PreserveAll_SRAFPRSVE = SRAFPR; + constexpr std::array PreserveAll_SRAFPRSVE = SRAFPR; constexpr uint32_t PreserveAll_SRAFPRSVEMask = {[]() -> uint32_t { uint32_t Mask {}; @@ -198,89 +195,86 @@ namespace x64 { }()}; // Dynamic FPRs when the host supports SVE-256bit. - constexpr std::array PreserveAll_DynamicFPRSVE = { + constexpr std::array PreserveAll_DynamicFPRSVE = { // v0 ~ v1 are used as temps. - FEXCore::ARMEmitter::VReg::v2, FEXCore::ARMEmitter::VReg::v3, FEXCore::ARMEmitter::VReg::v4, FEXCore::ARMEmitter::VReg::v5, - FEXCore::ARMEmitter::VReg::v6, FEXCore::ARMEmitter::VReg::v7, FEXCore::ARMEmitter::VReg::v8, FEXCore::ARMEmitter::VReg::v9, - FEXCore::ARMEmitter::VReg::v10, FEXCore::ARMEmitter::VReg::v11, FEXCore::ARMEmitter::VReg::v12, FEXCore::ARMEmitter::VReg::v13, - FEXCore::ARMEmitter::VReg::v14, FEXCore::ARMEmitter::VReg::v15, + ARMEmitter::VReg::v2, ARMEmitter::VReg::v3, ARMEmitter::VReg::v4, ARMEmitter::VReg::v5, ARMEmitter::VReg::v6, + ARMEmitter::VReg::v7, ARMEmitter::VReg::v8, ARMEmitter::VReg::v9, ARMEmitter::VReg::v10, ARMEmitter::VReg::v11, + ARMEmitter::VReg::v12, ARMEmitter::VReg::v13, ARMEmitter::VReg::v14, ARMEmitter::VReg::v15, }; } // namespace x64 namespace x32 { // All but x19 and x29 are caller saved - constexpr std::array SRA = { - FEXCore::ARMEmitter::Reg::r4, - FEXCore::ARMEmitter::Reg::r5, - FEXCore::ARMEmitter::Reg::r6, - FEXCore::ARMEmitter::Reg::r7, - FEXCore::ARMEmitter::Reg::r8, - FEXCore::ARMEmitter::Reg::r9, - FEXCore::ARMEmitter::Reg::r10, - FEXCore::ARMEmitter::Reg::r11, + constexpr std::array SRA = { + ARMEmitter::Reg::r4, + ARMEmitter::Reg::r5, + ARMEmitter::Reg::r6, + ARMEmitter::Reg::r7, + ARMEmitter::Reg::r8, + ARMEmitter::Reg::r9, + ARMEmitter::Reg::r10, + ARMEmitter::Reg::r11, // PF/AF must be last. REG_PF, REG_AF, }; - constexpr std::array RA = { + constexpr std::array RA = { // All these callee saved - FEXCore::ARMEmitter::Reg::r20, - FEXCore::ARMEmitter::Reg::r21, - FEXCore::ARMEmitter::Reg::r22, - FEXCore::ARMEmitter::Reg::r23, - FEXCore::ARMEmitter::Reg::r24, - FEXCore::ARMEmitter::Reg::r25, + ARMEmitter::Reg::r20, + ARMEmitter::Reg::r21, + ARMEmitter::Reg::r22, + ARMEmitter::Reg::r23, + ARMEmitter::Reg::r24, + ARMEmitter::Reg::r25, // Registers only available on 32-bit // All these are caller saved (except for r19). - FEXCore::ARMEmitter::Reg::r12, - FEXCore::ARMEmitter::Reg::r13, - FEXCore::ARMEmitter::Reg::r14, - FEXCore::ARMEmitter::Reg::r15, - FEXCore::ARMEmitter::Reg::r16, - FEXCore::ARMEmitter::Reg::r17, - FEXCore::ARMEmitter::Reg::r29, - FEXCore::ARMEmitter::Reg::r30, + ARMEmitter::Reg::r12, + ARMEmitter::Reg::r13, + ARMEmitter::Reg::r14, + ARMEmitter::Reg::r15, + ARMEmitter::Reg::r16, + ARMEmitter::Reg::r17, + ARMEmitter::Reg::r29, + ARMEmitter::Reg::r30, - FEXCore::ARMEmitter::Reg::r19, + ARMEmitter::Reg::r19, }; - constexpr std::array, 7> RAPair = {{ - {FEXCore::ARMEmitter::Reg::r20, FEXCore::ARMEmitter::Reg::r21}, - {FEXCore::ARMEmitter::Reg::r22, FEXCore::ARMEmitter::Reg::r23}, - {FEXCore::ARMEmitter::Reg::r24, FEXCore::ARMEmitter::Reg::r25}, + constexpr std::array, 7> RAPair = {{ + {ARMEmitter::Reg::r20, ARMEmitter::Reg::r21}, + {ARMEmitter::Reg::r22, ARMEmitter::Reg::r23}, + {ARMEmitter::Reg::r24, ARMEmitter::Reg::r25}, - {FEXCore::ARMEmitter::Reg::r12, FEXCore::ARMEmitter::Reg::r13}, - {FEXCore::ARMEmitter::Reg::r14, FEXCore::ARMEmitter::Reg::r15}, - {FEXCore::ARMEmitter::Reg::r16, FEXCore::ARMEmitter::Reg::r17}, - {FEXCore::ARMEmitter::Reg::r29, FEXCore::ARMEmitter::Reg::r30}, + {ARMEmitter::Reg::r12, ARMEmitter::Reg::r13}, + {ARMEmitter::Reg::r14, ARMEmitter::Reg::r15}, + {ARMEmitter::Reg::r16, ARMEmitter::Reg::r17}, + {ARMEmitter::Reg::r29, ARMEmitter::Reg::r30}, }}; // All are caller saved - constexpr std::array SRAFPR = { - FEXCore::ARMEmitter::VReg::v16, FEXCore::ARMEmitter::VReg::v17, FEXCore::ARMEmitter::VReg::v18, FEXCore::ARMEmitter::VReg::v19, - FEXCore::ARMEmitter::VReg::v20, FEXCore::ARMEmitter::VReg::v21, FEXCore::ARMEmitter::VReg::v22, FEXCore::ARMEmitter::VReg::v23, + constexpr std::array SRAFPR = { + ARMEmitter::VReg::v16, ARMEmitter::VReg::v17, ARMEmitter::VReg::v18, ARMEmitter::VReg::v19, + ARMEmitter::VReg::v20, ARMEmitter::VReg::v21, ARMEmitter::VReg::v22, ARMEmitter::VReg::v23, }; // v8..v15 = (lower 64bits) Callee saved - constexpr std::array RAFPR = { + constexpr std::array RAFPR = { // v0 ~ v1 are used as temps. - // FEXCore::ARMEmitter::VReg::v0, FEXCore::ARMEmitter::VReg::v1, + // ARMEmitter::VReg::v0, ARMEmitter::VReg::v1, - FEXCore::ARMEmitter::VReg::v2, FEXCore::ARMEmitter::VReg::v3, FEXCore::ARMEmitter::VReg::v4, FEXCore::ARMEmitter::VReg::v5, - FEXCore::ARMEmitter::VReg::v6, FEXCore::ARMEmitter::VReg::v7, FEXCore::ARMEmitter::VReg::v8, FEXCore::ARMEmitter::VReg::v9, - FEXCore::ARMEmitter::VReg::v10, FEXCore::ARMEmitter::VReg::v11, FEXCore::ARMEmitter::VReg::v12, FEXCore::ARMEmitter::VReg::v13, - FEXCore::ARMEmitter::VReg::v14, FEXCore::ARMEmitter::VReg::v15, + ARMEmitter::VReg::v2, ARMEmitter::VReg::v3, ARMEmitter::VReg::v4, ARMEmitter::VReg::v5, ARMEmitter::VReg::v6, + ARMEmitter::VReg::v7, ARMEmitter::VReg::v8, ARMEmitter::VReg::v9, ARMEmitter::VReg::v10, ARMEmitter::VReg::v11, + ARMEmitter::VReg::v12, ARMEmitter::VReg::v13, ARMEmitter::VReg::v14, ARMEmitter::VReg::v15, - FEXCore::ARMEmitter::VReg::v24, FEXCore::ARMEmitter::VReg::v25, FEXCore::ARMEmitter::VReg::v26, FEXCore::ARMEmitter::VReg::v27, - FEXCore::ARMEmitter::VReg::v28, FEXCore::ARMEmitter::VReg::v29, FEXCore::ARMEmitter::VReg::v30, FEXCore::ARMEmitter::VReg::v31}; + ARMEmitter::VReg::v24, ARMEmitter::VReg::v25, ARMEmitter::VReg::v26, ARMEmitter::VReg::v27, ARMEmitter::VReg::v28, + ARMEmitter::VReg::v29, ARMEmitter::VReg::v30, ARMEmitter::VReg::v31}; // I wish this could get constexpr generated from SRA's definition but impossible until libstdc++12, libc++15. // SRA GPRs that need to be spilled when calling a function with `preserve_all` ABI. - constexpr std::array PreserveAll_SRA = { - FEXCore::ARMEmitter::Reg::r4, FEXCore::ARMEmitter::Reg::r5, FEXCore::ARMEmitter::Reg::r6, - FEXCore::ARMEmitter::Reg::r7, FEXCore::ARMEmitter::Reg::r8, + constexpr std::array PreserveAll_SRA = { + ARMEmitter::Reg::r4, ARMEmitter::Reg::r5, ARMEmitter::Reg::r6, ARMEmitter::Reg::r7, ARMEmitter::Reg::r8, }; constexpr uint32_t PreserveAll_SRAMask = {[]() -> uint32_t { @@ -306,11 +300,10 @@ namespace x32 { }()}; // Dynamic GPRs - constexpr std::array PreserveAll_Dynamic = { - FEXCore::ARMEmitter::Reg::r16, FEXCore::ARMEmitter::Reg::r17, FEXCore::ARMEmitter::Reg::r30}; + constexpr std::array PreserveAll_Dynamic = {ARMEmitter::Reg::r16, ARMEmitter::Reg::r17, ARMEmitter::Reg::r30}; // SRA FPRs that need to be spilled when calling a function with `preserve_all` ABI. - constexpr std::array PreserveAll_SRAFPR = { + constexpr std::array PreserveAll_SRAFPR = { // None. }; @@ -324,15 +317,14 @@ namespace x32 { // Dynamic FPRs // - v0-v7 - constexpr std::array PreserveAll_DynamicFPR = { + constexpr std::array PreserveAll_DynamicFPR = { // v0 ~ v1 are temps - FEXCore::ARMEmitter::VReg::v2, FEXCore::ARMEmitter::VReg::v3, FEXCore::ARMEmitter::VReg::v4, - FEXCore::ARMEmitter::VReg::v5, FEXCore::ARMEmitter::VReg::v6, FEXCore::ARMEmitter::VReg::v7, + ARMEmitter::VReg::v2, ARMEmitter::VReg::v3, ARMEmitter::VReg::v4, ARMEmitter::VReg::v5, ARMEmitter::VReg::v6, ARMEmitter::VReg::v7, }; // SRA FPRs that need to be spilled when the host supports SVE-256bit with `preserve_all` ABI. // This is /all/ of the SRA registers - constexpr std::array PreserveAll_SRAFPRSVE = SRAFPR; + constexpr std::array PreserveAll_SRAFPRSVE = SRAFPR; constexpr uint32_t PreserveAll_SRAFPRSVEMask = {[]() -> uint32_t { uint32_t Mask {}; @@ -343,15 +335,14 @@ namespace x32 { }()}; // Dynamic FPRs when the host supports SVE-256bit. - constexpr std::array PreserveAll_DynamicFPRSVE = { + constexpr std::array PreserveAll_DynamicFPRSVE = { // v0 ~ v1 are used as temps. - FEXCore::ARMEmitter::VReg::v2, FEXCore::ARMEmitter::VReg::v3, FEXCore::ARMEmitter::VReg::v4, FEXCore::ARMEmitter::VReg::v5, - FEXCore::ARMEmitter::VReg::v6, FEXCore::ARMEmitter::VReg::v7, FEXCore::ARMEmitter::VReg::v8, FEXCore::ARMEmitter::VReg::v9, - FEXCore::ARMEmitter::VReg::v10, FEXCore::ARMEmitter::VReg::v11, FEXCore::ARMEmitter::VReg::v12, FEXCore::ARMEmitter::VReg::v13, - FEXCore::ARMEmitter::VReg::v14, FEXCore::ARMEmitter::VReg::v15, + ARMEmitter::VReg::v2, ARMEmitter::VReg::v3, ARMEmitter::VReg::v4, ARMEmitter::VReg::v5, ARMEmitter::VReg::v6, + ARMEmitter::VReg::v7, ARMEmitter::VReg::v8, ARMEmitter::VReg::v9, ARMEmitter::VReg::v10, ARMEmitter::VReg::v11, + ARMEmitter::VReg::v12, ARMEmitter::VReg::v13, ARMEmitter::VReg::v14, ARMEmitter::VReg::v15, - FEXCore::ARMEmitter::VReg::v24, FEXCore::ARMEmitter::VReg::v25, FEXCore::ARMEmitter::VReg::v26, FEXCore::ARMEmitter::VReg::v27, - FEXCore::ARMEmitter::VReg::v28, FEXCore::ARMEmitter::VReg::v29, FEXCore::ARMEmitter::VReg::v30, FEXCore::ARMEmitter::VReg::v31}; + ARMEmitter::VReg::v24, ARMEmitter::VReg::v25, ARMEmitter::VReg::v26, ARMEmitter::VReg::v27, ARMEmitter::VReg::v28, + ARMEmitter::VReg::v29, ARMEmitter::VReg::v30, ARMEmitter::VReg::v31}; } // namespace x32 // We want vixl to not allocate a default buffer. Jit and dispatcher will manually create one. @@ -589,7 +580,7 @@ void Arm64Emitter::PopCalleeSavedRegisters() { } } -void Arm64Emitter::SpillStaticRegs(FEXCore::ARMEmitter::Register TmpReg, bool FPRs, uint32_t GPRSpillMask, uint32_t FPRSpillMask) { +void Arm64Emitter::SpillStaticRegs(ARMEmitter::Register TmpReg, bool FPRs, uint32_t GPRSpillMask, uint32_t FPRSpillMask) { #ifndef VIXL_SIMULATOR if (EmitterCTX->HostFeatures.SupportsAFP) { // Disable AFP features when spilling registers. @@ -683,7 +674,7 @@ void Arm64Emitter::SpillStaticRegs(FEXCore::ARMEmitter::Register TmpReg, bool FP } void Arm64Emitter::FillStaticRegs(bool FPRs, uint32_t GPRFillMask, uint32_t FPRFillMask) { - FEXCore::ARMEmitter::Register TmpReg = FEXCore::ARMEmitter::Reg::r0; + ARMEmitter::Register TmpReg = ARMEmitter::Reg::r0; LOGMAN_THROW_A_FMT(GPRFillMask != 0, "Must fill at least 1 GPR for a temp"); [[maybe_unused]] bool FoundRegister {}; for (auto Reg : StaticRegisters) { @@ -798,7 +789,7 @@ void Arm64Emitter::FillStaticRegs(bool FPRs, uint32_t GPRFillMask, uint32_t FPRF } } -void Arm64Emitter::PushVectorRegisters(FEXCore::ARMEmitter::Register TmpReg, bool SVERegs, std::span VRegs) { +void Arm64Emitter::PushVectorRegisters(ARMEmitter::Register TmpReg, bool SVERegs, std::span VRegs) { if (SVERegs) { size_t i = 0; @@ -835,7 +826,7 @@ void Arm64Emitter::PushVectorRegisters(FEXCore::ARMEmitter::Register TmpReg, boo } } -void Arm64Emitter::PushGeneralRegisters(FEXCore::ARMEmitter::Register TmpReg, std::span Regs) { +void Arm64Emitter::PushGeneralRegisters(ARMEmitter::Register TmpReg, std::span Regs) { size_t i = 0; for (; i < (Regs.size() % 2); ++i) { const auto Reg1 = Regs[i]; @@ -849,7 +840,7 @@ void Arm64Emitter::PushGeneralRegisters(FEXCore::ARMEmitter::Register TmpReg, st } } -void Arm64Emitter::PopVectorRegisters(bool SVERegs, std::span VRegs) { +void Arm64Emitter::PopVectorRegisters(bool SVERegs, std::span VRegs) { if (SVERegs) { size_t i = 0; for (; i < (VRegs.size() % 4); i += 2) { @@ -885,7 +876,7 @@ void Arm64Emitter::PopVectorRegisters(bool SVERegs, std::span Regs) { +void Arm64Emitter::PopGeneralRegisters(std::span Regs) { size_t i = 0; for (; i < (Regs.size() % 2); ++i) { const auto Reg1 = Regs[i]; @@ -898,7 +889,7 @@ void Arm64Emitter::PopGeneralRegisters(std::spanHostFeatures.SupportsAVX; const auto GPRSize = (ConfiguredDynamicRegisterBase.size() + 1) * Core::CPUState::GPR_REG_SIZE; const auto FPRRegSize = CanUseSVE ? Core::CPUState::XMM_AVX_REG_SIZE : Core::CPUState::XMM_SSE_REG_SIZE; @@ -937,12 +928,12 @@ void Arm64Emitter::PopDynamicRegsAndLR() { #endif } -void Arm64Emitter::SpillForPreserveAllABICall(FEXCore::ARMEmitter::Register TmpReg, bool FPRs) { +void Arm64Emitter::SpillForPreserveAllABICall(ARMEmitter::Register TmpReg, bool FPRs) { const auto CanUseSVE = EmitterCTX->HostFeatures.SupportsAVX; const auto FPRRegSize = CanUseSVE ? Core::CPUState::XMM_AVX_REG_SIZE : Core::CPUState::XMM_SSE_REG_SIZE; - std::span DynamicGPRs {}; - std::span DynamicFPRs {}; + std::span DynamicGPRs {}; + std::span DynamicFPRs {}; uint32_t PreserveSRAMask {}; uint32_t PreserveSRAFPRMask {}; if (EmitterCTX->Config.Is64BitMode()) { @@ -989,8 +980,8 @@ void Arm64Emitter::SpillForPreserveAllABICall(FEXCore::ARMEmitter::Register TmpR void Arm64Emitter::FillForPreserveAllABICall(bool FPRs) { const auto CanUseSVE = EmitterCTX->HostFeatures.SupportsAVX; - std::span DynamicGPRs {}; - std::span DynamicFPRs {}; + std::span DynamicGPRs {}; + std::span DynamicFPRs {}; uint32_t PreserveSRAMask {}; uint32_t PreserveSRAFPRMask {}; diff --git a/FEXCore/Source/Interface/Core/ArchHelpers/Arm64Emitter.h b/FEXCore/Source/Interface/Core/ArchHelpers/Arm64Emitter.h index 1fb17c257..86deedd35 100644 --- a/FEXCore/Source/Interface/Core/ArchHelpers/Arm64Emitter.h +++ b/FEXCore/Source/Interface/Core/ArchHelpers/Arm64Emitter.h @@ -2,9 +2,6 @@ #pragma once #include "FEXCore/Utils/EnumUtils.h" -#include "Interface/Core/ArchHelpers/CodeEmitter/Emitter.h" -#include "Interface/Core/ArchHelpers/CodeEmitter/Registers.h" - #include "Interface/Core/ObjectCache/Relocations.h" #include @@ -22,6 +19,8 @@ #include #include +#include +#include #include #include @@ -35,66 +34,66 @@ class ContextImpl; namespace FEXCore::CPU { // Contains the address to the currently available CPU state -constexpr auto STATE = FEXCore::ARMEmitter::XReg::x28; +constexpr auto STATE = ARMEmitter::XReg::x28; #ifndef _M_ARM_64EC // GPR temporaries. Only x3 can be used across spill boundaries // so if these ever need to change, be very careful about that. -constexpr auto TMP1 = FEXCore::ARMEmitter::XReg::x0; -constexpr auto TMP2 = FEXCore::ARMEmitter::XReg::x1; -constexpr auto TMP3 = FEXCore::ARMEmitter::XReg::x2; -constexpr auto TMP4 = FEXCore::ARMEmitter::XReg::x3; +constexpr auto TMP1 = ARMEmitter::XReg::x0; +constexpr auto TMP2 = ARMEmitter::XReg::x1; +constexpr auto TMP3 = ARMEmitter::XReg::x2; +constexpr auto TMP4 = ARMEmitter::XReg::x3; constexpr bool TMP_ABIARGS = true; // We pin r26/r27 as PF/AF respectively, this is internal FEX ABI. -constexpr auto REG_PF = FEXCore::ARMEmitter::Reg::r26; -constexpr auto REG_AF = FEXCore::ARMEmitter::Reg::r27; +constexpr auto REG_PF = ARMEmitter::Reg::r26; +constexpr auto REG_AF = ARMEmitter::Reg::r27; // Vector temporaries -constexpr auto VTMP1 = FEXCore::ARMEmitter::VReg::v0; -constexpr auto VTMP2 = FEXCore::ARMEmitter::VReg::v1; +constexpr auto VTMP1 = ARMEmitter::VReg::v0; +constexpr auto VTMP2 = ARMEmitter::VReg::v1; #else -constexpr auto TMP1 = FEXCore::ARMEmitter::XReg::x10; -constexpr auto TMP2 = FEXCore::ARMEmitter::XReg::x11; -constexpr auto TMP3 = FEXCore::ARMEmitter::XReg::x12; -constexpr auto TMP4 = FEXCore::ARMEmitter::XReg::x13; +constexpr auto TMP1 = ARMEmitter::XReg::x10; +constexpr auto TMP2 = ARMEmitter::XReg::x11; +constexpr auto TMP3 = ARMEmitter::XReg::x12; +constexpr auto TMP4 = ARMEmitter::XReg::x13; constexpr bool TMP_ABIARGS = false; // We pin r11/r12 as PF/AF respectively for arm64ec, as r26/r27 are used for SRA. -constexpr auto REG_PF = FEXCore::ARMEmitter::Reg::r9; -constexpr auto REG_AF = FEXCore::ARMEmitter::Reg::r24; +constexpr auto REG_PF = ARMEmitter::Reg::r9; +constexpr auto REG_AF = ARMEmitter::Reg::r24; // Vector temporaries -constexpr auto VTMP1 = FEXCore::ARMEmitter::VReg::v16; -constexpr auto VTMP2 = FEXCore::ARMEmitter::VReg::v17; +constexpr auto VTMP1 = ARMEmitter::VReg::v16; +constexpr auto VTMP2 = ARMEmitter::VReg::v17; // Entry/Exit ABI -constexpr auto EC_CALL_CHECKER_PC_REG = FEXCore::ARMEmitter::XReg::x9; -constexpr auto EC_ENTRY_CPUAREA_REG = FEXCore::ARMEmitter::XReg::x17; +constexpr auto EC_CALL_CHECKER_PC_REG = ARMEmitter::XReg::x9; +constexpr auto EC_ENTRY_CPUAREA_REG = ARMEmitter::XReg::x17; #endif // Predicate register temporaries (used when AVX support is enabled) // PRED_TMP_16B indicates a predicate register that indicates the first 16 bytes set to 1. // PRED_TMP_32B indicates a predicate register that indicates the first 32 bytes set to 1. -constexpr FEXCore::ARMEmitter::PRegister PRED_TMP_16B = FEXCore::ARMEmitter::PReg::p6; -constexpr FEXCore::ARMEmitter::PRegister PRED_TMP_32B = FEXCore::ARMEmitter::PReg::p7; +constexpr ARMEmitter::PRegister PRED_TMP_16B = ARMEmitter::PReg::p6; +constexpr ARMEmitter::PRegister PRED_TMP_32B = ARMEmitter::PReg::p7; // This class contains common emitter utility functions that can // be used by both Arm64 JIT and ARM64 Dispatcher -class Arm64Emitter : public FEXCore::ARMEmitter::Emitter { +class Arm64Emitter : public ARMEmitter::Emitter { protected: Arm64Emitter(FEXCore::Context::ContextImpl* ctx, void* EmissionPtr = nullptr, size_t size = 0); FEXCore::Context::ContextImpl* EmitterCTX; vixl::aarch64::CPU CPU; - std::span ConfiguredDynamicRegisterBase {}; - std::span StaticRegisters {}; - std::span GeneralRegisters {}; - std::span> GeneralPairRegisters {}; - std::span StaticFPRegisters {}; - std::span GeneralFPRegisters {}; + std::span ConfiguredDynamicRegisterBase {}; + std::span StaticRegisters {}; + std::span GeneralRegisters {}; + std::span> GeneralPairRegisters {}; + std::span StaticFPRegisters {}; + std::span GeneralFPRegisters {}; /** * @name Register Allocation @@ -111,13 +110,13 @@ protected: constexpr static uint8_t RA_64 = 1; constexpr static uint8_t RA_FPR = 2; - void LoadConstant(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register Reg, uint64_t Constant, bool NOPPad = false); + void LoadConstant(ARMEmitter::Size s, ARMEmitter::Register Reg, uint64_t Constant, bool NOPPad = false); // NOTE: These functions WILL clobber the register TMP4 if AVX support is enabled // and FPRs are being spilled or filled. If only GPRs are spilled/filled, then // TMP4 is left alone. - void SpillStaticRegs(FEXCore::ARMEmitter::Register TmpReg, bool FPRs = true, uint32_t GPRSpillMask = ~0U, uint32_t FPRSpillMask = ~0U); + void SpillStaticRegs(ARMEmitter::Register TmpReg, bool FPRs = true, uint32_t GPRSpillMask = ~0U, uint32_t FPRSpillMask = ~0U); void FillStaticRegs(bool FPRs = true, uint32_t GPRFillMask = ~0U, uint32_t FPRFillMask = ~0U); // Register 0-18 + 29 + 30 are caller saved @@ -128,13 +127,13 @@ protected: static constexpr uint32_t CALLER_FPR_MASK = ~0U; // Generic push and pop vector registers. - void PushVectorRegisters(FEXCore::ARMEmitter::Register TmpReg, bool SVERegs, std::span VRegs); - void PushGeneralRegisters(FEXCore::ARMEmitter::Register TmpReg, std::span Regs); + void PushVectorRegisters(ARMEmitter::Register TmpReg, bool SVERegs, std::span VRegs); + void PushGeneralRegisters(ARMEmitter::Register TmpReg, std::span Regs); - void PopVectorRegisters(bool SVERegs, std::span VRegs); - void PopGeneralRegisters(std::span Regs); + void PopVectorRegisters(bool SVERegs, std::span VRegs); + void PopGeneralRegisters(std::span Regs); - void PushDynamicRegsAndLR(FEXCore::ARMEmitter::Register TmpReg); + void PushDynamicRegsAndLR(ARMEmitter::Register TmpReg); void PopDynamicRegsAndLR(); void PushCalleeSavedRegisters(); @@ -150,10 +149,10 @@ protected: // Callee Saved: // - X9-X15, X19-X31 // - Low 128-bits of v8-v31 - void SpillForPreserveAllABICall(FEXCore::ARMEmitter::Register TmpReg, bool FPRs = true); + void SpillForPreserveAllABICall(ARMEmitter::Register TmpReg, bool FPRs = true); void FillForPreserveAllABICall(bool FPRs = true); - void SpillForABICall(bool SupportsPreserveAllABI, FEXCore::ARMEmitter::Register TmpReg, bool FPRs = true) { + void SpillForABICall(bool SupportsPreserveAllABI, ARMEmitter::Register TmpReg, bool FPRs = true) { if (SupportsPreserveAllABI) { SpillForPreserveAllABICall(TmpReg, FPRs); } else { diff --git a/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/ALUOps.inl b/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/ALUOps.inl deleted file mode 100644 index 08eb1b6cc..000000000 --- a/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/ALUOps.inl +++ /dev/null @@ -1,1171 +0,0 @@ -// SPDX-License-Identifier: MIT -/* ALU instruction emitters. - * - * Almost all of these operations have `ARMEmitter::Size` as their first argument. - * This allows both 32-bit and 64-bit selection of how that instruction is going to operate. - * - * Some emitter operations explicitly use `XRegister` or `WRegister`. - * This is usually due to the instruction only supporting one operating size. - * Although in some cases is a minor convenience without any performance implications. - * - * FEX-Emu ALU operations usually have a 32-bit or 64-bit operating size encoded in the IR operation, - * This allows FEX to use a single helper function which decodes to both handlers. - */ -private: - static bool IsADRRange(int64_t Imm) { - return Imm >= -1048576 && Imm <= 1048575; - } - static bool IsADRPRange(int64_t Imm) { - return Imm >= -4294967296 && Imm <= 4294963200; - } - static bool IsADRPAligned(int64_t Imm) { - return (Imm & 0xFFF) == 0; - } -public: - // PC relative - void adr(FEXCore::ARMEmitter::Register rd, uint32_t Imm) { - constexpr uint32_t Op = 0b0001'0000 << 24; - DataProcessing_PCRel_Imm(Op, rd, Imm); - } - - void adr(FEXCore::ARMEmitter::Register rd, BackwardLabel const* Label) { - int32_t Imm = static_cast(Label->Location - GetCursorAddress()); - LOGMAN_THROW_A_FMT(IsADRRange(Imm), "Unscaled offset too large"); - - constexpr uint32_t Op = 0b0001'0000 << 24; - DataProcessing_PCRel_Imm(Op, rd, Imm); - } - template - requires (std::is_same_v || std::is_same_v) - void adr(FEXCore::ARMEmitter::Register rd, LabelType *Label) { - AddLocationToLabel(Label, SingleUseForwardLabel{ .Location = GetCursorAddress(), .Type = SingleUseForwardLabel::InstType::ADR }); - constexpr uint32_t Op = 0b0001'0000 << 24; - DataProcessing_PCRel_Imm(Op, rd, 0); - } - - void adr(FEXCore::ARMEmitter::Register rd, BiDirectionalLabel *Label) { - if (Label->Backward.Location) { - adr(rd, &Label->Backward); - } - else { - adr(rd, &Label->Forward); - } - } - - void adrp(FEXCore::ARMEmitter::Register rd, uint32_t Imm) { - constexpr uint32_t Op = 0b1001'0000 << 24; - DataProcessing_PCRel_Imm(Op, rd, Imm); - } - - void adrp(FEXCore::ARMEmitter::Register rd, BackwardLabel const* Label) { - int64_t Imm = reinterpret_cast(Label->Location) - (GetCursorAddress() & ~0xFFFLL); - LOGMAN_THROW_A_FMT(IsADRPRange(Imm) && IsADRPAligned(Imm), "Unscaled offset too large"); - - constexpr uint32_t Op = 0b1001'0000 << 24; - DataProcessing_PCRel_Imm(Op, rd, Imm); - } - template - requires (std::is_same_v || std::is_same_v) - void adrp(FEXCore::ARMEmitter::Register rd, LabelType *Label) { - AddLocationToLabel(Label, SingleUseForwardLabel{ .Location = GetCursorAddress(), .Type = SingleUseForwardLabel::InstType::ADRP }); - constexpr uint32_t Op = 0b1001'0000 << 24; - DataProcessing_PCRel_Imm(Op, rd, 0); - } - - void adrp(FEXCore::ARMEmitter::Register rd, BiDirectionalLabel *Label) { - if (Label->Backward.Location) { - adrp(rd, &Label->Backward); - } - else { - adrp(rd, &Label->Forward); - } - } - - void LongAddressGen(FEXCore::ARMEmitter::Register rd, BackwardLabel const* Label) { - int64_t Imm = reinterpret_cast(Label->Location) - (GetCursorAddress()); - if (IsADRRange(Imm)) { - // If the range is in ADR range then we can just use ADR. - adr(rd, Label); - } - else if (IsADRPRange(Imm)) { - int64_t ADRPImm = (reinterpret_cast(Label->Location) & ~0xFFFLL) - - (GetCursorAddress() & ~0xFFFLL); - - // If the range is in the ADRP range then we can use ADRP. - bool NeedsOffset = !IsADRPAligned(reinterpret_cast(Label->Location)); - uint64_t AlignedOffset = reinterpret_cast(Label->Location) & 0xFFFULL; - - // First emit ADRP - adrp(rd, ADRPImm >> 12); - - if (NeedsOffset) { - // Now even an add - add(ARMEmitter::Size::i64Bit, rd, rd, AlignedOffset); - } - } - else { - LOGMAN_MSG_A_FMT("Unscaled offset too large"); - FEX_UNREACHABLE; - } - } - void LongAddressGen(FEXCore::ARMEmitter::Register rd, ForwardLabel* Label) { - Label->Insts.emplace_back(SingleUseForwardLabel{ .Location = GetCursorAddress(), .Type = SingleUseForwardLabel::InstType::LONG_ADDRESS_GEN }); - // Emit a register index and a nop. These will be backpatched. - dc32(rd.Idx()); - nop(); - } - - void LongAddressGen(FEXCore::ARMEmitter::Register rd, BiDirectionalLabel *Label) { - if (Label->Backward.Location) { - LongAddressGen(rd, &Label->Backward); - } - else { - LongAddressGen(rd, &Label->Forward); - } - } - - // Add/subtract immediate - void add(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, uint32_t Imm, bool LSL12 = false) { - constexpr uint32_t Op = 0b0001'0001'0 << 23; - DataProcessing_AddSub_Imm(Op, s, rd, rn, Imm, LSL12); - } - - void adds(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, uint32_t Imm, bool LSL12 = false) { - constexpr uint32_t Op = 0b0011'0001'0 << 23; - DataProcessing_AddSub_Imm(Op, s, rd, rn, Imm, LSL12); - } - void cmn(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rn, uint32_t Imm, bool LSL12 = false) { - adds(s, FEXCore::ARMEmitter::Reg::zr, rn, Imm, LSL12); - } - void sub(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, uint32_t Imm, bool LSL12 = false) { - constexpr uint32_t Op = 0b0101'0001'0 << 23; - DataProcessing_AddSub_Imm(Op, s, rd, rn, Imm, LSL12); - } - - void cmp(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rn, uint32_t Imm, bool LSL12 = false) { - constexpr uint32_t Op = 0b0111'0001'0 << 23; - DataProcessing_AddSub_Imm(Op, s, FEXCore::ARMEmitter::Reg::rsp, rn, Imm, LSL12); - } - - void subs(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, uint32_t Imm, bool LSL12 = false) { - constexpr uint32_t Op = 0b0111'0001'0 << 23; - DataProcessing_AddSub_Imm(Op, s, rd, rn, Imm, LSL12); - } - - // Min/max immediate - void smax(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, int64_t Imm) { - LOGMAN_THROW_A_FMT(Imm >= -128 && Imm <= 127, "{} Immediate too large", __func__); - MinMaxImmediate(0b0000, s, rd, rn, Imm); - } - - void umax(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, uint64_t Imm) { - LOGMAN_THROW_A_FMT(Imm <= 255, "{} Immediate too large", __func__); - MinMaxImmediate(0b0001, s, rd, rn, Imm); - } - - void smin(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, int64_t Imm) { - LOGMAN_THROW_A_FMT(Imm >= -128 && Imm <= 127, "{} Immediate too large", __func__); - MinMaxImmediate(0b0010, s, rd, rn, Imm); - } - - void umin(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, uint64_t Imm) { - LOGMAN_THROW_A_FMT(Imm <= 255, "{} Immediate too large", __func__); - MinMaxImmediate(0b0011, s, rd, rn, Imm); - } - - // Logical immediate - void and_(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, uint64_t Imm) { - uint32_t n, immr, imms; - [[maybe_unused]] const auto IsImm = IsImmLogical(Imm, - RegSizeInBits(s), - &n, - &imms, - &immr); - LOGMAN_THROW_A_FMT(IsImm, "Couldn't encode immediate to logical op"); - and_(s, rd, rn, n, immr, imms); - } - - void bic(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, uint64_t Imm) { - and_(s, rd, rn, ~Imm); - } - - void ands(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, uint64_t Imm) { - uint32_t n, immr, imms; - [[maybe_unused]] const auto IsImm = IsImmLogical(Imm, - RegSizeInBits(s), - &n, - &imms, - &immr); - LOGMAN_THROW_A_FMT(IsImm, "Couldn't encode immediate to logical op"); - ands(s, rd, rn, n, immr, imms); - } - - void bics(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, uint64_t Imm) { - ands(s, rd, rn, ~Imm); - } - - void orr(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, uint64_t Imm) { - uint32_t n, immr, imms; - [[maybe_unused]] const auto IsImm = IsImmLogical(Imm, - RegSizeInBits(s), - &n, - &imms, - &immr); - LOGMAN_THROW_A_FMT(IsImm, "Couldn't encode immediate to logical op"); - orr(s, rd, rn, n, immr, imms); - } - - void eor(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, uint64_t Imm) { - uint32_t n, immr, imms; - [[maybe_unused]] const auto IsImm = IsImmLogical(Imm, - RegSizeInBits(s), - &n, - &imms, - &immr); - LOGMAN_THROW_A_FMT(IsImm, "Couldn't encode immediate to logical op"); - eor(s, rd, rn, n, immr, imms); - } - - void tst(ARMEmitter::Size s, Register rn, uint64_t imm) { - ands(s, Reg::zr, rn, imm); - } - - // Move wide immediate - void movn(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, uint32_t Imm, uint32_t Offset = 0) { - LOGMAN_THROW_A_FMT((Imm & 0xFFFF0000U) == 0, "Upper bits of move wide not valid"); - LOGMAN_THROW_A_FMT((Offset % 16) == 0, "Offset must be 16bit aligned"); - - constexpr uint32_t Op = 0b001'0010'100 << 21; - DataProcessing_MoveWide(Op, s, rd, Imm, Offset >> 4); - } - void mov(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, uint32_t Imm) { - movz(s, rd, Imm, 0); - } - void mov(FEXCore::ARMEmitter::XRegister rd, uint32_t Imm) { - movz(FEXCore::ARMEmitter::Size::i64Bit, rd.R(), Imm, 0); - } - void mov(FEXCore::ARMEmitter::WRegister rd, uint32_t Imm) { - movz(FEXCore::ARMEmitter::Size::i32Bit, rd.R(), Imm, 0); - } - - void movz(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, uint32_t Imm, uint32_t Offset = 0) { - LOGMAN_THROW_A_FMT((Imm & 0xFFFF0000U) == 0, "Upper bits of move wide not valid"); - LOGMAN_THROW_A_FMT((Offset % 16) == 0, "Offset must be 16bit aligned"); - - constexpr uint32_t Op = 0b101'0010'100 << 21; - DataProcessing_MoveWide(Op, s, rd, Imm, Offset >> 4); - } - void movk(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, uint32_t Imm, uint32_t Offset = 0) { - LOGMAN_THROW_A_FMT((Imm & 0xFFFF0000U) == 0, "Upper bits of move wide not valid"); - LOGMAN_THROW_A_FMT((Offset % 16) == 0, "Offset must be 16bit aligned"); - - constexpr uint32_t Op = 0b111'0010'100 << 21; - DataProcessing_MoveWide(Op, s, rd, Imm, Offset >> 4); - } - - void movn(FEXCore::ARMEmitter::XRegister rd, uint32_t Imm, uint32_t Offset = 0) { - movn(FEXCore::ARMEmitter::Size::i64Bit, rd.R(), Imm, Offset); - } - void movz(FEXCore::ARMEmitter::XRegister rd, uint32_t Imm, uint32_t Offset = 0) { - movz(FEXCore::ARMEmitter::Size::i64Bit, rd.R(), Imm, Offset); - } - void movk(FEXCore::ARMEmitter::XRegister rd, uint32_t Imm, uint32_t Offset = 0) { - movk(FEXCore::ARMEmitter::Size::i64Bit, rd.R(), Imm, Offset); - } - void movn(FEXCore::ARMEmitter::WRegister rd, uint32_t Imm, uint32_t Offset = 0) { - movn(FEXCore::ARMEmitter::Size::i32Bit, rd.R(), Imm, Offset); - } - void movz(FEXCore::ARMEmitter::WRegister rd, uint32_t Imm, uint32_t Offset = 0) { - movz(FEXCore::ARMEmitter::Size::i32Bit, rd.R(), Imm, Offset); - } - void movk(FEXCore::ARMEmitter::WRegister rd, uint32_t Imm, uint32_t Offset = 0) { - movk(FEXCore::ARMEmitter::Size::i32Bit, rd.R(), Imm, Offset); - } - - // Bitfield - void sxtb(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn) { - sbfm(s, rd, rn, 0, 7); - } - void sxth(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn) { - sbfm(s, rd, rn, 0, 15); - } - void sxtw(FEXCore::ARMEmitter::XRegister rd, FEXCore::ARMEmitter::WRegister rn) { - sbfm(ARMEmitter::Size::i64Bit, rd, rn.X(), 0, 31); - } - void sbfx(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, uint32_t lsb, uint32_t width) { - LOGMAN_THROW_A_FMT(width > 0, "sbfx needs width > 0"); - LOGMAN_THROW_A_FMT((lsb + width) <= RegSizeInBits(s), "Tried to sbfx a region larger than the register"); - sbfm(s, rd, rn, lsb, lsb + width - 1); - } - void sbfiz(ARMEmitter::Size s, Register rd, Register rn, uint32_t lsb, uint32_t width) { - xbfiz_helper(true, s, rd, rn, lsb, width); - } - void asr(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, uint32_t shift) { - LOGMAN_THROW_A_FMT(shift <= RegSizeInBits(s), "Tried to asr a region larger than the register"); - sbfm(s, rd, rn, shift, RegSizeInBits(s) - 1); - } - - void uxtb(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn) { - ubfm(s, rd, rn, 0, 7); - } - void uxth(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn) { - ubfm(s, rd, rn, 0, 15); - } - void uxtw(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn) { - ubfm(s, rd, rn, 0, 31); - } - - void ubfm(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, uint32_t immr, uint32_t imms) { - constexpr uint32_t Op = 0b0101'0011'00 << 22; - DataProcessing_Logical_Imm(Op, s, rd, rn, s == ARMEmitter::Size::i64Bit, immr, imms); - } - - void ubfiz(ARMEmitter::Size s, Register rd, Register rn, uint32_t lsb, uint32_t width) { - xbfiz_helper(false, s, rd, rn, lsb, width); - } - - void lsl(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, uint32_t shift) { - const auto RegSize = RegSizeInBits(s); - LOGMAN_THROW_A_FMT(shift < RegSize, "Tried to lsl a region larger than the register"); - ubfm(s, rd, rn, (RegSize - shift) % RegSize, RegSize - shift - 1); - } - void lsr(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, uint32_t shift) { - const auto RegSize = RegSizeInBits(s); - LOGMAN_THROW_A_FMT(shift < RegSize, "Tried to lsr a region larger than the register"); - ubfm(s, rd, rn, shift, RegSize - 1); - } - void ubfx(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, uint32_t lsb, uint32_t width) { - LOGMAN_THROW_A_FMT(width > 0, "ubfx needs width > 0"); - LOGMAN_THROW_A_FMT((lsb + width) <= RegSizeInBits(s), "Tried to ubfx a region larger than the register"); - ubfm(s, rd, rn, lsb, lsb + width - 1); - } - - void bfi(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, uint32_t lsb, uint32_t width) { - const auto RegSize = RegSizeInBits(s); - LOGMAN_THROW_A_FMT(width > 0, "bfc/bfi needs width > 0"); - LOGMAN_THROW_A_FMT((lsb + width) <= RegSize, "Tried to bfc/bfi a region larger than the register"); - bfm(s, rd, rn, (RegSize - lsb) & (RegSize - 1), width - 1); - } - void bfc(ARMEmitter::Size s, Register rd, uint32_t lsb, uint32_t width) { - bfi(s, rd, Reg::zr, lsb, width); - } - void bfxil(ARMEmitter::Size s, Register rd, Register rn, uint32_t lsb, uint32_t width) { - [[maybe_unused]] const auto reg_size_bits = RegSizeInBits(s); - const auto lsb_p_width = lsb + width; - - LOGMAN_THROW_A_FMT(width >= 1, "bfxil needs width >= 1"); - LOGMAN_THROW_A_FMT(lsb_p_width <= reg_size_bits, "bfxil lsb + width ({}) must be <= {}. lsb={}, width={}", - lsb_p_width, reg_size_bits, lsb, width); - - bfm(s, rd, rn, lsb, lsb_p_width - 1); - } - - // Extract - void extr(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, uint32_t Imm) { - constexpr uint32_t Op = 0b001'0011'100 << 21; - LOGMAN_THROW_A_FMT(Imm < RegSizeInBits(s), "Tried to extr a region larger than the register"); - DataProcessing_Extract(Op, s, rd, rn, rm, Imm); - } - - void ror(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, uint32_t Imm) { - extr(s, rd, rn, rn, Imm); - } - - // Data processing - 2 source - void udiv(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm) { - constexpr uint32_t Op = (0b001'1010'110U << 21) | - (0b0000'10U << 10); - DataProcessing_2Source(Op, s, rd, rn, rm); - } - void sdiv(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm) { - constexpr uint32_t Op = (0b001'1010'110U << 21) | - (0b0000'11U << 10); - DataProcessing_2Source(Op, s, rd, rn, rm); - } - - void lslv(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm) { - constexpr uint32_t Op = (0b001'1010'110U << 21) | - (0b0010'00U << 10); - DataProcessing_2Source(Op, s, rd, rn, rm); - } - void lsrv(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm) { - constexpr uint32_t Op = (0b001'1010'110U << 21) | - (0b0010'01U << 10); - DataProcessing_2Source(Op, s, rd, rn, rm); - } - void asrv(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm) { - constexpr uint32_t Op = (0b001'1010'110U << 21) | - (0b0010'10U << 10); - DataProcessing_2Source(Op, s, rd, rn, rm); - } - void rorv(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm) { - constexpr uint32_t Op = (0b001'1010'110U << 21) | - (0b0010'11U << 10); - DataProcessing_2Source(Op, s, rd, rn, rm); - } - void crc32b(FEXCore::ARMEmitter::WRegister rd, FEXCore::ARMEmitter::WRegister rn, FEXCore::ARMEmitter::WRegister rm) { - constexpr uint32_t Op = (0b001'1010'110U << 21) | - (0b0100'00U << 10); - DataProcessing_2Source(Op, ARMEmitter::Size::i32Bit, rd, rn, rm); - } - void crc32h(FEXCore::ARMEmitter::WRegister rd, FEXCore::ARMEmitter::WRegister rn, FEXCore::ARMEmitter::WRegister rm) { - constexpr uint32_t Op = (0b001'1010'110U << 21) | - (0b0100'01U << 10); - DataProcessing_2Source(Op, ARMEmitter::Size::i32Bit, rd, rn, rm); - } - void crc32w(FEXCore::ARMEmitter::WRegister rd, FEXCore::ARMEmitter::WRegister rn, FEXCore::ARMEmitter::WRegister rm) { - constexpr uint32_t Op = (0b001'1010'110U << 21) | - (0b0100'10U << 10); - DataProcessing_2Source(Op, ARMEmitter::Size::i32Bit, rd, rn, rm); - } - void crc32cb(FEXCore::ARMEmitter::WRegister rd, FEXCore::ARMEmitter::WRegister rn, FEXCore::ARMEmitter::WRegister rm) { - constexpr uint32_t Op = (0b001'1010'110U << 21) | - (0b0101'00U << 10); - DataProcessing_2Source(Op, ARMEmitter::Size::i32Bit, rd, rn, rm); - } - void crc32ch(FEXCore::ARMEmitter::WRegister rd, FEXCore::ARMEmitter::WRegister rn, FEXCore::ARMEmitter::WRegister rm) { - constexpr uint32_t Op = (0b001'1010'110U << 21) | - (0b0101'01U << 10); - DataProcessing_2Source(Op, ARMEmitter::Size::i32Bit, rd, rn, rm); - } - void crc32cw(FEXCore::ARMEmitter::WRegister rd, FEXCore::ARMEmitter::WRegister rn, FEXCore::ARMEmitter::WRegister rm) { - constexpr uint32_t Op = (0b001'1010'110U << 21) | - (0b0101'10U << 10); - DataProcessing_2Source(Op, ARMEmitter::Size::i32Bit, rd, rn, rm); - } - void smax(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm) { - constexpr uint32_t Op = (0b001'1010'110U << 21) | - (0b0110'00U << 10); - DataProcessing_2Source(Op, s, rd, rn, rm); - } - void umax(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm) { - constexpr uint32_t Op = (0b001'1010'110U << 21) | - (0b0110'01U << 10); - DataProcessing_2Source(Op, s, rd, rn, rm); - } - void smin(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm) { - constexpr uint32_t Op = (0b001'1010'110U << 21) | - (0b0110'10U << 10); - DataProcessing_2Source(Op, s, rd, rn, rm); - } - void umin(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm) { - constexpr uint32_t Op = (0b001'1010'110U << 21) | - (0b0110'11U << 10); - DataProcessing_2Source(Op, s, rd, rn, rm); - } - void subp(FEXCore::ARMEmitter::XRegister rd, FEXCore::ARMEmitter::XRegister rn, FEXCore::ARMEmitter::XRegister rm) { - constexpr uint32_t Op = (0b001'1010'110U << 21) | - (0b0000'00U << 10); - DataProcessing_2Source(Op, FEXCore::ARMEmitter::Size::i64Bit, rd, rn, rm); - } - void irg(FEXCore::ARMEmitter::XRegister rd, FEXCore::ARMEmitter::XRegister rn, FEXCore::ARMEmitter::XRegister rm) { - constexpr uint32_t Op = (0b001'1010'110U << 21) | - (0b0001'00U << 10); - DataProcessing_2Source(Op, FEXCore::ARMEmitter::Size::i64Bit, rd, rn, rm); - } - void gmi(FEXCore::ARMEmitter::XRegister rd, FEXCore::ARMEmitter::XRegister rn, FEXCore::ARMEmitter::XRegister rm) { - constexpr uint32_t Op = (0b001'1010'110U << 21) | - (0b0001'01U << 10); - DataProcessing_2Source(Op, FEXCore::ARMEmitter::Size::i64Bit, rd, rn, rm); - } - void pacga(FEXCore::ARMEmitter::XRegister rd, FEXCore::ARMEmitter::XRegister rn, FEXCore::ARMEmitter::XRegister rm) { - constexpr uint32_t Op = (0b001'1010'110U << 21) | - (0b0011'00U << 10); - DataProcessing_2Source(Op, FEXCore::ARMEmitter::Size::i64Bit, rd, rn, rm); - } - void crc32x(FEXCore::ARMEmitter::XRegister rd, FEXCore::ARMEmitter::XRegister rn, FEXCore::ARMEmitter::XRegister rm) { - constexpr uint32_t Op = (0b001'1010'110U << 21) | - (0b0100'11U << 10); - DataProcessing_2Source(Op, FEXCore::ARMEmitter::Size::i64Bit, rd, rn, rm); - } - void crc32cx(FEXCore::ARMEmitter::XRegister rd, FEXCore::ARMEmitter::XRegister rn, FEXCore::ARMEmitter::XRegister rm) { - constexpr uint32_t Op = (0b001'1010'110U << 21) | - (0b0101'11U << 10); - DataProcessing_2Source(Op, FEXCore::ARMEmitter::Size::i64Bit, rd, rn, rm); - } - void subps(FEXCore::ARMEmitter::XRegister rd, FEXCore::ARMEmitter::XRegister rn, FEXCore::ARMEmitter::XRegister rm) { - constexpr uint32_t Op = (0b011'1010'110U << 21) | - (0b0000'00U << 10); - DataProcessing_2Source(Op, FEXCore::ARMEmitter::Size::i64Bit, rd, rn, rm); - } - - // Data processing - 1 source - void rbit(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn) { - constexpr uint32_t Op = (0b101'1010'110U << 21) | - (0b0'0000U << 16) | - (0b0000'00U << 10); - DataProcessing_1Source(Op, s, rd, rn); - } - void rev16(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn) { - constexpr uint32_t Op = (0b101'1010'110U << 21) | - (0b0'0000U << 16) | - (0b0000'01U << 10); - DataProcessing_1Source(Op, s, rd, rn); - } - void rev(FEXCore::ARMEmitter::WRegister rd, FEXCore::ARMEmitter::WRegister rn) { - constexpr uint32_t Op = (0b101'1010'110U << 21) | - (0b0'0000U << 16) | - (0b0000'10U << 10); - DataProcessing_1Source(Op, FEXCore::ARMEmitter::Size::i32Bit, rd, rn); - } - void rev32(FEXCore::ARMEmitter::XRegister rd, FEXCore::ARMEmitter::XRegister rn) { - constexpr uint32_t Op = (0b101'1010'110U << 21) | - (0b0'0000U << 16) | - (0b0000'10U << 10); - DataProcessing_1Source(Op, FEXCore::ARMEmitter::Size::i64Bit, rd, rn); - } - void clz(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn) { - constexpr uint32_t Op = (0b101'1010'110U << 21) | - (0b0'0000U << 16) | - (0b0001'00U << 10); - DataProcessing_1Source(Op, s, rd, rn); - } - void cls(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn) { - constexpr uint32_t Op = (0b101'1010'110U << 21) | - (0b0'0000U << 16) | - (0b0001'01U << 10); - DataProcessing_1Source(Op, s, rd, rn); - } - void rev(FEXCore::ARMEmitter::XRegister rd, FEXCore::ARMEmitter::XRegister rn) { - constexpr uint32_t Op = (0b101'1010'110U << 21) | - (0b0'0000U << 16) | - (0b0000'11U << 10); - DataProcessing_1Source(Op, FEXCore::ARMEmitter::Size::i64Bit, rd, rn); - } - void rev(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn) { - uint32_t Op = (0b101'1010'110U << 21) | - (0b0'0000U << 16) | - (0b0000'10U << 10) | - (s == ARMEmitter::Size::i64Bit ? (1U << 10) : 0); - DataProcessing_1Source(Op, s, rd, rn); - } - void ctz(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn) { - constexpr uint32_t Op = (0b101'1010'110U << 21) | - (0b0'0000U << 16) | - (0b0001'10U << 10); - DataProcessing_1Source(Op, s, rd, rn); - } - void cnt(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn) { - constexpr uint32_t Op = (0b101'1010'110U << 21) | - (0b0'0000U << 16) | - (0b0001'11U << 10); - DataProcessing_1Source(Op, s, rd, rn); - } - void abs(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn) { - constexpr uint32_t Op = (0b101'1010'110U << 21) | - (0b0'0000U << 16) | - (0b0010'00U << 10); - DataProcessing_1Source(Op, s, rd, rn); - } - - // TODO: PAUTH - - // Logical - shifted register - void mov(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn) { - orr(s, rd, FEXCore::ARMEmitter::Reg::zr, rn, ARMEmitter::ShiftType::LSL, 0); - } - void mov(FEXCore::ARMEmitter::XRegister rd, FEXCore::ARMEmitter::XRegister rn) { - orr(FEXCore::ARMEmitter::Size::i64Bit, rd.R(), FEXCore::ARMEmitter::Reg::zr, rn.R(), ARMEmitter::ShiftType::LSL, 0); - } - void mov(FEXCore::ARMEmitter::WRegister rd, FEXCore::ARMEmitter::WRegister rn) { - orr(FEXCore::ARMEmitter::Size::i32Bit, rd.R(), FEXCore::ARMEmitter::Reg::zr, rn.R(), ARMEmitter::ShiftType::LSL, 0); - } - - void mvn(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::ShiftType Shift = FEXCore::ARMEmitter::ShiftType::LSL, uint32_t amt = 0) { - orn(s, rd, FEXCore::ARMEmitter::Reg::zr, rn, Shift, amt); - } - - void and_(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::ShiftType Shift = FEXCore::ARMEmitter::ShiftType::LSL, uint32_t amt = 0) { - constexpr uint32_t Op = 0b000'1010'000U << 21; - DataProcessing_Shifted_Reg(Op, s, rd, rn, rm, Shift, amt); - } - void ands(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::ShiftType Shift = FEXCore::ARMEmitter::ShiftType::LSL, uint32_t amt = 0) { - constexpr uint32_t Op = 0b110'1010'000U << 21; - DataProcessing_Shifted_Reg(Op, s, rd, rn, rm, Shift, amt); - } - void bic(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::ShiftType Shift = FEXCore::ARMEmitter::ShiftType::LSL, uint32_t amt = 0) { - constexpr uint32_t Op = 0b000'1010'001U << 21; - DataProcessing_Shifted_Reg(Op, s, rd, rn, rm, Shift, amt); - } - void bics(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::ShiftType Shift = FEXCore::ARMEmitter::ShiftType::LSL, uint32_t amt = 0) { - constexpr uint32_t Op = 0b110'1010'001U << 21; - DataProcessing_Shifted_Reg(Op, s, rd, rn, rm, Shift, amt); - } - void orr(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::ShiftType Shift = FEXCore::ARMEmitter::ShiftType::LSL, uint32_t amt = 0) { - constexpr uint32_t Op = 0b010'1010'000U << 21; - DataProcessing_Shifted_Reg(Op, s, rd, rn, rm, Shift, amt); - } - void tst(ARMEmitter::Size s, Register rn, Register rm, ShiftType shift = ShiftType::LSL, uint32_t amt = 0) { - ands(s, Reg::zr, rn, rm, shift, amt); - } - - void orn(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::ShiftType Shift = FEXCore::ARMEmitter::ShiftType::LSL, uint32_t amt = 0) { - constexpr uint32_t Op = 0b010'1010'001U << 21; - DataProcessing_Shifted_Reg(Op, s, rd, rn, rm, Shift, amt); - } - void eor(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::ShiftType Shift = FEXCore::ARMEmitter::ShiftType::LSL, uint32_t amt = 0) { - constexpr uint32_t Op = 0b100'1010'000U << 21; - DataProcessing_Shifted_Reg(Op, s, rd, rn, rm, Shift, amt); - } - void eon(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::ShiftType Shift = FEXCore::ARMEmitter::ShiftType::LSL, uint32_t amt = 0) { - constexpr uint32_t Op = 0b100'1010'001U << 21; - DataProcessing_Shifted_Reg(Op, s, rd, rn, rm, Shift, amt); - } - - // AddSub - shifted register - void add(FEXCore::ARMEmitter::XRegister rd, FEXCore::ARMEmitter::XRegister rn, FEXCore::ARMEmitter::XRegister rm, FEXCore::ARMEmitter::ShiftType Shift = FEXCore::ARMEmitter::ShiftType::LSL, uint32_t amt = 0) { - add(ARMEmitter::Size::i64Bit, rd.R(), rn.R(), rm.R(), Shift, amt); - } - void adds(FEXCore::ARMEmitter::XRegister rd, FEXCore::ARMEmitter::XRegister rn, FEXCore::ARMEmitter::XRegister rm, FEXCore::ARMEmitter::ShiftType Shift = FEXCore::ARMEmitter::ShiftType::LSL, uint32_t amt = 0) { - adds(ARMEmitter::Size::i64Bit, rd.R(), rn.R(), rm.R(), Shift, amt); - } - void cmn(FEXCore::ARMEmitter::XRegister rn, FEXCore::ARMEmitter::XRegister rm, FEXCore::ARMEmitter::ShiftType Shift = FEXCore::ARMEmitter::ShiftType::LSL, uint32_t amt = 0) { - adds(ARMEmitter::Size::i64Bit, FEXCore::ARMEmitter::XReg::zr, rn.R(), rm.R(), Shift, amt); - } - void sub(FEXCore::ARMEmitter::XRegister rd, FEXCore::ARMEmitter::XRegister rn, FEXCore::ARMEmitter::XRegister rm, FEXCore::ARMEmitter::ShiftType Shift = FEXCore::ARMEmitter::ShiftType::LSL, uint32_t amt = 0) { - sub(ARMEmitter::Size::i64Bit, rd.R(), rn.R(), rm.R(), Shift, amt); - } - void neg(FEXCore::ARMEmitter::XRegister rd, FEXCore::ARMEmitter::XRegister rm, FEXCore::ARMEmitter::ShiftType Shift = FEXCore::ARMEmitter::ShiftType::LSL, uint32_t amt = 0) { - sub(rd, FEXCore::ARMEmitter::XReg::zr, rm, Shift, amt); - } - void cmp(FEXCore::ARMEmitter::XRegister rn, FEXCore::ARMEmitter::XRegister rm, FEXCore::ARMEmitter::ShiftType Shift = FEXCore::ARMEmitter::ShiftType::LSL, uint32_t amt = 0) { - subs(ARMEmitter::Size::i64Bit, FEXCore::ARMEmitter::Reg::rsp, rn.R(), rm.R(), Shift, amt); - } - void subs(FEXCore::ARMEmitter::XRegister rd, FEXCore::ARMEmitter::XRegister rn, FEXCore::ARMEmitter::XRegister rm, FEXCore::ARMEmitter::ShiftType Shift = FEXCore::ARMEmitter::ShiftType::LSL, uint32_t amt = 0) { - subs(ARMEmitter::Size::i64Bit, rd.R(), rn.R(), rm.R(), Shift, amt); - } - void negs(FEXCore::ARMEmitter::XRegister rd, FEXCore::ARMEmitter::XRegister rm, FEXCore::ARMEmitter::ShiftType Shift = FEXCore::ARMEmitter::ShiftType::LSL, uint32_t amt = 0) { - subs(rd, FEXCore::ARMEmitter::XReg::zr, rm, Shift, amt); - } - - void add(FEXCore::ARMEmitter::WRegister rd, FEXCore::ARMEmitter::WRegister rn, FEXCore::ARMEmitter::WRegister rm, FEXCore::ARMEmitter::ShiftType Shift = FEXCore::ARMEmitter::ShiftType::LSL, uint32_t amt = 0) { - add(ARMEmitter::Size::i32Bit, rd.R(), rn.R(), rm.R(), Shift, amt); - } - void adds(FEXCore::ARMEmitter::WRegister rd, FEXCore::ARMEmitter::WRegister rn, FEXCore::ARMEmitter::WRegister rm, FEXCore::ARMEmitter::ShiftType Shift = FEXCore::ARMEmitter::ShiftType::LSL, uint32_t amt = 0) { - adds(ARMEmitter::Size::i32Bit, rd.R(), rn.R(), rm.R(), Shift, amt); - } - void cmn(FEXCore::ARMEmitter::WRegister rn, FEXCore::ARMEmitter::WRegister rm, FEXCore::ARMEmitter::ShiftType Shift = FEXCore::ARMEmitter::ShiftType::LSL, uint32_t amt = 0) { - adds(ARMEmitter::Size::i32Bit, FEXCore::ARMEmitter::WReg::zr, rn.R(), rm.R(), Shift, amt); - } - void sub(FEXCore::ARMEmitter::WRegister rd, FEXCore::ARMEmitter::WRegister rn, FEXCore::ARMEmitter::WRegister rm, FEXCore::ARMEmitter::ShiftType Shift = FEXCore::ARMEmitter::ShiftType::LSL, uint32_t amt = 0) { - sub(ARMEmitter::Size::i32Bit, rd.R(), rn.R(), rm.R(), Shift, amt); - } - void neg(FEXCore::ARMEmitter::WRegister rd, FEXCore::ARMEmitter::WRegister rm, FEXCore::ARMEmitter::ShiftType Shift = FEXCore::ARMEmitter::ShiftType::LSL, uint32_t amt = 0) { - sub(rd, FEXCore::ARMEmitter::WReg::zr, rm, Shift, amt); - } - void cmp(FEXCore::ARMEmitter::WRegister rn, FEXCore::ARMEmitter::WRegister rm, FEXCore::ARMEmitter::ShiftType Shift = FEXCore::ARMEmitter::ShiftType::LSL, uint32_t amt = 0) { - subs(ARMEmitter::Size::i32Bit, FEXCore::ARMEmitter::Reg::rsp, rn.R(), rm.R(), Shift, amt); - } - void subs(FEXCore::ARMEmitter::WRegister rd, FEXCore::ARMEmitter::WRegister rn, FEXCore::ARMEmitter::WRegister rm, FEXCore::ARMEmitter::ShiftType Shift = FEXCore::ARMEmitter::ShiftType::LSL, uint32_t amt = 0) { - subs(ARMEmitter::Size::i32Bit, rd.R(), rn.R(), rm.R(), Shift, amt); - } - void negs(FEXCore::ARMEmitter::WRegister rd, FEXCore::ARMEmitter::WRegister rm, FEXCore::ARMEmitter::ShiftType Shift = FEXCore::ARMEmitter::ShiftType::LSL, uint32_t amt = 0) { - subs(rd, FEXCore::ARMEmitter::WReg::zr, rm, Shift, amt); - } - - void add(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::ShiftType Shift = FEXCore::ARMEmitter::ShiftType::LSL, uint32_t amt = 0) { - LOGMAN_THROW_AA_FMT(Shift != FEXCore::ARMEmitter::ShiftType::ROR, "Doesn't support ROR"); - constexpr uint32_t Op = 0b000'1011'000U << 21; - DataProcessing_Shifted_Reg(Op, s, rd, rn, rm, Shift, amt); - } - void adds(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::ShiftType Shift = FEXCore::ARMEmitter::ShiftType::LSL, uint32_t amt = 0) { - LOGMAN_THROW_AA_FMT(Shift != FEXCore::ARMEmitter::ShiftType::ROR, "Doesn't support ROR"); - constexpr uint32_t Op = 0b010'1011'000U << 21; - DataProcessing_Shifted_Reg(Op, s, rd, rn, rm, Shift, amt); - } - void cmn(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::ShiftType Shift = FEXCore::ARMEmitter::ShiftType::LSL, uint32_t amt = 0) { - adds(s, FEXCore::ARMEmitter::Reg::zr, rn, rm, Shift, amt); - } - void sub(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::ShiftType Shift = FEXCore::ARMEmitter::ShiftType::LSL, uint32_t amt = 0) { - LOGMAN_THROW_AA_FMT(Shift != FEXCore::ARMEmitter::ShiftType::ROR, "Doesn't support ROR"); - constexpr uint32_t Op = 0b100'1011'000U << 21; - DataProcessing_Shifted_Reg(Op, s, rd, rn, rm, Shift, amt); - } - void neg(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::ShiftType Shift = FEXCore::ARMEmitter::ShiftType::LSL, uint32_t amt = 0) { - sub(s, rd, FEXCore::ARMEmitter::Reg::zr, rm, Shift, amt); - } - void cmp(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::ShiftType Shift = FEXCore::ARMEmitter::ShiftType::LSL, uint32_t amt = 0) { - subs(s, FEXCore::ARMEmitter::Reg::zr, rn, rm, Shift, amt); - } - - void subs(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::ShiftType Shift = FEXCore::ARMEmitter::ShiftType::LSL, uint32_t amt = 0) { - LOGMAN_THROW_AA_FMT(Shift != FEXCore::ARMEmitter::ShiftType::ROR, "Doesn't support ROR"); - constexpr uint32_t Op = 0b110'1011'000U << 21; - DataProcessing_Shifted_Reg(Op, s, rd, rn, rm, Shift, amt); - } - void negs(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::ShiftType Shift = FEXCore::ARMEmitter::ShiftType::LSL, uint32_t amt = 0) { - subs(s, rd, FEXCore::ARMEmitter::Reg::zr, rm, Shift, amt); - } - - // AddSub - extended register - void add(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::ExtendedType Option, uint32_t Shift = 0) { - LOGMAN_THROW_AA_FMT(Shift <= 4, "Shift amount is too large"); - constexpr uint32_t Op = 0b000'1011'001U << 21; - DataProcessing_Extended_Reg(Op, s, rd, rn, rm, Option, Shift); - } - void adds(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::ExtendedType Option, uint32_t Shift = 0) { - constexpr uint32_t Op = 0b010'1011'001U << 21; - DataProcessing_Extended_Reg(Op, s, rd, rn, rm, Option, Shift); - } - void cmn(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::ExtendedType Option, uint32_t Shift = 0) { - adds(s, FEXCore::ARMEmitter::Reg::zr, rn, rm, Option, Shift); - } - void sub(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::ExtendedType Option, uint32_t Shift = 0) { - constexpr uint32_t Op = 0b100'1011'001U << 21; - DataProcessing_Extended_Reg(Op, s, rd, rn, rm, Option, Shift); - } - void subs(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::ExtendedType Option, uint32_t Shift = 0) { - constexpr uint32_t Op = 0b110'1011'001U << 21; - DataProcessing_Extended_Reg(Op, s, rd, rn, rm, Option, Shift); - } - void cmp(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::ExtendedType Option, uint32_t Shift = 0) { - constexpr uint32_t Op = 0b110'1011'001U << 21; - DataProcessing_Extended_Reg(Op, s, FEXCore::ARMEmitter::Reg::zr, rn, rm, Option, Shift); - } - - // AddSub - with carry - void adc(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm) { - constexpr uint32_t Op = 0b0001'1010'000U << 21; - DataProcessing_Extended_Reg(Op, s, rd, rn, rm, FEXCore::ARMEmitter::ExtendedType::UXTB, 0); - } - void adcs(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm) { - constexpr uint32_t Op = 0b0011'1010'000U << 21; - DataProcessing_Extended_Reg(Op, s, rd, rn, rm, FEXCore::ARMEmitter::ExtendedType::UXTB, 0); - } - void sbc(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm) { - constexpr uint32_t Op = 0b0101'1010'000U << 21; - DataProcessing_Extended_Reg(Op, s, rd, rn, rm, FEXCore::ARMEmitter::ExtendedType::UXTB, 0); - } - void sbcs(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm) { - constexpr uint32_t Op = 0b0111'1010'000U << 21; - DataProcessing_Extended_Reg(Op, s, rd, rn, rm, FEXCore::ARMEmitter::ExtendedType::UXTB, 0); - } - void ngc(ARMEmitter::Size s, Register rd, Register rm) { - sbc(s, rd, Reg::zr, rm); - } - void ngcs(ARMEmitter::Size s, Register rd, Register rm) { - sbcs(s, rd, Reg::zr, rm); - } - - // Rotate right into flags - void rmif(XRegister rn, uint32_t shift, uint32_t mask) { - LOGMAN_THROW_AA_FMT(shift <= 63, "Shift must be within 0-63. Shift: {}", shift); - LOGMAN_THROW_AA_FMT(mask <= 15, "Mask must be within 0-15. Mask: {}", mask); - - uint32_t Op = 0b1011'1010'0000'0000'0000'0100'0000'0000; - Op |= rn.Idx() << 5; - Op |= shift << 15; - Op |= mask; - - dc32(Op); - } - - // Evaluate into flags - void setf8(WRegister rn) { - constexpr uint32_t Op = 0b0011'1010'0000'0000'0000'1000'0000'1101; - EvaluateIntoFlags(Op, 0, rn); - } - void setf16(WRegister rn) { - constexpr uint32_t Op = 0b0011'1010'0000'0000'0000'1000'0000'1101; - EvaluateIntoFlags(Op, 1, rn); - } - - void cfinv() { - constexpr uint32_t Op = 0b1101'0101'0000'0000'0100'0000'0001'1111; - dc32(Op); - } - - void axflag() { - constexpr uint32_t Op = 0b1101'0101'0000'0000'0100'0000'0101'1111; - dc32(Op); - } - - void xaflag() { - constexpr uint32_t Op = 0b1101'0101'0000'0000'0100'0000'0011'1111; - dc32(Op); - } - - // Conditional compare - register - void ccmn(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::StatusFlags flags, FEXCore::ARMEmitter::Condition Cond) { - constexpr uint32_t Op = 0b0011'1010'010 << 21; - ConditionalCompare(Op, 0, 0b00, 0, s, rn, rm, flags, Cond); - } - void ccmp(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::StatusFlags flags, FEXCore::ARMEmitter::Condition Cond) { - constexpr uint32_t Op = 0b0011'1010'010 << 21; - ConditionalCompare(Op, 1, 0b00, 0, s, rn, rm, flags, Cond); - } - - // Conditional compare - immediate - void ccmn(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rn, uint32_t rm, FEXCore::ARMEmitter::StatusFlags flags, FEXCore::ARMEmitter::Condition Cond) { - LOGMAN_THROW_A_FMT((rm & ~0b1'1111) == 0, "Comparison imm too large"); - constexpr uint32_t Op = 0b0011'1010'010 << 21; - ConditionalCompare(Op, 0, 0b10, 0, s, rn, rm, flags, Cond); - } - void ccmp(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rn, uint32_t rm, FEXCore::ARMEmitter::StatusFlags flags, FEXCore::ARMEmitter::Condition Cond) { - LOGMAN_THROW_A_FMT((rm & ~0b1'1111) == 0, "Comparison imm too large"); - constexpr uint32_t Op = 0b0011'1010'010 << 21; - ConditionalCompare(Op, 1, 0b10, 0, s, rn, rm, flags, Cond); - } - - // Conditional select - void csel(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::Condition Cond) { - constexpr uint32_t Op = 0b0001'1010'100 << 21; - ConditionalCompare(Op, 0, 0b00, s, rd, rn, rm, Cond); - } - void cset(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Condition Cond) { - constexpr uint32_t Op = 0b0001'1010'100 << 21; - ConditionalCompare(Op, 0, 0b01, s, rd, FEXCore::ARMEmitter::Reg::zr, FEXCore::ARMEmitter::Reg::zr, static_cast(FEXCore::ToUnderlying(Cond) ^ FEXCore::ToUnderlying(FEXCore::ARMEmitter::Condition::CC_NE))); - } - void csinc(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::Condition Cond) { - constexpr uint32_t Op = 0b0001'1010'100 << 21; - ConditionalCompare(Op, 0, 0b01, s, rd, rn, rm, Cond); - } - void csinv(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::Condition Cond) { - constexpr uint32_t Op = 0b0001'1010'100 << 21; - ConditionalCompare(Op, 1, 0b00, s, rd, rn, rm, Cond); - } - void csneg(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::Condition Cond) { - constexpr uint32_t Op = 0b0001'1010'100 << 21; - ConditionalCompare(Op, 1, 0b01, s, rd, rn, rm, Cond); - } - void cneg(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Condition Cond) { - csneg(s, rd, rn, rn, InvertCondition(Cond)); - } - void cinc(ARMEmitter::Size s, Register rd, Register rn, Condition cond) { - csinc(s, rd, rn, rn, InvertCondition(cond)); - } - void cinv(ARMEmitter::Size s, Register rd, Register rn, Condition cond) { - csinv(s, rd, rn, rn, InvertCondition(cond)); - } - void csetm(ARMEmitter::Size s, Register rd, Condition cond) { - csinv(s, rd, Reg::zr, Reg::zr, InvertCondition(cond)); - } - - // Data processing - 3 source - void madd(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::Register ra) { - constexpr uint32_t Op = 0b001'1011'000U << 21; - DataProcessing_3Source(Op, 0, s, rd, rn, rm, ra); - } - void mul(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm) { - madd(s, rd, rn, rm, XReg::zr); - } - void msub(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::Register ra) { - constexpr uint32_t Op = 0b001'1011'000U << 21; - DataProcessing_3Source(Op, 1, s, rd, rn, rm, ra); - } - void mneg(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm) { - msub(s, rd, rn, rm, XReg::zr); - } - void smaddl(FEXCore::ARMEmitter::XRegister rd, FEXCore::ARMEmitter::WRegister rn, FEXCore::ARMEmitter::WRegister rm, FEXCore::ARMEmitter::XRegister ra) { - constexpr uint32_t Op = 0b001'1011'001U << 21; - DataProcessing_3Source(Op, 0, FEXCore::ARMEmitter::Size::i64Bit, rd, rn, rm, ra); - } - void smull(FEXCore::ARMEmitter::XRegister rd, FEXCore::ARMEmitter::WRegister rn, FEXCore::ARMEmitter::WRegister rm) { - smaddl(rd, rn, rm, XReg::zr); - } - void smsubl(FEXCore::ARMEmitter::XRegister rd, FEXCore::ARMEmitter::WRegister rn, FEXCore::ARMEmitter::WRegister rm, FEXCore::ARMEmitter::XRegister ra) { - constexpr uint32_t Op = 0b001'1011'001U << 21; - DataProcessing_3Source(Op, 1, FEXCore::ARMEmitter::Size::i64Bit, rd, rn, rm, ra); - } - void smnegl(FEXCore::ARMEmitter::XRegister rd, FEXCore::ARMEmitter::WRegister rn, FEXCore::ARMEmitter::WRegister rm) { - smsubl(rd, rn, rm, XReg::zr); - } - void smulh(FEXCore::ARMEmitter::XRegister rd, FEXCore::ARMEmitter::XRegister rn, FEXCore::ARMEmitter::XRegister rm) { - constexpr uint32_t Op = 0b001'1011'010U << 21; - DataProcessing_3Source(Op, 0, FEXCore::ARMEmitter::Size::i64Bit, rd, rn, rm, FEXCore::ARMEmitter::Reg::zr); - } - void umaddl(FEXCore::ARMEmitter::XRegister rd, FEXCore::ARMEmitter::WRegister rn, FEXCore::ARMEmitter::WRegister rm, FEXCore::ARMEmitter::XRegister ra) { - constexpr uint32_t Op = 0b001'1011'101U << 21; - DataProcessing_3Source(Op, 0, FEXCore::ARMEmitter::Size::i64Bit, rd, rn, rm, ra); - } - void umull(FEXCore::ARMEmitter::XRegister rd, FEXCore::ARMEmitter::WRegister rn, FEXCore::ARMEmitter::WRegister rm) { - umaddl(rd, rn, rm, XReg::zr); - } - void umsubl(FEXCore::ARMEmitter::XRegister rd, FEXCore::ARMEmitter::WRegister rn, FEXCore::ARMEmitter::WRegister rm, FEXCore::ARMEmitter::XRegister ra) { - constexpr uint32_t Op = 0b001'1011'101U << 21; - DataProcessing_3Source(Op, 1, FEXCore::ARMEmitter::Size::i64Bit, rd, rn, rm, ra); - } - void umnegl(FEXCore::ARMEmitter::XRegister rd, FEXCore::ARMEmitter::WRegister rn, FEXCore::ARMEmitter::WRegister rm) { - umsubl(rd, rn, rm, XReg::zr); - } - void umulh(FEXCore::ARMEmitter::XRegister rd, FEXCore::ARMEmitter::XRegister rn, FEXCore::ARMEmitter::XRegister rm) { - constexpr uint32_t Op = 0b001'1011'110U << 21; - DataProcessing_3Source(Op, 0, FEXCore::ARMEmitter::Size::i64Bit, rd, rn, rm, FEXCore::ARMEmitter::Reg::zr); - } - -private: - static constexpr Condition InvertCondition(Condition cond) { - // These behave as always, so it makes no sense to allow inverting these. - LOGMAN_THROW_AA_FMT(cond != Condition::CC_AL && cond != Condition::CC_NV, - "Cannot invert CC_AL or CC_NV"); - return static_cast(FEXCore::ToUnderlying(cond) ^ 1); - } - - void and_(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, uint32_t n, uint32_t immr, uint32_t imms) { - constexpr uint32_t Op = 0b001'0010'00 << 22; - DataProcessing_Logical_Imm(Op, s, rd, rn, n, immr, imms); - } - void ands(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, uint32_t n, uint32_t immr, uint32_t imms) { - constexpr uint32_t Op = 0b111'0010'00 << 22; - DataProcessing_Logical_Imm(Op, s, rd, rn, n, immr, imms); - } - void orr(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, uint32_t n, uint32_t immr, uint32_t imms) { - constexpr uint32_t Op = 0b011'0010'00 << 22; - DataProcessing_Logical_Imm(Op, s, rd, rn, n, immr, imms); - } - void eor(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, uint32_t n, uint32_t immr, uint32_t imms) { - constexpr uint32_t Op = 0b101'0010'00 << 22; - DataProcessing_Logical_Imm(Op, s, rd, rn, n, immr, imms); - } - - void sbfm(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, uint32_t immr, uint32_t imms) { - constexpr uint32_t Op = 0b0001'0011'00 << 22; - DataProcessing_Logical_Imm(Op, s, rd, rn, s == ARMEmitter::Size::i64Bit, immr, imms); - } - void bfm(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, uint32_t immr, uint32_t imms) { - constexpr uint32_t Op = 0b0011'0011'00 << 22; - DataProcessing_Logical_Imm(Op, s, rd, rn, s == ARMEmitter::Size::i64Bit, immr, imms); - } - // 4.1.64 - Data processing - Immediate - void DataProcessing_PCRel_Imm(uint32_t Op, FEXCore::ARMEmitter::Register rd, uint32_t Imm) { - // Ensure the immediate is masked. - Imm &= 0b1'1111'1111'1111'1111'1111U; - - uint32_t Instr = Op; - - Instr |= (Imm & 0b11) << 29; - Instr |= (Imm >> 2) << 5; - Instr |= Encode_rd(rd); - - dc32(Instr); - } - - void DataProcessing_AddSub_Imm(uint32_t Op, FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, uint32_t Imm, bool LSL12) { - bool TooLarge = (Imm & ~0b1111'1111'1111U) != 0; - if (TooLarge && !LSL12 && ((Imm >> 12) & ~0b1111'1111'1111U) == 0) { - // We can convert an immediate - TooLarge = false; - LSL12 = true; - Imm >>= 12; - } - LOGMAN_THROW_AA_FMT(TooLarge == false, "Imm amount too large: 0x{:x}", Imm); - - const uint32_t SF = s == FEXCore::ARMEmitter::Size::i64Bit ? (1U << 31) : 0; - - uint32_t Instr = Op; - - Instr |= SF; - Instr |= LSL12 << 22; - Instr |= Imm << 10; - Instr |= Encode_rn(rn); - Instr |= Encode_rd(rd); - - dc32(Instr); - } - - // Min/max immediate - void MinMaxImmediate(uint32_t opc, FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, uint64_t Imm) { - const uint32_t SF = s == FEXCore::ARMEmitter::Size::i64Bit ? (1U << 31) : 0; - - uint32_t Instr = 0b1'0001'11U << 22; - - Instr |= SF; - Instr |= opc << 18; - Instr |= (Imm & 0xFF) << 10; - Instr |= Encode_rn(rn); - Instr |= Encode_rd(rd); - - dc32(Instr); - } - - // Move Wide - void DataProcessing_MoveWide(uint32_t Op, FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, uint32_t Imm, uint32_t Offset) { - const uint32_t SF = s == FEXCore::ARMEmitter::Size::i64Bit ? (1U << 31) : 0; - - uint32_t Instr = Op; - - Instr |= SF; - Instr |= Imm << 5; - Instr |= Offset << 21; - Instr |= Encode_rd(rd); - - dc32(Instr); - } - - // Logical immediate - void DataProcessing_Logical_Imm(uint32_t Op, FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, uint32_t n, uint32_t immr, uint32_t imms) { - const uint32_t SF = s == FEXCore::ARMEmitter::Size::i64Bit ? (1U << 31) : 0; - - uint32_t Instr = Op; - - Instr |= SF; - Instr |= n << 22; - Instr |= immr << 16; - Instr |= imms << 10; - Instr |= Encode_rn(rn); - Instr |= Encode_rd(rd); - - dc32(Instr); - } - - void xbfiz_helper(bool is_signed, ARMEmitter::Size s, Register rd, Register rn, uint32_t lsb, uint32_t width) { - [[maybe_unused]] const auto lsb_p_width = lsb + width; - const auto reg_size_bits = RegSizeInBits(s); - - LOGMAN_THROW_AA_FMT(lsb_p_width <= reg_size_bits, "lsb + width ({}) must be <= {}. lsb={}, width={}", - lsb_p_width, reg_size_bits, lsb, width); - LOGMAN_THROW_AA_FMT(width >= 1, "xbfiz width must be >= 1"); - - const auto immr = (reg_size_bits - lsb) & (reg_size_bits - 1); - const auto imms = width - 1; - - if (is_signed) { - sbfm(s, rd, rn, immr, imms); - } else { - ubfm(s, rd, rn, immr, imms); - } - } - - void DataProcessing_Extract(uint32_t Op, FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, uint32_t Imm) { - const uint32_t SF = s == FEXCore::ARMEmitter::Size::i64Bit ? (1U << 31) : 0; - - // Current ARMv8 spec hardcodes SF == N for this class of instructions. - // Anythign else is undefined behaviour. - const uint32_t N = s == FEXCore::ARMEmitter::Size::i64Bit ? (1U << 22) : 0; - - uint32_t Instr = Op; - - Instr |= SF; - Instr |= N; - Instr |= Encode_rm(rm); - Instr |= Imm << 10; - Instr |= Encode_rn(rn); - Instr |= Encode_rd(rd); - - dc32(Instr); - } - - // Data-processing - 2 source - void DataProcessing_2Source(uint32_t Op, FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm) { - const uint32_t SF = s == FEXCore::ARMEmitter::Size::i64Bit ? (1U << 31) : 0; - - uint32_t Instr = Op; - - Instr |= SF; - Instr |= Encode_rm(rm); - Instr |= Encode_rn(rn); - Instr |= Encode_rd(rd); - - dc32(Instr); - } - - // Data processing - 1 source - template - void DataProcessing_1Source(uint32_t Op, FEXCore::ARMEmitter::Size s, T rd, T rn) { - const uint32_t SF = s == FEXCore::ARMEmitter::Size::i64Bit ? (1U << 31) : 0; - - uint32_t Instr = Op; - - Instr |= SF; - Instr |= Encode_rn(rn); - Instr |= Encode_rd(rd); - - dc32(Instr); - } - - // AddSub - shifted register - void DataProcessing_Shifted_Reg(uint32_t Op, FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::ShiftType Shift, uint32_t amt) { - LOGMAN_THROW_AA_FMT((amt & ~0b11'1111U) == 0, "Shift amount too large"); - if (s == FEXCore::ARMEmitter::Size::i32Bit) { - LOGMAN_THROW_AA_FMT(amt < 32, "Shift amount for 32-bit must be below 32"); - } - - const uint32_t SF = s == FEXCore::ARMEmitter::Size::i64Bit ? (1U << 31) : 0; - - uint32_t Instr = Op; - - Instr |= SF; - Instr |= FEXCore::ToUnderlying(Shift) << 22; - Instr |= Encode_rm(rm); - Instr |= static_cast(amt) << 10; - Instr |= Encode_rn(rn); - Instr |= Encode_rd(rd); - - dc32(Instr); - } - - // AddSub - extended register - void DataProcessing_Extended_Reg(uint32_t Op, FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::ExtendedType Option, uint32_t Shift) { - const uint32_t SF = s == FEXCore::ARMEmitter::Size::i64Bit ? (1U << 31) : 0; - - uint32_t Instr = Op; - - Instr |= SF; - Instr |= Encode_rm(rm); - Instr |= FEXCore::ToUnderlying(Option) << 13; - Instr |= static_cast(Shift) << 10; - Instr |= Encode_rn(rn); - Instr |= Encode_rd(rd); - - dc32(Instr); - } - // Conditional compare - register - template - void ConditionalCompare(uint32_t Op, uint32_t o1, uint32_t o2, uint32_t o3, FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rn, T rm, FEXCore::ARMEmitter::StatusFlags flags, FEXCore::ARMEmitter::Condition Cond) { - const uint32_t SF = s == FEXCore::ARMEmitter::Size::i64Bit ? (1U << 31) : 0; - - uint32_t Instr = Op; - - Instr |= SF; - Instr |= o1 << 30; - Instr |= Encode_rm(rm); - Instr |= FEXCore::ToUnderlying(Cond) << 12; - Instr |= o2 << 10; - Instr |= Encode_rn(rn); - Instr |= o3 << 4; - Instr |= FEXCore::ToUnderlying(flags); - - dc32(Instr); - } - - template - void ConditionalCompare(uint32_t Op, uint32_t o1, uint32_t o2, FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, T rm, FEXCore::ARMEmitter::Condition Cond) { - const uint32_t SF = s == FEXCore::ARMEmitter::Size::i64Bit ? (1U << 31) : 0; - - uint32_t Instr = Op; - - Instr |= SF; - Instr |= o1 << 30; - Instr |= Encode_rm(rm); - Instr |= FEXCore::ToUnderlying(Cond) << 12; - Instr |= o2 << 10; - Instr |= Encode_rn(rn); - Instr |= Encode_rd(rd); - - dc32(Instr); - } - - // Data-processing - 3 source - void DataProcessing_3Source(uint32_t Op, uint32_t Op0, FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::Register ra) { - const uint32_t SF = s == FEXCore::ARMEmitter::Size::i64Bit ? (1U << 31) : 0; - - uint32_t Instr = Op; - - Instr |= SF; - Instr |= Encode_rm(rm); - Instr |= Op0 << 15; - Instr |= Encode_ra(ra); - Instr |= Encode_rn(rn); - Instr |= Encode_rd(rd); - - dc32(Instr); - } - - void EvaluateIntoFlags(uint32_t op, uint32_t size, WRegister rn) { - uint32_t Instr = op; - Instr |= size << 14; - Instr |= rn.Idx() << 5; - dc32(Instr); - } - - diff --git a/FEXCore/Source/Interface/Core/Dispatcher/Dispatcher.cpp b/FEXCore/Source/Interface/Core/Dispatcher/Dispatcher.cpp index 8fc4da1ba..672609082 100644 --- a/FEXCore/Source/Interface/Core/Dispatcher/Dispatcher.cpp +++ b/FEXCore/Source/Interface/Core/Dispatcher/Dispatcher.cpp @@ -1,7 +1,6 @@ // SPDX-License-Identifier: MIT #include "Interface/Context/Context.h" -#include "Interface/Core/ArchHelpers/CodeEmitter/Emitter.h" #include "Interface/Core/Dispatcher/Dispatcher.h" #include "Interface/Core/LookupCache.h" #include "Interface/Core/X86HelperGen.h" @@ -17,6 +16,8 @@ #include #include +#include + #include #include #include diff --git a/FEXCore/Source/Interface/Core/JIT/Arm64/ALUOps.cpp b/FEXCore/Source/Interface/Core/JIT/Arm64/ALUOps.cpp index 3e9abda58..c25073a23 100644 --- a/FEXCore/Source/Interface/Core/JIT/Arm64/ALUOps.cpp +++ b/FEXCore/Source/Interface/Core/JIT/Arm64/ALUOps.cpp @@ -7,8 +7,6 @@ $end_info$ #include "FEXCore/IR/IR.h" #include "Interface/Context/Context.h" -#include "Interface/Core/ArchHelpers/CodeEmitter/Emitter.h" -#include "Interface/Core/ArchHelpers/CodeEmitter/Registers.h" #include "Interface/Core/JIT/Arm64/JITClass.h" #include "Interface/IR/Passes/RegisterAllocationPass.h" @@ -1373,23 +1371,23 @@ DEF_OP(Popcount) { case 0x1: fmov(ARMEmitter::Size::i32Bit, VTMP1.S(), Src); // only use lowest byte - cnt(FEXCore::ARMEmitter::SubRegSize::i8Bit, VTMP1.D(), VTMP1.D()); + cnt(ARMEmitter::SubRegSize::i8Bit, VTMP1.D(), VTMP1.D()); break; case 0x2: fmov(ARMEmitter::Size::i32Bit, VTMP1.S(), Src); - cnt(FEXCore::ARMEmitter::SubRegSize::i8Bit, VTMP1.D(), VTMP1.D()); + cnt(ARMEmitter::SubRegSize::i8Bit, VTMP1.D(), VTMP1.D()); // only count two lowest bytes - addp(FEXCore::ARMEmitter::SubRegSize::i8Bit, VTMP1.D(), VTMP1.D(), VTMP1.D()); + addp(ARMEmitter::SubRegSize::i8Bit, VTMP1.D(), VTMP1.D(), VTMP1.D()); break; case 0x4: fmov(ARMEmitter::Size::i32Bit, VTMP1.S(), Src); - cnt(FEXCore::ARMEmitter::SubRegSize::i8Bit, VTMP1.D(), VTMP1.D()); + cnt(ARMEmitter::SubRegSize::i8Bit, VTMP1.D(), VTMP1.D()); // fmov has zero extended, unused bytes are zero addv(ARMEmitter::SubRegSize::i8Bit, VTMP1.D(), VTMP1.D()); break; case 0x8: fmov(ARMEmitter::Size::i64Bit, VTMP1.D(), Src); - cnt(FEXCore::ARMEmitter::SubRegSize::i8Bit, VTMP1.D(), VTMP1.D()); + cnt(ARMEmitter::SubRegSize::i8Bit, VTMP1.D(), VTMP1.D()); // fmov has zero extended, unused bytes are zero addv(ARMEmitter::SubRegSize::i8Bit, VTMP1.D(), VTMP1.D()); break; diff --git a/FEXCore/Source/Interface/Core/JIT/Arm64/AtomicOps.cpp b/FEXCore/Source/Interface/Core/JIT/Arm64/AtomicOps.cpp index 2613f5120..b1a635d7b 100644 --- a/FEXCore/Source/Interface/Core/JIT/Arm64/AtomicOps.cpp +++ b/FEXCore/Source/Interface/Core/JIT/Arm64/AtomicOps.cpp @@ -6,7 +6,6 @@ $end_info$ */ #include "Interface/Context/Context.h" -#include "Interface/Core/ArchHelpers/CodeEmitter/Emitter.h" #include "Interface/Core/Dispatcher/Dispatcher.h" #include "Interface/Core/JIT/Arm64/JITClass.h" diff --git a/FEXCore/Source/Interface/Core/JIT/Arm64/BranchOps.cpp b/FEXCore/Source/Interface/Core/JIT/Arm64/BranchOps.cpp index 0d74b84d0..904535dad 100644 --- a/FEXCore/Source/Interface/Core/JIT/Arm64/BranchOps.cpp +++ b/FEXCore/Source/Interface/Core/JIT/Arm64/BranchOps.cpp @@ -7,7 +7,6 @@ $end_info$ #include "Interface/Context/Context.h" #include "FEXCore/IR/IR.h" -#include "Interface/Core/ArchHelpers/CodeEmitter/Emitter.h" #include "Interface/Core/LookupCache.h" #include "Interface/Core/JIT/Arm64/JITClass.h" diff --git a/FEXCore/Source/Interface/Core/JIT/Arm64/ConversionOps.cpp b/FEXCore/Source/Interface/Core/JIT/Arm64/ConversionOps.cpp index 7f77fbef6..92648f136 100644 --- a/FEXCore/Source/Interface/Core/JIT/Arm64/ConversionOps.cpp +++ b/FEXCore/Source/Interface/Core/JIT/Arm64/ConversionOps.cpp @@ -5,7 +5,6 @@ tags: backend|arm64 $end_info$ */ -#include "Interface/Core/ArchHelpers/CodeEmitter/Emitter.h" #include "Interface/Core/JIT/Arm64/JITClass.h" namespace FEXCore::CPU { @@ -66,7 +65,7 @@ DEF_OP(VInsGPR) { // Inserts the GPR value into the given V register. // Also automatically adjusts the index in the case of using the // moved upper lane. - const auto Insert = [&](const FEXCore::ARMEmitter::VRegister& reg, int index) { + const auto Insert = [&](const ARMEmitter::VRegister& reg, int index) { if (InUpperLane) { index -= ElementsPer128Bit; } @@ -353,23 +352,23 @@ DEF_OP(Vector_FToF) { switch (Conv) { case 0x0402: { // Float <- Half - zip1(FEXCore::ARMEmitter::SubRegSize::i16Bit, Dst.Z(), Vector.Z(), Vector.Z()); - fcvtlt(FEXCore::ARMEmitter::SubRegSize::i32Bit, Dst.Z(), Mask, Dst.Z()); + zip1(ARMEmitter::SubRegSize::i16Bit, Dst.Z(), Vector.Z(), Vector.Z()); + fcvtlt(ARMEmitter::SubRegSize::i32Bit, Dst.Z(), Mask, Dst.Z()); break; } case 0x0804: { // Double <- Float - zip1(FEXCore::ARMEmitter::SubRegSize::i32Bit, Dst.Z(), Vector.Z(), Vector.Z()); - fcvtlt(FEXCore::ARMEmitter::SubRegSize::i64Bit, Dst.Z(), Mask, Dst.Z()); + zip1(ARMEmitter::SubRegSize::i32Bit, Dst.Z(), Vector.Z(), Vector.Z()); + fcvtlt(ARMEmitter::SubRegSize::i64Bit, Dst.Z(), Mask, Dst.Z()); break; } case 0x0204: { // Half <- Float - fcvtnt(FEXCore::ARMEmitter::SubRegSize::i16Bit, Dst.Z(), Mask, Vector.Z()); - uzp2(FEXCore::ARMEmitter::SubRegSize::i16Bit, Dst.Z(), Dst.Z(), Dst.Z()); + fcvtnt(ARMEmitter::SubRegSize::i16Bit, Dst.Z(), Mask, Vector.Z()); + uzp2(ARMEmitter::SubRegSize::i16Bit, Dst.Z(), Dst.Z(), Dst.Z()); break; } case 0x0408: { // Float <- Double - fcvtnt(FEXCore::ARMEmitter::SubRegSize::i32Bit, Dst.Z(), Mask, Vector.Z()); - uzp2(FEXCore::ARMEmitter::SubRegSize::i32Bit, Dst.Z(), Dst.Z(), Dst.Z()); + fcvtnt(ARMEmitter::SubRegSize::i32Bit, Dst.Z(), Mask, Vector.Z()); + uzp2(ARMEmitter::SubRegSize::i32Bit, Dst.Z(), Dst.Z(), Dst.Z()); break; } default: LOGMAN_MSG_A_FMT("Unknown Vector_FToF Type : 0x{:04x}", Conv); break; diff --git a/FEXCore/Source/Interface/Core/JIT/Arm64/EncryptionOps.cpp b/FEXCore/Source/Interface/Core/JIT/Arm64/EncryptionOps.cpp index c77129fec..33af7f911 100644 --- a/FEXCore/Source/Interface/Core/JIT/Arm64/EncryptionOps.cpp +++ b/FEXCore/Source/Interface/Core/JIT/Arm64/EncryptionOps.cpp @@ -5,9 +5,7 @@ tags: backend|arm64 $end_info$ */ -#include "Interface/Core/ArchHelpers/CodeEmitter/Emitter.h" #include "Interface/Core/JIT/Arm64/JITClass.h" -#include "Interface/IR/Passes/RegisterAllocationPass.h" namespace FEXCore::CPU { #define DEF_OP(x) void Arm64JITCore::Op_##x(IR::IROp_Header const* IROp, IR::NodeID Node) diff --git a/FEXCore/Source/Interface/Core/JIT/Arm64/JIT.cpp b/FEXCore/Source/Interface/Core/JIT/Arm64/JIT.cpp index 9db0e7c52..82e4253f6 100644 --- a/FEXCore/Source/Interface/Core/JIT/Arm64/JIT.cpp +++ b/FEXCore/Source/Interface/Core/JIT/Arm64/JIT.cpp @@ -13,7 +13,6 @@ $end_info$ #include "FEXCore/Utils/Telemetry.h" #include "Interface/Context/Context.h" -#include "Interface/Core/ArchHelpers/CodeEmitter/Emitter.h" #include "Interface/Core/LookupCache.h" #include "Interface/Core/Dispatcher/Dispatcher.h" @@ -469,13 +468,13 @@ void Arm64JITCore::Op_Unhandled(const IR::IROp_Header* IROp, IR::NodeID Node) { static void DirectBlockDelinker(FEXCore::Core::CpuStateFrame* Frame, FEXCore::Context::ExitFunctionLinkData* Record) { auto LinkerAddress = Frame->Pointers.Common.ExitFunctionLinker; uintptr_t branch = (uintptr_t)(Record)-8; - FEXCore::ARMEmitter::Emitter emit((uint8_t*)(branch), 8); - FEXCore::ARMEmitter::SingleUseForwardLabel l_BranchHost; + ARMEmitter::Emitter emit((uint8_t*)(branch), 8); + ARMEmitter::SingleUseForwardLabel l_BranchHost; emit.ldr(TMP1, &l_BranchHost); emit.blr(TMP1); emit.Bind(&l_BranchHost); emit.dc64(LinkerAddress); - FEXCore::ARMEmitter::Emitter::ClearICache((void*)branch, 8); + ARMEmitter::Emitter::ClearICache((void*)branch, 8); } static void IndirectBlockDelinker(FEXCore::Core::CpuStateFrame* Frame, FEXCore::Context::ExitFunctionLinkData* Record) { @@ -500,9 +499,9 @@ static uint64_t Arm64JITCore_ExitFunctionLink(FEXCore::Core::CpuStateFrame* Fram if (vixl::IsInt26(offset)) { // optimal case - can branch directly // patch the code - FEXCore::ARMEmitter::Emitter emit((uint8_t*)(branch), 4); + ARMEmitter::Emitter emit((uint8_t*)(branch), 4); emit.b(offset); - FEXCore::ARMEmitter::Emitter::ClearICache((void*)branch, 4); + ARMEmitter::Emitter::ClearICache((void*)branch, 4); // Add de-linking handler Thread->LookupCache->AddBlockLink(GuestRip, Record, DirectBlockDelinker); diff --git a/FEXCore/Source/Interface/Core/JIT/Arm64/JITClass.h b/FEXCore/Source/Interface/Core/JIT/Arm64/JITClass.h index 3f8bd4aa2..9e071e336 100644 --- a/FEXCore/Source/Interface/Core/JIT/Arm64/JITClass.h +++ b/FEXCore/Source/Interface/Core/JIT/Arm64/JITClass.h @@ -8,7 +8,6 @@ $end_info$ #pragma once #include "Interface/Core/ArchHelpers/Arm64Emitter.h" -#include "Interface/Core/ArchHelpers/CodeEmitter/Emitter.h" #include "Interface/Core/CPUBackend.h" #include "Interface/Core/Dispatcher/Dispatcher.h" #include "Interface/IR/IR.h" @@ -24,6 +23,8 @@ $end_info$ #include #include +#include + #include #include #include @@ -83,7 +84,7 @@ private: fextl::map JumpTargets; [[nodiscard]] - FEXCore::ARMEmitter::Register GetReg(IR::NodeID Node) const { + ARMEmitter::Register GetReg(IR::NodeID Node) const { const auto Reg = GetPhys(Node); LOGMAN_THROW_AA_FMT(Reg.Class == IR::GPRFixedClass.Val || Reg.Class == IR::GPRClass.Val, "Unexpected Class: {}", Reg.Class); @@ -98,7 +99,7 @@ private: } [[nodiscard]] - FEXCore::ARMEmitter::VRegister GetVReg(IR::NodeID Node) const { + ARMEmitter::VRegister GetVReg(IR::NodeID Node) const { const auto Reg = GetPhys(Node); LOGMAN_THROW_AA_FMT(Reg.Class == IR::FPRFixedClass.Val || Reg.Class == IR::FPRClass.Val, "Unexpected Class: {}", Reg.Class); @@ -113,7 +114,7 @@ private: } [[nodiscard]] - std::pair GetRegPair(IR::NodeID Node) const { + std::pair GetRegPair(IR::NodeID Node) const { const auto Reg = GetPhys(Node); LOGMAN_THROW_AA_FMT(Reg.Class == IR::GPRPairClass.Val, "Unexpected Class: {}", Reg.Class); @@ -134,7 +135,7 @@ private: } [[nodiscard]] - FEXCore::ARMEmitter::Register GetZeroableReg(IR::OrderedNodeWrapper Src) const { + ARMEmitter::Register GetZeroableReg(IR::OrderedNodeWrapper Src) const { uint64_t Const; if (IsInlineConstant(Src, &Const)) { LOGMAN_THROW_AA_FMT(Const == 0, "Only valid constant"); @@ -162,8 +163,8 @@ private: bool IsGPRPair(IR::NodeID Node) const; [[nodiscard]] - FEXCore::ARMEmitter::ExtendedMemOperand GenerateMemOperand( - uint8_t AccessSize, FEXCore::ARMEmitter::Register Base, IR::OrderedNodeWrapper Offset, IR::MemOffsetType OffsetType, uint8_t OffsetScale); + ARMEmitter::ExtendedMemOperand GenerateMemOperand(uint8_t AccessSize, ARMEmitter::Register Base, IR::OrderedNodeWrapper Offset, + IR::MemOffsetType OffsetType, uint8_t OffsetScale); // NOTE: Will use TMP1 as a way to encode immediates that happen to fall outside // the limits of the scalar plus immediate variant of SVE load/stores. @@ -171,8 +172,8 @@ private: // TMP1 is safe to use again once this memory operand is used with its // equivalent loads or stores that this was called for. [[nodiscard]] - FEXCore::ARMEmitter::SVEMemOperand GenerateSVEMemOperand(uint8_t AccessSize, FEXCore::ARMEmitter::Register Base, - IR::OrderedNodeWrapper Offset, IR::MemOffsetType OffsetType, uint8_t OffsetScale); + ARMEmitter::SVEMemOperand GenerateSVEMemOperand(uint8_t AccessSize, ARMEmitter::Register Base, IR::OrderedNodeWrapper Offset, + IR::MemOffsetType OffsetType, uint8_t OffsetScale); [[nodiscard]] bool IsInlineConstant(const IR::OrderedNodeWrapper& Node, uint64_t* Value = nullptr) const; diff --git a/FEXCore/Source/Interface/Core/JIT/Arm64/MemoryOps.cpp b/FEXCore/Source/Interface/Core/JIT/Arm64/MemoryOps.cpp index c6729b962..f8da1d524 100644 --- a/FEXCore/Source/Interface/Core/JIT/Arm64/MemoryOps.cpp +++ b/FEXCore/Source/Interface/Core/JIT/Arm64/MemoryOps.cpp @@ -7,8 +7,6 @@ $end_info$ #include "FEXCore/Core/X86Enums.h" #include "Interface/Context/Context.h" -#include "Interface/Core/ArchHelpers/CodeEmitter/Emitter.h" -#include "Interface/Core/ArchHelpers/CodeEmitter/Registers.h" #include "Interface/Core/CPUID.h" #include "Interface/Core/JIT/Arm64/JITClass.h" #include @@ -170,7 +168,7 @@ DEF_OP(LoadContextIndexed) { case 2: case 4: case 8: { - add(ARMEmitter::Size::i64Bit, TMP1, STATE, Index, FEXCore::ARMEmitter::ShiftType::LSL, FEXCore::ilog2(Op->Stride)); + add(ARMEmitter::Size::i64Bit, TMP1, STATE, Index, ARMEmitter::ShiftType::LSL, FEXCore::ilog2(Op->Stride)); const auto Dst = GetReg(Node); switch (OpSize) { case 1: ldrb(Dst, TMP1, Op->BaseOffset); break; @@ -192,7 +190,7 @@ DEF_OP(LoadContextIndexed) { case 8: case 16: case 32: { - add(ARMEmitter::Size::i64Bit, TMP1, STATE, Index, FEXCore::ARMEmitter::ShiftType::LSL, FEXCore::ilog2(Op->Stride)); + add(ARMEmitter::Size::i64Bit, TMP1, STATE, Index, ARMEmitter::ShiftType::LSL, FEXCore::ilog2(Op->Stride)); const auto Dst = GetVReg(Node); switch (OpSize) { @@ -235,7 +233,7 @@ DEF_OP(StoreContextIndexed) { case 2: case 4: case 8: { - add(ARMEmitter::Size::i64Bit, TMP1, STATE, Index, FEXCore::ARMEmitter::ShiftType::LSL, FEXCore::ilog2(Op->Stride)); + add(ARMEmitter::Size::i64Bit, TMP1, STATE, Index, ARMEmitter::ShiftType::LSL, FEXCore::ilog2(Op->Stride)); switch (OpSize) { case 1: strb(Value, TMP1, Op->BaseOffset); break; @@ -259,7 +257,7 @@ DEF_OP(StoreContextIndexed) { case 8: case 16: case 32: { - add(ARMEmitter::Size::i64Bit, TMP1, STATE, Index, FEXCore::ARMEmitter::ShiftType::LSL, FEXCore::ilog2(Op->Stride)); + add(ARMEmitter::Size::i64Bit, TMP1, STATE, Index, ARMEmitter::ShiftType::LSL, FEXCore::ilog2(Op->Stride)); switch (OpSize) { case 1: strb(Value, TMP1, Op->BaseOffset); break; @@ -552,8 +550,8 @@ DEF_OP(StoreFlag) { strb(GetReg(Op->Value.ID()), STATE, offsetof(FEXCore::Core::CPUState, flags[0]) + Op->Flag); } -FEXCore::ARMEmitter::ExtendedMemOperand Arm64JITCore::GenerateMemOperand( - uint8_t AccessSize, FEXCore::ARMEmitter::Register Base, IR::OrderedNodeWrapper Offset, IR::MemOffsetType OffsetType, uint8_t OffsetScale) { +ARMEmitter::ExtendedMemOperand Arm64JITCore::GenerateMemOperand( + uint8_t AccessSize, ARMEmitter::Register Base, IR::OrderedNodeWrapper Offset, IR::MemOffsetType OffsetType, uint8_t OffsetScale) { if (Offset.IsInvalid()) { return ARMEmitter::ExtendedMemOperand(Base.X(), ARMEmitter::IndexType::OFFSET, 0); } else { @@ -580,17 +578,16 @@ FEXCore::ARMEmitter::ExtendedMemOperand Arm64JITCore::GenerateMemOperand( FEX_UNREACHABLE; } -FEXCore::ARMEmitter::SVEMemOperand Arm64JITCore::GenerateSVEMemOperand(uint8_t AccessSize, FEXCore::ARMEmitter::Register Base, - IR::OrderedNodeWrapper Offset, IR::MemOffsetType OffsetType, - [[maybe_unused]] uint8_t OffsetScale) { +ARMEmitter::SVEMemOperand Arm64JITCore::GenerateSVEMemOperand(uint8_t AccessSize, ARMEmitter::Register Base, IR::OrderedNodeWrapper Offset, + IR::MemOffsetType OffsetType, [[maybe_unused]] uint8_t OffsetScale) { if (Offset.IsInvalid()) { - return FEXCore::ARMEmitter::SVEMemOperand(Base.X(), 0); + return ARMEmitter::SVEMemOperand(Base.X(), 0); } uint64_t Const {}; if (IsInlineConstant(Offset, &Const)) { if (Const == 0) { - return FEXCore::ARMEmitter::SVEMemOperand(Base.X(), 0); + return ARMEmitter::SVEMemOperand(Base.X(), 0); } const auto SignedConst = static_cast(Const); @@ -613,13 +610,13 @@ FEXCore::ARMEmitter::SVEMemOperand Arm64JITCore::GenerateSVEMemOperand(uint8_t A // then we can encode it as an immediate offset. // if (IsCleanlyDivisible && Index >= -8 && Index <= 7) { - return FEXCore::ARMEmitter::SVEMemOperand(Base.X(), static_cast(Index)); + return ARMEmitter::SVEMemOperand(Base.X(), static_cast(Index)); } // If we can't do that for whatever reason, then unfortunately, we need // to move it over to a temporary to use as an offset. mov(TMP1, Const); - return FEXCore::ARMEmitter::SVEMemOperand(Base.X(), TMP1); + return ARMEmitter::SVEMemOperand(Base.X(), TMP1); } // Otherwise handle it like normal. @@ -629,7 +626,7 @@ FEXCore::ARMEmitter::SVEMemOperand Arm64JITCore::GenerateSVEMemOperand(uint8_t A LOGMAN_THROW_A_FMT(OffsetType.Val == IR::MEM_OFFSET_SXTX.Val, "Currently only the default offset type (SXTX) is supported."); const auto RegOffset = GetReg(Offset.ID()); - return FEXCore::ARMEmitter::SVEMemOperand(Base.X(), RegOffset.X()); + return ARMEmitter::SVEMemOperand(Base.X(), RegOffset.X()); } DEF_OP(LoadMem) { @@ -743,7 +740,7 @@ DEF_OP(LoadMemTSO) { } if (VectorTSOEnabled()) { // Half-barrier. - dmb(FEXCore::ARMEmitter::BarrierScope::ISHLD); + dmb(ARMEmitter::BarrierScope::ISHLD); } } } @@ -895,7 +892,7 @@ DEF_OP(VStoreVectorElement) { // Emit a half-barrier if TSO is enabled. if (CTX->IsAtomicTSOEnabled() && VectorTSOEnabled()) { - dmb(FEXCore::ARMEmitter::BarrierScope::ISH); + dmb(ARMEmitter::BarrierScope::ISH); } if (Is256Bit) { @@ -1141,7 +1138,7 @@ DEF_OP(StoreMemTSO) { } else { if (VectorTSOEnabled()) { // Half-Barrier. - dmb(FEXCore::ARMEmitter::BarrierScope::ISH); + dmb(ARMEmitter::BarrierScope::ISH); } const auto Src = GetVReg(Op->Value.ID()); const auto MemSrc = GenerateMemOperand(OpSize, MemReg, Op->Offset, Op->OffsetType, Op->OffsetScale); @@ -1180,7 +1177,7 @@ DEF_OP(MemSet) { uint64_t DirectionConstant; bool DirectionIsInline = IsInlineConstant(Op->Direction, &DirectionConstant); - FEXCore::ARMEmitter::Register DirectionReg = ARMEmitter::Reg::r0; + ARMEmitter::Register DirectionReg = ARMEmitter::Reg::r0; if (!DirectionIsInline) { DirectionReg = GetReg(Op->Direction.ID()); } @@ -1369,7 +1366,7 @@ DEF_OP(MemCpy) { const auto Length = GetReg(Op->Length.ID()); uint64_t DirectionConstant; bool DirectionIsInline = IsInlineConstant(Op->Direction, &DirectionConstant); - FEXCore::ARMEmitter::Register DirectionReg = ARMEmitter::Reg::r0; + ARMEmitter::Register DirectionReg = ARMEmitter::Reg::r0; if (!DirectionIsInline) { DirectionReg = GetReg(Op->Direction.ID()); } @@ -1712,9 +1709,9 @@ DEF_OP(ParanoidLoadMemTSO) { ins(ARMEmitter::SubRegSize::i64Bit, Dst, 1, TMP2); break; case 32: - dmb(FEXCore::ARMEmitter::BarrierScope::ISH); + dmb(ARMEmitter::BarrierScope::ISH); ld1b(Dst.Z(), PRED_TMP_32B.Zeroing(), MemReg); - dmb(FEXCore::ARMEmitter::BarrierScope::ISH); + dmb(ARMEmitter::BarrierScope::ISH); break; default: LOGMAN_MSG_A_FMT("Unhandled ParanoidLoadMemTSO size: {}", OpSize); break; } @@ -1788,9 +1785,9 @@ DEF_OP(ParanoidStoreMemTSO) { break; } case 32: { - dmb(FEXCore::ARMEmitter::BarrierScope::ISH); + dmb(ARMEmitter::BarrierScope::ISH); st1b(Src.Z(), PRED_TMP_32B, MemReg, 0); - dmb(FEXCore::ARMEmitter::BarrierScope::ISH); + dmb(ARMEmitter::BarrierScope::ISH); break; } default: LOGMAN_MSG_A_FMT("Unhandled ParanoidStoreMemTSO size: {}", OpSize); break; @@ -1818,7 +1815,7 @@ DEF_OP(CacheLineClear) { if (Op->Serialize) { // If requested, serialized all of the data cache operations. - dsb(FEXCore::ARMEmitter::BarrierScope::ISH); + dsb(ARMEmitter::BarrierScope::ISH); } } diff --git a/FEXCore/Source/Interface/Core/JIT/Arm64/MiscOps.cpp b/FEXCore/Source/Interface/Core/JIT/Arm64/MiscOps.cpp index 137258dc6..dacc9276a 100644 --- a/FEXCore/Source/Interface/Core/JIT/Arm64/MiscOps.cpp +++ b/FEXCore/Source/Interface/Core/JIT/Arm64/MiscOps.cpp @@ -10,7 +10,6 @@ $end_info$ #endif #include "Interface/Context/Context.h" -#include "Interface/Core/ArchHelpers/CodeEmitter/Emitter.h" #include "Interface/Core/JIT/Arm64/JITClass.h" #include "FEXCore/Debug/InternalThreadState.h" @@ -28,9 +27,9 @@ DEF_OP(GuestOpcode) { DEF_OP(Fence) { auto Op = IROp->C(); switch (Op->Fence) { - case IR::Fence_Load.Val: dmb(FEXCore::ARMEmitter::BarrierScope::LD); break; - case IR::Fence_LoadStore.Val: dmb(FEXCore::ARMEmitter::BarrierScope::SY); break; - case IR::Fence_Store.Val: dmb(FEXCore::ARMEmitter::BarrierScope::ST); break; + case IR::Fence_Load.Val: dmb(ARMEmitter::BarrierScope::LD); break; + case IR::Fence_LoadStore.Val: dmb(ARMEmitter::BarrierScope::SY); break; + case IR::Fence_Store.Val: dmb(ARMEmitter::BarrierScope::ST); break; default: LOGMAN_MSG_A_FMT("Unknown Fence: {}", Op->Fence); break; } } diff --git a/FEXCore/Source/Interface/Core/JIT/Arm64/VectorOps.cpp b/FEXCore/Source/Interface/Core/JIT/Arm64/VectorOps.cpp index 889fcd42f..e19247e3b 100644 --- a/FEXCore/Source/Interface/Core/JIT/Arm64/VectorOps.cpp +++ b/FEXCore/Source/Interface/Core/JIT/Arm64/VectorOps.cpp @@ -5,8 +5,6 @@ tags: backend|arm64 $end_info$ */ -#include "Interface/Core/ArchHelpers/CodeEmitter/Emitter.h" -#include "Interface/Core/ArchHelpers/CodeEmitter/Registers.h" #include "Interface/Core/Dispatcher/Dispatcher.h" #include "Interface/Core/JIT/Arm64/JITClass.h" @@ -792,7 +790,7 @@ DEF_OP(LoadNamedVectorConstant) { } } // Load the pointer. - auto GenerateMemOperand = [this](uint8_t OpSize, uint32_t NamedConstant, FEXCore::ARMEmitter::Register Base) { + auto GenerateMemOperand = [this](uint8_t OpSize, uint32_t NamedConstant, ARMEmitter::Register Base) { const auto ConstantOffset = offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.NamedVectorConstants[NamedConstant]); if (ConstantOffset <= 255 || // Unscaled 9-bit signed @@ -4794,7 +4792,8 @@ DEF_OP(VTBL2) { mov(VTMP2.Q(), VectorTable2.Q()); } - static_assert(ARMEmitter::AreVectorsSequential(VTMP1, VTMP2), "VTMP1 and VTMP2 must be sequential in order to use double-table TBL"); + static_assert(ARMEmitter::AreVectorsSequential(VTMP1, VTMP2), "VTMP1 and VTMP2 must be sequential in order to use double-table " + "TBL"); VectorTable1 = VTMP1; VectorTable2 = VTMP2; } diff --git a/FEXCore/unittests/Emitter/ALU_Tests.cpp b/FEXCore/unittests/Emitter/ALU_Tests.cpp index 0217a9662..619d06c73 100644 --- a/FEXCore/unittests/Emitter/ALU_Tests.cpp +++ b/FEXCore/unittests/Emitter/ALU_Tests.cpp @@ -3,7 +3,7 @@ #include #include -using namespace FEXCore::ARMEmitter; +using namespace ARMEmitter; TEST_CASE_METHOD(TestDisassembler, "Emitter: ALU: PC relative") { { diff --git a/FEXCore/unittests/Emitter/ASIMD_Tests.cpp b/FEXCore/unittests/Emitter/ASIMD_Tests.cpp index d085b972f..7a215c16b 100644 --- a/FEXCore/unittests/Emitter/ASIMD_Tests.cpp +++ b/FEXCore/unittests/Emitter/ASIMD_Tests.cpp @@ -3,7 +3,7 @@ #include #include -using namespace FEXCore::ARMEmitter; +using namespace ARMEmitter; TEST_CASE_METHOD(TestDisassembler, "Emitter: ASIMD: Cryptographic AES") { if (false) { diff --git a/FEXCore/unittests/Emitter/Branch_Tests.cpp b/FEXCore/unittests/Emitter/Branch_Tests.cpp index c051bb9b8..8bc09f273 100644 --- a/FEXCore/unittests/Emitter/Branch_Tests.cpp +++ b/FEXCore/unittests/Emitter/Branch_Tests.cpp @@ -3,7 +3,7 @@ #include #include -using namespace FEXCore::ARMEmitter; +using namespace ARMEmitter; TEST_CASE_METHOD(TestDisassembler, "Emitter: Branch: Conditional branch immediate") { { diff --git a/FEXCore/unittests/Emitter/Loadstore_Tests.cpp b/FEXCore/unittests/Emitter/Loadstore_Tests.cpp index 2244c9dc6..788750d15 100644 --- a/FEXCore/unittests/Emitter/Loadstore_Tests.cpp +++ b/FEXCore/unittests/Emitter/Loadstore_Tests.cpp @@ -3,7 +3,7 @@ #include #include -using namespace FEXCore::ARMEmitter; +using namespace ARMEmitter; TEST_CASE_METHOD(TestDisassembler, "Emitter: Loadstore: Compare and swap pair") { TEST_SINGLE(casp(Size::i32Bit, Reg::r28, Reg::r29, Reg::r26, Reg::r27, Reg::r30), "casp w28, w29, w26, w27, [x30]"); diff --git a/FEXCore/unittests/Emitter/SVE_Tests.cpp b/FEXCore/unittests/Emitter/SVE_Tests.cpp index f45de0d6b..a5a051d0e 100644 --- a/FEXCore/unittests/Emitter/SVE_Tests.cpp +++ b/FEXCore/unittests/Emitter/SVE_Tests.cpp @@ -3,7 +3,7 @@ #include #include -using namespace FEXCore::ARMEmitter; +using namespace ARMEmitter; TEST_CASE_METHOD(TestDisassembler, "Emitter: SVE: Base Encodings") { TEST_SINGLE(dup(SubRegSize::i8Bit, ZReg::z30, ZReg::z29, 0), "mov z30.b, b29"); @@ -287,11 +287,11 @@ TEST_CASE_METHOD(TestDisassembler, "Emitter: SVE: SVE floating-point convert pre TEST_SINGLE(fcvtlt(SubRegSize::i64Bit, ZReg::z30, PReg::p6.Merging(), ZReg::z29), "fcvtlt z30.d, p6/m, z29.s"); - // void fcvtxnt(FEXCore::ARMEmitter::ZRegister zd, FEXCore::ARMEmitter::PRegister pg, FEXCore::ARMEmitter::ZRegister zn) { + // void fcvtxnt(ARMEmitter::ZRegister zd, ARMEmitter::PRegister pg, ARMEmitter::ZRegister zn) { /////< Size is destination size - // void fcvtnt(FEXCore::ARMEmitter::SubRegSize size, FEXCore::ARMEmitter::ZRegister zd, FEXCore::ARMEmitter::PRegister pg, FEXCore::ARMEmitter::ZRegister zn) { + // void fcvtnt(ARMEmitter::SubRegSize size, ARMEmitter::ZRegister zd, ARMEmitter::PRegister pg, ARMEmitter::ZRegister zn) { /////< Size is destination size - // void fcvtlt(FEXCore::ARMEmitter::SubRegSize size, FEXCore::ARMEmitter::ZRegister zd, FEXCore::ARMEmitter::PRegister pg, FEXCore::ARMEmitter::ZRegister zn) { + // void fcvtlt(ARMEmitter::SubRegSize size, ARMEmitter::ZRegister zd, ARMEmitter::PRegister pg, ARMEmitter::ZRegister zn) { // XXX: BFCVTNT } @@ -1634,12 +1634,12 @@ TEST_CASE_METHOD(TestDisassembler, "Emitter: SVE: SVE conditionally extract elem } TEST_CASE_METHOD(TestDisassembler, "Emitter: SVE: SVE Permute Vector - Extract") { - TEST_SINGLE(ext(ZReg::z30, ZReg::z30, ZReg::z29, 0), "ext z30.b, z30.b, z29.b, #0"); - TEST_SINGLE(ext(ZReg::z30, ZReg::z30, ZReg::z29, 255), "ext z30.b, z30.b, z29.b, #255"); + TEST_SINGLE(ext(ZReg::z30, ZReg::z30, ZReg::z29, 0), "ext z30.b, z30.b, z29.b, #0"); + TEST_SINGLE(ext(ZReg::z30, ZReg::z30, ZReg::z29, 255), "ext z30.b, z30.b, z29.b, #255"); - TEST_SINGLE(ext(ZReg::z30, ZReg::z28, ZReg::z29, 0), "ext z30.b, {z28.b, z29.b}, #0"); - TEST_SINGLE(ext(ZReg::z30, ZReg::z28, ZReg::z29, 255), "ext z30.b, {z28.b, z29.b}, #255"); - TEST_SINGLE(ext(ZReg::z30, ZReg::z31, ZReg::z0, 255), "ext z30.b, {z31.b, z0.b}, #255"); + TEST_SINGLE(ext(ZReg::z30, ZReg::z28, ZReg::z29, 0), "ext z30.b, {z28.b, z29.b}, #0"); + TEST_SINGLE(ext(ZReg::z30, ZReg::z28, ZReg::z29, 255), "ext z30.b, {z28.b, z29.b}, #255"); + TEST_SINGLE(ext(ZReg::z30, ZReg::z31, ZReg::z0, 255), "ext z30.b, {z31.b, z0.b}, #255"); } TEST_CASE_METHOD(TestDisassembler, "Emitter: SVE: SVE permute vector segments") { diff --git a/FEXCore/unittests/Emitter/Scalar_Tests.cpp b/FEXCore/unittests/Emitter/Scalar_Tests.cpp index a79d17401..caca60176 100644 --- a/FEXCore/unittests/Emitter/Scalar_Tests.cpp +++ b/FEXCore/unittests/Emitter/Scalar_Tests.cpp @@ -3,7 +3,7 @@ #include #include -using namespace FEXCore::ARMEmitter; +using namespace ARMEmitter; TEST_CASE_METHOD(TestDisassembler, "Emitter: Scalar: Advanced SIMD scalar copy") { TEST_SINGLE(dup(ScalarRegSize::i8Bit, VReg::v30, VReg::v29, 0), "mov b30, v29.b[0]"); diff --git a/FEXCore/unittests/Emitter/System_Tests.cpp b/FEXCore/unittests/Emitter/System_Tests.cpp index e82d8ac69..b0d3afceb 100644 --- a/FEXCore/unittests/Emitter/System_Tests.cpp +++ b/FEXCore/unittests/Emitter/System_Tests.cpp @@ -3,7 +3,7 @@ #include #include -using namespace FEXCore::ARMEmitter; +using namespace ARMEmitter; TEST_CASE_METHOD(TestDisassembler, "Emitter: System: System with result") { // TODO: Implement in emitter. diff --git a/FEXCore/unittests/Emitter/TestDisassembler.h b/FEXCore/unittests/Emitter/TestDisassembler.h index c82b1eb93..99008c62c 100644 --- a/FEXCore/unittests/Emitter/TestDisassembler.h +++ b/FEXCore/unittests/Emitter/TestDisassembler.h @@ -1,7 +1,6 @@ #pragma once #include - -#include "Interface/Core/ArchHelpers/CodeEmitter/Emitter.h" +#include #include #include @@ -9,7 +8,7 @@ #include -class TestDisassembler : public FEXCore::ARMEmitter::Emitter { +class TestDisassembler : public ARMEmitter::Emitter { public: TestDisassembler() { fp = tmpfile();