From 9d936a89890353d6edfb1d3f0fd0bbba8dbcce2e Mon Sep 17 00:00:00 2001 From: Ryan Houdek Date: Mon, 14 Sep 2026 19:24:51 -0700 Subject: [PATCH] OpcodeDispatcher: Removes DST_RAX from ADC --- FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp | 8 ++++++-- FEXCore/Source/Interface/Core/OpcodeDispatcher.h | 2 +- .../Source/Interface/Core/OpcodeDispatcher/BaseTables.h | 3 ++- .../Interface/Core/OpcodeDispatcher/PrimaryGroupTables.h | 6 +++--- FEXCore/Source/Interface/Core/X86Tables/BaseTables.cpp | 4 ++-- .../Interface/Core/X86Tables/PrimaryGroupTables.cpp | 2 +- 6 files changed, 15 insertions(+), 10 deletions(-) diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp index 8da1dcc7d..a4d452024 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp @@ -230,7 +230,7 @@ void OpDispatchBuilder::SecondaryALUOp(OpcodeArgs) { ALUOp(Op, IROp, AtomicIROp, 1, false); } -void OpDispatchBuilder::ADCOp(OpcodeArgs, uint32_t SrcIndex) { +void OpDispatchBuilder::ADCOp(OpcodeArgs, uint32_t SrcIndex, bool DestRAX) { // Calculate flags early. CalculateDeferredFlags(); @@ -245,6 +245,8 @@ void OpDispatchBuilder::ADCOp(OpcodeArgs, uint32_t SrcIndex) { Ref DestMem = MakeSegmentAddress(Op, Op->Dest); Before = _AtomicFetchAdd(Size, ALUOp, DestMem); + } else if (DestRAX) { + Before = LoadGPRRegister(X86State::REG_RAX, OpSizeFromSrc(Op), 0, true); } else { Before = LoadSourceGPR(Op, Op->Dest, Op->Flags, {.AllowUpperGarbage = true}); } @@ -261,7 +263,9 @@ void OpDispatchBuilder::ADCOp(OpcodeArgs, uint32_t SrcIndex) { Result = CalculateFlags_ADC(Size, Before, Src); } - if (!DestIsLockedMem(Op)) { + if (DestRAX) { + StoreGPRResultWithZExtSemantics(X86State::REG_RAX, Result, OpSizeFromDst(Op)); + } else if (!DestIsLockedMem(Op)) { StoreResultGPR(Op, Result); } } diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher.h b/FEXCore/Source/Interface/Core/OpcodeDispatcher.h index ee30abc6e..0b5f2322d 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher.h +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher.h @@ -375,7 +375,7 @@ public: void IRETOp(OpcodeArgs); void CallbackReturnOp(OpcodeArgs); void SecondaryALUOp(OpcodeArgs); - void ADCOp(OpcodeArgs, uint32_t SrcIndex); + void ADCOp(OpcodeArgs, uint32_t SrcIndex, bool DestRAX); void SBBOp(OpcodeArgs, uint32_t SrcIndex); void SALCOp(OpcodeArgs); void PUSHOp(OpcodeArgs); diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher/BaseTables.h b/FEXCore/Source/Interface/Core/OpcodeDispatcher/BaseTables.h index 2c2002acb..bad9d07f7 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher/BaseTables.h +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher/BaseTables.h @@ -11,7 +11,8 @@ constexpr inline DispatchTableEntry OpDispatch_BaseOpTable[] = { {0x08, 4, &OpDispatchBuilder::Bind<&OpDispatchBuilder::ALUOp, FEXCore::IR::IROps::OP_OR, FEXCore::IR::IROps::OP_ATOMICFETCHOR, 0, false>}, {0x0c, 2, &OpDispatchBuilder::Bind<&OpDispatchBuilder::ALUOp, FEXCore::IR::IROps::OP_OR, FEXCore::IR::IROps::OP_ATOMICFETCHOR, 0, true>}, - {0x10, 6, &OpDispatchBuilder::Bind<&OpDispatchBuilder::ADCOp, 0>}, + {0x10, 4, &OpDispatchBuilder::Bind<&OpDispatchBuilder::ADCOp, 0, false>}, + {0x14, 2, &OpDispatchBuilder::Bind<&OpDispatchBuilder::ADCOp, 0, true>}, {0x18, 6, &OpDispatchBuilder::Bind<&OpDispatchBuilder::SBBOp, 0>}, diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher/PrimaryGroupTables.h b/FEXCore/Source/Interface/Core/OpcodeDispatcher/PrimaryGroupTables.h index 7fccb784e..2d9c6d10e 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher/PrimaryGroupTables.h +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher/PrimaryGroupTables.h @@ -9,7 +9,7 @@ constexpr DispatchTableEntry OpDispatch_PrimaryGroupTables[] = { // GROUP 1 {OPD(FEXCore::X86Tables::TYPE_GROUP_1, OpToIndex(0x80), 0), 1, &OpDispatchBuilder::SecondaryALUOp}, {OPD(FEXCore::X86Tables::TYPE_GROUP_1, OpToIndex(0x80), 1), 1, &OpDispatchBuilder::SecondaryALUOp}, - {OPD(FEXCore::X86Tables::TYPE_GROUP_1, OpToIndex(0x80), 2), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::ADCOp, 1>}, + {OPD(FEXCore::X86Tables::TYPE_GROUP_1, OpToIndex(0x80), 2), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::ADCOp, 1, false>}, {OPD(FEXCore::X86Tables::TYPE_GROUP_1, OpToIndex(0x80), 3), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::SBBOp, 1>}, {OPD(FEXCore::X86Tables::TYPE_GROUP_1, OpToIndex(0x80), 4), 1, &OpDispatchBuilder::SecondaryALUOp}, {OPD(FEXCore::X86Tables::TYPE_GROUP_1, OpToIndex(0x80), 5), 1, &OpDispatchBuilder::SecondaryALUOp}, @@ -18,7 +18,7 @@ constexpr DispatchTableEntry OpDispatch_PrimaryGroupTables[] = { {OPD(FEXCore::X86Tables::TYPE_GROUP_1, OpToIndex(0x81), 0), 1, &OpDispatchBuilder::SecondaryALUOp}, {OPD(FEXCore::X86Tables::TYPE_GROUP_1, OpToIndex(0x81), 1), 1, &OpDispatchBuilder::SecondaryALUOp}, - {OPD(FEXCore::X86Tables::TYPE_GROUP_1, OpToIndex(0x81), 2), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::ADCOp, 1>}, + {OPD(FEXCore::X86Tables::TYPE_GROUP_1, OpToIndex(0x81), 2), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::ADCOp, 1, false>}, {OPD(FEXCore::X86Tables::TYPE_GROUP_1, OpToIndex(0x81), 3), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::SBBOp, 1>}, {OPD(FEXCore::X86Tables::TYPE_GROUP_1, OpToIndex(0x81), 4), 1, &OpDispatchBuilder::SecondaryALUOp}, {OPD(FEXCore::X86Tables::TYPE_GROUP_1, OpToIndex(0x81), 5), 1, &OpDispatchBuilder::SecondaryALUOp}, @@ -27,7 +27,7 @@ constexpr DispatchTableEntry OpDispatch_PrimaryGroupTables[] = { {OPD(FEXCore::X86Tables::TYPE_GROUP_1, OpToIndex(0x83), 0), 1, &OpDispatchBuilder::SecondaryALUOp}, {OPD(FEXCore::X86Tables::TYPE_GROUP_1, OpToIndex(0x83), 1), 1, &OpDispatchBuilder::SecondaryALUOp}, - {OPD(FEXCore::X86Tables::TYPE_GROUP_1, OpToIndex(0x83), 2), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::ADCOp, 1>}, + {OPD(FEXCore::X86Tables::TYPE_GROUP_1, OpToIndex(0x83), 2), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::ADCOp, 1, false>}, {OPD(FEXCore::X86Tables::TYPE_GROUP_1, OpToIndex(0x83), 3), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::SBBOp, 1>}, {OPD(FEXCore::X86Tables::TYPE_GROUP_1, OpToIndex(0x83), 4), 1, &OpDispatchBuilder::SecondaryALUOp}, {OPD(FEXCore::X86Tables::TYPE_GROUP_1, OpToIndex(0x83), 5), 1, &OpDispatchBuilder::SecondaryALUOp}, diff --git a/FEXCore/Source/Interface/Core/X86Tables/BaseTables.cpp b/FEXCore/Source/Interface/Core/X86Tables/BaseTables.cpp index 896b6632c..fa2fcaf3f 100644 --- a/FEXCore/Source/Interface/Core/X86Tables/BaseTables.cpp +++ b/FEXCore/Source/Interface/Core/X86Tables/BaseTables.cpp @@ -222,8 +222,8 @@ const std::array BaseOps = []() consteval { {0x11, 1, X86InstInfo{"ADC", TYPE_INST, FLAGS_MODRM | FLAGS_SF_MOD_DST | FLAGS_DISPLACE_SIZE_DIV_2 | FLAGS_SUPPORTS_LOCK, 0}}, {0x12, 1, X86InstInfo{"ADC", TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_MODRM, 0}}, {0x13, 1, X86InstInfo{"ADC", TYPE_INST, FLAGS_MODRM, 0}}, - {0x14, 1, X86InstInfo{"ADC", TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_SF_DST_RAX , 1}}, - {0x15, 1, X86InstInfo{"ADC", TYPE_INST, FLAGS_SF_DST_RAX | FLAGS_SRC_SEXT | FLAGS_DISPLACE_SIZE_DIV_2 | FLAGS_LITERAL_PATCHABLE, 4}}, + {0x14, 1, X86InstInfo{"ADC", TYPE_INST, GenFlagsSameSize(SIZE_8BIT), 1}}, + {0x15, 1, X86InstInfo{"ADC", TYPE_INST, FLAGS_SRC_SEXT | FLAGS_DISPLACE_SIZE_DIV_2 | FLAGS_LITERAL_PATCHABLE, 4}}, {0x16, 1, X86InstInfo{"", TYPE_ARCH_DISPATCHER, FLAGS_NONE, 0, { .Indirect = Primary_ArchSelect_LUT[ENTRY_16] }}}, {0x17, 1, X86InstInfo{"", TYPE_ARCH_DISPATCHER, FLAGS_NONE, 0, { .Indirect = Primary_ArchSelect_LUT[ENTRY_17] }}}, diff --git a/FEXCore/Source/Interface/Core/X86Tables/PrimaryGroupTables.cpp b/FEXCore/Source/Interface/Core/X86Tables/PrimaryGroupTables.cpp index 7b3ac484a..b697a1a49 100644 --- a/FEXCore/Source/Interface/Core/X86Tables/PrimaryGroupTables.cpp +++ b/FEXCore/Source/Interface/Core/X86Tables/PrimaryGroupTables.cpp @@ -36,7 +36,7 @@ constexpr std::array PrimaryGroup_ArchSelect_LUT = {{ {"", TYPE_INVALID, FLAGS_NONE, 0, { .OpDispatch = nullptr } }, }, { - {"ADC", TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_MODRM | FLAGS_SF_MOD_DST | FLAGS_SUPPORTS_LOCK, 1, { .OpDispatch = &IR::OpDispatchBuilder::Bind<&IR::OpDispatchBuilder::ADCOp, 1> }}, + {"ADC", TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_MODRM | FLAGS_SF_MOD_DST | FLAGS_SUPPORTS_LOCK, 1, { .OpDispatch = &IR::OpDispatchBuilder::Bind<&IR::OpDispatchBuilder::ADCOp, 1, false> }}, {"", TYPE_INVALID, FLAGS_NONE, 0, { .OpDispatch = nullptr } }, }, {