diff --git a/unittests/InstructionCountCI/FlagM/HotBlocks.json b/unittests/InstructionCountCI/FlagM/HotBlocks.json
index c12cd6a5e..fa606875e 100644
--- a/unittests/InstructionCountCI/FlagM/HotBlocks.json
+++ b/unittests/InstructionCountCI/FlagM/HotBlocks.json
@@ -428,6 +428,198 @@
         "mov x11, x26"
       ]
     },
+    "glibc AVX memcpy block 1": {
+      "ExpectedInstructionCount": 43,
+      "x86Insts": [
+        "vmovdqu ymm5,yword [rsi+0x20]",
+        "vmovdqu ymm6,yword [rsi+0x40]",
+        "lea    rcx,[rdi+rdx*1-0x81]",
+        "vmovdqu ymm7,yword [rsi+0x60]",
+        "vmovdqu ymm8,yword [rsi+rdx*1-0x20]",
+        "sub    rsi,rdi",
+        "and    rcx,0xffffffffffffffe0",
+        "add    rsi,rcx",
+        "nop    dword [rax+0x0]",
+        "vmovdqu ymm1,yword [rsi+0x60]",
+        "vmovdqu ymm2,yword [rsi+0x40]",
+        "vmovdqu ymm3,yword [rsi+0x20]",
+        "vmovdqu ymm4,yword [rsi]",
+        "add    rsi,0xffffffffffffff80",
+        "vmovdqa yword [rcx+0x60],ymm1",
+        "vmovdqa yword [rcx+0x40],ymm2",
+        "vmovdqa yword [rcx+0x20],ymm3",
+        "vmovdqa yword [rcx],ymm4",
+        "add    rcx,0xffffffffffffff80",
+        "cmp    rdi,rcx"
+      ],
+      "ExpectedArm64ASM": [
+        "ldr q21, [x10, #32]",
+        "ldr q2, [x10, #48]",
+        "ldr q22, [x10, #64]",
+        "ldr q3, [x10, #80]",
+        "sub x20, x11, #0x81 (129)",
+        "add x5, x20, x6",
+        "ldr q23, [x10, #96]",
+        "ldr q4, [x10, #112]",
+        "add x20, x10, x6",
+        "ldur q24, [x20, #-32]",
+        "add x20, x10, x6",
+        "ldur q5, [x20, #-16]",
+        "sub x10, x10, x11",
+        "and x5, x5, #0xffffffffffffffe0",
+        "add x10, x10, x5",
+        "ldr q17, [x10, #96]",
+        "ldr q6, [x10, #112]",
+        "ldr q18, [x10, #64]",
+        "ldr q7, [x10, #80]",
+        "ldr q19, [x10, #32]",
+        "ldr q8, [x10, #48]",
+        "ldr q20, [x10]",
+        "ldr q9, [x10, #16]",
+        "sub x10, x10, #0x80 (128)",
+        "str q17, [x5, #96]",
+        "str q6, [x5, #112]",
+        "str q18, [x5, #64]",
+        "str q7, [x5, #80]",
+        "str q19, [x5, #32]",
+        "str q8, [x5, #48]",
+        "str q20, [x5]",
+        "str q9, [x5, #16]",
+        "sub x5, x5, #0x80 (128)",
+        "eor w27, w11, w5",
+        "subs x26, x11, x5",
+        "str q5, [x28, #144]",
+        "str q4, [x28, #128]",
+        "str q3, [x28, #112]",
+        "str q2, [x28, #96]",
+        "str q9, [x28, #80]",
+        "str q8, [x28, #64]",
+        "str q7, [x28, #48]",
+        "str q6, [x28, #32]"
+      ]
+    },
+    "glibc AVX memcpy block 2": {
+      "ExpectedInstructionCount": 51,
+      "x86Insts": [
+        "vmovdqu ymm5,yword [rsi+rdx*1-0x20]",
+        "vmovdqu ymm6,yword [rsi+rdx*1-0x40]",
+        "mov    rcx,rdi",
+        "or     rdi,0x1f",
+        "vmovdqu ymm7,yword [rsi+rdx*1-0x60]",
+        "vmovdqu ymm8,yword [rsi+rdx*1-0x80]",
+        "sub    rsi,rcx",
+        "inc    rdi",
+        "add    rsi,rdi",
+        "lea    rdx,[rcx+rdx*1-0x80]",
+        "nop    dword [rax+rax*1+0x0]",
+        "vmovdqu ymm1,yword [rsi]",
+        "vmovdqu ymm2,yword [rsi+0x20]",
+        "vmovdqu ymm3,yword [rsi+0x40]",
+        "vmovdqu ymm4,yword [rsi+0x60]",
+        "sub    rsi,0xffffffffffffff80",
+        "vmovdqa yword [rdi],ymm1",
+        "vmovdqa yword [rdi+0x20],ymm2",
+        "vmovdqa yword [rdi+0x40],ymm3",
+        "vmovdqa yword [rdi+0x60],ymm4",
+        "sub    rdi,0xffffffffffffff80",
+        "cmp    rdx,rdi"
+      ],
+      "ExpectedArm64ASM": [
+        "add x20, x10, x6",
+        "ldur q21, [x20, #-32]",
+        "add x20, x10, x6",
+        "ldur q2, [x20, #-16]",
+        "add x20, x10, x6",
+        "ldur q22, [x20, #-64]",
+        "add x20, x10, x6",
+        "ldur q3, [x20, #-48]",
+        "mov x5, x11",
+        "orr x11, x11, #0x1f",
+        "add x20, x10, x6",
+        "ldur q23, [x20, #-96]",
+        "add x20, x10, x6",
+        "ldur q4, [x20, #-80]",
+        "add x20, x10, x6",
+        "ldur q24, [x20, #-128]",
+        "add x20, x10, x6",
+        "ldur q5, [x20, #-112]",
+        "sub x10, x10, x5",
+        "add x11, x11, #0x1 (1)",
+        "add x10, x10, x11",
+        "sub x20, x5, #0x80 (128)",
+        "add x6, x20, x6",
+        "ldr q17, [x10]",
+        "ldr q6, [x10, #16]",
+        "ldr q18, [x10, #32]",
+        "ldr q7, [x10, #48]",
+        "ldr q19, [x10, #64]",
+        "ldr q8, [x10, #80]",
+        "ldr q20, [x10, #96]",
+        "ldr q9, [x10, #112]",
+        "add x10, x10, #0x80 (128)",
+        "str q17, [x11]",
+        "str q6, [x11, #16]",
+        "str q18, [x11, #32]",
+        "str q7, [x11, #48]",
+        "str q19, [x11, #64]",
+        "str q8, [x11, #80]",
+        "str q20, [x11, #96]",
+        "str q9, [x11, #112]",
+        "add x11, x11, #0x80 (128)",
+        "eor w27, w6, w11",
+        "subs x26, x6, x11",
+        "str q5, [x28, #144]",
+        "str q4, [x28, #128]",
+        "str q3, [x28, #112]",
+        "str q2, [x28, #96]",
+        "str q9, [x28, #80]",
+        "str q8, [x28, #64]",
+        "str q7, [x28, #48]",
+        "str q6, [x28, #32]"
+      ]
+    },
+    "bytemark strsift": {
+      "ExpectedInstructionCount": 20,
+      "x86Insts": [
+        "mov    rsi,rdx",
+        "and    rsi,0xfffffffffffffffc",
+        "movq   xmm0,rcx",
+        "pshufd xmm0,xmm0,0x44",
+        "mov    rdi,qword [rsp+0x20]",
+        "lea    rdi,[rdi+r13*8]",
+        "xor    r8d,r8d",
+        "movdqu xmm1,oword [rdi+r8*8-0x10]",
+        "movdqu xmm2,oword [rdi+r8*8]",
+        "paddq  xmm1,xmm0",
+        "paddq  xmm2,xmm0",
+        "movdqu oword [rdi+r8*8-0x10],xmm1",
+        "movdqu oword [rdi+r8*8],xmm2",
+        "add    r8,0x4",
+        "cmp    rsi,r8"
+      ],
+      "ExpectedArm64ASM": [
+        "mov x10, x6",
+        "and x10, x10, #0xfffffffffffffffc",
+        "fmov d16, x5",
+        "dup v16.2d, v16.d[0]",
+        "ldr x11, [x8, #32]",
+        "add x11, x11, x17, lsl #3",
+        "mov w12, #0x0",
+        "add x20, x11, x12, lsl #3",
+        "ldur q17, [x20, #-16]",
+        "add x20, x11, x12, lsl #3",
+        "ldr q18, [x20]",
+        "add v17.2d, v17.2d, v16.2d",
+        "add v18.2d, v18.2d, v16.2d",
+        "add x20, x11, x12, lsl #3",
+        "stur q17, [x20, #-16]",
+        "add x20, x11, x12, lsl #3",
+        "str q18, [x20]",
+        "add x12, x12, #0x4 (4)",
+        "eor w27, w10, w12",
+        "subs x26, x10, x12"
+      ]
+    },
     "pcmpistri xmm0, xmm1, 0_0_00_11_01b": {
       "ExpectedInstructionCount": 41,
       "Comment": [