From 76bd81af1511e070a6bb351de2ae77cc672b50cc Mon Sep 17 00:00:00 2001 From: Ryan Houdek Date: Tue, 12 Sep 2023 05:02:44 -0700 Subject: [PATCH 1/2] FEXCore: Defer setting x87 softflow rounding mode until use Currently FEX will always jump out of the JIT any time FCW was getting written to, ensuring that the softfloat state is setup to rounding at the time of FCW getting written. This has the unintended side-effect that even in "x87 reduced precision" mode we were jumping out of the JIT. This hit a real world use case of an installer reloading FCW after every x87 operation and generating a block with 2297 instructions. Instead when jumping out of the JIT for handling x87 operations, load FCW and pass it as the first argument of the handler. Setting the softfloat state at that point. This helps the installer's hottest block by cutting it down to 1477 instructions. 64.3% of the original size. The code block is still burning 90% of the CPU time of the installer but the performance is significantly better while it is doing its decompression. In order to optimize this installer's block of code more then we will likely need to optimize out x87 stack usage. --- .../Interface/Core/Interpreter/F80Ops.cpp | 138 +++-------- .../Core/Interpreter/Fallbacks/F80Fallbacks.h | 184 ++++++++------ .../Fallbacks/InterpreterFallbacks.cpp | 67 +++--- .../Core/Interpreter/InterpreterOps.cpp | 1 - .../Core/Interpreter/InterpreterOps.h | 29 ++- .../Source/Interface/Core/JIT/Arm64/JIT.cpp | 227 +++++++++--------- .../Source/Interface/Core/JIT/x86_64/JIT.cpp | 96 ++++---- .../Core/OpcodeDispatcher/Vector.cpp | 1 - .../Interface/Core/OpcodeDispatcher/X87.cpp | 4 - .../Core/OpcodeDispatcher/X87F64.cpp | 5 - FEXCore/Source/Interface/IR/IR.json | 3 - 11 files changed, 344 insertions(+), 411 deletions(-) diff --git a/FEXCore/Source/Interface/Core/Interpreter/F80Ops.cpp b/FEXCore/Source/Interface/Core/Interpreter/F80Ops.cpp index 0569d465a..f223e6375 100644 --- a/FEXCore/Source/Interface/Core/Interpreter/F80Ops.cpp +++ b/FEXCore/Source/Interface/Core/Interpreter/F80Ops.cpp @@ -14,15 +14,11 @@ $end_info$ namespace FEXCore::CPU { #define DEF_OP(x) void InterpreterOps::Op_##x(IR::IROp_Header *IROp, IROpData *Data, IR::NodeID Node) -DEF_OP(F80LOADFCW) { - FEXCore::CPU::OpHandlers::handle(*GetSrc(Data->SSAData, IROp->Args[0])); -} - DEF_OP(F80ADD) { auto Op = IROp->C(); const auto Src1 = *GetSrc(Data->SSAData, Op->X80Src1); const auto Src2 = *GetSrc(Data->SSAData, Op->X80Src2); - const auto Tmp = X80SoftFloat::FADD(Src1, Src2); + const auto Tmp = CPU::OpHandlers::handle(Data->State->CurrentFrame->State.FCW, Src1, Src2); memcpy(GDP, &Tmp, sizeof(X80SoftFloat)); } @@ -31,7 +27,7 @@ DEF_OP(F80SUB) { auto Op = IROp->C(); const auto Src1 = *GetSrc(Data->SSAData, Op->X80Src1); const auto Src2 = *GetSrc(Data->SSAData, Op->X80Src2); - const auto Tmp = X80SoftFloat::FSUB(Src1, Src2); + const auto Tmp = CPU::OpHandlers::handle(Data->State->CurrentFrame->State.FCW, Src1, Src2); memcpy(GDP, &Tmp, sizeof(X80SoftFloat)); } @@ -40,7 +36,7 @@ DEF_OP(F80MUL) { auto Op = IROp->C(); const auto Src1 = *GetSrc(Data->SSAData, Op->X80Src1); const auto Src2 = *GetSrc(Data->SSAData, Op->X80Src2); - const auto Tmp = X80SoftFloat::FMUL(Src1, Src2); + const auto Tmp = CPU::OpHandlers::handle(Data->State->CurrentFrame->State.FCW, Src1, Src2); memcpy(GDP, &Tmp, sizeof(X80SoftFloat)); } @@ -49,7 +45,7 @@ DEF_OP(F80DIV) { auto Op = IROp->C(); const auto Src1 = *GetSrc(Data->SSAData, Op->X80Src1); const auto Src2 = *GetSrc(Data->SSAData, Op->X80Src2); - const auto Tmp = X80SoftFloat::FDIV(Src1, Src2); + const auto Tmp = CPU::OpHandlers::handle(Data->State->CurrentFrame->State.FCW, Src1, Src2); memcpy(GDP, &Tmp, sizeof(X80SoftFloat)); } @@ -58,7 +54,7 @@ DEF_OP(F80FYL2X) { auto Op = IROp->C(); const auto Src1 = *GetSrc(Data->SSAData, Op->X80Src1); const auto Src2 = *GetSrc(Data->SSAData, Op->X80Src2); - const auto Tmp = X80SoftFloat::FYL2X(Src1, Src2); + const auto Tmp = CPU::OpHandlers::handle(Data->State->CurrentFrame->State.FCW, Src1, Src2); memcpy(GDP, &Tmp, sizeof(X80SoftFloat)); } @@ -67,7 +63,7 @@ DEF_OP(F80ATAN) { auto Op = IROp->C(); const auto Src1 = *GetSrc(Data->SSAData, Op->X80Src1); const auto Src2 = *GetSrc(Data->SSAData, Op->X80Src2); - const auto Tmp = X80SoftFloat::FATAN(Src1, Src2); + const auto Tmp = CPU::OpHandlers::handle(Data->State->CurrentFrame->State.FCW, Src1, Src2); memcpy(GDP, &Tmp, sizeof(X80SoftFloat)); } @@ -76,7 +72,7 @@ DEF_OP(F80FPREM1) { auto Op = IROp->C(); const auto Src1 = *GetSrc(Data->SSAData, Op->X80Src1); const auto Src2 = *GetSrc(Data->SSAData, Op->X80Src2); - const auto Tmp = X80SoftFloat::FREM1(Src1, Src2); + const auto Tmp = CPU::OpHandlers::handle(Data->State->CurrentFrame->State.FCW, Src1, Src2); memcpy(GDP, &Tmp, sizeof(X80SoftFloat)); } @@ -85,7 +81,7 @@ DEF_OP(F80FPREM) { auto Op = IROp->C(); const auto Src1 = *GetSrc(Data->SSAData, Op->X80Src1); const auto Src2 = *GetSrc(Data->SSAData, Op->X80Src2); - const auto Tmp = X80SoftFloat::FREM(Src1, Src2); + const auto Tmp = CPU::OpHandlers::handle(Data->State->CurrentFrame->State.FCW, Src1, Src2); memcpy(GDP, &Tmp, sizeof(X80SoftFloat)); } @@ -94,7 +90,7 @@ DEF_OP(F80SCALE) { auto Op = IROp->C(); const auto Src1 = *GetSrc(Data->SSAData, Op->X80Src1); const auto Src2 = *GetSrc(Data->SSAData, Op->X80Src2); - const auto Tmp = X80SoftFloat::FSCALE(Src1, Src2); + const auto Tmp = CPU::OpHandlers::handle(Data->State->CurrentFrame->State.FCW, Src1, Src2); memcpy(GDP, &Tmp, sizeof(X80SoftFloat)); } @@ -107,12 +103,12 @@ DEF_OP(F80CVT) { switch (OpSize) { case 4: { - float Tmp = Src; + const auto Tmp = CPU::OpHandlers::handle4(Data->State->CurrentFrame->State.FCW, Src); memcpy(GDP, &Tmp, OpSize); break; } case 8: { - double Tmp = Src; + const auto Tmp = CPU::OpHandlers::handle8(Data->State->CurrentFrame->State.FCW, Src); memcpy(GDP, &Tmp, OpSize); break; } @@ -128,17 +124,17 @@ DEF_OP(F80CVTINT) { switch (OpSize) { case 2: { - int16_t Tmp = (Op->Truncate? FEXCore::CPU::OpHandlers::handle2t : FEXCore::CPU::OpHandlers::handle2)(Src); + int16_t Tmp = (Op->Truncate? FEXCore::CPU::OpHandlers::handle2t : FEXCore::CPU::OpHandlers::handle2)(Data->State->CurrentFrame->State.FCW, Src); memcpy(GDP, &Tmp, sizeof(Tmp)); break; } case 4: { - int32_t Tmp = (Op->Truncate? FEXCore::CPU::OpHandlers::handle4t : FEXCore::CPU::OpHandlers::handle4)(Src); + int32_t Tmp = (Op->Truncate? FEXCore::CPU::OpHandlers::handle4t : FEXCore::CPU::OpHandlers::handle4)(Data->State->CurrentFrame->State.FCW, Src); memcpy(GDP, &Tmp, sizeof(Tmp)); break; } case 8: { - int64_t Tmp = (Op->Truncate? FEXCore::CPU::OpHandlers::handle8t : FEXCore::CPU::OpHandlers::handle8)(Src); + int64_t Tmp = (Op->Truncate? FEXCore::CPU::OpHandlers::handle8t : FEXCore::CPU::OpHandlers::handle8)(Data->State->CurrentFrame->State.FCW, Src); memcpy(GDP, &Tmp, sizeof(Tmp)); break; } @@ -152,13 +148,13 @@ DEF_OP(F80CVTTO) { switch (Op->SrcSize) { case 4: { float Src = *GetSrc(Data->SSAData, Op->X80Src); - X80SoftFloat Tmp = Src; + const auto Tmp = CPU::OpHandlers::handle4(Data->State->CurrentFrame->State.FCW, Src); memcpy(GDP, &Tmp, sizeof(X80SoftFloat)); break; } case 8: { double Src = *GetSrc(Data->SSAData, Op->X80Src); - X80SoftFloat Tmp = Src; + const auto Tmp = CPU::OpHandlers::handle8(Data->State->CurrentFrame->State.FCW, Src); memcpy(GDP, &Tmp, sizeof(X80SoftFloat)); break; } @@ -172,13 +168,13 @@ DEF_OP(F80CVTTOINT) { switch (Op->SrcSize) { case 2: { int16_t Src = *GetSrc(Data->SSAData, Op->Src); - X80SoftFloat Tmp = Src; + const auto Tmp = CPU::OpHandlers::handle2(Data->State->CurrentFrame->State.FCW, Src); memcpy(GDP, &Tmp, sizeof(X80SoftFloat)); break; } case 4: { int32_t Src = *GetSrc(Data->SSAData, Op->Src); - X80SoftFloat Tmp = Src; + const auto Tmp = CPU::OpHandlers::handle4(Data->State->CurrentFrame->State.FCW, Src); memcpy(GDP, &Tmp, sizeof(X80SoftFloat)); break; } @@ -189,7 +185,7 @@ DEF_OP(F80CVTTOINT) { DEF_OP(F80ROUND) { auto Op = IROp->C(); const auto Src = *GetSrc(Data->SSAData, Op->X80Src); - const auto Tmp = X80SoftFloat::FRNDINT(Src); + const auto Tmp = CPU::OpHandlers::handle(Data->State->CurrentFrame->State.FCW, Src); memcpy(GDP, &Tmp, sizeof(X80SoftFloat)); } @@ -197,7 +193,7 @@ DEF_OP(F80ROUND) { DEF_OP(F80F2XM1) { auto Op = IROp->C(); const auto Src = *GetSrc(Data->SSAData, Op->X80Src); - const auto Tmp = X80SoftFloat::F2XM1(Src); + const auto Tmp = CPU::OpHandlers::handle(Data->State->CurrentFrame->State.FCW, Src); memcpy(GDP, &Tmp, sizeof(X80SoftFloat)); } @@ -205,7 +201,7 @@ DEF_OP(F80F2XM1) { DEF_OP(F80TAN) { auto Op = IROp->C(); const auto Src = *GetSrc(Data->SSAData, Op->X80Src); - const auto Tmp = X80SoftFloat::FTAN(Src); + const auto Tmp = CPU::OpHandlers::handle(Data->State->CurrentFrame->State.FCW, Src); memcpy(GDP, &Tmp, sizeof(X80SoftFloat)); } @@ -213,7 +209,7 @@ DEF_OP(F80TAN) { DEF_OP(F80SQRT) { auto Op = IROp->C(); const auto Src = *GetSrc(Data->SSAData, Op->X80Src); - const auto Tmp = X80SoftFloat::FSQRT(Src); + const auto Tmp = CPU::OpHandlers::handle(Data->State->CurrentFrame->State.FCW, Src); memcpy(GDP, &Tmp, sizeof(X80SoftFloat)); } @@ -221,7 +217,7 @@ DEF_OP(F80SQRT) { DEF_OP(F80SIN) { auto Op = IROp->C(); const auto Src = *GetSrc(Data->SSAData, Op->X80Src); - const auto Tmp = X80SoftFloat::FSIN(Src); + const auto Tmp = CPU::OpHandlers::handle(Data->State->CurrentFrame->State.FCW, Src); memcpy(GDP, &Tmp, sizeof(X80SoftFloat)); } @@ -229,7 +225,7 @@ DEF_OP(F80SIN) { DEF_OP(F80COS) { auto Op = IROp->C(); const auto Src = *GetSrc(Data->SSAData, Op->X80Src); - const auto Tmp = X80SoftFloat::FCOS(Src); + const auto Tmp = CPU::OpHandlers::handle(Data->State->CurrentFrame->State.FCW, Src); memcpy(GDP, &Tmp, sizeof(X80SoftFloat)); } @@ -237,7 +233,7 @@ DEF_OP(F80COS) { DEF_OP(F80XTRACT_EXP) { auto Op = IROp->C(); const auto Src = *GetSrc(Data->SSAData, Op->X80Src); - const auto Tmp = X80SoftFloat::FXTRACT_EXP(Src); + const auto Tmp = CPU::OpHandlers::handle(Data->State->CurrentFrame->State.FCW, Src); memcpy(GDP, &Tmp, sizeof(X80SoftFloat)); } @@ -245,102 +241,32 @@ DEF_OP(F80XTRACT_EXP) { DEF_OP(F80XTRACT_SIG) { auto Op = IROp->C(); const auto Src = *GetSrc(Data->SSAData, Op->X80Src); - const auto Tmp = X80SoftFloat::FXTRACT_SIG(Src); + const auto Tmp = CPU::OpHandlers::handle(Data->State->CurrentFrame->State.FCW, Src); memcpy(GDP, &Tmp, sizeof(X80SoftFloat)); } DEF_OP(F80CMP) { auto Op = IROp->C(); - uint32_t ResultFlags{}; const auto Src1 = *GetSrc(Data->SSAData, Op->X80Src1); const auto Src2 = *GetSrc(Data->SSAData, Op->X80Src2); - bool eq, lt, nan; - X80SoftFloat::FCMP(Src1, Src2, &eq, <, &nan); - if (Op->Flags & (1 << IR::FCMP_FLAG_LT) && - lt) { - ResultFlags |= (1 << IR::FCMP_FLAG_LT); - } - if (Op->Flags & (1 << IR::FCMP_FLAG_UNORDERED) && - nan) { - ResultFlags |= (1 << IR::FCMP_FLAG_UNORDERED); - } - if (Op->Flags & (1 << IR::FCMP_FLAG_EQ) && - eq) { - ResultFlags |= (1 << IR::FCMP_FLAG_EQ); - } + const auto ResultFlags = CPU::OpHandlers::handle(Data->State->CurrentFrame->State.FCW, Src1, Src2); GD = ResultFlags; } DEF_OP(F80BCDLOAD) { auto Op = IROp->C(); - const uint8_t *Src1 = GetSrc(Data->SSAData, Op->X80Src); - uint64_t BCD{}; - // We walk through each uint8_t and pull out the BCD encoding - // Each 4bit split is a digit - // Only 0-9 is supported, A-F results in undefined data - // | 4 bit | 4 bit | - // | 10s place | 1s place | - // EG 0x48 = 48 - // EG 0x4847 = 4847 - // This gives us an 18digit value encoded in BCD - // The last byte lets us know if it negative or not - for (size_t i = 0; i < 9; ++i) { - uint8_t Digit = Src1[8 - i]; - // First shift our last value over - BCD *= 100; - - // Add the tens place digit - BCD += (Digit >> 4) * 10; - - // Add the ones place digit - BCD += Digit & 0xF; - } - - // Set negative flag once converted to x87 - bool Negative = Src1[9] & 0x80; - X80SoftFloat Tmp; - - Tmp = BCD; - Tmp.Sign = Negative; - + const auto Src = *GetSrc(Data->SSAData, Op->X80Src); + const auto Tmp = CPU::OpHandlers::handle(Data->State->CurrentFrame->State.FCW, Src); memcpy(GDP, &Tmp, sizeof(X80SoftFloat)); } DEF_OP(F80BCDSTORE) { auto Op = IROp->C(); - X80SoftFloat Src1 = X80SoftFloat::FRNDINT(*GetSrc(Data->SSAData, Op->X80Src)); - bool Negative = Src1.Sign; - - // Clear the Sign bit - Src1.Sign = 0; - - uint64_t Tmp = Src1; - uint8_t BCD[10]{}; - - for (size_t i = 0; i < 9; ++i) { - if (Tmp == 0) { - // Nothing left? Just leave - break; - } - // Extract the lower 100 values - uint8_t Digit = Tmp % 100; - - // Now divide it for the next iteration - Tmp /= 100; - - uint8_t UpperNibble = Digit / 10; - uint8_t LowerNibble = Digit % 10; - - // Now store the BCD - BCD[i] = (UpperNibble << 4) | LowerNibble; - } - - // Set negative flag once converted to x87 - BCD[9] = Negative ? 0x80 : 0; - - memcpy(GDP, BCD, 10); + const auto Src = *GetSrc(Data->SSAData, Op->X80Src); + const auto Tmp = CPU::OpHandlers::handle(Data->State->CurrentFrame->State.FCW, Src); + memcpy(GDP, &Tmp, sizeof(X80SoftFloat)); } DEF_OP(F64SIN) { diff --git a/FEXCore/Source/Interface/Core/Interpreter/Fallbacks/F80Fallbacks.h b/FEXCore/Source/Interface/Core/Interpreter/Fallbacks/F80Fallbacks.h index efea1a24c..a31b5f657 100644 --- a/FEXCore/Source/Interface/Core/Interpreter/Fallbacks/F80Fallbacks.h +++ b/FEXCore/Source/Interface/Core/Interpreter/Fallbacks/F80Fallbacks.h @@ -7,13 +7,41 @@ #include "Interface/Core/Interpreter/Fallbacks/FallbackOpHandler.h" namespace FEXCore::CPU { +static void LoadDeferredFCW(uint16_t NewFCW) { + auto PC = (NewFCW >> 8) & 3; + switch(PC) { + case 0: extF80_roundingPrecision = 32; break; + case 2: extF80_roundingPrecision = 64; break; + case 3: extF80_roundingPrecision = 80; break; + case 1: LOGMAN_MSG_A_FMT("Invalid x87 precision mode, {}", PC); + } + + auto RC = (NewFCW >> 10) & 3; + switch(RC) { + case 0: + softfloat_roundingMode = softfloat_round_near_even; + break; + case 1: + softfloat_roundingMode = softfloat_round_min; + break; + case 2: + softfloat_roundingMode = softfloat_round_max; + break; + case 3: + softfloat_roundingMode = softfloat_round_minMag; + break; + } +} + template<> struct OpHandlers { - static X80SoftFloat handle4(float src) { + static X80SoftFloat handle4(uint16_t NewFCW, float src) { + LoadDeferredFCW(NewFCW); return src; } - static X80SoftFloat handle8(double src) { + static X80SoftFloat handle8(uint16_t NewFCW, double src) { + LoadDeferredFCW(NewFCW); return src; } }; @@ -21,7 +49,9 @@ struct OpHandlers { template<> struct OpHandlers { template - static uint64_t handle(X80SoftFloat Src1, X80SoftFloat Src2) { + static uint64_t handle(uint16_t NewFCW, X80SoftFloat Src1, X80SoftFloat Src2) { + LoadDeferredFCW(NewFCW); + bool eq, lt, nan; uint64_t ResultFlags = 0; @@ -44,30 +74,36 @@ struct OpHandlers { template<> struct OpHandlers { - static float handle4(X80SoftFloat src) { + static float handle4(uint16_t NewFCW, X80SoftFloat src) { + LoadDeferredFCW(NewFCW); return src; } - static double handle8(X80SoftFloat src) { + static double handle8(uint16_t NewFCW, X80SoftFloat src) { + LoadDeferredFCW(NewFCW); return src; } }; template<> struct OpHandlers { - static int16_t handle2(X80SoftFloat src) { + static int16_t handle2(uint16_t NewFCW, X80SoftFloat src) { + LoadDeferredFCW(NewFCW); return src; } - static int32_t handle4(X80SoftFloat src) { + static int32_t handle4(uint16_t NewFCW, X80SoftFloat src) { + LoadDeferredFCW(NewFCW); return src; } - static int64_t handle8(X80SoftFloat src) { + static int64_t handle8(uint16_t NewFCW, X80SoftFloat src) { + LoadDeferredFCW(NewFCW); return src; } - static int16_t handle2t(X80SoftFloat src) { + static int16_t handle2t(uint16_t NewFCW, X80SoftFloat src) { + LoadDeferredFCW(NewFCW); auto rv = extF80_to_i32(src, softfloat_round_minMag, false); if (rv > INT16_MAX) { @@ -79,216 +115,243 @@ struct OpHandlers { } } - static int32_t handle4t(X80SoftFloat src) { + static int32_t handle4t(uint16_t NewFCW, X80SoftFloat src) { + LoadDeferredFCW(NewFCW); return extF80_to_i32(src, softfloat_round_minMag, false); } - static int64_t handle8t(X80SoftFloat src) { + static int64_t handle8t(uint16_t NewFCW, X80SoftFloat src) { + LoadDeferredFCW(NewFCW); return extF80_to_i64(src, softfloat_round_minMag, false); } }; template<> struct OpHandlers { - static X80SoftFloat handle2(int16_t src) { + static X80SoftFloat handle2(uint16_t NewFCW, int16_t src) { + LoadDeferredFCW(NewFCW); return src; } - static X80SoftFloat handle4(int32_t src) { + static X80SoftFloat handle4(uint16_t NewFCW, int32_t src) { + LoadDeferredFCW(NewFCW); return src; } }; template<> struct OpHandlers { - static X80SoftFloat handle(X80SoftFloat Src1) { + static X80SoftFloat handle(uint16_t NewFCW, X80SoftFloat Src1) { + LoadDeferredFCW(NewFCW); return X80SoftFloat::FRNDINT(Src1); } }; template<> struct OpHandlers { - static X80SoftFloat handle(X80SoftFloat Src1) { + static X80SoftFloat handle(uint16_t NewFCW, X80SoftFloat Src1) { + LoadDeferredFCW(NewFCW); return X80SoftFloat::F2XM1(Src1); } }; template<> struct OpHandlers { - static X80SoftFloat handle(X80SoftFloat Src1) { + static X80SoftFloat handle(uint16_t NewFCW, X80SoftFloat Src1) { + LoadDeferredFCW(NewFCW); return X80SoftFloat::FTAN(Src1); } }; template<> struct OpHandlers { - static X80SoftFloat handle(X80SoftFloat Src1) { + static X80SoftFloat handle(uint16_t NewFCW, X80SoftFloat Src1) { + LoadDeferredFCW(NewFCW); return X80SoftFloat::FSQRT(Src1); } }; template<> struct OpHandlers { - static X80SoftFloat handle(X80SoftFloat Src1) { + static X80SoftFloat handle(uint16_t NewFCW, X80SoftFloat Src1) { + LoadDeferredFCW(NewFCW); return X80SoftFloat::FSIN(Src1); } }; template<> struct OpHandlers { - static X80SoftFloat handle(X80SoftFloat Src1) { + static X80SoftFloat handle(uint16_t NewFCW, X80SoftFloat Src1) { + LoadDeferredFCW(NewFCW); return X80SoftFloat::FCOS(Src1); } }; template<> struct OpHandlers { - static X80SoftFloat handle(X80SoftFloat Src1) { + static X80SoftFloat handle(uint16_t NewFCW, X80SoftFloat Src1) { + LoadDeferredFCW(NewFCW); return X80SoftFloat::FXTRACT_EXP(Src1); } }; template<> struct OpHandlers { - static X80SoftFloat handle(X80SoftFloat Src1) { + static X80SoftFloat handle(uint16_t NewFCW, X80SoftFloat Src1) { + LoadDeferredFCW(NewFCW); return X80SoftFloat::FXTRACT_SIG(Src1); } }; template<> struct OpHandlers { - static X80SoftFloat handle(X80SoftFloat Src1, X80SoftFloat Src2) { + static X80SoftFloat handle(uint16_t NewFCW, X80SoftFloat Src1, X80SoftFloat Src2) { + LoadDeferredFCW(NewFCW); return X80SoftFloat::FADD(Src1, Src2); } }; template<> struct OpHandlers { - static X80SoftFloat handle(X80SoftFloat Src1, X80SoftFloat Src2) { + static X80SoftFloat handle(uint16_t NewFCW, X80SoftFloat Src1, X80SoftFloat Src2) { + LoadDeferredFCW(NewFCW); return X80SoftFloat::FSUB(Src1, Src2); } }; template<> struct OpHandlers { - static X80SoftFloat handle(X80SoftFloat Src1, X80SoftFloat Src2) { + static X80SoftFloat handle(uint16_t NewFCW, X80SoftFloat Src1, X80SoftFloat Src2) { + LoadDeferredFCW(NewFCW); return X80SoftFloat::FMUL(Src1, Src2); } }; template<> struct OpHandlers { - static X80SoftFloat handle(X80SoftFloat Src1, X80SoftFloat Src2) { + static X80SoftFloat handle(uint16_t NewFCW, X80SoftFloat Src1, X80SoftFloat Src2) { + LoadDeferredFCW(NewFCW); return X80SoftFloat::FDIV(Src1, Src2); } }; - template<> struct OpHandlers { - static X80SoftFloat handle(X80SoftFloat Src1, X80SoftFloat Src2) { + static X80SoftFloat handle(uint16_t NewFCW, X80SoftFloat Src1, X80SoftFloat Src2) { + LoadDeferredFCW(NewFCW); return X80SoftFloat::FYL2X(Src1, Src2); } }; template<> struct OpHandlers { - static X80SoftFloat handle(X80SoftFloat Src1, X80SoftFloat Src2) { + static X80SoftFloat handle(uint16_t NewFCW, X80SoftFloat Src1, X80SoftFloat Src2) { + LoadDeferredFCW(NewFCW); return X80SoftFloat::FATAN(Src1, Src2); } }; template<> struct OpHandlers { - static X80SoftFloat handle(X80SoftFloat Src1, X80SoftFloat Src2) { + static X80SoftFloat handle(uint16_t NewFCW, X80SoftFloat Src1, X80SoftFloat Src2) { + LoadDeferredFCW(NewFCW); return X80SoftFloat::FREM1(Src1, Src2); } }; template<> struct OpHandlers { - static X80SoftFloat handle(X80SoftFloat Src1, X80SoftFloat Src2) { + static X80SoftFloat handle(uint16_t NewFCW, X80SoftFloat Src1, X80SoftFloat Src2) { + LoadDeferredFCW(NewFCW); return X80SoftFloat::FREM(Src1, Src2); } }; template<> struct OpHandlers { - static X80SoftFloat handle(X80SoftFloat Src1, X80SoftFloat Src2) { + static X80SoftFloat handle(uint16_t NewFCW, X80SoftFloat Src1, X80SoftFloat Src2) { + LoadDeferredFCW(NewFCW); return X80SoftFloat::FSCALE(Src1, Src2); } }; template<> struct OpHandlers { - static double handle(double src) { + static double handle(uint16_t NewFCW, double src) { + LoadDeferredFCW(NewFCW); return sin(src); } }; template<> struct OpHandlers { - static double handle(double src) { + static double handle(uint16_t NewFCW, double src) { + LoadDeferredFCW(NewFCW); return cos(src); } }; template<> struct OpHandlers { - static double handle(double src) { + static double handle(uint16_t NewFCW, double src) { + LoadDeferredFCW(NewFCW); return tan(src); } }; template<> struct OpHandlers { - static double handle(double src) { + static double handle(uint16_t NewFCW, double src) { + LoadDeferredFCW(NewFCW); return exp2(src) - 1.0; } }; template<> struct OpHandlers { - static double handle(double src1, double src2) { + static double handle(uint16_t NewFCW, double src1, double src2) { + LoadDeferredFCW(NewFCW); return atan2(src1, src2); } }; template<> struct OpHandlers { - static double handle(double src1, double src2) { + static double handle(uint16_t NewFCW, double src1, double src2) { + LoadDeferredFCW(NewFCW); return fmod(src1, src2); } }; template<> struct OpHandlers { - static double handle(double src1, double src2) { + static double handle(uint16_t NewFCW, double src1, double src2) { + LoadDeferredFCW(NewFCW); return remainder(src1, src2); } }; - template<> struct OpHandlers { - static double handle(double src1, double src2) { + static double handle(uint16_t NewFCW, double src1, double src2) { + LoadDeferredFCW(NewFCW); return src2 * log2(src1); } }; template<> struct OpHandlers { - static double handle(double src1, double src2) { + static double handle(uint16_t NewFCW, double src1, double src2) { + LoadDeferredFCW(NewFCW); double trunc = (double)(int64_t)(src2); //truncate return src1 * exp2(trunc); } }; - - template<> struct OpHandlers { - static X80SoftFloat handle(X80SoftFloat Src1) { + static X80SoftFloat handle(uint16_t NewFCW, X80SoftFloat Src1) { + LoadDeferredFCW(NewFCW); bool Negative = Src1.Sign; Src1 = X80SoftFloat::FRNDINT(Src1); @@ -328,7 +391,8 @@ struct OpHandlers { template<> struct OpHandlers { - static X80SoftFloat handle(X80SoftFloat Src) { + static X80SoftFloat handle(uint16_t NewFCW, X80SoftFloat Src) { + LoadDeferredFCW(NewFCW); uint8_t *Src1 = reinterpret_cast(&Src); uint64_t BCD{}; // We walk through each uint8_t and pull out the BCD encoding @@ -362,34 +426,4 @@ struct OpHandlers { } }; -template<> -struct OpHandlers { - static void handle(uint16_t NewFCW) { - - auto PC = (NewFCW >> 8) & 3; - switch(PC) { - case 0: extF80_roundingPrecision = 32; break; - case 2: extF80_roundingPrecision = 64; break; - case 3: extF80_roundingPrecision = 80; break; - case 1: LOGMAN_MSG_A_FMT("Invalid x87 precision mode, {}", PC); - } - - auto RC = (NewFCW >> 10) & 3; - switch(RC) { - case 0: - softfloat_roundingMode = softfloat_round_near_even; - break; - case 1: - softfloat_roundingMode = softfloat_round_min; - break; - case 2: - softfloat_roundingMode = softfloat_round_max; - break; - case 3: - softfloat_roundingMode = softfloat_round_minMag; - break; - } - } -}; - } // namespace FEXCore::CPU diff --git a/FEXCore/Source/Interface/Core/Interpreter/Fallbacks/InterpreterFallbacks.cpp b/FEXCore/Source/Interface/Core/Interpreter/Fallbacks/InterpreterFallbacks.cpp index 40b2095ed..460ec227f 100644 --- a/FEXCore/Source/Interface/Core/Interpreter/Fallbacks/InterpreterFallbacks.cpp +++ b/FEXCore/Source/Interface/Core/Interpreter/Fallbacks/InterpreterFallbacks.cpp @@ -15,78 +15,73 @@ static FallbackInfo GetFallbackInfo(R(*fn)(Args...), FEXCore::Core::FallbackHand } template<> -FallbackInfo GetFallbackInfo(X80SoftFloat(*fn)(float), FEXCore::Core::FallbackHandlerIndex HandlerIndex) { - return {FABI_F80_F32, (void*)fn, HandlerIndex}; +FallbackInfo GetFallbackInfo(X80SoftFloat(*fn)(uint16_t, float), FEXCore::Core::FallbackHandlerIndex HandlerIndex) { + return {FABI_F80_I16_F32, (void*)fn, HandlerIndex}; } template<> -FallbackInfo GetFallbackInfo(X80SoftFloat(*fn)(double), FEXCore::Core::FallbackHandlerIndex HandlerIndex) { - return {FABI_F80_F64, (void*)fn, HandlerIndex}; +FallbackInfo GetFallbackInfo(X80SoftFloat(*fn)(uint16_t, double), FEXCore::Core::FallbackHandlerIndex HandlerIndex) { + return {FABI_F80_I16_F64, (void*)fn, HandlerIndex}; } template<> -FallbackInfo GetFallbackInfo(X80SoftFloat(*fn)(int16_t), FEXCore::Core::FallbackHandlerIndex HandlerIndex) { - return {FABI_F80_I16, (void*)fn, HandlerIndex}; +FallbackInfo GetFallbackInfo(X80SoftFloat(*fn)(uint16_t, int16_t), FEXCore::Core::FallbackHandlerIndex HandlerIndex) { + return {FABI_F80_I16_I16, (void*)fn, HandlerIndex}; } template<> -FallbackInfo GetFallbackInfo(void(*fn)(uint16_t), FEXCore::Core::FallbackHandlerIndex HandlerIndex) { - return {FABI_VOID_U16, (void*)fn, HandlerIndex}; +FallbackInfo GetFallbackInfo(X80SoftFloat(*fn)(uint16_t, int32_t), FEXCore::Core::FallbackHandlerIndex HandlerIndex) { + return {FABI_F80_I16_I32, (void*)fn, HandlerIndex}; } template<> -FallbackInfo GetFallbackInfo(X80SoftFloat(*fn)(int32_t), FEXCore::Core::FallbackHandlerIndex HandlerIndex) { - return {FABI_F80_I32, (void*)fn, HandlerIndex}; +FallbackInfo GetFallbackInfo(float(*fn)(uint16_t, X80SoftFloat), FEXCore::Core::FallbackHandlerIndex HandlerIndex) { + return {FABI_F32_I16_F80, (void*)fn, HandlerIndex}; } template<> -FallbackInfo GetFallbackInfo(float(*fn)(X80SoftFloat), FEXCore::Core::FallbackHandlerIndex HandlerIndex) { - return {FABI_F32_F80, (void*)fn, HandlerIndex}; +FallbackInfo GetFallbackInfo(double(*fn)(uint16_t, X80SoftFloat), FEXCore::Core::FallbackHandlerIndex HandlerIndex) { + return {FABI_F64_I16_F80, (void*)fn, HandlerIndex}; } template<> -FallbackInfo GetFallbackInfo(double(*fn)(X80SoftFloat), FEXCore::Core::FallbackHandlerIndex HandlerIndex) { - return {FABI_F64_F80, (void*)fn, HandlerIndex}; +FallbackInfo GetFallbackInfo(double(*fn)(uint16_t, double), FEXCore::Core::FallbackHandlerIndex HandlerIndex) { + return {FABI_F64_I16_F64, (void*)fn, HandlerIndex}; } template<> -FallbackInfo GetFallbackInfo(double(*fn)(double), FEXCore::Core::FallbackHandlerIndex HandlerIndex) { - return {FABI_F64_F64, (void*)fn, HandlerIndex}; +FallbackInfo GetFallbackInfo(double(*fn)(uint16_t, double,double), FEXCore::Core::FallbackHandlerIndex HandlerIndex) { + return {FABI_F64_I16_F64_F64, (void*)fn, HandlerIndex}; } template<> -FallbackInfo GetFallbackInfo(double(*fn)(double,double), FEXCore::Core::FallbackHandlerIndex HandlerIndex) { - return {FABI_F64_F64_F64, (void*)fn, HandlerIndex}; +FallbackInfo GetFallbackInfo(int16_t(*fn)(uint16_t, X80SoftFloat), FEXCore::Core::FallbackHandlerIndex HandlerIndex) { + return {FABI_I16_I16_F80, (void*)fn, HandlerIndex}; } template<> -FallbackInfo GetFallbackInfo(int16_t(*fn)(X80SoftFloat), FEXCore::Core::FallbackHandlerIndex HandlerIndex) { - return {FABI_I16_F80, (void*)fn, HandlerIndex}; +FallbackInfo GetFallbackInfo(int32_t(*fn)(uint16_t, X80SoftFloat), FEXCore::Core::FallbackHandlerIndex HandlerIndex) { + return {FABI_I32_I16_F80, (void*)fn, HandlerIndex}; } template<> -FallbackInfo GetFallbackInfo(int32_t(*fn)(X80SoftFloat), FEXCore::Core::FallbackHandlerIndex HandlerIndex) { - return {FABI_I32_F80, (void*)fn, HandlerIndex}; +FallbackInfo GetFallbackInfo(int64_t(*fn)(uint16_t, X80SoftFloat), FEXCore::Core::FallbackHandlerIndex HandlerIndex) { + return {FABI_I64_I16_F80, (void*)fn, HandlerIndex}; } template<> -FallbackInfo GetFallbackInfo(int64_t(*fn)(X80SoftFloat), FEXCore::Core::FallbackHandlerIndex HandlerIndex) { - return {FABI_I64_F80, (void*)fn, HandlerIndex}; +FallbackInfo GetFallbackInfo(uint64_t(*fn)(uint16_t, X80SoftFloat, X80SoftFloat), FEXCore::Core::FallbackHandlerIndex HandlerIndex) { + return {FABI_I64_I16_F80_F80, (void*)fn, HandlerIndex}; } template<> -FallbackInfo GetFallbackInfo(uint64_t(*fn)(X80SoftFloat, X80SoftFloat), FEXCore::Core::FallbackHandlerIndex HandlerIndex) { - return {FABI_I64_F80_F80, (void*)fn, HandlerIndex}; +FallbackInfo GetFallbackInfo(X80SoftFloat(*fn)(uint16_t, X80SoftFloat), FEXCore::Core::FallbackHandlerIndex HandlerIndex) { + return {FABI_F80_I16_F80, (void*)fn, HandlerIndex}; } template<> -FallbackInfo GetFallbackInfo(X80SoftFloat(*fn)(X80SoftFloat), FEXCore::Core::FallbackHandlerIndex HandlerIndex) { - return {FABI_F80_F80, (void*)fn, HandlerIndex}; -} - -template<> -FallbackInfo GetFallbackInfo(X80SoftFloat(*fn)(X80SoftFloat, X80SoftFloat), FEXCore::Core::FallbackHandlerIndex HandlerIndex) { - return {FABI_F80_F80_F80, (void*)fn, HandlerIndex}; +FallbackInfo GetFallbackInfo(X80SoftFloat(*fn)(uint16_t, X80SoftFloat, X80SoftFloat), FEXCore::Core::FallbackHandlerIndex HandlerIndex) { + return {FABI_F80_I16_F80_F80, (void*)fn, HandlerIndex}; } template<> @@ -100,7 +95,6 @@ FallbackInfo GetFallbackInfo(uint32_t(*fn)(__uint128_t, __uint128_t, uint16_t), } void InterpreterOps::FillFallbackIndexPointers(uint64_t *Info) { - Info[Core::OPINDEX_F80LOADFCW] = reinterpret_cast(GetFallbackInfo(&FEXCore::CPU::OpHandlers::handle, Core::OPINDEX_F80LOADFCW).fn); Info[Core::OPINDEX_F80CVTTO_4] = reinterpret_cast(GetFallbackInfo(&FEXCore::CPU::OpHandlers::handle4, Core::OPINDEX_F80CVTTO_4).fn); Info[Core::OPINDEX_F80CVTTO_8] = reinterpret_cast(GetFallbackInfo(&FEXCore::CPU::OpHandlers::handle8, Core::OPINDEX_F80CVTTO_8).fn); Info[Core::OPINDEX_F80CVT_4] = reinterpret_cast(GetFallbackInfo(&FEXCore::CPU::OpHandlers::handle4, Core::OPINDEX_F80CVT_4).fn); @@ -164,11 +158,6 @@ void InterpreterOps::FillFallbackIndexPointers(uint64_t *Info) { bool InterpreterOps::GetFallbackHandler(IR::IROp_Header const *IROp, FallbackInfo *Info) { uint8_t OpSize = IROp->Size; switch(IROp->Op) { - case IR::OP_F80LOADFCW: { - *Info = GetFallbackInfo(&FEXCore::CPU::OpHandlers::handle, Core::OPINDEX_F80LOADFCW); - return true; - } - case IR::OP_F80CVTTO: { auto Op = IROp->C(); diff --git a/FEXCore/Source/Interface/Core/Interpreter/InterpreterOps.cpp b/FEXCore/Source/Interface/Core/Interpreter/InterpreterOps.cpp index 2f96f64fa..49e79dd4e 100644 --- a/FEXCore/Source/Interface/Core/Interpreter/InterpreterOps.cpp +++ b/FEXCore/Source/Interface/Core/Interpreter/InterpreterOps.cpp @@ -298,7 +298,6 @@ constexpr OpHandlerArray InterpreterOpHandlers = [] { REGISTER_OP(PCLMUL, PCLMUL); // F80 ops - REGISTER_OP(F80LOADFCW, F80LOADFCW); REGISTER_OP(F80ADD, F80ADD); REGISTER_OP(F80SUB, F80SUB); REGISTER_OP(F80MUL, F80MUL); diff --git a/FEXCore/Source/Interface/Core/Interpreter/InterpreterOps.h b/FEXCore/Source/Interface/Core/Interpreter/InterpreterOps.h index 604550017..b6a5cbc0e 100644 --- a/FEXCore/Source/Interface/Core/Interpreter/InterpreterOps.h +++ b/FEXCore/Source/Interface/Core/Interpreter/InterpreterOps.h @@ -24,21 +24,20 @@ namespace FEXCore::Core{ namespace FEXCore::CPU { enum FallbackABI { FABI_UNKNOWN, - FABI_VOID_U16, - FABI_F80_F32, - FABI_F80_F64, - FABI_F80_I16, - FABI_F80_I32, - FABI_F32_F80, - FABI_F64_F80, - FABI_F64_F64, - FABI_F64_F64_F64, - FABI_I16_F80, - FABI_I32_F80, - FABI_I64_F80, - FABI_I64_F80_F80, - FABI_F80_F80, - FABI_F80_F80_F80, + FABI_F80_I16_F32, + FABI_F80_I16_F64, + FABI_F80_I16_I16, + FABI_F80_I16_I32, + FABI_F32_I16_F80, + FABI_F64_I16_F80, + FABI_F64_I16_F64, + FABI_F64_I16_F64_F64, + FABI_I16_I16_F80, + FABI_I32_I16_F80, + FABI_I64_I16_F80, + FABI_I64_I16_F80_F80, + FABI_F80_I16_F80, + FABI_F80_I16_F80_F80, FABI_I32_I64_I64_I128_I128_I16, FABI_I32_I128_I128_I16, }; diff --git a/FEXCore/Source/Interface/Core/JIT/Arm64/JIT.cpp b/FEXCore/Source/Interface/Core/JIT/Arm64/JIT.cpp index 63a568aa6..735120dd9 100644 --- a/FEXCore/Source/Interface/Core/JIT/Arm64/JIT.cpp +++ b/FEXCore/Source/Interface/Core/JIT/Arm64/JIT.cpp @@ -83,37 +83,18 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) { #endif } else { switch(Info.ABI) { - case FABI_VOID_U16:{ - SpillStaticRegs(TMP1); - - PushDynamicRegsAndLR(TMP1); - - const auto Src1 = GetReg(IROp->Args[0].ID()); - uxth(ARMEmitter::Size::i32Bit, ARMEmitter::Reg::r0, Src1); - ldr(ARMEmitter::XReg::x1, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex])); -#ifdef VIXL_SIMULATOR - GenerateIndirectRuntimeCall(ARMEmitter::Reg::r1); -#else - blr(ARMEmitter::Reg::r1); -#endif - - PopDynamicRegsAndLR(); - - FillStaticRegs(); - } - break; - - case FABI_F80_F32:{ + case FABI_F80_I16_F32:{ SpillStaticRegs(TMP1); PushDynamicRegsAndLR(TMP1); const auto Src1 = GetVReg(IROp->Args[0].ID()); fmov(ARMEmitter::SReg::s0, Src1.S()); - ldr(ARMEmitter::XReg::x0, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex])); + ldrh(ARMEmitter::WReg::w0, STATE, offsetof(FEXCore::Core::CPUState, FCW)); + ldr(ARMEmitter::XReg::x1, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex])); #ifdef VIXL_SIMULATOR - GenerateIndirectRuntimeCall<__uint128_t, float>(ARMEmitter::Reg::r0); + GenerateIndirectRuntimeCall<__uint128_t, uint16_t, float>(ARMEmitter::Reg::r1); #else - blr(ARMEmitter::Reg::r0); + blr(ARMEmitter::Reg::r1); #endif PopDynamicRegsAndLR(); @@ -127,47 +108,17 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) { } break; - case FABI_F80_F64:{ + case FABI_F80_I16_F64:{ SpillStaticRegs(TMP1); PushDynamicRegsAndLR(TMP1); const auto Src1 = GetVReg(IROp->Args[0].ID()); mov(ARMEmitter::DReg::d0, Src1.D()); - ldr(ARMEmitter::XReg::x0, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex])); -#ifdef VIXL_SIMULATOR - GenerateIndirectRuntimeCall<__uint128_t, double>(ARMEmitter::Reg::r0); -#else - blr(ARMEmitter::Reg::r0); -#endif - - PopDynamicRegsAndLR(); - - FillStaticRegs(); - - const auto Dst = GetVReg(Node); - eor(Dst.Q(), Dst.Q(), Dst.Q()); - ins(ARMEmitter::SubRegSize::i64Bit, Dst, 0, ARMEmitter::Reg::r0); - ins(ARMEmitter::SubRegSize::i16Bit, Dst, 4, ARMEmitter::Reg::r1); - } - break; - - case FABI_F80_I16: - case FABI_F80_I32: { - SpillStaticRegs(TMP1); - - PushDynamicRegsAndLR(TMP1); - - const auto Src1 = GetReg(IROp->Args[0].ID()); - if (Info.ABI == FABI_F80_I16) { - sxth(ARMEmitter::Size::i32Bit, ARMEmitter::Reg::r0, Src1); - } - else { - mov(ARMEmitter::Size::i32Bit, ARMEmitter::Reg::r0, Src1); - } + ldrh(ARMEmitter::WReg::w0, STATE, offsetof(FEXCore::Core::CPUState, FCW)); ldr(ARMEmitter::XReg::x1, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex])); #ifdef VIXL_SIMULATOR - GenerateIndirectRuntimeCall<__uint128_t, uint32_t>(ARMEmitter::Reg::r1); + GenerateIndirectRuntimeCall<__uint128_t, uint16_t, double>(ARMEmitter::Reg::r1); #else blr(ARMEmitter::Reg::r1); #endif @@ -183,21 +134,54 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) { } break; - case FABI_F32_F80:{ + case FABI_F80_I16_I16: + case FABI_F80_I16_I32: { + SpillStaticRegs(TMP1); + + PushDynamicRegsAndLR(TMP1); + + const auto Src1 = GetReg(IROp->Args[0].ID()); + ldrh(ARMEmitter::WReg::w0, STATE, offsetof(FEXCore::Core::CPUState, FCW)); + if (Info.ABI == FABI_F80_I16_I16) { + sxth(ARMEmitter::Size::i32Bit, ARMEmitter::Reg::r1, Src1); + } + else { + mov(ARMEmitter::Size::i32Bit, ARMEmitter::Reg::r1, Src1); + } + ldr(ARMEmitter::XReg::x2, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex])); +#ifdef VIXL_SIMULATOR + GenerateIndirectRuntimeCall<__uint128_t, uint16_t, uint32_t>(ARMEmitter::Reg::r2); +#else + blr(ARMEmitter::Reg::r2); +#endif + + PopDynamicRegsAndLR(); + + FillStaticRegs(); + + const auto Dst = GetVReg(Node); + eor(Dst.Q(), Dst.Q(), Dst.Q()); + ins(ARMEmitter::SubRegSize::i64Bit, Dst, 0, ARMEmitter::Reg::r0); + ins(ARMEmitter::SubRegSize::i16Bit, Dst, 4, ARMEmitter::Reg::r1); + } + break; + + case FABI_F32_I16_F80:{ SpillStaticRegs(TMP1); PushDynamicRegsAndLR(TMP1); const auto Src1 = GetVReg(IROp->Args[0].ID()); - umov(ARMEmitter::Reg::r0, Src1, 0); - umov(ARMEmitter::Reg::r1, Src1, 4); + ldrh(ARMEmitter::WReg::w0, STATE, offsetof(FEXCore::Core::CPUState, FCW)); + umov(ARMEmitter::Reg::r1, Src1, 0); + umov(ARMEmitter::Reg::r2, Src1, 4); - ldr(ARMEmitter::XReg::x2, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex])); + ldr(ARMEmitter::XReg::x3, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex])); #ifdef VIXL_SIMULATOR - GenerateIndirectRuntimeCall(ARMEmitter::Reg::r2); + GenerateIndirectRuntimeCall(ARMEmitter::Reg::r3); #else - blr(ARMEmitter::Reg::r2); + blr(ARMEmitter::Reg::r3); #endif PopDynamicRegsAndLR(); @@ -209,21 +193,22 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) { } break; - case FABI_F64_F80:{ + case FABI_F64_I16_F80:{ SpillStaticRegs(TMP1); PushDynamicRegsAndLR(TMP1); const auto Src1 = GetVReg(IROp->Args[0].ID()); - umov(ARMEmitter::Reg::r0, Src1, 0); - umov(ARMEmitter::Reg::r1, Src1, 4); + ldrh(ARMEmitter::WReg::w0, STATE, offsetof(FEXCore::Core::CPUState, FCW)); + umov(ARMEmitter::Reg::r1, Src1, 0); + umov(ARMEmitter::Reg::r2, Src1, 4); - ldr(ARMEmitter::XReg::x2, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex])); + ldr(ARMEmitter::XReg::x3, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex])); #ifdef VIXL_SIMULATOR - GenerateIndirectRuntimeCall(ARMEmitter::Reg::r2); + GenerateIndirectRuntimeCall(ARMEmitter::Reg::r3); #else - blr(ARMEmitter::Reg::r2); + blr(ARMEmitter::Reg::r3); #endif PopDynamicRegsAndLR(); @@ -235,7 +220,7 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) { } break; - case FABI_F64_F64: { + case FABI_F64_I16_F64: { SpillStaticRegs(TMP1); PushDynamicRegsAndLR(TMP1); @@ -243,11 +228,12 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) { const auto Src1 = GetVReg(IROp->Args[0].ID()); mov(ARMEmitter::DReg::d0, Src1.D()); - ldr(ARMEmitter::XReg::x0, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex])); + ldrh(ARMEmitter::WReg::w0, STATE, offsetof(FEXCore::Core::CPUState, FCW)); + ldr(ARMEmitter::XReg::x1, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex])); #ifdef VIXL_SIMULATOR - GenerateIndirectRuntimeCall(ARMEmitter::Reg::r0); + GenerateIndirectRuntimeCall(ARMEmitter::Reg::r1); #else - blr(ARMEmitter::Reg::r0); + blr(ARMEmitter::Reg::r1); #endif PopDynamicRegsAndLR(); @@ -259,7 +245,7 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) { } break; - case FABI_F64_F64_F64: { + case FABI_F64_I16_F64_F64: { SpillStaticRegs(TMP1); PushDynamicRegsAndLR(TMP1); @@ -269,11 +255,12 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) { mov(ARMEmitter::DReg::d0, Src1.D()); mov(ARMEmitter::DReg::d1, Src2.D()); - ldr(ARMEmitter::XReg::x0, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex])); + ldrh(ARMEmitter::WReg::w0, STATE, offsetof(FEXCore::Core::CPUState, FCW)); + ldr(ARMEmitter::XReg::x1, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex])); #ifdef VIXL_SIMULATOR - GenerateIndirectRuntimeCall(ARMEmitter::Reg::r0); + GenerateIndirectRuntimeCall(ARMEmitter::Reg::r1); #else - blr(ARMEmitter::Reg::r0); + blr(ARMEmitter::Reg::r1); #endif PopDynamicRegsAndLR(); @@ -285,21 +272,22 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) { } break; - case FABI_I16_F80:{ + case FABI_I16_I16_F80:{ SpillStaticRegs(TMP1); PushDynamicRegsAndLR(TMP1); const auto Src1 = GetVReg(IROp->Args[0].ID()); - umov(ARMEmitter::Reg::r0, Src1, 0); - umov(ARMEmitter::Reg::r1, Src1, 4); + ldrh(ARMEmitter::WReg::w0, STATE, offsetof(FEXCore::Core::CPUState, FCW)); + umov(ARMEmitter::Reg::r1, Src1, 0); + umov(ARMEmitter::Reg::r2, Src1, 4); - ldr(ARMEmitter::XReg::x2, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex])); + ldr(ARMEmitter::XReg::x3, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex])); #ifdef VIXL_SIMULATOR - GenerateIndirectRuntimeCall(ARMEmitter::Reg::r2); + GenerateIndirectRuntimeCall(ARMEmitter::Reg::r3); #else - blr(ARMEmitter::Reg::r2); + blr(ARMEmitter::Reg::r3); #endif PopDynamicRegsAndLR(); @@ -310,21 +298,22 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) { sxth(ARMEmitter::Size::i64Bit, Dst, ARMEmitter::Reg::r0); } break; - case FABI_I32_F80:{ + case FABI_I32_I16_F80:{ SpillStaticRegs(TMP1); PushDynamicRegsAndLR(TMP1); const auto Src1 = GetVReg(IROp->Args[0].ID()); - umov(ARMEmitter::Reg::r0, Src1, 0); - umov(ARMEmitter::Reg::r1, Src1, 4); + ldrh(ARMEmitter::WReg::w0, STATE, offsetof(FEXCore::Core::CPUState, FCW)); + umov(ARMEmitter::Reg::r1, Src1, 0); + umov(ARMEmitter::Reg::r2, Src1, 4); - ldr(ARMEmitter::XReg::x2, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex])); + ldr(ARMEmitter::XReg::x3, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex])); #ifdef VIXL_SIMULATOR - GenerateIndirectRuntimeCall(ARMEmitter::Reg::r2); + GenerateIndirectRuntimeCall(ARMEmitter::Reg::r3); #else - blr(ARMEmitter::Reg::r2); + blr(ARMEmitter::Reg::r3); #endif PopDynamicRegsAndLR(); @@ -335,21 +324,22 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) { mov(ARMEmitter::Size::i32Bit, Dst, ARMEmitter::Reg::r0); } break; - case FABI_I64_F80:{ + case FABI_I64_I16_F80:{ SpillStaticRegs(TMP1); PushDynamicRegsAndLR(TMP1); const auto Src1 = GetVReg(IROp->Args[0].ID()); - umov(ARMEmitter::Reg::r0, Src1, 0); - umov(ARMEmitter::Reg::r1, Src1, 4); + ldrh(ARMEmitter::WReg::w0, STATE, offsetof(FEXCore::Core::CPUState, FCW)); + umov(ARMEmitter::Reg::r1, Src1, 0); + umov(ARMEmitter::Reg::r2, Src1, 4); - ldr(ARMEmitter::XReg::x2, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex])); + ldr(ARMEmitter::XReg::x3, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex])); #ifdef VIXL_SIMULATOR - GenerateIndirectRuntimeCall(ARMEmitter::Reg::r2); + GenerateIndirectRuntimeCall(ARMEmitter::Reg::r3); #else - blr(ARMEmitter::Reg::r2); + blr(ARMEmitter::Reg::r3); #endif PopDynamicRegsAndLR(); @@ -360,7 +350,7 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) { mov(ARMEmitter::Size::i64Bit, Dst, ARMEmitter::Reg::r0); } break; - case FABI_I64_F80_F80:{ + case FABI_I64_I16_F80_F80:{ SpillStaticRegs(TMP1); PushDynamicRegsAndLR(TMP1); @@ -368,17 +358,18 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) { const auto Src1 = GetVReg(IROp->Args[0].ID()); const auto Src2 = GetVReg(IROp->Args[1].ID()); - umov(ARMEmitter::Reg::r0, Src1, 0); - umov(ARMEmitter::Reg::r1, Src1, 4); + ldrh(ARMEmitter::WReg::w0, STATE, offsetof(FEXCore::Core::CPUState, FCW)); + umov(ARMEmitter::Reg::r1, Src1, 0); + umov(ARMEmitter::Reg::r2, Src1, 4); - umov(ARMEmitter::Reg::r2, Src2, 0); - umov(ARMEmitter::Reg::r3, Src2, 4); + umov(ARMEmitter::Reg::r3, Src2, 0); + umov(ARMEmitter::Reg::r4, Src2, 4); - ldr(ARMEmitter::XReg::x4, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex])); + ldr(ARMEmitter::XReg::x5, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex])); #ifdef VIXL_SIMULATOR - GenerateIndirectRuntimeCall(ARMEmitter::Reg::r4); + GenerateIndirectRuntimeCall(ARMEmitter::Reg::r5); #else - blr(ARMEmitter::Reg::r4); + blr(ARMEmitter::Reg::r5); #endif PopDynamicRegsAndLR(); @@ -388,21 +379,22 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) { mov(ARMEmitter::Size::i64Bit, Dst, ARMEmitter::Reg::r0); } break; - case FABI_F80_F80:{ + case FABI_F80_I16_F80:{ SpillStaticRegs(TMP1); PushDynamicRegsAndLR(TMP1); const auto Src1 = GetVReg(IROp->Args[0].ID()); - umov(ARMEmitter::Reg::r0, Src1, 0); - umov(ARMEmitter::Reg::r1, Src1, 4); + ldrh(ARMEmitter::WReg::w0, STATE, offsetof(FEXCore::Core::CPUState, FCW)); + umov(ARMEmitter::Reg::r1, Src1, 0); + umov(ARMEmitter::Reg::r2, Src1, 4); - ldr(ARMEmitter::XReg::x2, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex])); + ldr(ARMEmitter::XReg::x3, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex])); #ifdef VIXL_SIMULATOR - GenerateIndirectRuntimeCall<__uint128_t, uint64_t, uint64_t>(ARMEmitter::Reg::r2); + GenerateIndirectRuntimeCall<__uint128_t, uint16_t, uint64_t, uint64_t>(ARMEmitter::Reg::r3); #else - blr(ARMEmitter::Reg::r2); + blr(ARMEmitter::Reg::r3); #endif PopDynamicRegsAndLR(); @@ -415,7 +407,7 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) { ins(ARMEmitter::SubRegSize::i16Bit, Dst, 4, ARMEmitter::Reg::r1); } break; - case FABI_F80_F80_F80:{ + case FABI_F80_I16_F80_F80:{ SpillStaticRegs(TMP1); PushDynamicRegsAndLR(TMP1); @@ -423,17 +415,18 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) { const auto Src1 = GetVReg(IROp->Args[0].ID()); const auto Src2 = GetVReg(IROp->Args[1].ID()); - umov(ARMEmitter::Reg::r0, Src1, 0); - umov(ARMEmitter::Reg::r1, Src1, 4); + ldrh(ARMEmitter::WReg::w0, STATE, offsetof(FEXCore::Core::CPUState, FCW)); + umov(ARMEmitter::Reg::r1, Src1, 0); + umov(ARMEmitter::Reg::r2, Src1, 4); - umov(ARMEmitter::Reg::r2, Src2, 0); - umov(ARMEmitter::Reg::r3, Src2, 4); + umov(ARMEmitter::Reg::r3, Src2, 0); + umov(ARMEmitter::Reg::r4, Src2, 4); - ldr(ARMEmitter::XReg::x4, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex])); + ldr(ARMEmitter::XReg::x5, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex])); #ifdef VIXL_SIMULATOR - GenerateIndirectRuntimeCall<__uint128_t, uint64_t, uint64_t, uint64_t, uint64_t>(ARMEmitter::Reg::r4); + GenerateIndirectRuntimeCall<__uint128_t, uint16_t, uint64_t, uint64_t, uint64_t, uint64_t>(ARMEmitter::Reg::r5); #else - blr(ARMEmitter::Reg::r4); + blr(ARMEmitter::Reg::r5); #endif PopDynamicRegsAndLR(); diff --git a/FEXCore/Source/Interface/Core/JIT/x86_64/JIT.cpp b/FEXCore/Source/Interface/Core/JIT/x86_64/JIT.cpp index 41baf89bb..2e0f988ea 100644 --- a/FEXCore/Source/Interface/Core/JIT/x86_64/JIT.cpp +++ b/FEXCore/Source/Interface/Core/JIT/x86_64/JIT.cpp @@ -104,18 +104,11 @@ void X86JITCore::Op_Unhandled(IR::IROp_Header *IROp, IR::NodeID Node) { #endif } else { switch(Info.ABI) { - case FABI_VOID_U16: { - PushRegs(); - mov(edi, GetSrc(IROp->Args[0].ID())); - call(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex])]); - - PopRegs(); - break; - } - case FABI_F80_F32:{ + case FABI_F80_I16_F32:{ PushRegs(); movss(xmm0, GetSrc(IROp->Args[0].ID())); + mov(rdi, word [STATE + offsetof(FEXCore::Core::CPUState, FCW)]); call(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex])]); PopRegs(); @@ -126,10 +119,11 @@ void X86JITCore::Op_Unhandled(IR::IROp_Header *IROp, IR::NodeID Node) { } break; - case FABI_F80_F64:{ + case FABI_F80_I16_F64:{ PushRegs(); movsd(xmm0, GetSrc(IROp->Args[0].ID())); + mov(rdi, word [STATE + offsetof(FEXCore::Core::CPUState, FCW)]); call(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex])]); PopRegs(); @@ -140,15 +134,17 @@ void X86JITCore::Op_Unhandled(IR::IROp_Header *IROp, IR::NodeID Node) { } break; - case FABI_F80_I16: - case FABI_F80_I32: { + case FABI_F80_I16_I16: + case FABI_F80_I16_I32: { PushRegs(); - if (Info.ABI == FABI_F80_I16) { - movsx(rdi, GetSrc(IROp->Args[0].ID()).cvt16()); + mov(rdi, word [STATE + offsetof(FEXCore::Core::CPUState, FCW)]); + + if (Info.ABI == FABI_F80_I16_I16) { + movsx(rsi, GetSrc(IROp->Args[0].ID()).cvt16()); } else { - mov(edi, GetSrc(IROp->Args[0].ID())); + mov(esi, GetSrc(IROp->Args[0].ID())); } call(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex])]); @@ -160,11 +156,12 @@ void X86JITCore::Op_Unhandled(IR::IROp_Header *IROp, IR::NodeID Node) { } break; - case FABI_F32_F80:{ + case FABI_F32_I16_F80:{ PushRegs(); - movq(rdi, GetSrc(IROp->Args[0].ID())); - pextrq(rsi, GetSrc(IROp->Args[0].ID()), 1); + mov(rdi, word [STATE + offsetof(FEXCore::Core::CPUState, FCW)]); + movq(rsi, GetSrc(IROp->Args[0].ID())); + pextrq(rdx, GetSrc(IROp->Args[0].ID()), 1); call(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex])]); @@ -174,11 +171,12 @@ void X86JITCore::Op_Unhandled(IR::IROp_Header *IROp, IR::NodeID Node) { } break; - case FABI_F64_F80:{ + case FABI_F64_I16_F80:{ PushRegs(); - movq(rdi, GetSrc(IROp->Args[0].ID())); - pextrq(rsi, GetSrc(IROp->Args[0].ID()), 1); + mov(rdi, word [STATE + offsetof(FEXCore::Core::CPUState, FCW)]); + movq(rsi, GetSrc(IROp->Args[0].ID())); + pextrq(rdx, GetSrc(IROp->Args[0].ID()), 1); call(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex])]); @@ -188,9 +186,10 @@ void X86JITCore::Op_Unhandled(IR::IROp_Header *IROp, IR::NodeID Node) { } break; - case FABI_F64_F64: { + case FABI_F64_I16_F64: { PushRegs(); + mov(rdi, word [STATE + offsetof(FEXCore::Core::CPUState, FCW)]); movsd(xmm0, GetSrc(IROp->Args[0].ID())); call(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex])]); @@ -201,9 +200,10 @@ void X86JITCore::Op_Unhandled(IR::IROp_Header *IROp, IR::NodeID Node) { } break; - case FABI_F64_F64_F64: { + case FABI_F64_I16_F64_F64: { PushRegs(); + mov(rdi, word [STATE + offsetof(FEXCore::Core::CPUState, FCW)]); movsd(xmm0, GetSrc(IROp->Args[0].ID())); movsd(xmm1, GetSrc(IROp->Args[1].ID())); @@ -215,11 +215,12 @@ void X86JITCore::Op_Unhandled(IR::IROp_Header *IROp, IR::NodeID Node) { } break; - case FABI_I16_F80:{ + case FABI_I16_I16_F80:{ PushRegs(); - movq(rdi, GetSrc(IROp->Args[0].ID())); - pextrq(rsi, GetSrc(IROp->Args[0].ID()), 1); + mov(rdi, word [STATE + offsetof(FEXCore::Core::CPUState, FCW)]); + movq(rsi, GetSrc(IROp->Args[0].ID())); + pextrq(rdx, GetSrc(IROp->Args[0].ID()), 1); call(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex])]); @@ -228,11 +229,12 @@ void X86JITCore::Op_Unhandled(IR::IROp_Header *IROp, IR::NodeID Node) { movsx(GetDst(Node), ax); } break; - case FABI_I32_F80:{ + case FABI_I32_I16_F80:{ PushRegs(); - movq(rdi, GetSrc(IROp->Args[0].ID())); - pextrq(rsi, GetSrc(IROp->Args[0].ID()), 1); + mov(rdi, word [STATE + offsetof(FEXCore::Core::CPUState, FCW)]); + movq(rsi, GetSrc(IROp->Args[0].ID())); + pextrq(rdx, GetSrc(IROp->Args[0].ID()), 1); call(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex])]); @@ -241,11 +243,12 @@ void X86JITCore::Op_Unhandled(IR::IROp_Header *IROp, IR::NodeID Node) { mov(GetDst(Node), eax); } break; - case FABI_I64_F80:{ + case FABI_I64_I16_F80:{ PushRegs(); - movq(rdi, GetSrc(IROp->Args[0].ID())); - pextrq(rsi, GetSrc(IROp->Args[0].ID()), 1); + mov(rdi, word [STATE + offsetof(FEXCore::Core::CPUState, FCW)]); + movq(rsi, GetSrc(IROp->Args[0].ID())); + pextrq(rdx, GetSrc(IROp->Args[0].ID()), 1); call(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex])]); @@ -254,14 +257,15 @@ void X86JITCore::Op_Unhandled(IR::IROp_Header *IROp, IR::NodeID Node) { mov(GetDst(Node), rax); } break; - case FABI_I64_F80_F80:{ + case FABI_I64_I16_F80_F80:{ PushRegs(); - movq(rdi, GetSrc(IROp->Args[0].ID())); - pextrq(rsi, GetSrc(IROp->Args[0].ID()), 1); + mov(rdi, word [STATE + offsetof(FEXCore::Core::CPUState, FCW)]); + movq(rsi, GetSrc(IROp->Args[0].ID())); + pextrq(rdx, GetSrc(IROp->Args[0].ID()), 1); - movq(rdx, GetSrc(IROp->Args[1].ID())); - pextrq(rcx, GetSrc(IROp->Args[1].ID()), 1); + movq(rcx, GetSrc(IROp->Args[1].ID())); + pextrq(r8, GetSrc(IROp->Args[1].ID()), 1); call(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex])]); @@ -270,11 +274,12 @@ void X86JITCore::Op_Unhandled(IR::IROp_Header *IROp, IR::NodeID Node) { mov(GetDst(Node), rax); } break; - case FABI_F80_F80:{ + case FABI_F80_I16_F80:{ PushRegs(); - movq(rdi, GetSrc(IROp->Args[0].ID())); - pextrq(rsi, GetSrc(IROp->Args[0].ID()), 1); + mov(rdi, word [STATE + offsetof(FEXCore::Core::CPUState, FCW)]); + movq(rsi, GetSrc(IROp->Args[0].ID())); + pextrq(rdx, GetSrc(IROp->Args[0].ID()), 1); call(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex])]); @@ -285,14 +290,15 @@ void X86JITCore::Op_Unhandled(IR::IROp_Header *IROp, IR::NodeID Node) { pinsrw(GetDst(Node), edx, 4); } break; - case FABI_F80_F80_F80:{ + case FABI_F80_I16_F80_F80:{ PushRegs(); - movq(rdi, GetSrc(IROp->Args[0].ID())); - pextrq(rsi, GetSrc(IROp->Args[0].ID()), 1); + mov(rdi, word [STATE + offsetof(FEXCore::Core::CPUState, FCW)]); + movq(rsi, GetSrc(IROp->Args[0].ID())); + pextrq(rdx, GetSrc(IROp->Args[0].ID()), 1); - movq(rdx, GetSrc(IROp->Args[1].ID())); - pextrq(rcx, GetSrc(IROp->Args[1].ID()), 1); + movq(rcx, GetSrc(IROp->Args[1].ID())); + pextrq(r8, GetSrc(IROp->Args[1].ID()), 1); call(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex])]); diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp index 57fabfb49..f4e2fb68f 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp @@ -2816,7 +2816,6 @@ void OpDispatchBuilder::RestoreX87State(OrderedNode *MemBase) { const auto OpSize = IR::SizeToOpSize(CTX->GetGPRSize()); auto NewFCW = _LoadMem(GPRClass, 2, MemBase, 2); - _F80LoadFCW(NewFCW); _StoreContext(2, GPRClass, NewFCW, offsetof(FEXCore::Core::CPUState, FCW)); { diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher/X87.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher/X87.cpp index d38a38500..3d443b433 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher/X87.cpp +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher/X87.cpp @@ -694,7 +694,6 @@ void OpDispatchBuilder::FNINIT(OpcodeArgs) { auto Zero = _Constant(0); // Init FCW to 0x037F auto NewFCW = _Constant(16, 0x037F); - _F80LoadFCW(NewFCW); _StoreContext(2, GPRClass, NewFCW, offsetof(FEXCore::Core::CPUState, FCW)); // Init FSW to 0 @@ -1015,7 +1014,6 @@ void OpDispatchBuilder::X87LDENV(OpcodeArgs) { Mem = AppendSegmentOffset(Mem, Op->Flags); auto NewFCW = _LoadMem(GPRClass, 2, Mem, 2); - _F80LoadFCW(NewFCW); _StoreContext(2, GPRClass, NewFCW, offsetof(FEXCore::Core::CPUState, FCW)); OrderedNode *MemLocation = _Add(OpSize::i64Bit, Mem, _Constant(Size * 1)); @@ -1098,7 +1096,6 @@ void OpDispatchBuilder::X87FNSTENV(OpcodeArgs) { void OpDispatchBuilder::X87FLDCW(OpcodeArgs) { OrderedNode *NewFCW = LoadSource(GPRClass, Op, Op->Src[0], Op->Flags, -1); - _F80LoadFCW(NewFCW); _StoreContext(2, GPRClass, NewFCW, offsetof(FEXCore::Core::CPUState, FCW)); } @@ -1216,7 +1213,6 @@ void OpDispatchBuilder::X87FRSTOR(OpcodeArgs) { Mem = AppendSegmentOffset(Mem, Op->Flags); auto NewFCW = _LoadMem(GPRClass, 2, Mem, 2); - _F80LoadFCW(NewFCW); _StoreContext(2, GPRClass, NewFCW, offsetof(FEXCore::Core::CPUState, FCW)); OrderedNode *MemLocation = _Add(OpSize::i64Bit, Mem, _Constant(Size * 1)); diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher/X87F64.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher/X87F64.cpp index c66c8e651..bf86a7ebe 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher/X87F64.cpp +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher/X87F64.cpp @@ -46,7 +46,6 @@ class OrderedNode; void OpDispatchBuilder::FNINITF64(OpcodeArgs) { // Init FCW to 0x037F auto NewFCW = _Constant(16, 0x037F); - _F80LoadFCW(NewFCW); // Init host rounding mode to zero auto Zero = _Constant(0); _SetRoundingMode(Zero); @@ -78,8 +77,6 @@ void OpDispatchBuilder::X87LDENVF64(OpcodeArgs) { roundingMode = _Lshr(OpSize::i32Bit, roundingMode, roundShift); roundingMode = _And(OpSize::i32Bit, roundingMode, roundMask); _SetRoundingMode(roundingMode); - _F80LoadFCW(NewFCW); - _StoreContext(2, GPRClass, NewFCW, offsetof(FEXCore::Core::CPUState, FCW)); OrderedNode *MemLocation = _Add(OpSize::i64Bit, Mem, _Constant(Size * 1)); @@ -96,7 +93,6 @@ void OpDispatchBuilder::X87LDENVF64(OpcodeArgs) { void OpDispatchBuilder::X87FLDCWF64(OpcodeArgs) { OrderedNode *NewFCW = LoadSource(GPRClass, Op, Op->Src[0], Op->Flags, -1); - _F80LoadFCW(NewFCW); //keeps BCD code working //ignore the rounding precision, we're always 64-bit in F64. //extract rounding mode OrderedNode *roundingMode = NewFCW; @@ -1026,7 +1022,6 @@ void OpDispatchBuilder::X87FRSTORF64(OpcodeArgs) { roundingMode = _Lshr(OpSize::i32Bit, roundingMode, roundShift); roundingMode = _And(OpSize::i32Bit, roundingMode, roundMask); _SetRoundingMode(roundingMode); - _F80LoadFCW(NewFCW); _StoreContext(2, GPRClass, NewFCW, offsetof(FEXCore::Core::CPUState, FCW)); _StoreContext(2, GPRClass, NewFCW, offsetof(FEXCore::Core::CPUState, FCW)); diff --git a/FEXCore/Source/Interface/IR/IR.json b/FEXCore/Source/Interface/IR/IR.json index 1e1490bdc..13d23df28 100644 --- a/FEXCore/Source/Interface/IR/IR.json +++ b/FEXCore/Source/Interface/IR/IR.json @@ -1891,9 +1891,6 @@ } }, "F80": { - "F80LoadFCW GPR:$Src": { - "HasSideEffects": true - }, "FPR = F80Add FPR:$X80Src1, FPR:$X80Src2": { "DestSize": "16" }, From 97a6184e530b96055f6441f1900ca82f0be1d46d Mon Sep 17 00:00:00 2001 From: Ryan Houdek Date: Tue, 12 Sep 2023 05:09:08 -0700 Subject: [PATCH 2/2] InstCountCI: Update for FCW optimization --- .../InstructionCountCI/SecondaryGroup.json | 131 +- unittests/InstructionCountCI/x87.json | 4418 +++++++++-------- 2 files changed, 2264 insertions(+), 2285 deletions(-) diff --git a/unittests/InstructionCountCI/SecondaryGroup.json b/unittests/InstructionCountCI/SecondaryGroup.json index 4c13b5dc3..0bebb0ba7 100644 --- a/unittests/InstructionCountCI/SecondaryGroup.json +++ b/unittests/InstructionCountCI/SecondaryGroup.json @@ -1039,52 +1039,11 @@ ] }, "fxrstor [rax]": { - "ExpectedInstructionCount": 105, + "ExpectedInstructionCount": 64, "Optimal": "No", "Comment": "GROUP15 0x0F 0xAE /1", "ExpectedArm64ASM": [ "ldrh w20, [x4]", - "stp x4, x5, [x28, #8]", - "stp x6, x7, [x28, #24]", - "stp x8, x9, [x28, #40]", - "stp x10, x11, [x28, #56]", - "stp x12, x13, [x28, #72]", - "stp x14, x15, [x28, #88]", - "stp x16, x17, [x28, #104]", - "stp x19, x29, [x28, #120]", - "add x0, x28, #0xc0 (192)", - "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", - "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", - "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", - "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", - "sub sp, sp, #0xf0 (240)", - "mov x0, sp", - "st1 {v2.2d, v3.2d}, [x0], #32", - "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", - "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", - "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", - "str x30, [x0]", - "uxth w0, w20", - "ldr x1, [x28, #1144]", - "blr x1", - "ld1 {v2.2d, v3.2d}, [sp], #32", - "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", - "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", - "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", - "ldr x30, [sp], #16", - "add x5, x28, #0xc0 (192)", - "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", - "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", - "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", - "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", - "ldp x4, x5, [x28, #8]", - "ldp x6, x7, [x28, #24]", - "ldp x8, x9, [x28, #40]", - "ldp x10, x11, [x28, #56]", - "ldp x12, x13, [x28, #72]", - "ldp x14, x15, [x28, #88]", - "ldp x16, x17, [x28, #104]", - "ldp x19, x29, [x28, #120]", "strh w20, [x28, #1008]", "ldrh w20, [x4, #2]", "ubfx w21, w20, #11, #3", @@ -1350,7 +1309,7 @@ ] }, "xrstor [rax]": { - "ExpectedInstructionCount": 194, + "ExpectedInstructionCount": 112, "Optimal": "No", "Comment": "GROUP15 0x0F 0xAE /5", "ExpectedArm64ASM": [ @@ -1358,49 +1317,8 @@ "ldr x21, [x20, #512]", "ubfx x22, x21, #0, #1", "cbnz x22, #+0x8", - "b #+0x128", + "b #+0x84", "ldrh w22, [x20]", - "stp x4, x5, [x28, #8]", - "stp x6, x7, [x28, #24]", - "stp x8, x9, [x28, #40]", - "stp x10, x11, [x28, #56]", - "stp x12, x13, [x28, #72]", - "stp x14, x15, [x28, #88]", - "stp x16, x17, [x28, #104]", - "stp x19, x29, [x28, #120]", - "add x0, x28, #0xc0 (192)", - "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", - "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", - "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", - "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", - "sub sp, sp, #0xf0 (240)", - "mov x0, sp", - "st1 {v2.2d, v3.2d}, [x0], #32", - "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", - "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", - "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", - "str x30, [x0]", - "uxth w0, w22", - "ldr x1, [x28, #1144]", - "blr x1", - "ld1 {v2.2d, v3.2d}, [sp], #32", - "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", - "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", - "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", - "ldr x30, [sp], #16", - "add x5, x28, #0xc0 (192)", - "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", - "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", - "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", - "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", - "ldp x4, x5, [x28, #8]", - "ldp x6, x7, [x28, #24]", - "ldp x8, x9, [x28, #40]", - "ldp x10, x11, [x28, #56]", - "ldp x12, x13, [x28, #72]", - "ldp x14, x15, [x28, #88]", - "ldp x16, x17, [x28, #104]", - "ldp x19, x29, [x28, #120]", "strh w22, [x28, #1008]", "ldrh w22, [x20, #2]", "ubfx w23, w22, #11, #3", @@ -1431,50 +1349,9 @@ "str q2, [x28, #848]", "ldr q2, [x20, #144]", "str q2, [x28, #864]", - "b #+0xf0", + "b #+0x4c", "mov w22, #0x0", "mov w23, #0x37f", - "stp x4, x5, [x28, #8]", - "stp x6, x7, [x28, #24]", - "stp x8, x9, [x28, #40]", - "stp x10, x11, [x28, #56]", - "stp x12, x13, [x28, #72]", - "stp x14, x15, [x28, #88]", - "stp x16, x17, [x28, #104]", - "stp x19, x29, [x28, #120]", - "add x0, x28, #0xc0 (192)", - "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", - "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", - "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", - "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", - "sub sp, sp, #0xf0 (240)", - "mov x0, sp", - "st1 {v2.2d, v3.2d}, [x0], #32", - "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", - "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", - "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", - "str x30, [x0]", - "uxth w0, w23", - "ldr x1, [x28, #1144]", - "blr x1", - "ld1 {v2.2d, v3.2d}, [sp], #32", - "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", - "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", - "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", - "ldr x30, [sp], #16", - "add x5, x28, #0xc0 (192)", - "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", - "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", - "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", - "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", - "ldp x4, x5, [x28, #8]", - "ldp x6, x7, [x28, #24]", - "ldp x8, x9, [x28, #40]", - "ldp x10, x11, [x28, #56]", - "ldp x12, x13, [x28, #72]", - "ldp x14, x15, [x28, #88]", - "ldp x16, x17, [x28, #104]", - "ldp x19, x29, [x28, #120]", "strh w23, [x28, #1008]", "strb w22, [x28, #747]", "strb w22, [x28, #744]", diff --git a/unittests/InstructionCountCI/x87.json b/unittests/InstructionCountCI/x87.json index f120abff6..1881e2a8a 100644 --- a/unittests/InstructionCountCI/x87.json +++ b/unittests/InstructionCountCI/x87.json @@ -9,7 +9,7 @@ }, "Instructions": { "fadd dword [rax]": { - "ExpectedInstructionCount": 97, + "ExpectedInstructionCount": 99, "Optimal": "No", "Comment": [ "0xd8 !11b /0" @@ -38,8 +38,9 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "fmov s0, s2", - "ldr x0, [x28, #1152]", - "blr x0", + "ldrh w0, [x28, #1008]", + "ldr x1, [x28, #1152]", + "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -83,12 +84,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1392]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1392]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -115,7 +117,7 @@ ] }, "fmul dword [rax]": { - "ExpectedInstructionCount": 97, + "ExpectedInstructionCount": 99, "Optimal": "No", "Comment": [ "0xd8 !11b /1" @@ -144,8 +146,9 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "fmov s0, s2", - "ldr x0, [x28, #1152]", - "blr x0", + "ldrh w0, [x28, #1008]", + "ldr x1, [x28, #1152]", + "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -189,12 +192,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1408]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1408]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -221,7 +225,7 @@ ] }, "fcom dword [rax]": { - "ExpectedInstructionCount": 103, + "ExpectedInstructionCount": 105, "Optimal": "No", "Comment": [ "0xd8 !11b /2" @@ -250,8 +254,9 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "fmov s0, s2", - "ldr x0, [x28, #1152]", - "blr x0", + "ldrh w0, [x28, #1008]", + "ldr x1, [x28, #1152]", + "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -295,12 +300,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1288]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1288]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -333,7 +339,7 @@ ] }, "fcomp dword [rax]": { - "ExpectedInstructionCount": 111, + "ExpectedInstructionCount": 113, "Optimal": "No", "Comment": [ "0xd8 !11b /3" @@ -362,8 +368,9 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "fmov s0, s2", - "ldr x0, [x28, #1152]", - "blr x0", + "ldrh w0, [x28, #1008]", + "ldr x1, [x28, #1152]", + "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -407,12 +414,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1288]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1288]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -453,7 +461,7 @@ ] }, "fsub dword [rax]": { - "ExpectedInstructionCount": 97, + "ExpectedInstructionCount": 99, "Optimal": "No", "Comment": [ "0xd8 !11b /4" @@ -482,8 +490,9 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "fmov s0, s2", - "ldr x0, [x28, #1152]", - "blr x0", + "ldrh w0, [x28, #1008]", + "ldr x1, [x28, #1152]", + "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -527,12 +536,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1400]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -559,7 +569,7 @@ ] }, "fsubr dword [rax]": { - "ExpectedInstructionCount": 97, + "ExpectedInstructionCount": 99, "Optimal": "No", "Comment": [ "0xd8 !11b /5" @@ -588,8 +598,9 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "fmov s0, s2", - "ldr x0, [x28, #1152]", - "blr x0", + "ldrh w0, [x28, #1008]", + "ldr x1, [x28, #1152]", + "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -633,12 +644,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v2.d[0]", - "umov w1, v2.h[4]", - "mov x2, v3.d[0]", - "umov w3, v3.h[4]", - "ldr x4, [x28, #1400]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -665,7 +677,7 @@ ] }, "fdiv dword [rax]": { - "ExpectedInstructionCount": 97, + "ExpectedInstructionCount": 99, "Optimal": "No", "Comment": [ "0xd8 !11b /6" @@ -694,8 +706,9 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "fmov s0, s2", - "ldr x0, [x28, #1152]", - "blr x0", + "ldrh w0, [x28, #1008]", + "ldr x1, [x28, #1152]", + "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -739,12 +752,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1416]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1416]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -771,7 +785,7 @@ ] }, "fdivr dword [rax]": { - "ExpectedInstructionCount": 97, + "ExpectedInstructionCount": 99, "Optimal": "No", "Comment": [ "0xd8 !11b /7" @@ -800,8 +814,9 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "fmov s0, s2", - "ldr x0, [x28, #1152]", - "blr x0", + "ldrh w0, [x28, #1008]", + "ldr x1, [x28, #1152]", + "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -845,12 +860,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v2.d[0]", - "umov w1, v2.h[4]", - "mov x2, v3.d[0]", - "umov w3, v3.h[4]", - "ldr x4, [x28, #1416]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1416]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -877,7 +893,7 @@ ] }, "fadd st0, st0": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "0xd8 11b 0xc0 /0" @@ -910,12 +926,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1392]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1392]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -942,7 +959,7 @@ ] }, "fadd st0, st1": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "0xd8 11b 0xc1 /0" @@ -975,12 +992,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1392]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1392]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -1007,7 +1025,7 @@ ] }, "fadd st0, st2": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "0xd8 11b 0xc2 /0" @@ -1040,12 +1058,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1392]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1392]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -1072,7 +1091,7 @@ ] }, "fadd st0, st3": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "0xd8 11b 0xc3 /0" @@ -1105,12 +1124,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1392]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1392]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -1137,7 +1157,7 @@ ] }, "fadd st0, st4": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "0xd8 11b 0xc4 /0" @@ -1170,12 +1190,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1392]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1392]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -1202,7 +1223,7 @@ ] }, "fadd st0, st5": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "0xd8 11b 0xc5 /0" @@ -1235,12 +1256,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1392]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1392]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -1267,7 +1289,7 @@ ] }, "fadd st0, st6": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "0xd8 11b 0xc6 /0" @@ -1300,12 +1322,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1392]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1392]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -1332,7 +1355,7 @@ ] }, "fadd st0, st7": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "0xd8 11b 0xc7 /0" @@ -1365,12 +1388,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1392]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1392]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -1397,7 +1421,7 @@ ] }, "fmul st0, st0": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "0xd8 11b 0xc8 /1" @@ -1430,12 +1454,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1408]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1408]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -1462,7 +1487,7 @@ ] }, "fmul st0, st1": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "0xd8 11b 0xc9 /1" @@ -1495,12 +1520,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1408]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1408]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -1527,7 +1553,7 @@ ] }, "fmul st0, st2": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "0xd8 11b 0xca /1" @@ -1560,12 +1586,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1408]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1408]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -1592,7 +1619,7 @@ ] }, "fmul st0, st3": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "0xd8 11b 0xcb /1" @@ -1625,12 +1652,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1408]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1408]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -1657,7 +1685,7 @@ ] }, "fmul st0, st4": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "0xd8 11b 0xcc /1" @@ -1690,12 +1718,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1408]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1408]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -1722,7 +1751,7 @@ ] }, "fmul st0, st5": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "0xd8 11b 0xcd /1" @@ -1755,12 +1784,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1408]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1408]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -1787,7 +1817,7 @@ ] }, "fmul st0, st6": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "0xd8 11b 0xce /1" @@ -1820,12 +1850,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1408]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1408]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -1852,7 +1883,7 @@ ] }, "fmul st0, st7": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "0xd8 11b 0xcf /1" @@ -1885,12 +1916,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1408]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1408]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -1917,7 +1949,7 @@ ] }, "fcom st0, st0": { - "ExpectedInstructionCount": 62, + "ExpectedInstructionCount": 63, "Optimal": "No", "Comment": [ "0xd8 11b 0xd0 /2" @@ -1951,12 +1983,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1288]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1288]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -1988,7 +2021,7 @@ ] }, "fcom st0, st1": { - "ExpectedInstructionCount": 62, + "ExpectedInstructionCount": 63, "Optimal": "No", "Comment": [ "0xd8 11b 0xd1 /2" @@ -2021,12 +2054,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1288]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1288]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -2059,7 +2093,7 @@ ] }, "fcom st0, st2": { - "ExpectedInstructionCount": 62, + "ExpectedInstructionCount": 63, "Optimal": "No", "Comment": [ "0xd8 11b 0xd2 /2" @@ -2092,12 +2126,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1288]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1288]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -2130,7 +2165,7 @@ ] }, "fcom st0, st3": { - "ExpectedInstructionCount": 62, + "ExpectedInstructionCount": 63, "Optimal": "No", "Comment": [ "0xd8 11b 0xd3 /2" @@ -2163,12 +2198,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1288]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1288]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -2201,7 +2237,7 @@ ] }, "fcom st0, st4": { - "ExpectedInstructionCount": 62, + "ExpectedInstructionCount": 63, "Optimal": "No", "Comment": [ "0xd8 11b 0xd4 /2" @@ -2234,12 +2270,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1288]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1288]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -2272,7 +2309,7 @@ ] }, "fcom st0, st5": { - "ExpectedInstructionCount": 62, + "ExpectedInstructionCount": 63, "Optimal": "No", "Comment": [ "0xd8 11b 0xd5 /2" @@ -2305,12 +2342,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1288]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1288]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -2343,7 +2381,7 @@ ] }, "fcom st0, st6": { - "ExpectedInstructionCount": 62, + "ExpectedInstructionCount": 63, "Optimal": "No", "Comment": [ "0xd8 11b 0xd6 /2" @@ -2376,12 +2414,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1288]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1288]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -2414,7 +2453,7 @@ ] }, "fcom st0, st7": { - "ExpectedInstructionCount": 62, + "ExpectedInstructionCount": 63, "Optimal": "No", "Comment": [ "0xd8 11b 0xd7 /2" @@ -2447,12 +2486,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1288]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1288]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -2485,7 +2525,7 @@ ] }, "fcomp st0, st0": { - "ExpectedInstructionCount": 70, + "ExpectedInstructionCount": 71, "Optimal": "No", "Comment": [ "0xd8 11b 0xd8 /3" @@ -2519,12 +2559,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1288]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1288]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -2564,7 +2605,7 @@ ] }, "fcomp st0, st1": { - "ExpectedInstructionCount": 70, + "ExpectedInstructionCount": 71, "Optimal": "No", "Comment": [ "0xd8 11b 0xd9 /3" @@ -2598,12 +2639,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1288]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1288]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -2643,7 +2685,7 @@ ] }, "fcomp st0, st2": { - "ExpectedInstructionCount": 70, + "ExpectedInstructionCount": 71, "Optimal": "No", "Comment": [ "0xd8 11b 0xda /3" @@ -2676,12 +2718,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1288]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1288]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -2722,7 +2765,7 @@ ] }, "fcomp st0, st3": { - "ExpectedInstructionCount": 70, + "ExpectedInstructionCount": 71, "Optimal": "No", "Comment": [ "0xd8 11b 0xdb /3" @@ -2755,12 +2798,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1288]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1288]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -2801,7 +2845,7 @@ ] }, "fcomp st0, st4": { - "ExpectedInstructionCount": 70, + "ExpectedInstructionCount": 71, "Optimal": "No", "Comment": [ "0xd8 11b 0xdc /3" @@ -2834,12 +2878,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1288]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1288]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -2880,7 +2925,7 @@ ] }, "fcomp st0, st5": { - "ExpectedInstructionCount": 70, + "ExpectedInstructionCount": 71, "Optimal": "No", "Comment": [ "0xd8 11b 0xdd /3" @@ -2913,12 +2958,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1288]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1288]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -2959,7 +3005,7 @@ ] }, "fcomp st0, st6": { - "ExpectedInstructionCount": 70, + "ExpectedInstructionCount": 71, "Optimal": "No", "Comment": [ "0xd8 11b 0xde /3" @@ -2992,12 +3038,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1288]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1288]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -3038,7 +3085,7 @@ ] }, "fcomp st0, st7": { - "ExpectedInstructionCount": 70, + "ExpectedInstructionCount": 71, "Optimal": "No", "Comment": [ "0xd8 11b 0xdf /3" @@ -3071,12 +3118,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1288]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1288]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -3117,7 +3165,7 @@ ] }, "fsub st0, st0": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "0xd8 11b 0xe0 /4" @@ -3150,12 +3198,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v2.d[0]", - "umov w1, v2.h[4]", - "mov x2, v3.d[0]", - "umov w3, v3.h[4]", - "ldr x4, [x28, #1400]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -3182,7 +3231,7 @@ ] }, "fsub st0, st1": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "0xd8 11b 0xe1 /4" @@ -3215,12 +3264,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1400]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -3247,7 +3297,7 @@ ] }, "fsub st0, st2": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "0xd8 11b 0xe2 /4" @@ -3280,12 +3330,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1400]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -3312,7 +3363,7 @@ ] }, "fsub st0, st3": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "0xd8 11b 0xe3 /4" @@ -3345,12 +3396,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1400]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -3377,7 +3429,7 @@ ] }, "fsub st0, st4": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "0xd8 11b 0xe4 /4" @@ -3410,12 +3462,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1400]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -3442,7 +3495,7 @@ ] }, "fsub st0, st5": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "0xd8 11b 0xe5 /4" @@ -3475,12 +3528,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1400]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -3507,7 +3561,7 @@ ] }, "fsub st0, st6": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "0xd8 11b 0xe6 /4" @@ -3540,12 +3594,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1400]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -3572,7 +3627,7 @@ ] }, "fsub st0, st7": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "0xd8 11b 0xe7 /4" @@ -3605,12 +3660,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1400]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -3637,7 +3693,7 @@ ] }, "fsubr st0, st0": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "0xd8 11b 0xe8 /5" @@ -3670,12 +3726,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1400]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -3702,7 +3759,7 @@ ] }, "fsubr st0, st1": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "0xd8 11b 0xe9 /5" @@ -3735,12 +3792,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v2.d[0]", - "umov w1, v2.h[4]", - "mov x2, v3.d[0]", - "umov w3, v3.h[4]", - "ldr x4, [x28, #1400]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -3767,7 +3825,7 @@ ] }, "fsubr st0, st2": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "0xd8 11b 0xea /5" @@ -3800,12 +3858,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v2.d[0]", - "umov w1, v2.h[4]", - "mov x2, v3.d[0]", - "umov w3, v3.h[4]", - "ldr x4, [x28, #1400]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -3832,7 +3891,7 @@ ] }, "fsubr st0, st3": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "0xd8 11b 0xeb /5" @@ -3865,12 +3924,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v2.d[0]", - "umov w1, v2.h[4]", - "mov x2, v3.d[0]", - "umov w3, v3.h[4]", - "ldr x4, [x28, #1400]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -3897,7 +3957,7 @@ ] }, "fsubr st0, st4": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "0xd8 11b 0xec /5" @@ -3930,12 +3990,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v2.d[0]", - "umov w1, v2.h[4]", - "mov x2, v3.d[0]", - "umov w3, v3.h[4]", - "ldr x4, [x28, #1400]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -3962,7 +4023,7 @@ ] }, "fsubr st0, st5": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "0xd8 11b 0xed /5" @@ -3995,12 +4056,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v2.d[0]", - "umov w1, v2.h[4]", - "mov x2, v3.d[0]", - "umov w3, v3.h[4]", - "ldr x4, [x28, #1400]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -4027,7 +4089,7 @@ ] }, "fsubr st0, st6": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "0xd8 11b 0xee /5" @@ -4060,12 +4122,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v2.d[0]", - "umov w1, v2.h[4]", - "mov x2, v3.d[0]", - "umov w3, v3.h[4]", - "ldr x4, [x28, #1400]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -4092,7 +4155,7 @@ ] }, "fsubr st0, st7": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "0xd8 11b 0xef /5" @@ -4125,12 +4188,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v2.d[0]", - "umov w1, v2.h[4]", - "mov x2, v3.d[0]", - "umov w3, v3.h[4]", - "ldr x4, [x28, #1400]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -4157,7 +4221,7 @@ ] }, "fdiv st0, st0": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "0xd8 11b 0xf0 /6" @@ -4190,12 +4254,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v2.d[0]", - "umov w1, v2.h[4]", - "mov x2, v3.d[0]", - "umov w3, v3.h[4]", - "ldr x4, [x28, #1416]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1416]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -4222,7 +4287,7 @@ ] }, "fdiv st0, st1": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "0xd8 11b 0xf1 /6" @@ -4255,12 +4320,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1416]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1416]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -4287,7 +4353,7 @@ ] }, "fdiv st0, st2": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "0xd8 11b 0xf2 /6" @@ -4320,12 +4386,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1416]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1416]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -4352,7 +4419,7 @@ ] }, "fdiv st0, st3": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "0xd8 11b 0xf3 /6" @@ -4385,12 +4452,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1416]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1416]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -4417,7 +4485,7 @@ ] }, "fdiv st0, st4": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "0xd8 11b 0xf4 /6" @@ -4450,12 +4518,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1416]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1416]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -4482,7 +4551,7 @@ ] }, "fdiv st0, st5": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "0xd8 11b 0xf5 /6" @@ -4515,12 +4584,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1416]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1416]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -4547,7 +4617,7 @@ ] }, "fdiv st0, st6": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "0xd8 11b 0xf6 /6" @@ -4580,12 +4650,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1416]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1416]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -4612,7 +4683,7 @@ ] }, "fdiv st0, st7": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "0xd8 11b 0xf7 /6" @@ -4645,12 +4716,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1416]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1416]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -4677,7 +4749,7 @@ ] }, "fdivr st0, st0": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "0xd8 11b 0xf8 /7" @@ -4710,12 +4782,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1416]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1416]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -4742,7 +4815,7 @@ ] }, "fdivr st0, st1": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "0xd8 11b 0xf9 /7" @@ -4775,12 +4848,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v2.d[0]", - "umov w1, v2.h[4]", - "mov x2, v3.d[0]", - "umov w3, v3.h[4]", - "ldr x4, [x28, #1416]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1416]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -4807,7 +4881,7 @@ ] }, "fdivr st0, st2": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "0xd8 11b 0xfa /7" @@ -4840,12 +4914,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v2.d[0]", - "umov w1, v2.h[4]", - "mov x2, v3.d[0]", - "umov w3, v3.h[4]", - "ldr x4, [x28, #1416]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1416]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -4872,7 +4947,7 @@ ] }, "fdivr st0, st3": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "0xd8 11b 0xfb /7" @@ -4905,12 +4980,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v2.d[0]", - "umov w1, v2.h[4]", - "mov x2, v3.d[0]", - "umov w3, v3.h[4]", - "ldr x4, [x28, #1416]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1416]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -4937,7 +5013,7 @@ ] }, "fdivr st0, st4": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "0xd8 11b 0xfc /7" @@ -4970,12 +5046,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v2.d[0]", - "umov w1, v2.h[4]", - "mov x2, v3.d[0]", - "umov w3, v3.h[4]", - "ldr x4, [x28, #1416]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1416]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -5002,7 +5079,7 @@ ] }, "fdivr st0, st5": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "0xd8 11b 0xfd /7" @@ -5035,12 +5112,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v2.d[0]", - "umov w1, v2.h[4]", - "mov x2, v3.d[0]", - "umov w3, v3.h[4]", - "ldr x4, [x28, #1416]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1416]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -5067,7 +5145,7 @@ ] }, "fdivr st0, st6": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "0xd8 11b 0xfe /7" @@ -5100,12 +5178,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v2.d[0]", - "umov w1, v2.h[4]", - "mov x2, v3.d[0]", - "umov w3, v3.h[4]", - "ldr x4, [x28, #1416]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1416]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -5132,7 +5211,7 @@ ] }, "fdivr st0, st7": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "0xd8 11b 0xff /7" @@ -5165,12 +5244,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v2.d[0]", - "umov w1, v2.h[4]", - "mov x2, v3.d[0]", - "umov w3, v3.h[4]", - "ldr x4, [x28, #1416]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1416]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -5197,7 +5277,7 @@ ] }, "fld dword [rax]": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "0xd9 !11b /0" @@ -5226,8 +5306,9 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "fmov s0, s2", - "ldr x0, [x28, #1152]", - "blr x0", + "ldrh w0, [x28, #1008]", + "ldr x1, [x28, #1152]", + "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -5262,7 +5343,7 @@ ] }, "fst dword [rax]": { - "ExpectedInstructionCount": 47, + "ExpectedInstructionCount": 48, "Optimal": "No", "Comment": [ "0xd9 !11b /2" @@ -5291,10 +5372,11 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v2.d[0]", - "umov w1, v2.h[4]", - "ldr x2, [x28, #1168]", - "blr x2", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1168]", + "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -5318,7 +5400,7 @@ ] }, "fstp dword [rax]": { - "ExpectedInstructionCount": 55, + "ExpectedInstructionCount": 56, "Optimal": "No", "Comment": [ "0xd9 !11b /3" @@ -5347,10 +5429,11 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v2.d[0]", - "umov w1, v2.h[4]", - "ldr x2, [x28, #1168]", - "blr x2", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1168]", + "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -5382,54 +5465,13 @@ ] }, "fldenv [rax]": { - "ExpectedInstructionCount": 104, + "ExpectedInstructionCount": 63, "Optimal": "No", "Comment": [ "0xd9 !11b /4" ], "ExpectedArm64ASM": [ "ldrh w20, [x4]", - "stp x4, x5, [x28, #8]", - "stp x6, x7, [x28, #24]", - "stp x8, x9, [x28, #40]", - "stp x10, x11, [x28, #56]", - "stp x12, x13, [x28, #72]", - "stp x14, x15, [x28, #88]", - "stp x16, x17, [x28, #104]", - "stp x19, x29, [x28, #120]", - "add x0, x28, #0xc0 (192)", - "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", - "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", - "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", - "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", - "sub sp, sp, #0xf0 (240)", - "mov x0, sp", - "st1 {v2.2d, v3.2d}, [x0], #32", - "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", - "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", - "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", - "str x30, [x0]", - "uxth w0, w20", - "ldr x1, [x28, #1144]", - "blr x1", - "ld1 {v2.2d, v3.2d}, [sp], #32", - "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", - "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", - "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", - "ldr x30, [sp], #16", - "add x5, x28, #0xc0 (192)", - "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", - "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", - "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", - "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", - "ldp x4, x5, [x28, #8]", - "ldp x6, x7, [x28, #24]", - "ldp x8, x9, [x28, #40]", - "ldp x10, x11, [x28, #56]", - "ldp x12, x13, [x28, #72]", - "ldp x14, x15, [x28, #88]", - "ldp x16, x17, [x28, #104]", - "ldp x19, x29, [x28, #120]", "strh w20, [x28, #1008]", "ldr w20, [x4, #4]", "ubfx w21, w20, #11, #3", @@ -5495,54 +5537,13 @@ ] }, "fldcw [rax]": { - "ExpectedInstructionCount": 43, + "ExpectedInstructionCount": 2, "Optimal": "No", "Comment": [ "0xd9 !11b /5" ], "ExpectedArm64ASM": [ "ldrh w20, [x4]", - "stp x4, x5, [x28, #8]", - "stp x6, x7, [x28, #24]", - "stp x8, x9, [x28, #40]", - "stp x10, x11, [x28, #56]", - "stp x12, x13, [x28, #72]", - "stp x14, x15, [x28, #88]", - "stp x16, x17, [x28, #104]", - "stp x19, x29, [x28, #120]", - "add x0, x28, #0xc0 (192)", - "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", - "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", - "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", - "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", - "sub sp, sp, #0xf0 (240)", - "mov x0, sp", - "st1 {v2.2d, v3.2d}, [x0], #32", - "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", - "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", - "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", - "str x30, [x0]", - "uxth w0, w20", - "ldr x1, [x28, #1144]", - "blr x1", - "ld1 {v2.2d, v3.2d}, [sp], #32", - "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", - "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", - "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", - "ldr x30, [sp], #16", - "add x5, x28, #0xc0 (192)", - "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", - "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", - "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", - "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", - "ldp x4, x5, [x28, #8]", - "ldp x6, x7, [x28, #24]", - "ldp x8, x9, [x28, #40]", - "ldp x10, x11, [x28, #56]", - "ldp x12, x13, [x28, #72]", - "ldp x14, x15, [x28, #88]", - "ldp x16, x17, [x28, #104]", - "ldp x19, x29, [x28, #120]", "strh w20, [x28, #1008]" ] }, @@ -6037,7 +6038,7 @@ ] }, "ftst": { - "ExpectedInstructionCount": 59, + "ExpectedInstructionCount": 60, "Optimal": "No", "Comment": [ "0xd9 11b 0xe4 /4" @@ -6068,12 +6069,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v2.d[0]", - "umov w1, v2.h[4]", - "mov x2, v3.d[0]", - "umov w3, v3.h[4]", - "ldr x4, [x28, #1288]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1288]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -6312,7 +6314,7 @@ ] }, "f2xm1": { - "ExpectedInstructionCount": 50, + "ExpectedInstructionCount": 51, "Optimal": "No", "Comment": [ "0xd9 11b 0xf0 /6" @@ -6341,10 +6343,11 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v2.d[0]", - "umov w1, v2.h[4]", - "ldr x2, [x28, #1320]", - "blr x2", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1320]", + "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -6371,7 +6374,7 @@ ] }, "fyl2x": { - "ExpectedInstructionCount": 62, + "ExpectedInstructionCount": 63, "Optimal": "No", "Comment": [ "0xd9 11b 0xf1 /6" @@ -6410,12 +6413,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v2.d[0]", - "umov w1, v2.h[4]", - "mov x2, v3.d[0]", - "umov w3, v3.h[4]", - "ldr x4, [x28, #1424]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1424]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -6442,7 +6446,7 @@ ] }, "fptan": { - "ExpectedInstructionCount": 66, + "ExpectedInstructionCount": 67, "Optimal": "No", "Comment": [ "0xd9 11b 0xf2 /6" @@ -6479,10 +6483,11 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v2.d[0]", - "umov w1, v2.h[4]", - "ldr x2, [x28, #1328]", - "blr x2", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1328]", + "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -6517,7 +6522,7 @@ ] }, "fpatan": { - "ExpectedInstructionCount": 62, + "ExpectedInstructionCount": 63, "Optimal": "No", "Comment": [ "0xd9 11b 0xf3 /6" @@ -6556,12 +6561,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1432]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1432]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -6588,7 +6594,7 @@ ] }, "fxtract": { - "ExpectedInstructionCount": 105, + "ExpectedInstructionCount": 107, "Optimal": "No", "Comment": [ "0xd9 11b 0xf4 /6" @@ -6625,10 +6631,11 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v2.d[0]", - "umov w1, v2.h[4]", - "ldr x2, [x28, #1360]", - "blr x2", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1360]", + "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -6670,10 +6677,11 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v2.d[0]", - "umov w1, v2.h[4]", - "ldr x2, [x28, #1368]", - "blr x2", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1368]", + "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -6702,7 +6710,7 @@ ] }, "fprem1": { - "ExpectedInstructionCount": 58, + "ExpectedInstructionCount": 59, "Optimal": "No", "Comment": [ "0xd9 11b 0xf5 /6" @@ -6735,12 +6743,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v2.d[0]", - "umov w1, v2.h[4]", - "mov x2, v3.d[0]", - "umov w3, v3.h[4]", - "ldr x4, [x28, #1440]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1440]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -6795,7 +6804,7 @@ ] }, "fprem": { - "ExpectedInstructionCount": 58, + "ExpectedInstructionCount": 59, "Optimal": "No", "Comment": [ "0xd9 11b 0xf8 /7" @@ -6828,12 +6837,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v2.d[0]", - "umov w1, v2.h[4]", - "mov x2, v3.d[0]", - "umov w3, v3.h[4]", - "ldr x4, [x28, #1448]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1448]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -6862,7 +6872,7 @@ ] }, "fyl2xp1": { - "ExpectedInstructionCount": 113, + "ExpectedInstructionCount": 115, "Optimal": "No", "Comment": [ "0xd9 11b 0xf9 /7" @@ -6905,12 +6915,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v2.d[0]", - "umov w1, v2.h[4]", - "mov x2, v4.d[0]", - "umov w3, v4.h[4]", - "ldr x4, [x28, #1392]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v4.d[0]", + "umov w4, v4.h[4]", + "ldr x5, [x28, #1392]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -6952,12 +6963,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v2.d[0]", - "umov w1, v2.h[4]", - "mov x2, v3.d[0]", - "umov w3, v3.h[4]", - "ldr x4, [x28, #1424]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1424]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -6984,7 +6996,7 @@ ] }, "fsqrt": { - "ExpectedInstructionCount": 50, + "ExpectedInstructionCount": 51, "Optimal": "No", "Comment": [ "0xd9 11b 0xfa /7" @@ -7013,10 +7025,11 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v2.d[0]", - "umov w1, v2.h[4]", - "ldr x2, [x28, #1336]", - "blr x2", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1336]", + "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -7043,7 +7056,7 @@ ] }, "fsincos": { - "ExpectedInstructionCount": 107, + "ExpectedInstructionCount": 109, "Optimal": "No", "Comment": [ "0xd9 11b 0xfb /7" @@ -7080,10 +7093,11 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v2.d[0]", - "umov w1, v2.h[4]", - "ldr x2, [x28, #1344]", - "blr x2", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1344]", + "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -7125,10 +7139,11 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v2.d[0]", - "umov w1, v2.h[4]", - "ldr x2, [x28, #1352]", - "blr x2", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1352]", + "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -7159,7 +7174,7 @@ ] }, "frndint": { - "ExpectedInstructionCount": 50, + "ExpectedInstructionCount": 51, "Optimal": "No", "Comment": [ "0xd9 11b 0xfc /7" @@ -7188,10 +7203,11 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v2.d[0]", - "umov w1, v2.h[4]", - "ldr x2, [x28, #1312]", - "blr x2", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1312]", + "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -7218,7 +7234,7 @@ ] }, "fscale": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "0xd9 11b 0xfd /7" @@ -7251,12 +7267,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v2.d[0]", - "umov w1, v2.h[4]", - "mov x2, v3.d[0]", - "umov w3, v3.h[4]", - "ldr x4, [x28, #1456]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1456]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -7283,7 +7300,7 @@ ] }, "fsin": { - "ExpectedInstructionCount": 52, + "ExpectedInstructionCount": 53, "Optimal": "No", "Comment": [ "0xd9 11b 0xfe /7" @@ -7312,10 +7329,11 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v2.d[0]", - "umov w1, v2.h[4]", - "ldr x2, [x28, #1344]", - "blr x2", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1344]", + "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -7344,7 +7362,7 @@ ] }, "fcos": { - "ExpectedInstructionCount": 52, + "ExpectedInstructionCount": 53, "Optimal": "No", "Comment": [ "0xd9 11b 0xff /7" @@ -7373,10 +7391,11 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v2.d[0]", - "umov w1, v2.h[4]", - "ldr x2, [x28, #1352]", - "blr x2", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1352]", + "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -7405,7 +7424,7 @@ ] }, "fiadd dword [rax]": { - "ExpectedInstructionCount": 97, + "ExpectedInstructionCount": 99, "Optimal": "No", "Comment": [ "0xda !11b /0" @@ -7433,9 +7452,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov w0, w21", - "ldr x1, [x28, #1304]", - "blr x1", + "ldrh w0, [x28, #1008]", + "mov w1, w21", + "ldr x2, [x28, #1304]", + "blr x2", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -7479,12 +7499,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1392]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1392]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -7511,7 +7532,7 @@ ] }, "fimul dword [rax]": { - "ExpectedInstructionCount": 97, + "ExpectedInstructionCount": 99, "Optimal": "No", "Comment": [ "0xda !11b /1" @@ -7539,9 +7560,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov w0, w21", - "ldr x1, [x28, #1304]", - "blr x1", + "ldrh w0, [x28, #1008]", + "mov w1, w21", + "ldr x2, [x28, #1304]", + "blr x2", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -7585,12 +7607,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1408]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1408]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -7617,7 +7640,7 @@ ] }, "ficom dword [rax]": { - "ExpectedInstructionCount": 103, + "ExpectedInstructionCount": 105, "Optimal": "No", "Comment": [ "0xda !11b /2" @@ -7645,9 +7668,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov w0, w21", - "ldr x1, [x28, #1304]", - "blr x1", + "ldrh w0, [x28, #1008]", + "mov w1, w21", + "ldr x2, [x28, #1304]", + "blr x2", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -7691,12 +7715,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1288]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1288]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -7729,7 +7754,7 @@ ] }, "ficomp dword [rax]": { - "ExpectedInstructionCount": 111, + "ExpectedInstructionCount": 113, "Optimal": "No", "Comment": [ "0xda !11b /3" @@ -7757,9 +7782,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov w0, w21", - "ldr x1, [x28, #1304]", - "blr x1", + "ldrh w0, [x28, #1008]", + "mov w1, w21", + "ldr x2, [x28, #1304]", + "blr x2", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -7803,12 +7829,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1288]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1288]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -7849,7 +7876,7 @@ ] }, "fisub dword [rax]": { - "ExpectedInstructionCount": 97, + "ExpectedInstructionCount": 99, "Optimal": "No", "Comment": [ "0xda !11b /4" @@ -7877,9 +7904,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov w0, w21", - "ldr x1, [x28, #1304]", - "blr x1", + "ldrh w0, [x28, #1008]", + "mov w1, w21", + "ldr x2, [x28, #1304]", + "blr x2", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -7923,12 +7951,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1400]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -7955,7 +7984,7 @@ ] }, "fisubr dword [rax]": { - "ExpectedInstructionCount": 97, + "ExpectedInstructionCount": 99, "Optimal": "No", "Comment": [ "0xda !11b /5" @@ -7983,9 +8012,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov w0, w21", - "ldr x1, [x28, #1304]", - "blr x1", + "ldrh w0, [x28, #1008]", + "mov w1, w21", + "ldr x2, [x28, #1304]", + "blr x2", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -8029,12 +8059,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v2.d[0]", - "umov w1, v2.h[4]", - "mov x2, v3.d[0]", - "umov w3, v3.h[4]", - "ldr x4, [x28, #1400]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -8061,7 +8092,7 @@ ] }, "fidiv dword [rax]": { - "ExpectedInstructionCount": 97, + "ExpectedInstructionCount": 99, "Optimal": "No", "Comment": [ "0xda !11b /6" @@ -8089,9 +8120,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov w0, w21", - "ldr x1, [x28, #1304]", - "blr x1", + "ldrh w0, [x28, #1008]", + "mov w1, w21", + "ldr x2, [x28, #1304]", + "blr x2", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -8135,12 +8167,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1416]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1416]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -8167,7 +8200,7 @@ ] }, "fidivr dword [rax]": { - "ExpectedInstructionCount": 97, + "ExpectedInstructionCount": 99, "Optimal": "No", "Comment": [ "0xda !11b /7" @@ -8195,9 +8228,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov w0, w21", - "ldr x1, [x28, #1304]", - "blr x1", + "ldrh w0, [x28, #1008]", + "mov w1, w21", + "ldr x2, [x28, #1304]", + "blr x2", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -8241,12 +8275,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v2.d[0]", - "umov w1, v2.h[4]", - "mov x2, v3.d[0]", - "umov w3, v3.h[4]", - "ldr x4, [x28, #1416]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1416]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -9217,7 +9252,7 @@ ] }, "fucompp": { - "ExpectedInstructionCount": 76, + "ExpectedInstructionCount": 77, "Optimal": "No", "Comment": [ "0xda 11b 0xe9 /5" @@ -9251,12 +9286,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1288]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1288]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -9344,7 +9380,7 @@ ] }, "fisttp dword [rax]": { - "ExpectedInstructionCount": 55, + "ExpectedInstructionCount": 56, "Optimal": "No", "Comment": [ "0xdb !11b /1" @@ -9373,10 +9409,11 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v2.d[0]", - "umov w1, v2.h[4]", - "ldr x2, [x28, #1216]", - "blr x2", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1216]", + "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -9408,7 +9445,7 @@ ] }, "fist dword [rax]": { - "ExpectedInstructionCount": 47, + "ExpectedInstructionCount": 48, "Optimal": "No", "Comment": [ "0xdb !11b /2" @@ -9437,10 +9474,11 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v2.d[0]", - "umov w1, v2.h[4]", - "ldr x2, [x28, #1192]", - "blr x2", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1192]", + "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -9464,7 +9502,7 @@ ] }, "fistp dword [rax]": { - "ExpectedInstructionCount": 55, + "ExpectedInstructionCount": 56, "Optimal": "No", "Comment": [ "0xdf !11b /7" @@ -9493,10 +9531,11 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v2.d[0]", - "umov w1, v2.h[4]", - "ldr x2, [x28, #1192]", - "blr x2", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1192]", + "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -10524,7 +10563,7 @@ "ExpectedArm64ASM": [] }, "fninit": { - "ExpectedInstructionCount": 50, + "ExpectedInstructionCount": 9, "Optimal": "No", "Comment": [ "0xdb 11b 0xe3 /4" @@ -10532,47 +10571,6 @@ "ExpectedArm64ASM": [ "mov w20, #0x0", "mov w21, #0x37f", - "stp x4, x5, [x28, #8]", - "stp x6, x7, [x28, #24]", - "stp x8, x9, [x28, #40]", - "stp x10, x11, [x28, #56]", - "stp x12, x13, [x28, #72]", - "stp x14, x15, [x28, #88]", - "stp x16, x17, [x28, #104]", - "stp x19, x29, [x28, #120]", - "add x0, x28, #0xc0 (192)", - "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", - "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", - "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", - "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", - "sub sp, sp, #0xf0 (240)", - "mov x0, sp", - "st1 {v2.2d, v3.2d}, [x0], #32", - "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", - "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", - "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", - "str x30, [x0]", - "uxth w0, w21", - "ldr x1, [x28, #1144]", - "blr x1", - "ld1 {v2.2d, v3.2d}, [sp], #32", - "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", - "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", - "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", - "ldr x30, [sp], #16", - "add x5, x28, #0xc0 (192)", - "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", - "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", - "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", - "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", - "ldp x4, x5, [x28, #8]", - "ldp x6, x7, [x28, #24]", - "ldp x8, x9, [x28, #40]", - "ldp x10, x11, [x28, #56]", - "ldp x12, x13, [x28, #72]", - "ldp x14, x15, [x28, #88]", - "ldp x16, x17, [x28, #104]", - "ldp x19, x29, [x28, #120]", "strh w21, [x28, #1008]", "strb w20, [x28, #747]", "strb w20, [x28, #744]", @@ -10583,7 +10581,7 @@ ] }, "fucomi st0, st0": { - "ExpectedInstructionCount": 62, + "ExpectedInstructionCount": 63, "Optimal": "No", "Comment": [ "0xdb 11b 0xe8 /5" @@ -10616,12 +10614,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1288]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1288]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -10654,7 +10653,7 @@ ] }, "fucomi st0, st1": { - "ExpectedInstructionCount": 62, + "ExpectedInstructionCount": 63, "Optimal": "No", "Comment": [ "0xdb 11b 0xe9 /5" @@ -10687,12 +10686,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1288]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1288]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -10725,7 +10725,7 @@ ] }, "fucomi st0, st2": { - "ExpectedInstructionCount": 62, + "ExpectedInstructionCount": 63, "Optimal": "No", "Comment": [ "0xdb 11b 0xea /5" @@ -10758,12 +10758,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1288]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1288]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -10796,7 +10797,7 @@ ] }, "fucomi st0, st3": { - "ExpectedInstructionCount": 62, + "ExpectedInstructionCount": 63, "Optimal": "No", "Comment": [ "0xdb 11b 0xeb /5" @@ -10829,12 +10830,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1288]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1288]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -10867,7 +10869,7 @@ ] }, "fucomi st0, st4": { - "ExpectedInstructionCount": 62, + "ExpectedInstructionCount": 63, "Optimal": "No", "Comment": [ "0xdb 11b 0xec /5" @@ -10900,12 +10902,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1288]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1288]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -10938,7 +10941,7 @@ ] }, "fucomi st0, st5": { - "ExpectedInstructionCount": 62, + "ExpectedInstructionCount": 63, "Optimal": "No", "Comment": [ "0xdb 11b 0xed /5" @@ -10971,12 +10974,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1288]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1288]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -11009,7 +11013,7 @@ ] }, "fucomi st0, st6": { - "ExpectedInstructionCount": 62, + "ExpectedInstructionCount": 63, "Optimal": "No", "Comment": [ "0xdb 11b 0xee /5" @@ -11042,12 +11046,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1288]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1288]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -11080,7 +11085,7 @@ ] }, "fucomi st0, st7": { - "ExpectedInstructionCount": 62, + "ExpectedInstructionCount": 63, "Optimal": "No", "Comment": [ "0xdb 11b 0xef /5" @@ -11113,12 +11118,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1288]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1288]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -11151,7 +11157,7 @@ ] }, "fcomi st0, st0": { - "ExpectedInstructionCount": 62, + "ExpectedInstructionCount": 63, "Optimal": "No", "Comment": [ "0xdb 11b 0xf0 /6" @@ -11184,12 +11190,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1288]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1288]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -11222,7 +11229,7 @@ ] }, "fcomi st0, st1": { - "ExpectedInstructionCount": 62, + "ExpectedInstructionCount": 63, "Optimal": "No", "Comment": [ "0xdb 11b 0xf1 /6" @@ -11255,12 +11262,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1288]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1288]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -11293,7 +11301,7 @@ ] }, "fcomi st0, st2": { - "ExpectedInstructionCount": 62, + "ExpectedInstructionCount": 63, "Optimal": "No", "Comment": [ "0xdb 11b 0xf2 /6" @@ -11326,12 +11334,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1288]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1288]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -11364,7 +11373,7 @@ ] }, "fcomi st0, st3": { - "ExpectedInstructionCount": 62, + "ExpectedInstructionCount": 63, "Optimal": "No", "Comment": [ "0xdb 11b 0xf3 /6" @@ -11397,12 +11406,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1288]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1288]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -11435,7 +11445,7 @@ ] }, "fcomi st0, st4": { - "ExpectedInstructionCount": 62, + "ExpectedInstructionCount": 63, "Optimal": "No", "Comment": [ "0xdb 11b 0xf4 /6" @@ -11468,12 +11478,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1288]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1288]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -11506,7 +11517,7 @@ ] }, "fcomi st0, st5": { - "ExpectedInstructionCount": 62, + "ExpectedInstructionCount": 63, "Optimal": "No", "Comment": [ "0xdb 11b 0xf5 /6" @@ -11539,12 +11550,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1288]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1288]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -11577,7 +11589,7 @@ ] }, "fcomi st0, st6": { - "ExpectedInstructionCount": 62, + "ExpectedInstructionCount": 63, "Optimal": "No", "Comment": [ "0xdb 11b 0xf6 /6" @@ -11610,12 +11622,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1288]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1288]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -11648,7 +11661,7 @@ ] }, "fcomi st0, st7": { - "ExpectedInstructionCount": 62, + "ExpectedInstructionCount": 63, "Optimal": "No", "Comment": [ "0xdb 11b 0xf7 /6" @@ -11681,12 +11694,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1288]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1288]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -11719,7 +11733,7 @@ ] }, "fadd qword [rax]": { - "ExpectedInstructionCount": 97, + "ExpectedInstructionCount": 99, "Optimal": "No", "Comment": [ "0xdc !11b /0" @@ -11748,8 +11762,9 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldr x0, [x28, #1160]", - "blr x0", + "ldrh w0, [x28, #1008]", + "ldr x1, [x28, #1160]", + "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -11793,12 +11808,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1392]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1392]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -11825,7 +11841,7 @@ ] }, "fmul qword [rax]": { - "ExpectedInstructionCount": 97, + "ExpectedInstructionCount": 99, "Optimal": "No", "Comment": [ "0xdc !11b /1" @@ -11854,8 +11870,9 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldr x0, [x28, #1160]", - "blr x0", + "ldrh w0, [x28, #1008]", + "ldr x1, [x28, #1160]", + "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -11899,12 +11916,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1408]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1408]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -11931,7 +11949,7 @@ ] }, "fcom qword [rax]": { - "ExpectedInstructionCount": 103, + "ExpectedInstructionCount": 105, "Optimal": "No", "Comment": [ "0xdc !11b /2" @@ -11960,8 +11978,9 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldr x0, [x28, #1160]", - "blr x0", + "ldrh w0, [x28, #1008]", + "ldr x1, [x28, #1160]", + "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -12005,12 +12024,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1288]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1288]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -12043,7 +12063,7 @@ ] }, "fcomp qword [rax]": { - "ExpectedInstructionCount": 111, + "ExpectedInstructionCount": 113, "Optimal": "No", "Comment": [ "0xdc !11b /3" @@ -12072,8 +12092,9 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldr x0, [x28, #1160]", - "blr x0", + "ldrh w0, [x28, #1008]", + "ldr x1, [x28, #1160]", + "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -12117,12 +12138,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1288]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1288]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -12163,7 +12185,7 @@ ] }, "fsub qword [rax]": { - "ExpectedInstructionCount": 97, + "ExpectedInstructionCount": 99, "Optimal": "No", "Comment": [ "0xdc !11b /4" @@ -12192,8 +12214,9 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldr x0, [x28, #1160]", - "blr x0", + "ldrh w0, [x28, #1008]", + "ldr x1, [x28, #1160]", + "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -12237,12 +12260,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1400]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -12269,7 +12293,7 @@ ] }, "fsubr qword [rax]": { - "ExpectedInstructionCount": 97, + "ExpectedInstructionCount": 99, "Optimal": "No", "Comment": [ "0xdc !11b /5" @@ -12298,8 +12322,9 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldr x0, [x28, #1160]", - "blr x0", + "ldrh w0, [x28, #1008]", + "ldr x1, [x28, #1160]", + "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -12343,12 +12368,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v2.d[0]", - "umov w1, v2.h[4]", - "mov x2, v3.d[0]", - "umov w3, v3.h[4]", - "ldr x4, [x28, #1400]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -12375,7 +12401,7 @@ ] }, "fdiv qword [rax]": { - "ExpectedInstructionCount": 97, + "ExpectedInstructionCount": 99, "Optimal": "No", "Comment": [ "0xdc !11b /6" @@ -12404,8 +12430,9 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldr x0, [x28, #1160]", - "blr x0", + "ldrh w0, [x28, #1008]", + "ldr x1, [x28, #1160]", + "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -12449,12 +12476,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1416]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1416]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -12481,7 +12509,7 @@ ] }, "fdivr qword [rax]": { - "ExpectedInstructionCount": 97, + "ExpectedInstructionCount": 99, "Optimal": "No", "Comment": [ "0xdc !11b /7" @@ -12510,8 +12538,9 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldr x0, [x28, #1160]", - "blr x0", + "ldrh w0, [x28, #1008]", + "ldr x1, [x28, #1160]", + "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -12555,12 +12584,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v2.d[0]", - "umov w1, v2.h[4]", - "mov x2, v3.d[0]", - "umov w3, v3.h[4]", - "ldr x4, [x28, #1416]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1416]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -12587,7 +12617,7 @@ ] }, "db 0xdc, 0xc0": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "fadd st0, st0", @@ -12622,12 +12652,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1392]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1392]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -12654,7 +12685,7 @@ ] }, "fadd st1, st0": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "0xdc 11b 0xc1 /0" @@ -12687,12 +12718,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1392]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1392]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -12719,7 +12751,7 @@ ] }, "fadd st2, st0": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "0xdc 11b 0xc2 /0" @@ -12752,12 +12784,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1392]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1392]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -12784,7 +12817,7 @@ ] }, "fadd st3, st0": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "0xdc 11b 0xc3 /0" @@ -12817,12 +12850,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1392]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1392]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -12849,7 +12883,7 @@ ] }, "fadd st4, st0": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "0xdc 11b 0xc4 /0" @@ -12882,12 +12916,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1392]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1392]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -12914,7 +12949,7 @@ ] }, "fadd st5, st0": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "0xdc 11b 0xc5 /0" @@ -12947,12 +12982,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1392]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1392]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -12979,7 +13015,7 @@ ] }, "fadd st6, st0": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "0xdc 11b 0xc6 /0" @@ -13012,12 +13048,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1392]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1392]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -13044,7 +13081,7 @@ ] }, "fadd st7, st0": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "0xdc 11b 0xc7 /0" @@ -13077,12 +13114,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1392]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1392]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -13109,7 +13147,7 @@ ] }, "db 0xdc, 0xc8": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "fmul st0, st0", @@ -13144,12 +13182,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1408]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1408]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -13176,7 +13215,7 @@ ] }, "fmul st1, st0": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "0xdc 11b 0xc9 /1" @@ -13209,12 +13248,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1408]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1408]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -13241,7 +13281,7 @@ ] }, "fmul st2, st0": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "0xdc 11b 0xca /1" @@ -13274,12 +13314,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1408]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1408]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -13306,7 +13347,7 @@ ] }, "fmul st3, st0": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "0xdc 11b 0xcb /1" @@ -13339,12 +13380,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1408]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1408]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -13371,7 +13413,7 @@ ] }, "fmul st4, st0": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "0xdc 11b 0xcc /1" @@ -13404,12 +13446,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1408]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1408]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -13436,7 +13479,7 @@ ] }, "fmul st5, st0": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "0xdc 11b 0xcd /1" @@ -13469,12 +13512,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1408]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1408]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -13501,7 +13545,7 @@ ] }, "fmul st6, st0": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "0xdc 11b 0xce /1" @@ -13534,12 +13578,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1408]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1408]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -13566,7 +13611,7 @@ ] }, "fmul st7, st0": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "0xdc 11b 0xcf /1" @@ -13599,12 +13644,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1408]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1408]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -13631,7 +13677,7 @@ ] }, "db 0xdc, 0xe0": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "fsubr st0, st0", @@ -13666,12 +13712,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1400]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -13698,7 +13745,7 @@ ] }, "fsubr st1, st0": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "0xdc 11b 0xe1 /4" @@ -13731,12 +13778,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1400]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -13763,7 +13811,7 @@ ] }, "fsubr st2, st0": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "0xdc 11b 0xe2 /4" @@ -13796,12 +13844,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1400]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -13828,7 +13877,7 @@ ] }, "fsubr st3, st0": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "0xdc 11b 0xe3 /4" @@ -13861,12 +13910,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1400]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -13893,7 +13943,7 @@ ] }, "fsubr st4, st0": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "0xdc 11b 0xe4 /4" @@ -13926,12 +13976,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1400]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -13958,7 +14009,7 @@ ] }, "fsubr st5, st0": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "0xdc 11b 0xe5 /4" @@ -13991,12 +14042,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1400]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -14023,7 +14075,7 @@ ] }, "fsubr st6, st0": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "0xdc 11b 0xe6 /4" @@ -14056,12 +14108,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1400]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -14088,7 +14141,7 @@ ] }, "fsubr st7, st0": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "0xdc 11b 0xe7 /4" @@ -14121,12 +14174,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1400]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -14153,7 +14207,7 @@ ] }, "db 0xdc, 0xe8": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "fsub st0, st0", @@ -14188,12 +14242,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v2.d[0]", - "umov w1, v2.h[4]", - "mov x2, v3.d[0]", - "umov w3, v3.h[4]", - "ldr x4, [x28, #1400]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -14220,7 +14275,7 @@ ] }, "fsub st1, st0": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "0xdc 11b 0xe9 /5" @@ -14253,12 +14308,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v2.d[0]", - "umov w1, v2.h[4]", - "mov x2, v3.d[0]", - "umov w3, v3.h[4]", - "ldr x4, [x28, #1400]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -14285,7 +14341,7 @@ ] }, "fsub st2, st0": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "0xdc 11b 0xea /5" @@ -14318,12 +14374,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v2.d[0]", - "umov w1, v2.h[4]", - "mov x2, v3.d[0]", - "umov w3, v3.h[4]", - "ldr x4, [x28, #1400]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -14350,7 +14407,7 @@ ] }, "fsub st3, st0": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "0xdc 11b 0xeb /5" @@ -14383,12 +14440,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v2.d[0]", - "umov w1, v2.h[4]", - "mov x2, v3.d[0]", - "umov w3, v3.h[4]", - "ldr x4, [x28, #1400]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -14415,7 +14473,7 @@ ] }, "fsub st4, st0": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "0xdc 11b 0xec /5" @@ -14448,12 +14506,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v2.d[0]", - "umov w1, v2.h[4]", - "mov x2, v3.d[0]", - "umov w3, v3.h[4]", - "ldr x4, [x28, #1400]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -14480,7 +14539,7 @@ ] }, "fsub st5, st0": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "0xdc 11b 0xed /5" @@ -14513,12 +14572,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v2.d[0]", - "umov w1, v2.h[4]", - "mov x2, v3.d[0]", - "umov w3, v3.h[4]", - "ldr x4, [x28, #1400]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -14545,7 +14605,7 @@ ] }, "fsub st6, st0": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "0xdc 11b 0xee /5" @@ -14578,12 +14638,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v2.d[0]", - "umov w1, v2.h[4]", - "mov x2, v3.d[0]", - "umov w3, v3.h[4]", - "ldr x4, [x28, #1400]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -14610,7 +14671,7 @@ ] }, "fsub st7, st0": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "0xdc 11b 0xef /5" @@ -14643,12 +14704,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v2.d[0]", - "umov w1, v2.h[4]", - "mov x2, v3.d[0]", - "umov w3, v3.h[4]", - "ldr x4, [x28, #1400]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -14675,7 +14737,7 @@ ] }, "db 0xdc, 0xf0": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "fdivr st0, st0", @@ -14710,12 +14772,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1416]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1416]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -14742,7 +14805,7 @@ ] }, "fdivr st1, st0": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "0xdc 11b 0xf1 /6" @@ -14775,12 +14838,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1416]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1416]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -14807,7 +14871,7 @@ ] }, "fdivr st2, st0": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "0xdc 11b 0xf2 /6" @@ -14840,12 +14904,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1416]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1416]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -14872,7 +14937,7 @@ ] }, "fdivr st3, st0": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "0xdc 11b 0xf3 /6" @@ -14905,12 +14970,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1416]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1416]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -14937,7 +15003,7 @@ ] }, "fdivr st4, st0": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "0xdc 11b 0xf4 /6" @@ -14970,12 +15036,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1416]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1416]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -15002,7 +15069,7 @@ ] }, "fdivr st5, st0": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "0xdc 11b 0xf5 /6" @@ -15035,12 +15102,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1416]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1416]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -15067,7 +15135,7 @@ ] }, "fdivr st6, st0": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "0xdc 11b 0xf6 /6" @@ -15100,12 +15168,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1416]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1416]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -15132,7 +15201,7 @@ ] }, "fdivr st7, st0": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "0xdc 11b 0xf7 /6" @@ -15165,12 +15234,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1416]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1416]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -15197,7 +15267,7 @@ ] }, "db 0xdc, 0xf8": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "fdiv st0, st0", @@ -15232,12 +15302,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v2.d[0]", - "umov w1, v2.h[4]", - "mov x2, v3.d[0]", - "umov w3, v3.h[4]", - "ldr x4, [x28, #1416]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1416]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -15264,7 +15335,7 @@ ] }, "fdiv st1, st0": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "0xdc 11b 0xf9 /7" @@ -15297,12 +15368,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v2.d[0]", - "umov w1, v2.h[4]", - "mov x2, v3.d[0]", - "umov w3, v3.h[4]", - "ldr x4, [x28, #1416]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1416]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -15329,7 +15401,7 @@ ] }, "fdiv st2, st0": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "0xdc 11b 0xfa /7" @@ -15362,12 +15434,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v2.d[0]", - "umov w1, v2.h[4]", - "mov x2, v3.d[0]", - "umov w3, v3.h[4]", - "ldr x4, [x28, #1416]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1416]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -15394,7 +15467,7 @@ ] }, "fdiv st3, st0": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "0xdc 11b 0xfb /7" @@ -15427,12 +15500,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v2.d[0]", - "umov w1, v2.h[4]", - "mov x2, v3.d[0]", - "umov w3, v3.h[4]", - "ldr x4, [x28, #1416]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1416]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -15459,7 +15533,7 @@ ] }, "fdiv st4, st0": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "0xdc 11b 0xfc /7" @@ -15492,12 +15566,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v2.d[0]", - "umov w1, v2.h[4]", - "mov x2, v3.d[0]", - "umov w3, v3.h[4]", - "ldr x4, [x28, #1416]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1416]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -15524,7 +15599,7 @@ ] }, "fdiv st5, st0": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "0xdc 11b 0xfd /7" @@ -15557,12 +15632,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v2.d[0]", - "umov w1, v2.h[4]", - "mov x2, v3.d[0]", - "umov w3, v3.h[4]", - "ldr x4, [x28, #1416]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1416]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -15589,7 +15665,7 @@ ] }, "fdiv st6, st0": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "0xdc 11b 0xfe /7" @@ -15622,12 +15698,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v2.d[0]", - "umov w1, v2.h[4]", - "mov x2, v3.d[0]", - "umov w3, v3.h[4]", - "ldr x4, [x28, #1416]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1416]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -15654,7 +15731,7 @@ ] }, "fdiv st7, st0": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "0xdc 11b 0xff /7" @@ -15687,12 +15764,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v2.d[0]", - "umov w1, v2.h[4]", - "mov x2, v3.d[0]", - "umov w3, v3.h[4]", - "ldr x4, [x28, #1416]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1416]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -15719,7 +15797,7 @@ ] }, "fld qword [rax]": { - "ExpectedInstructionCount": 56, + "ExpectedInstructionCount": 57, "Optimal": "No", "Comment": [ "0xdd !11b /0" @@ -15748,8 +15826,9 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldr x0, [x28, #1160]", - "blr x0", + "ldrh w0, [x28, #1008]", + "ldr x1, [x28, #1160]", + "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -15784,7 +15863,7 @@ ] }, "fisttp qword [rax]": { - "ExpectedInstructionCount": 55, + "ExpectedInstructionCount": 56, "Optimal": "No", "Comment": [ "0xdd !11b /1" @@ -15813,10 +15892,11 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v2.d[0]", - "umov w1, v2.h[4]", - "ldr x2, [x28, #1224]", - "blr x2", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1224]", + "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -15848,7 +15928,7 @@ ] }, "fst qword [rax]": { - "ExpectedInstructionCount": 47, + "ExpectedInstructionCount": 48, "Optimal": "No", "Comment": [ "0xdd !11b /2" @@ -15877,10 +15957,11 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v2.d[0]", - "umov w1, v2.h[4]", - "ldr x2, [x28, #1176]", - "blr x2", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1176]", + "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -15904,7 +15985,7 @@ ] }, "fstp qword [rax]": { - "ExpectedInstructionCount": 55, + "ExpectedInstructionCount": 56, "Optimal": "No", "Comment": [ "0xdd !11b /3" @@ -15933,10 +16014,11 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v2.d[0]", - "umov w1, v2.h[4]", - "ldr x2, [x28, #1176]", - "blr x2", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1176]", + "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -15968,54 +16050,13 @@ ] }, "frstor [rax]": { - "ExpectedInstructionCount": 163, + "ExpectedInstructionCount": 122, "Optimal": "No", "Comment": [ "0xdd !11b /4" ], "ExpectedArm64ASM": [ "ldrh w20, [x4]", - "stp x4, x5, [x28, #8]", - "stp x6, x7, [x28, #24]", - "stp x8, x9, [x28, #40]", - "stp x10, x11, [x28, #56]", - "stp x12, x13, [x28, #72]", - "stp x14, x15, [x28, #88]", - "stp x16, x17, [x28, #104]", - "stp x19, x29, [x28, #120]", - "add x0, x28, #0xc0 (192)", - "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", - "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", - "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", - "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", - "sub sp, sp, #0xf0 (240)", - "mov x0, sp", - "st1 {v2.2d, v3.2d}, [x0], #32", - "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", - "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", - "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", - "str x30, [x0]", - "uxth w0, w20", - "ldr x1, [x28, #1144]", - "blr x1", - "ld1 {v2.2d, v3.2d}, [sp], #32", - "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", - "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", - "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", - "ldr x30, [sp], #16", - "add x5, x28, #0xc0 (192)", - "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", - "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", - "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", - "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", - "ldp x4, x5, [x28, #8]", - "ldp x6, x7, [x28, #24]", - "ldp x8, x9, [x28, #40]", - "ldp x10, x11, [x28, #56]", - "ldp x12, x13, [x28, #72]", - "ldp x14, x15, [x28, #88]", - "ldp x16, x17, [x28, #104]", - "ldp x19, x29, [x28, #120]", "strh w20, [x28, #1008]", "ldr w20, [x4, #4]", "ubfx w21, w20, #11, #3", @@ -16140,7 +16181,7 @@ ] }, "fnsave [rax]": { - "ExpectedInstructionCount": 169, + "ExpectedInstructionCount": 128, "Optimal": "No", "Comment": [ "0xdd !11b /6" @@ -16267,47 +16308,6 @@ "dup v2.8h, v2.h[4]", "str h2, [x23, #8]", "mov w20, #0x37f", - "stp x4, x5, [x28, #8]", - "stp x6, x7, [x28, #24]", - "stp x8, x9, [x28, #40]", - "stp x10, x11, [x28, #56]", - "stp x12, x13, [x28, #72]", - "stp x14, x15, [x28, #88]", - "stp x16, x17, [x28, #104]", - "stp x19, x29, [x28, #120]", - "add x0, x28, #0xc0 (192)", - "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", - "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", - "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", - "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", - "sub sp, sp, #0xf0 (240)", - "mov x0, sp", - "st1 {v2.2d, v3.2d}, [x0], #32", - "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", - "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", - "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", - "str x30, [x0]", - "uxth w0, w20", - "ldr x1, [x28, #1144]", - "blr x1", - "ld1 {v2.2d, v3.2d}, [sp], #32", - "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", - "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", - "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", - "ldr x30, [sp], #16", - "add x5, x28, #0xc0 (192)", - "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64", - "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64", - "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64", - "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64", - "ldp x4, x5, [x28, #8]", - "ldp x6, x7, [x28, #24]", - "ldp x8, x9, [x28, #40]", - "ldp x10, x11, [x28, #56]", - "ldp x12, x13, [x28, #72]", - "ldp x14, x15, [x28, #88]", - "ldp x16, x17, [x28, #104]", - "ldp x19, x29, [x28, #120]", "strh w20, [x28, #1008]", "strb w21, [x28, #747]", "strb w21, [x28, #744]", @@ -16800,7 +16800,7 @@ ] }, "fucom st0": { - "ExpectedInstructionCount": 62, + "ExpectedInstructionCount": 63, "Optimal": "No", "Comment": [ "0xdd 11b 0xe0 /4" @@ -16834,12 +16834,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1288]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1288]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -16871,7 +16872,7 @@ ] }, "fucom st1": { - "ExpectedInstructionCount": 62, + "ExpectedInstructionCount": 63, "Optimal": "No", "Comment": [ "0xdd 11b 0xe1 /4" @@ -16904,12 +16905,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1288]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1288]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -16942,7 +16944,7 @@ ] }, "fucom st2": { - "ExpectedInstructionCount": 62, + "ExpectedInstructionCount": 63, "Optimal": "No", "Comment": [ "0xdd 11b 0xe2 /4" @@ -16975,12 +16977,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1288]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1288]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -17013,7 +17016,7 @@ ] }, "fucom st3": { - "ExpectedInstructionCount": 62, + "ExpectedInstructionCount": 63, "Optimal": "No", "Comment": [ "0xdd 11b 0xe3 /4" @@ -17046,12 +17049,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1288]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1288]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -17084,7 +17088,7 @@ ] }, "fucom st4": { - "ExpectedInstructionCount": 62, + "ExpectedInstructionCount": 63, "Optimal": "No", "Comment": [ "0xdd 11b 0xe4 /4" @@ -17117,12 +17121,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1288]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1288]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -17155,7 +17160,7 @@ ] }, "fucom st5": { - "ExpectedInstructionCount": 62, + "ExpectedInstructionCount": 63, "Optimal": "No", "Comment": [ "0xdd 11b 0xe5 /4" @@ -17188,12 +17193,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1288]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1288]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -17226,7 +17232,7 @@ ] }, "fucom st6": { - "ExpectedInstructionCount": 62, + "ExpectedInstructionCount": 63, "Optimal": "No", "Comment": [ "0xdd 11b 0xe6 /4" @@ -17259,12 +17265,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1288]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1288]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -17297,7 +17304,7 @@ ] }, "fucom st7": { - "ExpectedInstructionCount": 62, + "ExpectedInstructionCount": 63, "Optimal": "No", "Comment": [ "0xdd 11b 0xe7 /4" @@ -17330,12 +17337,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1288]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1288]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -17368,7 +17376,7 @@ ] }, "fucomp st0": { - "ExpectedInstructionCount": 70, + "ExpectedInstructionCount": 71, "Optimal": "No", "Comment": [ "0xdd 11b 0xe8 /5" @@ -17402,12 +17410,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1288]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1288]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -17447,7 +17456,7 @@ ] }, "fucomp st1": { - "ExpectedInstructionCount": 70, + "ExpectedInstructionCount": 71, "Optimal": "No", "Comment": [ "0xdd 11b 0xe9 /5" @@ -17481,12 +17490,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1288]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1288]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -17526,7 +17536,7 @@ ] }, "fucomp st2": { - "ExpectedInstructionCount": 70, + "ExpectedInstructionCount": 71, "Optimal": "No", "Comment": [ "0xdd 11b 0xea /5" @@ -17559,12 +17569,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1288]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1288]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -17605,7 +17616,7 @@ ] }, "fucomp st3": { - "ExpectedInstructionCount": 70, + "ExpectedInstructionCount": 71, "Optimal": "No", "Comment": [ "0xdd 11b 0xeb /5" @@ -17638,12 +17649,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1288]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1288]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -17684,7 +17696,7 @@ ] }, "fucomp st4": { - "ExpectedInstructionCount": 70, + "ExpectedInstructionCount": 71, "Optimal": "No", "Comment": [ "0xdd 11b 0xec /5" @@ -17717,12 +17729,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1288]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1288]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -17763,7 +17776,7 @@ ] }, "fucomp st5": { - "ExpectedInstructionCount": 70, + "ExpectedInstructionCount": 71, "Optimal": "No", "Comment": [ "0xdd 11b 0xed /5" @@ -17796,12 +17809,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1288]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1288]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -17842,7 +17856,7 @@ ] }, "fucomp st6": { - "ExpectedInstructionCount": 70, + "ExpectedInstructionCount": 71, "Optimal": "No", "Comment": [ "0xdd 11b 0xee /5" @@ -17875,12 +17889,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1288]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1288]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -17921,7 +17936,7 @@ ] }, "fucomp st7": { - "ExpectedInstructionCount": 70, + "ExpectedInstructionCount": 71, "Optimal": "No", "Comment": [ "0xdd 11b 0xef /5" @@ -17954,12 +17969,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1288]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1288]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -18000,7 +18016,7 @@ ] }, "fiadd word [rax]": { - "ExpectedInstructionCount": 97, + "ExpectedInstructionCount": 99, "Optimal": "No", "Comment": [ "0xde !11b /0" @@ -18028,9 +18044,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "sxth w0, w21", - "ldr x1, [x28, #1296]", - "blr x1", + "ldrh w0, [x28, #1008]", + "sxth w1, w21", + "ldr x2, [x28, #1296]", + "blr x2", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -18074,12 +18091,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1392]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1392]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -18106,7 +18124,7 @@ ] }, "fimul word [rax]": { - "ExpectedInstructionCount": 97, + "ExpectedInstructionCount": 99, "Optimal": "No", "Comment": [ "0xde !11b /1" @@ -18134,9 +18152,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "sxth w0, w21", - "ldr x1, [x28, #1296]", - "blr x1", + "ldrh w0, [x28, #1008]", + "sxth w1, w21", + "ldr x2, [x28, #1296]", + "blr x2", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -18180,12 +18199,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1408]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1408]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -18212,7 +18232,7 @@ ] }, "ficom word [rax]": { - "ExpectedInstructionCount": 103, + "ExpectedInstructionCount": 105, "Optimal": "No", "Comment": [ "0xde !11b /2" @@ -18240,9 +18260,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "sxth w0, w21", - "ldr x1, [x28, #1296]", - "blr x1", + "ldrh w0, [x28, #1008]", + "sxth w1, w21", + "ldr x2, [x28, #1296]", + "blr x2", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -18286,12 +18307,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1288]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1288]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -18324,7 +18346,7 @@ ] }, "ficomp word [rax]": { - "ExpectedInstructionCount": 111, + "ExpectedInstructionCount": 113, "Optimal": "No", "Comment": [ "0xde !11b /3" @@ -18352,9 +18374,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "sxth w0, w21", - "ldr x1, [x28, #1296]", - "blr x1", + "ldrh w0, [x28, #1008]", + "sxth w1, w21", + "ldr x2, [x28, #1296]", + "blr x2", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -18398,12 +18421,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1288]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1288]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -18444,7 +18468,7 @@ ] }, "fisub word [rax]": { - "ExpectedInstructionCount": 97, + "ExpectedInstructionCount": 99, "Optimal": "No", "Comment": [ "0xde !11b /4" @@ -18472,9 +18496,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "sxth w0, w21", - "ldr x1, [x28, #1296]", - "blr x1", + "ldrh w0, [x28, #1008]", + "sxth w1, w21", + "ldr x2, [x28, #1296]", + "blr x2", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -18518,12 +18543,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1400]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -18550,7 +18576,7 @@ ] }, "fisubr word [rax]": { - "ExpectedInstructionCount": 97, + "ExpectedInstructionCount": 99, "Optimal": "No", "Comment": [ "0xde !11b /5" @@ -18578,9 +18604,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "sxth w0, w21", - "ldr x1, [x28, #1296]", - "blr x1", + "ldrh w0, [x28, #1008]", + "sxth w1, w21", + "ldr x2, [x28, #1296]", + "blr x2", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -18624,12 +18651,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v2.d[0]", - "umov w1, v2.h[4]", - "mov x2, v3.d[0]", - "umov w3, v3.h[4]", - "ldr x4, [x28, #1400]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -18656,7 +18684,7 @@ ] }, "fidiv word [rax]": { - "ExpectedInstructionCount": 97, + "ExpectedInstructionCount": 99, "Optimal": "No", "Comment": [ "0xde !11b /6" @@ -18684,9 +18712,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "sxth w0, w21", - "ldr x1, [x28, #1296]", - "blr x1", + "ldrh w0, [x28, #1008]", + "sxth w1, w21", + "ldr x2, [x28, #1296]", + "blr x2", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -18730,12 +18759,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1416]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1416]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -18762,7 +18792,7 @@ ] }, "fidivr word [rax]": { - "ExpectedInstructionCount": 97, + "ExpectedInstructionCount": 99, "Optimal": "No", "Comment": [ "0xde !11b /7" @@ -18790,9 +18820,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "sxth w0, w21", - "ldr x1, [x28, #1296]", - "blr x1", + "ldrh w0, [x28, #1008]", + "sxth w1, w21", + "ldr x2, [x28, #1296]", + "blr x2", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -18836,12 +18867,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v2.d[0]", - "umov w1, v2.h[4]", - "mov x2, v3.d[0]", - "umov w3, v3.h[4]", - "ldr x4, [x28, #1416]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1416]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -18868,7 +18900,7 @@ ] }, "faddp st0": { - "ExpectedInstructionCount": 64, + "ExpectedInstructionCount": 65, "Optimal": "No", "Comment": [ "0xd8 11b 0xc0 /0" @@ -18901,12 +18933,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1392]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1392]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -18941,7 +18974,7 @@ ] }, "faddp st1": { - "ExpectedInstructionCount": 64, + "ExpectedInstructionCount": 65, "Optimal": "No", "Comment": [ "0xde 11b 0xc1 /0" @@ -18975,12 +19008,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1392]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1392]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -19014,7 +19048,7 @@ ] }, "faddp st2": { - "ExpectedInstructionCount": 64, + "ExpectedInstructionCount": 65, "Optimal": "No", "Comment": [ "0xde 11b 0xc2 /0" @@ -19047,12 +19081,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1392]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1392]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -19087,7 +19122,7 @@ ] }, "faddp st3": { - "ExpectedInstructionCount": 64, + "ExpectedInstructionCount": 65, "Optimal": "No", "Comment": [ "0xde 11b 0xc3 /0" @@ -19120,12 +19155,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1392]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1392]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -19160,7 +19196,7 @@ ] }, "faddp st4": { - "ExpectedInstructionCount": 64, + "ExpectedInstructionCount": 65, "Optimal": "No", "Comment": [ "0xde 11b 0xc4 /0" @@ -19193,12 +19229,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1392]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1392]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -19233,7 +19270,7 @@ ] }, "faddp st5": { - "ExpectedInstructionCount": 64, + "ExpectedInstructionCount": 65, "Optimal": "No", "Comment": [ "0xde 11b 0xc5 /0" @@ -19266,12 +19303,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1392]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1392]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -19306,7 +19344,7 @@ ] }, "faddp st6": { - "ExpectedInstructionCount": 64, + "ExpectedInstructionCount": 65, "Optimal": "No", "Comment": [ "0xde 11b 0xc6 /0" @@ -19339,12 +19377,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1392]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1392]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -19379,7 +19418,7 @@ ] }, "faddp st7": { - "ExpectedInstructionCount": 64, + "ExpectedInstructionCount": 65, "Optimal": "No", "Comment": [ "0xde 11b 0xc7 /0" @@ -19412,12 +19451,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1392]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1392]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -19452,7 +19492,7 @@ ] }, "fmulp st0": { - "ExpectedInstructionCount": 64, + "ExpectedInstructionCount": 65, "Optimal": "No", "Comment": [ "0xde 11b 0xc8 /1" @@ -19485,12 +19525,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1408]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1408]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -19525,7 +19566,7 @@ ] }, "fmulp st1": { - "ExpectedInstructionCount": 64, + "ExpectedInstructionCount": 65, "Optimal": "No", "Comment": [ "0xde 11b 0xc9 /1" @@ -19559,12 +19600,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1408]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1408]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -19598,7 +19640,7 @@ ] }, "fmulp st2": { - "ExpectedInstructionCount": 64, + "ExpectedInstructionCount": 65, "Optimal": "No", "Comment": [ "0xde 11b 0xca /1" @@ -19631,12 +19673,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1408]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1408]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -19671,7 +19714,7 @@ ] }, "fmulp st3": { - "ExpectedInstructionCount": 64, + "ExpectedInstructionCount": 65, "Optimal": "No", "Comment": [ "0xde 11b 0xcb /1" @@ -19704,12 +19747,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1408]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1408]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -19744,7 +19788,7 @@ ] }, "fmulp st4": { - "ExpectedInstructionCount": 64, + "ExpectedInstructionCount": 65, "Optimal": "No", "Comment": [ "0xde 11b 0xcc /1" @@ -19777,12 +19821,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1408]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1408]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -19817,7 +19862,7 @@ ] }, "fmulp st5": { - "ExpectedInstructionCount": 64, + "ExpectedInstructionCount": 65, "Optimal": "No", "Comment": [ "0xde 11b 0xcd /1" @@ -19850,12 +19895,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1408]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1408]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -19890,7 +19936,7 @@ ] }, "fmulp st6": { - "ExpectedInstructionCount": 64, + "ExpectedInstructionCount": 65, "Optimal": "No", "Comment": [ "0xde 11b 0xce /1" @@ -19923,12 +19969,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1408]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1408]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -19963,7 +20010,7 @@ ] }, "fmulp st7": { - "ExpectedInstructionCount": 64, + "ExpectedInstructionCount": 65, "Optimal": "No", "Comment": [ "0xde 11b 0xcf /1" @@ -19996,12 +20043,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1408]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1408]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -20036,7 +20084,7 @@ ] }, "fcompp": { - "ExpectedInstructionCount": 76, + "ExpectedInstructionCount": 77, "Optimal": "No", "Comment": [ "0xde 11b 0xd9 /3" @@ -20070,12 +20118,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1288]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1288]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -20121,7 +20170,7 @@ ] }, "db 0xde, 0xe0": { - "ExpectedInstructionCount": 64, + "ExpectedInstructionCount": 65, "Optimal": "No", "Comment": [ "fsubrp st0, st0", @@ -20156,12 +20205,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1400]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -20196,7 +20246,7 @@ ] }, "fsubrp st1, st0": { - "ExpectedInstructionCount": 64, + "ExpectedInstructionCount": 65, "Optimal": "No", "Comment": [ "0xde 11b 0xe1 /4" @@ -20230,12 +20280,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1400]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -20269,7 +20320,7 @@ ] }, "fsubrp st2, st0": { - "ExpectedInstructionCount": 64, + "ExpectedInstructionCount": 65, "Optimal": "No", "Comment": [ "0xde 11b 0xe2 /4" @@ -20302,12 +20353,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1400]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -20342,7 +20394,7 @@ ] }, "fsubrp st3, st0": { - "ExpectedInstructionCount": 64, + "ExpectedInstructionCount": 65, "Optimal": "No", "Comment": [ "0xde 11b 0xe3 /4" @@ -20375,12 +20427,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1400]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -20415,7 +20468,7 @@ ] }, "fsubrp st4, st0": { - "ExpectedInstructionCount": 64, + "ExpectedInstructionCount": 65, "Optimal": "No", "Comment": [ "0xde 11b 0xe4 /4" @@ -20448,12 +20501,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1400]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -20488,7 +20542,7 @@ ] }, "fsubrp st5, st0": { - "ExpectedInstructionCount": 64, + "ExpectedInstructionCount": 65, "Optimal": "No", "Comment": [ "0xde 11b 0xe5 /4" @@ -20521,12 +20575,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1400]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -20561,7 +20616,7 @@ ] }, "fsubrp st6, st0": { - "ExpectedInstructionCount": 64, + "ExpectedInstructionCount": 65, "Optimal": "No", "Comment": [ "0xde 11b 0xe6 /4" @@ -20594,12 +20649,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1400]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -20634,7 +20690,7 @@ ] }, "fsubrp st7, st0": { - "ExpectedInstructionCount": 64, + "ExpectedInstructionCount": 65, "Optimal": "No", "Comment": [ "0xde 11b 0xe7 /4" @@ -20667,12 +20723,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1400]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -20707,7 +20764,7 @@ ] }, "db 0xde, 0xe8": { - "ExpectedInstructionCount": 64, + "ExpectedInstructionCount": 65, "Optimal": "No", "Comment": [ "fsubp st0, st0", @@ -20742,12 +20799,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v2.d[0]", - "umov w1, v2.h[4]", - "mov x2, v3.d[0]", - "umov w3, v3.h[4]", - "ldr x4, [x28, #1400]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -20782,7 +20840,7 @@ ] }, "fsubp st1, st0": { - "ExpectedInstructionCount": 64, + "ExpectedInstructionCount": 65, "Optimal": "No", "Comment": [ "0xde 11b 0xe9 /5" @@ -20816,12 +20874,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v2.d[0]", - "umov w1, v2.h[4]", - "mov x2, v3.d[0]", - "umov w3, v3.h[4]", - "ldr x4, [x28, #1400]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -20855,7 +20914,7 @@ ] }, "fsubp st2, st0": { - "ExpectedInstructionCount": 64, + "ExpectedInstructionCount": 65, "Optimal": "No", "Comment": [ "0xde 11b 0xea /5" @@ -20888,12 +20947,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v2.d[0]", - "umov w1, v2.h[4]", - "mov x2, v3.d[0]", - "umov w3, v3.h[4]", - "ldr x4, [x28, #1400]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -20928,7 +20988,7 @@ ] }, "fsubp st3, st0": { - "ExpectedInstructionCount": 64, + "ExpectedInstructionCount": 65, "Optimal": "No", "Comment": [ "0xde 11b 0xeb /5" @@ -20961,12 +21021,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v2.d[0]", - "umov w1, v2.h[4]", - "mov x2, v3.d[0]", - "umov w3, v3.h[4]", - "ldr x4, [x28, #1400]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -21001,7 +21062,7 @@ ] }, "fsubp st4, st0": { - "ExpectedInstructionCount": 64, + "ExpectedInstructionCount": 65, "Optimal": "No", "Comment": [ "0xde 11b 0xec /5" @@ -21034,12 +21095,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v2.d[0]", - "umov w1, v2.h[4]", - "mov x2, v3.d[0]", - "umov w3, v3.h[4]", - "ldr x4, [x28, #1400]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -21074,7 +21136,7 @@ ] }, "fsubp st5, st0": { - "ExpectedInstructionCount": 64, + "ExpectedInstructionCount": 65, "Optimal": "No", "Comment": [ "0xde 11b 0xed /5" @@ -21107,12 +21169,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v2.d[0]", - "umov w1, v2.h[4]", - "mov x2, v3.d[0]", - "umov w3, v3.h[4]", - "ldr x4, [x28, #1400]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -21147,7 +21210,7 @@ ] }, "fsubp st6, st0": { - "ExpectedInstructionCount": 64, + "ExpectedInstructionCount": 65, "Optimal": "No", "Comment": [ "0xde 11b 0xee /5" @@ -21180,12 +21243,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v2.d[0]", - "umov w1, v2.h[4]", - "mov x2, v3.d[0]", - "umov w3, v3.h[4]", - "ldr x4, [x28, #1400]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -21220,7 +21284,7 @@ ] }, "fsubp st7, st0": { - "ExpectedInstructionCount": 64, + "ExpectedInstructionCount": 65, "Optimal": "No", "Comment": [ "0xde 11b 0xef /5" @@ -21253,12 +21317,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v2.d[0]", - "umov w1, v2.h[4]", - "mov x2, v3.d[0]", - "umov w3, v3.h[4]", - "ldr x4, [x28, #1400]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -21293,7 +21358,7 @@ ] }, "db 0xde, 0xf0": { - "ExpectedInstructionCount": 64, + "ExpectedInstructionCount": 65, "Optimal": "No", "Comment": [ "fdivrp st0, st0", @@ -21328,12 +21393,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1416]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1416]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -21368,7 +21434,7 @@ ] }, "fdivrp st1, st0": { - "ExpectedInstructionCount": 64, + "ExpectedInstructionCount": 65, "Optimal": "No", "Comment": [ "0xde 11b 0xf1 /6" @@ -21402,12 +21468,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1416]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1416]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -21441,7 +21508,7 @@ ] }, "fdivrp st2, st0": { - "ExpectedInstructionCount": 64, + "ExpectedInstructionCount": 65, "Optimal": "No", "Comment": [ "0xde 11b 0xf2 /6" @@ -21474,12 +21541,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1416]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1416]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -21514,7 +21582,7 @@ ] }, "fdivrp st3, st0": { - "ExpectedInstructionCount": 64, + "ExpectedInstructionCount": 65, "Optimal": "No", "Comment": [ "0xde 11b 0xf3 /6" @@ -21547,12 +21615,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1416]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1416]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -21587,7 +21656,7 @@ ] }, "fdivrp st4, st0": { - "ExpectedInstructionCount": 64, + "ExpectedInstructionCount": 65, "Optimal": "No", "Comment": [ "0xde 11b 0xf4 /6" @@ -21620,12 +21689,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1416]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1416]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -21660,7 +21730,7 @@ ] }, "fdivrp st5, st0": { - "ExpectedInstructionCount": 64, + "ExpectedInstructionCount": 65, "Optimal": "No", "Comment": [ "0xde 11b 0xf5 /6" @@ -21693,12 +21763,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1416]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1416]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -21733,7 +21804,7 @@ ] }, "fdivrp st6, st0": { - "ExpectedInstructionCount": 64, + "ExpectedInstructionCount": 65, "Optimal": "No", "Comment": [ "0xde 11b 0xf6 /6" @@ -21766,12 +21837,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1416]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1416]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -21806,7 +21878,7 @@ ] }, "fdivrp st7, st0": { - "ExpectedInstructionCount": 64, + "ExpectedInstructionCount": 65, "Optimal": "No", "Comment": [ "0xde 11b 0xf7 /6" @@ -21839,12 +21911,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1416]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1416]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -21879,7 +21952,7 @@ ] }, "db 0xde, 0xf8": { - "ExpectedInstructionCount": 64, + "ExpectedInstructionCount": 65, "Optimal": "No", "Comment": [ "fdivp st0, st0", @@ -21914,12 +21987,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v2.d[0]", - "umov w1, v2.h[4]", - "mov x2, v3.d[0]", - "umov w3, v3.h[4]", - "ldr x4, [x28, #1416]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1416]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -21954,7 +22028,7 @@ ] }, "fdivp st1, st0": { - "ExpectedInstructionCount": 64, + "ExpectedInstructionCount": 65, "Optimal": "No", "Comment": [ "0xde 11b 0xf9 /7" @@ -21988,12 +22062,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v2.d[0]", - "umov w1, v2.h[4]", - "mov x2, v3.d[0]", - "umov w3, v3.h[4]", - "ldr x4, [x28, #1416]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1416]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -22027,7 +22102,7 @@ ] }, "fdivp st2, st0": { - "ExpectedInstructionCount": 64, + "ExpectedInstructionCount": 65, "Optimal": "No", "Comment": [ "0xde 11b 0xfa /7" @@ -22060,12 +22135,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v2.d[0]", - "umov w1, v2.h[4]", - "mov x2, v3.d[0]", - "umov w3, v3.h[4]", - "ldr x4, [x28, #1416]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1416]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -22100,7 +22176,7 @@ ] }, "fdivp st3, st0": { - "ExpectedInstructionCount": 64, + "ExpectedInstructionCount": 65, "Optimal": "No", "Comment": [ "0xde 11b 0xfb /7" @@ -22133,12 +22209,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v2.d[0]", - "umov w1, v2.h[4]", - "mov x2, v3.d[0]", - "umov w3, v3.h[4]", - "ldr x4, [x28, #1416]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1416]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -22173,7 +22250,7 @@ ] }, "fdivp st4, st0": { - "ExpectedInstructionCount": 64, + "ExpectedInstructionCount": 65, "Optimal": "No", "Comment": [ "0xde 11b 0xfc /7" @@ -22206,12 +22283,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v2.d[0]", - "umov w1, v2.h[4]", - "mov x2, v3.d[0]", - "umov w3, v3.h[4]", - "ldr x4, [x28, #1416]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1416]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -22246,7 +22324,7 @@ ] }, "fdivp st5, st0": { - "ExpectedInstructionCount": 64, + "ExpectedInstructionCount": 65, "Optimal": "No", "Comment": [ "0xde 11b 0xfd /7" @@ -22279,12 +22357,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v2.d[0]", - "umov w1, v2.h[4]", - "mov x2, v3.d[0]", - "umov w3, v3.h[4]", - "ldr x4, [x28, #1416]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1416]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -22319,7 +22398,7 @@ ] }, "fdivp st6, st0": { - "ExpectedInstructionCount": 64, + "ExpectedInstructionCount": 65, "Optimal": "No", "Comment": [ "0xde 11b 0xfe /7" @@ -22352,12 +22431,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v2.d[0]", - "umov w1, v2.h[4]", - "mov x2, v3.d[0]", - "umov w3, v3.h[4]", - "ldr x4, [x28, #1416]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1416]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -22392,7 +22472,7 @@ ] }, "fdivp st7, st0": { - "ExpectedInstructionCount": 64, + "ExpectedInstructionCount": 65, "Optimal": "No", "Comment": [ "0xde 11b 0xff /7" @@ -22425,12 +22505,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v2.d[0]", - "umov w1, v2.h[4]", - "mov x2, v3.d[0]", - "umov w3, v3.h[4]", - "ldr x4, [x28, #1416]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1416]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -22507,7 +22588,7 @@ ] }, "fisttp word [rax]": { - "ExpectedInstructionCount": 55, + "ExpectedInstructionCount": 56, "Optimal": "No", "Comment": [ "0xdf !11b /1" @@ -22536,10 +22617,11 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v2.d[0]", - "umov w1, v2.h[4]", - "ldr x2, [x28, #1208]", - "blr x2", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1208]", + "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -22571,7 +22653,7 @@ ] }, "fist word [rax]": { - "ExpectedInstructionCount": 47, + "ExpectedInstructionCount": 48, "Optimal": "No", "Comment": [ "0xdf !11b /2" @@ -22600,10 +22682,11 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v2.d[0]", - "umov w1, v2.h[4]", - "ldr x2, [x28, #1184]", - "blr x2", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1184]", + "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -22627,7 +22710,7 @@ ] }, "fistp word [rax]": { - "ExpectedInstructionCount": 55, + "ExpectedInstructionCount": 56, "Optimal": "No", "Comment": [ "0xdf !11b /3" @@ -22656,10 +22739,11 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v2.d[0]", - "umov w1, v2.h[4]", - "ldr x2, [x28, #1184]", - "blr x2", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1184]", + "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -22691,7 +22775,7 @@ ] }, "fbld tword [rax]": { - "ExpectedInstructionCount": 57, + "ExpectedInstructionCount": 58, "Optimal": "No", "Comment": [ "0xdf !11b /4" @@ -22727,10 +22811,11 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v2.d[0]", - "umov w1, v2.h[4]", - "ldr x2, [x28, #1384]", - "blr x2", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1384]", + "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -22757,7 +22842,7 @@ ] }, "fbstp tword [rax]": { - "ExpectedInstructionCount": 59, + "ExpectedInstructionCount": 60, "Optimal": "No", "Comment": [ "0xdf !11b /6" @@ -22786,10 +22871,11 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v2.d[0]", - "umov w1, v2.h[4]", - "ldr x2, [x28, #1376]", - "blr x2", + "ldrh w0, [x28, #1008]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1376]", + "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -22955,7 +23041,7 @@ ] }, "fucomip st0": { - "ExpectedInstructionCount": 70, + "ExpectedInstructionCount": 71, "Optimal": "No", "Comment": [ "0xdf 11b 0xe8 /5" @@ -22988,12 +23074,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1288]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1288]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -23034,7 +23121,7 @@ ] }, "fucomip st1": { - "ExpectedInstructionCount": 70, + "ExpectedInstructionCount": 71, "Optimal": "No", "Comment": [ "0xdf 11b 0xe9 /5" @@ -23068,12 +23155,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1288]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1288]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -23113,7 +23201,7 @@ ] }, "fucomip st2": { - "ExpectedInstructionCount": 70, + "ExpectedInstructionCount": 71, "Optimal": "No", "Comment": [ "0xdf 11b 0xea /5" @@ -23146,12 +23234,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1288]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1288]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -23192,7 +23281,7 @@ ] }, "fucomip st3": { - "ExpectedInstructionCount": 70, + "ExpectedInstructionCount": 71, "Optimal": "No", "Comment": [ "0xdf 11b 0xeb /5" @@ -23225,12 +23314,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1288]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1288]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -23271,7 +23361,7 @@ ] }, "fucomip st4": { - "ExpectedInstructionCount": 70, + "ExpectedInstructionCount": 71, "Optimal": "No", "Comment": [ "0xdf 11b 0xec /5" @@ -23304,12 +23394,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1288]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1288]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -23350,7 +23441,7 @@ ] }, "fucomip st5": { - "ExpectedInstructionCount": 70, + "ExpectedInstructionCount": 71, "Optimal": "No", "Comment": [ "0xdf 11b 0xed /5" @@ -23383,12 +23474,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1288]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1288]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -23429,7 +23521,7 @@ ] }, "fucomip st6": { - "ExpectedInstructionCount": 70, + "ExpectedInstructionCount": 71, "Optimal": "No", "Comment": [ "0xdf 11b 0xee /5" @@ -23462,12 +23554,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1288]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1288]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -23508,7 +23601,7 @@ ] }, "fucomip st7": { - "ExpectedInstructionCount": 70, + "ExpectedInstructionCount": 71, "Optimal": "No", "Comment": [ "0xdf 11b 0xef /5" @@ -23541,12 +23634,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1288]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1288]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -23587,7 +23681,7 @@ ] }, "fcomip st0": { - "ExpectedInstructionCount": 70, + "ExpectedInstructionCount": 71, "Optimal": "No", "Comment": [ "0xdf 11b 0xf0 /6" @@ -23620,12 +23714,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1288]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1288]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -23666,7 +23761,7 @@ ] }, "fcomip st1": { - "ExpectedInstructionCount": 70, + "ExpectedInstructionCount": 71, "Optimal": "No", "Comment": [ "0xdf 11b 0xf1 /6" @@ -23700,12 +23795,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1288]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1288]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -23745,7 +23841,7 @@ ] }, "fcomip st2": { - "ExpectedInstructionCount": 70, + "ExpectedInstructionCount": 71, "Optimal": "No", "Comment": [ "0xdf 11b 0xf2 /6" @@ -23778,12 +23874,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1288]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1288]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -23824,7 +23921,7 @@ ] }, "fcomip st3": { - "ExpectedInstructionCount": 70, + "ExpectedInstructionCount": 71, "Optimal": "No", "Comment": [ "0xdf 11b 0xf3 /6" @@ -23857,12 +23954,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1288]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1288]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -23903,7 +24001,7 @@ ] }, "fcomip st4": { - "ExpectedInstructionCount": 70, + "ExpectedInstructionCount": 71, "Optimal": "No", "Comment": [ "0xdf 11b 0xf4 /6" @@ -23936,12 +24034,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1288]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1288]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -23982,7 +24081,7 @@ ] }, "fcomip st5": { - "ExpectedInstructionCount": 70, + "ExpectedInstructionCount": 71, "Optimal": "No", "Comment": [ "0xdf 11b 0xf5 /6" @@ -24015,12 +24114,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1288]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1288]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -24061,7 +24161,7 @@ ] }, "fcomip st6": { - "ExpectedInstructionCount": 70, + "ExpectedInstructionCount": 71, "Optimal": "No", "Comment": [ "0xdf 11b 0xf6 /6" @@ -24094,12 +24194,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1288]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1288]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -24140,7 +24241,7 @@ ] }, "fcomip st7": { - "ExpectedInstructionCount": 70, + "ExpectedInstructionCount": 71, "Optimal": "No", "Comment": [ "0xdf 11b 0xf7 /6" @@ -24173,12 +24274,13 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "mov x0, v3.d[0]", - "umov w1, v3.h[4]", - "mov x2, v2.d[0]", - "umov w3, v2.h[4]", - "ldr x4, [x28, #1288]", - "blr x4", + "ldrh w0, [x28, #1008]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1288]", + "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",