Merge pull request #3071 from Sonicadvance1/update_rcl_opsize

OpcodeDispatcher: Update 32/64-bit RCL for operating size

FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp

@@ -2789,6 +2789,7 @@ void OpDispatchBuilder::RCLOp(OpcodeArgs) {
     RCLSmallerOp(Op);
     return;
   }
+  const auto OpSize = OpSizeFromSrc(Op);
 
   // Calculate flags early.
   CalculateDeferredFlags();
@@ -2798,11 +2799,11 @@ void OpDispatchBuilder::RCLOp(OpcodeArgs) {
   auto CF = GetRFLAG(FEXCore::X86State::RFLAG_CF_LOC);
 
   // Res = Src << Shift
-  OrderedNode *Res = _Lshl(OpSizeFromSrc(Op), Dest, Src);
+  OrderedNode *Res = _Lshl(OpSize, Dest, Src);
 
   // Res |= (Src << (Size - Shift + 1));
-  OrderedNode *SrcShl = _Sub(OpSizeFromSrc(Op), _Constant(Size, Size + 1), Src);
-  auto TmpHigher = _Lshr(OpSizeFromSrc(Op), Dest, SrcShl);
+  OrderedNode *SrcShl = _Sub(OpSize, _Constant(Size, Size + 1), Src);
+  auto TmpHigher = _Lshr(OpSize, Dest, SrcShl);
 
   auto One = _Constant(Size, 1);
   auto Zero = _Constant(Size, 0);
@@ -2811,26 +2812,24 @@ void OpDispatchBuilder::RCLOp(OpcodeArgs) {
     Src, One,
     TmpHigher, Zero);
 
-  // TODO: Can use OpSizeFromSrc(Op)
-  Res = _Or(IR::SizeToOpSize(std::max<uint8_t>(4u, std::max(GetOpSize(Res), GetOpSize(CompareResult)))), Res, CompareResult);
+  Res = _Or(OpSize, Res, CompareResult);
 
   // If Shift != 0 then we can inject the CF
-  OrderedNode *CFShl = _Sub(OpSizeFromSrc(Op), Src, _Constant(Size, 1));
+  OrderedNode *CFShl = _Sub(OpSize, Src, _Constant(Size, 1));
   auto TmpCF = _Lshl(OpSize::i64Bit, CF, CFShl);
 
   CompareResult = _Select(FEXCore::IR::COND_UGE,
     Src, One,
     TmpCF, Zero);
 
-  // TODO: Can use OpSizeFromSrc(Op)
-  Res = _Or(IR::SizeToOpSize(std::max<uint8_t>(4u, std::max(GetOpSize(Res), GetOpSize(CompareResult)))), Res, CompareResult);
+  Res = _Or(OpSize, Res, CompareResult);
 
   StoreResult(GPRClass, Op, Res, -1);
 
   {
     // CF only changes if we actually shifted
     // Our new CF will be bit (Shift - 1) of the source
-    auto NewCF = _Bfe(OpSizeFromSrc(Op), 1, 0, _Lshr(OpSizeFromSrc(Op), Dest, _Sub(OpSizeFromSrc(Op), _Constant(Size, Size), Src)));
+    auto NewCF = _Bfe(OpSize, 1, 0, _Lshr(OpSize, Dest, _Sub(OpSize, _Constant(Size, Size), Src)));
     CompareResult = _Select(FEXCore::IR::COND_UGE,
       Src, One,
       NewCF, CF);
@@ -2841,7 +2840,7 @@ void OpDispatchBuilder::RCLOp(OpcodeArgs) {
     // Only when Shift == 1, it is undefined otherwise
     // Only changed if shift isn't zero
     auto OF = GetRFLAG(FEXCore::X86State::RFLAG_OF_LOC);
-    auto NewOF = _Xor(IR::SizeToOpSize(std::max<uint8_t>(4u, GetOpSize(Res))), _Bfe(IR::SizeToOpSize(GetOpSize(Res)), 1, Size - 1, Res), NewCF);
+    auto NewOF = _Xor(OpSize, _Bfe(OpSize, 1, Size - 1, Res), NewCF);
     CompareResult = _Select(FEXCore::IR::COND_EQ,
       Src, _Constant(0),
       OF, NewOF);

unittests/InstructionCountCI/PrimaryGroup.json

@@ -1141,7 +1141,7 @@
       ]
     },
     "rcl eax, 2": {
-      "ExpectedInstructionCount": 26,
+      "ExpectedInstructionCount": 25,
       "Optimal": "No",
       "Comment": "GROUP2 0xC1 /2",
       "ExpectedArm64ASM": [
@@ -1158,8 +1158,7 @@
         "lsl x25, x23, #1",
         "cmp w20, #0x1 (1)",
         "csel x25, x25, x26, hs",
-        "orr x24, x24, x25",
-        "lsr w4, w24, #0",
+        "orr w4, w24, w25",
         "lsr w21, w21, #30",
         "ubfx w21, w21, #0, #1",
         "cmp w20, #0x1 (1)",
@@ -1167,8 +1166,8 @@
         "mov w0, w22",
         "bfi w0, w20, #29, #1",
         "mov w20, w0",
-        "ubfx x22, x24, #31, #1",
-        "eor x21, x22, x21",
+        "lsr w22, w4, #31",
+        "eor w21, w22, w21",
         "bfi w20, w21, #28, #1",
         "str w20, [x28, #728]"
       ]
@@ -2387,7 +2386,7 @@
       ]
     },
     "rcl eax, cl": {
-      "ExpectedInstructionCount": 34,
+      "ExpectedInstructionCount": 33,
       "Optimal": "No",
       "Comment": "GROUP2 0xd3 /2",
       "ExpectedArm64ASM": [
@@ -2407,20 +2406,19 @@
         "lsl x25, x23, x25",
         "cmp w20, #0x1 (1)",
         "csel x25, x25, x26, hs",
-        "orr x24, x24, x25",
-        "lsr w4, w24, #0",
-        "mov w25, #0x20",
-        "sub w25, w25, w20",
-        "lsr w21, w21, w25",
+        "orr w4, w24, w25",
+        "mov w24, #0x20",
+        "sub w24, w24, w20",
+        "lsr w21, w21, w24",
         "ubfx w21, w21, #0, #1",
         "cmp w20, #0x1 (1)",
         "csel w23, w21, w23, hs",
         "bfi w22, w23, #29, #1",
         "ubfx w23, w22, #28, #1",
-        "ubfx x24, x24, #31, #1",
-        "eor x21, x24, x21",
+        "lsr w24, w4, #31",
+        "eor w21, w24, w21",
         "cmp x20, #0x0 (0)",
-        "csel x20, x23, x21, eq",
+        "csel w20, w23, w21, eq",
         "mov w0, w22",
         "bfi w0, w20, #28, #1",
         "mov w20, w0",