diff --git a/FEXCore/Source/Interface/Core/CPUID.cpp b/FEXCore/Source/Interface/Core/CPUID.cpp index 773c26683..6d80f2aa4 100644 --- a/FEXCore/Source/Interface/Core/CPUID.cpp +++ b/FEXCore/Source/Interface/Core/CPUID.cpp @@ -434,7 +434,7 @@ FEXCore::CPUID::FunctionResults CPUIDEmu::Function_01h(uint32_t Leaf) const { (SupportsAVX() << 26) | // XSAVE (SupportsAVX() << 27) | // OSXSAVE (SupportsAVX() << 28) | // AVX - (0 << 29) | // F16C + (SupportsAVX() << 29) | // F16C (CTX->HostFeatures.SupportsRAND << 30) | // RDRAND (Hypervisor << 31); diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp index cac2b2988..2196a528e 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp @@ -5238,6 +5238,7 @@ void OpDispatchBuilder::InstallHostSpecificOpcodeHandlers() { {OPD(2, 0b01, 0x0E), 1, &OpDispatchBuilder::VTESTPOp<4>}, {OPD(2, 0b01, 0x0F), 1, &OpDispatchBuilder::VTESTPOp<8>}, + {OPD(2, 0b01, 0x13), 1, &OpDispatchBuilder::VCVTPH2PSOp}, {OPD(2, 0b01, 0x16), 1, &OpDispatchBuilder::VPERMDOp}, {OPD(2, 0b01, 0x17), 1, &OpDispatchBuilder::PTestOp}, {OPD(2, 0b01, 0x18), 1, &OpDispatchBuilder::VBROADCASTOp<4>}, @@ -5361,6 +5362,7 @@ void OpDispatchBuilder::InstallHostSpecificOpcodeHandlers() { {OPD(3, 0b01, 0x18), 1, &OpDispatchBuilder::VINSERTOp}, {OPD(3, 0b01, 0x19), 1, &OpDispatchBuilder::VEXTRACT128Op}, + {OPD(3, 0b01, 0x1D), 1, &OpDispatchBuilder::VCVTPS2PHOp}, {OPD(3, 0b01, 0x20), 1, &OpDispatchBuilder::VPINSRBOp}, {OPD(3, 0b01, 0x21), 1, &OpDispatchBuilder::VINSERTPSOp}, {OPD(3, 0b01, 0x22), 1, &OpDispatchBuilder::VPINSRDQOp}, diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher.h b/FEXCore/Source/Interface/Core/OpcodeDispatcher.h index 4dc232f53..147f6e766 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher.h +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher.h @@ -663,8 +663,10 @@ public: void VPCMPISTRIOp(OpcodeArgs); void VPCMPISTRMOp(OpcodeArgs); - Ref VPERMDIndices(OpSize DstSize, Ref Indices, Ref IndexMask, Ref Repeating3210); + void VCVTPH2PSOp(OpcodeArgs); + void VCVTPS2PHOp(OpcodeArgs); + Ref VPERMDIndices(OpSize DstSize, Ref Indices, Ref IndexMask, Ref Repeating3210); void VPERM2Op(OpcodeArgs); void VPERMDOp(OpcodeArgs); void VPERMQOp(OpcodeArgs); diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp index 5f2cfb255..cc8bd58c2 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp @@ -4464,6 +4464,55 @@ void OpDispatchBuilder::VINSERTOp(OpcodeArgs) { StoreResult(FPRClass, Op, Result, -1); } +void OpDispatchBuilder::VCVTPH2PSOp(OpcodeArgs) { + // In the event that a memory operand is used as the source operand, + // the access width will always be half the size of the destination vector width + // (i.e. 128-bit vector -> 64-bit mem, 256-bit vector -> 128-bit mem) + const auto DstSize = GetDstSize(Op); + const auto SrcLoadSize = Op->Src[0].IsGPR() ? DstSize : DstSize / 2; + + Ref Src = LoadSource_WithOpSize(FPRClass, Op, Op->Src[0], SrcLoadSize, Op->Flags); + Ref Result = _Vector_FToF(DstSize, 4, Src, 2); + + StoreResult(FPRClass, Op, Result, -1); +} + +void OpDispatchBuilder::VCVTPS2PHOp(OpcodeArgs) { + const auto SrcSize = GetSrcSize(Op); + const auto StoreSize = Op->Dest.IsGPR() ? 16 : SrcSize / 2; + + const auto Imm8 = Op->Src[1].Literal(); + const auto UseMXCSR = (Imm8 & 0b100) != 0; + + Ref Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags); + + Ref Result = nullptr; + if (UseMXCSR) { + Result = _Vector_FToF(SrcSize, 2, Src, 4); + } else { + // No ARM float conversion instructions allow passing in + // a rounding mode as an immediate. All of them depend on + // the RM field in the FPCR. And so! We have to do some ugly + // rounding mode shuffling. + const auto NewRMode = Imm8 & 0b11; + + Ref OldRMode = _GetRoundingMode(); + _SetRoundingMode(_Constant(NewRMode)); + + Result = _Vector_FToF(SrcSize, 2, Src, 4); + + _SetRoundingMode(OldRMode); + } + + // We need to eliminate upper junk if we're storing into a register with + // a 256-bit source (VCVTPS2PH's destination for registers is an XMM). + if (Op->Src[0].IsGPR() && SrcSize == Core::CPUState::XMM_AVX_REG_SIZE) { + Result = _VMov(16, Result); + } + + StoreResult_WithOpSize(FPRClass, Op, Op->Dest, Result, StoreSize, -1); +} + void OpDispatchBuilder::VPERM2Op(OpcodeArgs) { const auto DstSize = GetDstSize(Op); Ref Src1 = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags); diff --git a/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp b/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp index 23d1e5323..6d21d1967 100644 --- a/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp +++ b/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp @@ -282,7 +282,7 @@ std::array VEXTableOps = []() consteval { {OPD(2, 0b01, 0x0E), 1, X86InstInfo{"VTESTPS", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}}, {OPD(2, 0b01, 0x0F), 1, X86InstInfo{"VTESTPD", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}}, - {OPD(2, 0b01, 0x13), 1, X86InstInfo{"VCVTPH2PS", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, + {OPD(2, 0b01, 0x13), 1, X86InstInfo{"VCVTPH2PS", TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}}, {OPD(2, 0b01, 0x16), 1, X86InstInfo{"VPERMPS", TYPE_INST, GenFlagsSameSize(SIZE_256BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 0, nullptr}}, {OPD(2, 0b01, 0x17), 1, X86InstInfo{"VPTEST", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}}, @@ -433,7 +433,7 @@ std::array VEXTableOps = []() consteval { {OPD(3, 0b01, 0x18), 1, X86InstInfo{"VINSERTF128", TYPE_INST, GenFlagsSameSize(SIZE_256BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 1, nullptr}}, {OPD(3, 0b01, 0x19), 1, X86InstInfo{"VEXTRACTF128", TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_256BIT) | FLAGS_MODRM | FLAGS_SF_MOD_DST | FLAGS_XMM_FLAGS, 1, nullptr}}, - {OPD(3, 0b01, 0x1D), 1, X86InstInfo{"VCVTPS2PH", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, + {OPD(3, 0b01, 0x1D), 1, X86InstInfo{"VCVTPS2PH", TYPE_INST, GenFlagsSizes(SIZE_64BIT, SIZE_128BIT) | FLAGS_MODRM | FLAGS_SF_MOD_DST | FLAGS_XMM_FLAGS, 1, nullptr}}, {OPD(3, 0b01, 0x20), 1, X86InstInfo{"VPINSRB", TYPE_INST, GenFlagsDstSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS | FLAGS_SF_SRC_GPR, 1, nullptr}}, {OPD(3, 0b01, 0x21), 1, X86InstInfo{"VINSERTPS", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 1, nullptr}}, diff --git a/unittests/ASM/Disabled_Tests_Simulator b/unittests/ASM/Disabled_Tests_Simulator index 7076a016b..ac6ee7f3c 100644 --- a/unittests/ASM/Disabled_Tests_Simulator +++ b/unittests/ASM/Disabled_Tests_Simulator @@ -88,6 +88,10 @@ Test_VEX/vroundpd.asm Test_VEX/vroundps.asm Test_VEX/vroundsd.asm Test_VEX/vroundss.asm +Test_VEX/vcvtps2ph_rtne.asm +Test_VEX/vcvtps2ph_rd.asm +Test_VEX/vcvtps2ph_ru.asm +Test_VEX/vcvtps2ph_trunc.asm # Simulator doesn't support cycle counter reading Test_TwoByte/0F_31.asm diff --git a/unittests/ASM/VEX/vcvtph2ps.asm b/unittests/ASM/VEX/vcvtph2ps.asm new file mode 100644 index 000000000..92ee21f75 --- /dev/null +++ b/unittests/ASM/VEX/vcvtph2ps.asm @@ -0,0 +1,67 @@ +%ifdef CONFIG +{ + "HostFeatures": ["AVX"], + "RegData": { + "XMM0": ["0xFC007C00BC003C00", "0x42487E0003FF0001", "0", "0"], + "XMM1": ["0x800000007BFFFBFF", "0x42A53DC534D136F3", "0", "0"], + "XMM2": ["0xBF8000003F800000", "0xFF8000007F800000", "0", "0"], + "XMM3": ["0x477FE000C77FE000", "0x8000000000000000", "0", "0"], + "XMM4": ["0xBF8000003F800000", "0xFF8000007F800000", "0", "0"], + "XMM5": ["0x387FC00033800000", "0x404900007FC00000", "0", "0"], + "XMM6": ["0xFC007C00BC003C00", "0x42487E0003FF0001", "0x800000007BFFFBFF", "0x42A53DC534D136F3"], + "XMM7": ["0xBF8000003F800000", "0xFF8000007F800000", "0x387FC00033800000", "0x404900007FC00000"], + "XMM8": ["0xBF8000003F800000", "0xFF8000007F800000", "0x387FC00033800000", "0x404900007FC00000"], + "XMM9": ["0x477FE000C77FE000", "0x8000000000000000", "0x3E9A20003EDE6000", "0x4054A0003FB8A000"] + } +} +%endif + +lea rdx, [rel .data] + +; 128-bit + +vmovapd xmm0, [rdx] +vmovapd xmm1, [rdx + 16] + +; 128-bit register +vcvtph2ps xmm2, xmm0 +vcvtph2ps xmm3, xmm1 + +; 128-bit memory +vcvtph2ps xmm4, [rdx] +vcvtph2ps xmm5, [rdx + 8] + +; 256-bit + +vmovapd ymm6, [rdx] + +; 256-bit register +vcvtph2ps ymm7, xmm6 + +; 256-bit memory +vcvtph2ps ymm8, [rdx] +vcvtph2ps ymm9, [rdx + 16] + +hlt + +align 32 +.data: +dw 0x3C00 ; 1.0 +dw 0xBC00 ; -1.0 +dw 0x7C00 ; +inf +dw 0xFC00 ; -inf + +dw 0x0001 ; min positive subnormal +dw 0x03FF ; max subnormal +dw 0x7E00 ; NaN +dw 0x4248 ; pi + +dw 0xFBFF ; min finite value +dw 0x7BFF ; max finite value +dw 0x0000 ; +0.0 +dw 0x8000 ; -0.0 + +dw 0x36F3 ; log_10(e) +dw 0x34D1 ; log_10(2) +dw 0x3DC5 ; log_2(e) +dw 0x42A5 ; log_2(10) diff --git a/unittests/ASM/VEX/vcvtps2ph_rd.asm b/unittests/ASM/VEX/vcvtps2ph_rd.asm new file mode 100644 index 000000000..333cbdcf4 --- /dev/null +++ b/unittests/ASM/VEX/vcvtps2ph_rd.asm @@ -0,0 +1,58 @@ +%ifdef CONFIG +{ + "HostFeatures": ["AVX"], + "RegData": { + "XMM0": ["0x008000003F800000", "0x7FC000007F7FFFFF", "0", "0"], + "XMM1": ["0x7F80000040600000", "0x00000001FF800000", "0", "0"], + "XMM2": ["0x7E007BFF00003C00", "0x0000000000000000", "0", "0"], + "XMM3": ["0x0000FC007C004300", "0x0000000000000000", "0", "0"], + "XMM4": ["0x7E007BFF00003C00", "0x0000FC007C004300", "0", "0"], + "XMM5": ["0x008000003F800000", "0x7FC000007F7FFFFF", "0x7F80000040600000", "0x00000001FF800000"], + "XMM6": ["0x7E007BFF00003C00", "0x0000FC007C004300", "0", "0"], + "XMM7": ["0x7E007BFF00003C00", "0x0000FC007C004300", "0", "0"] + } +} +%endif + +; Round Down + +lea rdx, [rel .data] + +; 128-bit + +vmovapd xmm0, [rdx] +vmovapd xmm1, [rdx + 16] + +; 128-bit register + +vcvtps2ph xmm2, xmm0, 1 +vcvtps2ph xmm3, xmm1, 1 + +; 128-bit memory +vcvtps2ph [rel .memarea + 0], xmm0, 1 +vcvtps2ph [rel .memarea + 8], xmm1, 1 +vmovapd xmm4, [rel .memarea] + +; 256-bit + +vmovapd ymm5, [rdx] + +; 256-bit register + +vcvtps2ph xmm6, ymm5, 1 + +; 256-bit memory + +vcvtps2ph [rel .memarea + 16], ymm5, 1 +vmovapd xmm7, [rel .memarea + 16] + +hlt + +align 32 +.data: +dd 0x3F800000, 0x00800000, 0x7F7FFFFF, 0x7FC00000 ; 1.0, FLT_MIN, FLT_MAX, QNaN +dd 0x40600000, 0x7F800000, 0xFF800000, 0x00000001 ; 3.5, +inf, -inf, FLT_TRUE_MIN + +; A quaint little area for testing the store variant of VCVTPS2PH +.memarea: times 16 dq 0 + diff --git a/unittests/ASM/VEX/vcvtps2ph_rtne.asm b/unittests/ASM/VEX/vcvtps2ph_rtne.asm new file mode 100644 index 000000000..e3f4b9e12 --- /dev/null +++ b/unittests/ASM/VEX/vcvtps2ph_rtne.asm @@ -0,0 +1,58 @@ +%ifdef CONFIG +{ + "HostFeatures": ["AVX"], + "RegData": { + "XMM0": ["0x008000003F800000", "0x7FC000007F7FFFFF", "0", "0"], + "XMM1": ["0x7F80000040600000", "0x00000001FF800000", "0", "0"], + "XMM2": ["0x7E007C0000003C00", "0x0000000000000000", "0", "0"], + "XMM3": ["0x0000FC007C004300", "0x0000000000000000", "0", "0"], + "XMM4": ["0x7E007C0000003C00", "0x0000FC007C004300", "0", "0"], + "XMM5": ["0x008000003F800000", "0x7FC000007F7FFFFF", "0x7F80000040600000", "0x00000001FF800000"], + "XMM6": ["0x7E007C0000003C00", "0x0000FC007C004300", "0", "0"], + "XMM7": ["0x7E007C0000003C00", "0x0000FC007C004300", "0", "0"] + } +} +%endif + +; Round to Nearest Even + +lea rdx, [rel .data] + +; 128-bit + +vmovapd xmm0, [rdx] +vmovapd xmm1, [rdx + 16] + +; 128-bit register + +vcvtps2ph xmm2, xmm0, 0 +vcvtps2ph xmm3, xmm1, 0 + +; 128-bit memory +vcvtps2ph [rel .memarea + 0], xmm0, 0 +vcvtps2ph [rel .memarea + 8], xmm1, 0 +vmovapd xmm4, [rel .memarea] + +; 256-bit + +vmovapd ymm5, [rdx] + +; 256-bit register + +vcvtps2ph xmm6, ymm5, 0 + +; 256-bit memory + +vcvtps2ph [rel .memarea + 16], ymm5, 0 +vmovapd xmm7, [rel .memarea + 16] + +hlt + +align 32 +.data: +dd 0x3F800000, 0x00800000, 0x7F7FFFFF, 0x7FC00000 ; 1.0, FLT_MIN, FLT_MAX, QNaN +dd 0x40600000, 0x7F800000, 0xFF800000, 0x00000001 ; 3.5, +inf, -inf, FLT_TRUE_MIN + +; A quaint little area for testing the store variant of VCVTPS2PH +.memarea: times 16 dq 0 + diff --git a/unittests/ASM/VEX/vcvtps2ph_ru.asm b/unittests/ASM/VEX/vcvtps2ph_ru.asm new file mode 100644 index 000000000..1bc3b0e15 --- /dev/null +++ b/unittests/ASM/VEX/vcvtps2ph_ru.asm @@ -0,0 +1,58 @@ +%ifdef CONFIG +{ + "HostFeatures": ["AVX"], + "RegData": { + "XMM0": ["0x008000003F800000", "0x7FC000007F7FFFFF", "0", "0"], + "XMM1": ["0x7F80000040600000", "0x00000001FF800000", "0", "0"], + "XMM2": ["0x7E007C0000013C00", "0x0000000000000000", "0", "0"], + "XMM3": ["0x0001FC007C004300", "0x0000000000000000", "0", "0"], + "XMM4": ["0x7E007C0000013C00", "0x0001FC007C004300", "0", "0"], + "XMM5": ["0x008000003F800000", "0x7FC000007F7FFFFF", "0x7F80000040600000", "0x00000001FF800000"], + "XMM6": ["0x7E007C0000013C00", "0x0001FC007C004300", "0", "0"], + "XMM7": ["0x7E007C0000013C00", "0x0001FC007C004300", "0", "0"] + } +} +%endif + +; Round Up + +lea rdx, [rel .data] + +; 128-bit + +vmovapd xmm0, [rdx] +vmovapd xmm1, [rdx + 16] + +; 128-bit register + +vcvtps2ph xmm2, xmm0, 2 +vcvtps2ph xmm3, xmm1, 2 + +; 128-bit memory +vcvtps2ph [rel .memarea + 0], xmm0, 2 +vcvtps2ph [rel .memarea + 8], xmm1, 2 +vmovapd xmm4, [rel .memarea] + +; 256-bit + +vmovapd ymm5, [rdx] + +; 256-bit register + +vcvtps2ph xmm6, ymm5, 2 + +; 256-bit memory + +vcvtps2ph [rel .memarea + 16], ymm5, 2 +vmovapd xmm7, [rel .memarea + 16] + +hlt + +align 32 +.data: +dd 0x3F800000, 0x00800000, 0x7F7FFFFF, 0x7FC00000 ; 1.0, FLT_MIN, FLT_MAX, QNaN +dd 0x40600000, 0x7F800000, 0xFF800000, 0x00000001 ; 3.5, +inf, -inf, FLT_TRUE_MIN + +; A quaint little area for testing the store variant of VCVTPS2PH +.memarea: times 16 dq 0 + diff --git a/unittests/ASM/VEX/vcvtps2ph_trunc.asm b/unittests/ASM/VEX/vcvtps2ph_trunc.asm new file mode 100644 index 000000000..3d45bcba5 --- /dev/null +++ b/unittests/ASM/VEX/vcvtps2ph_trunc.asm @@ -0,0 +1,58 @@ +%ifdef CONFIG +{ + "HostFeatures": ["AVX"], + "RegData": { + "XMM0": ["0x008000003F800000", "0x7FC000007F7FFFFF", "0", "0"], + "XMM1": ["0x7F80000040600000", "0x00000001FF800000", "0", "0"], + "XMM2": ["0x7E007BFF00003C00", "0x0000000000000000", "0", "0"], + "XMM3": ["0x0000FC007C004300", "0x0000000000000000", "0", "0"], + "XMM4": ["0x7E007BFF00003C00", "0x0000FC007C004300", "0", "0"], + "XMM5": ["0x008000003F800000", "0x7FC000007F7FFFFF", "0x7F80000040600000", "0x00000001FF800000"], + "XMM6": ["0x7E007BFF00003C00", "0x0000FC007C004300", "0", "0"], + "XMM7": ["0x7E007BFF00003C00", "0x0000FC007C004300", "0", "0"] + } +} +%endif + +; Truncate + +lea rdx, [rel .data] + +; 128-bit + +vmovapd xmm0, [rdx] +vmovapd xmm1, [rdx + 16] + +; 128-bit register + +vcvtps2ph xmm2, xmm0, 3 +vcvtps2ph xmm3, xmm1, 3 + +; 128-bit memory +vcvtps2ph [rel .memarea + 0], xmm0, 3 +vcvtps2ph [rel .memarea + 8], xmm1, 3 +vmovapd xmm4, [rel .memarea] + +; 256-bit + +vmovapd ymm5, [rdx] + +; 256-bit register + +vcvtps2ph xmm6, ymm5, 3 + +; 256-bit memory + +vcvtps2ph [rel .memarea + 16], ymm5, 3 +vmovapd xmm7, [rel .memarea + 16] + +hlt + +align 32 +.data: +dd 0x3F800000, 0x00800000, 0x7F7FFFFF, 0x7FC00000 ; 1.0, FLT_MIN, FLT_MAX, QNaN +dd 0x40600000, 0x7F800000, 0xFF800000, 0x00000001 ; 3.5, +inf, -inf, FLT_TRUE_MIN + +; A quaint little area for testing the store variant of VCVTPS2PH +.memarea: times 16 dq 0 + diff --git a/unittests/InstructionCountCI/VEX_map2.json b/unittests/InstructionCountCI/VEX_map2.json index 47a4ba194..e8913792d 100644 --- a/unittests/InstructionCountCI/VEX_map2.json +++ b/unittests/InstructionCountCI/VEX_map2.json @@ -603,17 +603,43 @@ ] }, "vcvtph2ps xmm0, xmm1": { - "ExpectedInstructionCount": -1, - "Skip": "Yes", + "ExpectedInstructionCount": 1, "Comment": [ "Map 2 0b01 0x13 128-bit" + ], + "ExpectedArm64ASM": [ + "fcvtl v16.4s, v17.4h" + ] + }, + "vcvtph2ps xmm0, [rax]": { + "ExpectedInstructionCount": 2, + "Comment": [ + "Map 2 0b01 0x13 128-bit" + ], + "ExpectedArm64ASM": [ + "ldr d2, [x4]", + "fcvtl v16.4s, v2.4h" ] }, "vcvtph2ps ymm0, xmm1": { - "ExpectedInstructionCount": -1, - "Skip": "Yes", + "ExpectedInstructionCount": 2, "Comment": [ "Map 2 0b01 0x13 256-bit" + ], + "ExpectedArm64ASM": [ + "zip1 z16.h, z17.h, z17.h", + "fcvtlt z16.s, p7/m, z16.h" + ] + }, + "vcvtph2ps ymm0, [rax]": { + "ExpectedInstructionCount": 3, + "Comment": [ + "Map 2 0b01 0x13 256-bit" + ], + "ExpectedArm64ASM": [ + "ldr q2, [x4]", + "zip1 z16.h, z2.h, z2.h", + "fcvtlt z16.s, p7/m, z16.h" ] }, "vpermps ymm0, ymm1, ymm2": { diff --git a/unittests/InstructionCountCI/VEX_map3.json b/unittests/InstructionCountCI/VEX_map3.json index 44ae251d7..b43886557 100644 --- a/unittests/InstructionCountCI/VEX_map3.json +++ b/unittests/InstructionCountCI/VEX_map3.json @@ -3058,83 +3058,265 @@ ] }, "vcvtps2ph xmm0, xmm1, 00000000b": { - "ExpectedInstructionCount": -1, - "Skip": "Yes", + "ExpectedInstructionCount": 20, "Comment": [ "nearest rounding", "Map 3 0b01 0x1D 128-bit" + ], + "ExpectedArm64ASM": [ + "mrs x20, fpcr", + "ubfx x20, x20, #22, #3", + "rbit w0, w20", + "bfi x20, x0, #30, #2", + "mov w21, #0x0", + "rbit w1, w21", + "lsr w1, w1, #30", + "mrs x0, fpcr", + "bfi x0, x1, #22, #2", + "lsr x1, x21, #2", + "bfi x0, x1, #24, #1", + "msr fpcr, x0", + "fcvtn v16.4h, v17.4s", + "rbit w1, w20", + "lsr w1, w1, #30", + "mrs x0, fpcr", + "bfi x0, x1, #22, #2", + "lsr x1, x20, #2", + "bfi x0, x1, #24, #1", + "msr fpcr, x0" ] }, "vcvtps2ph xmm0, xmm1, 00000001b": { - "ExpectedInstructionCount": -1, - "Skip": "Yes", + "ExpectedInstructionCount": 20, "Comment": [ "-inf rounding", "Map 3 0b01 0x1D 128-bit" + ], + "ExpectedArm64ASM": [ + "mrs x20, fpcr", + "ubfx x20, x20, #22, #3", + "rbit w0, w20", + "bfi x20, x0, #30, #2", + "mov w21, #0x1", + "rbit w1, w21", + "lsr w1, w1, #30", + "mrs x0, fpcr", + "bfi x0, x1, #22, #2", + "lsr x1, x21, #2", + "bfi x0, x1, #24, #1", + "msr fpcr, x0", + "fcvtn v16.4h, v17.4s", + "rbit w1, w20", + "lsr w1, w1, #30", + "mrs x0, fpcr", + "bfi x0, x1, #22, #2", + "lsr x1, x20, #2", + "bfi x0, x1, #24, #1", + "msr fpcr, x0" ] }, "vcvtps2ph xmm0, xmm1, 00000010b": { - "ExpectedInstructionCount": -1, - "Skip": "Yes", + "ExpectedInstructionCount": 20, "Comment": [ "+inf rounding", "Map 3 0b01 0x1D 128-bit" + ], + "ExpectedArm64ASM": [ + "mrs x20, fpcr", + "ubfx x20, x20, #22, #3", + "rbit w0, w20", + "bfi x20, x0, #30, #2", + "mov w21, #0x2", + "rbit w1, w21", + "lsr w1, w1, #30", + "mrs x0, fpcr", + "bfi x0, x1, #22, #2", + "lsr x1, x21, #2", + "bfi x0, x1, #24, #1", + "msr fpcr, x0", + "fcvtn v16.4h, v17.4s", + "rbit w1, w20", + "lsr w1, w1, #30", + "mrs x0, fpcr", + "bfi x0, x1, #22, #2", + "lsr x1, x20, #2", + "bfi x0, x1, #24, #1", + "msr fpcr, x0" ] }, "vcvtps2ph xmm0, xmm1, 00000011b": { - "ExpectedInstructionCount": -1, - "Skip": "Yes", + "ExpectedInstructionCount": 20, "Comment": [ "truncate rounding", "Map 3 0b01 0x1D 128-bit" + ], + "ExpectedArm64ASM": [ + "mrs x20, fpcr", + "ubfx x20, x20, #22, #3", + "rbit w0, w20", + "bfi x20, x0, #30, #2", + "mov w21, #0x3", + "rbit w1, w21", + "lsr w1, w1, #30", + "mrs x0, fpcr", + "bfi x0, x1, #22, #2", + "lsr x1, x21, #2", + "bfi x0, x1, #24, #1", + "msr fpcr, x0", + "fcvtn v16.4h, v17.4s", + "rbit w1, w20", + "lsr w1, w1, #30", + "mrs x0, fpcr", + "bfi x0, x1, #22, #2", + "lsr x1, x20, #2", + "bfi x0, x1, #24, #1", + "msr fpcr, x0" ] }, "vcvtps2ph xmm0, xmm1, 00000100b": { - "ExpectedInstructionCount": -1, - "Skip": "Yes", + "ExpectedInstructionCount": 1, "Comment": [ "host mode rounding", "Map 3 0b01 0x1D 128-bit" + ], + "ExpectedArm64ASM": [ + "fcvtn v16.4h, v17.4s" ] }, "vcvtps2ph xmm0, ymm1, 00000000b": { - "ExpectedInstructionCount": -1, - "Skip": "Yes", + "ExpectedInstructionCount": 22, "Comment": [ "nearest rounding", "Map 3 0b01 0x1D 256-bit" + ], + "ExpectedArm64ASM": [ + "mrs x20, fpcr", + "ubfx x20, x20, #22, #3", + "rbit w0, w20", + "bfi x20, x0, #30, #2", + "mov w21, #0x0", + "rbit w1, w21", + "lsr w1, w1, #30", + "mrs x0, fpcr", + "bfi x0, x1, #22, #2", + "lsr x1, x21, #2", + "bfi x0, x1, #24, #1", + "msr fpcr, x0", + "fcvtnt z2.h, p7/m, z17.s", + "uzp2 z2.h, z2.h, z2.h", + "rbit w1, w20", + "lsr w1, w1, #30", + "mrs x0, fpcr", + "bfi x0, x1, #22, #2", + "lsr x1, x20, #2", + "bfi x0, x1, #24, #1", + "msr fpcr, x0", + "mov v16.16b, v2.16b" ] }, "vcvtps2ph xmm0, ymm1, 00000001b": { - "ExpectedInstructionCount": -1, - "Skip": "Yes", + "ExpectedInstructionCount": 22, "Comment": [ "-inf rounding", "Map 3 0b01 0x1D 256-bit" + ], + "ExpectedArm64ASM": [ + "mrs x20, fpcr", + "ubfx x20, x20, #22, #3", + "rbit w0, w20", + "bfi x20, x0, #30, #2", + "mov w21, #0x1", + "rbit w1, w21", + "lsr w1, w1, #30", + "mrs x0, fpcr", + "bfi x0, x1, #22, #2", + "lsr x1, x21, #2", + "bfi x0, x1, #24, #1", + "msr fpcr, x0", + "fcvtnt z2.h, p7/m, z17.s", + "uzp2 z2.h, z2.h, z2.h", + "rbit w1, w20", + "lsr w1, w1, #30", + "mrs x0, fpcr", + "bfi x0, x1, #22, #2", + "lsr x1, x20, #2", + "bfi x0, x1, #24, #1", + "msr fpcr, x0", + "mov v16.16b, v2.16b" ] }, "vcvtps2ph xmm0, ymm1, 00000010b": { - "ExpectedInstructionCount": -1, - "Skip": "Yes", + "ExpectedInstructionCount": 22, "Comment": [ "+inf rounding", "Map 3 0b01 0x1D 256-bit" + ], + "ExpectedArm64ASM": [ + "mrs x20, fpcr", + "ubfx x20, x20, #22, #3", + "rbit w0, w20", + "bfi x20, x0, #30, #2", + "mov w21, #0x2", + "rbit w1, w21", + "lsr w1, w1, #30", + "mrs x0, fpcr", + "bfi x0, x1, #22, #2", + "lsr x1, x21, #2", + "bfi x0, x1, #24, #1", + "msr fpcr, x0", + "fcvtnt z2.h, p7/m, z17.s", + "uzp2 z2.h, z2.h, z2.h", + "rbit w1, w20", + "lsr w1, w1, #30", + "mrs x0, fpcr", + "bfi x0, x1, #22, #2", + "lsr x1, x20, #2", + "bfi x0, x1, #24, #1", + "msr fpcr, x0", + "mov v16.16b, v2.16b" ] }, "vcvtps2ph xmm0, ymm1, 00000011b": { - "ExpectedInstructionCount": -1, - "Skip": "Yes", + "ExpectedInstructionCount": 22, "Comment": [ "truncate rounding", "Map 3 0b01 0x1D 256-bit" + ], + "ExpectedArm64ASM": [ + "mrs x20, fpcr", + "ubfx x20, x20, #22, #3", + "rbit w0, w20", + "bfi x20, x0, #30, #2", + "mov w21, #0x3", + "rbit w1, w21", + "lsr w1, w1, #30", + "mrs x0, fpcr", + "bfi x0, x1, #22, #2", + "lsr x1, x21, #2", + "bfi x0, x1, #24, #1", + "msr fpcr, x0", + "fcvtnt z2.h, p7/m, z17.s", + "uzp2 z2.h, z2.h, z2.h", + "rbit w1, w20", + "lsr w1, w1, #30", + "mrs x0, fpcr", + "bfi x0, x1, #22, #2", + "lsr x1, x20, #2", + "bfi x0, x1, #24, #1", + "msr fpcr, x0", + "mov v16.16b, v2.16b" ] }, "vcvtps2ph xmm0, ymm1, 00000100b": { - "ExpectedInstructionCount": -1, - "Skip": "Yes", + "ExpectedInstructionCount": 3, "Comment": [ "host mode rounding", "Map 3 0b01 0x1D 256-bit" + ], + "ExpectedArm64ASM": [ + "fcvtnt z2.h, p7/m, z17.s", + "uzp2 z2.h, z2.h, z2.h", + "mov v16.16b, v2.16b" ] }, "vpinsrb xmm0, xmm0, eax, 0": {