diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
index 820aa9b7a..d05be8b63 100644
--- a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
+++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
@@ -389,7 +389,7 @@ void OpDispatchBuilder::SecondaryALUOp(OpcodeArgs) {
         break;
       }
       case FEXCore::IR::IROps::OP_AND: {
-        Dest = _AtomicFetchAnd(Size, Src, DestMem);
+        Dest = _AtomicFetchAnd(IR::SizeToOpSize(Size), Src, DestMem);
         Result = _And(Dest, Src);
         break;
       }
@@ -3021,7 +3021,7 @@ void OpDispatchBuilder::BTROp(OpcodeArgs) {
       BitMask = _Not(OpSize::i64Bit, BitMask);
       // XXX: Technically this can optimize to an AArch64 ldclralb
       // We don't current support this IR op though
-      Result = _AtomicFetchAnd(1, BitMask, MemoryLocation);
+      Result = _AtomicFetchAnd(OpSize::i8Bit, BitMask, MemoryLocation);
       // Now shift in to the correct bit location
       Result = _Lshr(Result, BitSelect);
     } else {
diff --git a/FEXCore/include/FEXCore/IR/IREmitter.h b/FEXCore/include/FEXCore/IR/IREmitter.h
index 9d12c3716..faf755d06 100644
--- a/FEXCore/include/FEXCore/IR/IREmitter.h
+++ b/FEXCore/include/FEXCore/IR/IREmitter.h
@@ -139,9 +139,6 @@ friend class FEXCore::IR::PassManager;
   IRPair<IROp_AtomicFetchSub> _AtomicFetchSub(uint8_t Size, OrderedNode *_Value, OrderedNode *_Addr) {
     return _AtomicFetchSub(static_cast<OpSize>(Size), _Value, _Addr);
   }
-  IRPair<IROp_AtomicFetchAnd> _AtomicFetchAnd(uint8_t Size, OrderedNode *_Value, OrderedNode *_Addr) {
-    return _AtomicFetchAnd(static_cast<OpSize>(Size), _Value, _Addr);
-  }
   ///< ALU
   IRPair<IROp_Add> _Add(OrderedNode *_Src1, OrderedNode *_Src2) {
     return _Add(static_cast<OpSize>(std::max<uint8_t>(4, std::max(GetOpSize(_Src1), GetOpSize(_Src2)))), _Src1, _Src2);