From 929f9a7ad25558710331e3077491fd07775d773a Mon Sep 17 00:00:00 2001
From: LC <mai.iam2048@gmail.com>
Date: Sat, 11 Jul 2026 15:03:27 -0400
Subject: [PATCH] Dispatcher: Avoid loading unnecessary reg in vixl single step

CompileSingleStep only takes one uint64_t, not two.
---
 FEXCore/Source/Interface/Core/Dispatcher/Dispatcher.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/FEXCore/Source/Interface/Core/Dispatcher/Dispatcher.cpp b/FEXCore/Source/Interface/Core/Dispatcher/Dispatcher.cpp
index e2c4075d2..748597e15 100644
--- a/FEXCore/Source/Interface/Core/Dispatcher/Dispatcher.cpp
+++ b/FEXCore/Source/Interface/Core/Dispatcher/Dispatcher.cpp
@@ -357,7 +357,7 @@ void Dispatcher::EmitDispatcher() {
       ldr(ARMEmitter::XReg::x4, &l_CompileSingleStep);
 
       if (!CTX->Config.DisableVixlIndirectCalls) [[unlikely]] {
-        GenerateIndirectRuntimeCall<uintptr_t, void*, void*, uint64_t, uint64_t>(ARMEmitter::Reg::r4);
+        GenerateIndirectRuntimeCall<uintptr_t, void*, void*, uint64_t>(ARMEmitter::Reg::r4);
       } else {
         blr(ARMEmitter::Reg::r4); // { CTX, Frame, RIP }
       }