From 91229c8ea25403cec8d0afbc31850ce393cc6256 Mon Sep 17 00:00:00 2001
From: Ryan Houdek <Sonicadvance1@gmail.com>
Date: Fri, 25 Sep 2020 23:03:07 -0700
Subject: [PATCH] Implements new VTBL1 IR op in x86 JIT

---
 .../Source/Interface/Core/JIT/x86_64/JIT.cpp    | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/External/FEXCore/Source/Interface/Core/JIT/x86_64/JIT.cpp b/External/FEXCore/Source/Interface/Core/JIT/x86_64/JIT.cpp
index c536990db..08024d56a 100644
--- a/External/FEXCore/Source/Interface/Core/JIT/x86_64/JIT.cpp
+++ b/External/FEXCore/Source/Interface/Core/JIT/x86_64/JIT.cpp
@@ -4219,6 +4219,23 @@ void *JITCore::CompileCode([[maybe_unused]] FEXCore::IR::IRListView<true> const
           }
           break;
         }
+        case IR::OP_VTBL1: {
+          auto Op = IROp->C<IR::IROp_VTBL1>();
+          switch (OpSize) {
+          case 8: {
+            vpshufb(GetDst(Node), GetSrc(Op->Header.Args[0].ID()), GetSrc(Op->Header.Args[1].ID()));
+            movq(GetDst(Node), GetDst(Node));
+            break;
+          }
+          case 16: {
+            vpshufb(GetDst(Node), GetSrc(Op->Header.Args[0].ID()), GetSrc(Op->Header.Args[1].ID()));
+            break;
+          }
+          default: LogMan::Msg::A("Unknown OpSize: %d", OpSize); break;
+          }
+          break;
+        }
+
         case IR::OP_FLOAT_FROMGPR_S: {
           auto Op = IROp->C<IR::IROp_Float_FromGPR_S>();
           if (Op->Header.ElementSize == 8) {