diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
index 440b98ea1..2d56b952c 100644
--- a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
+++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
@@ -5373,8 +5373,8 @@ void OpDispatchBuilder::InstallHostSpecificOpcodeHandlers() {
     {OPD(3, 0b01, 0x38), 1, &OpDispatchBuilder::VINSERTOp},
     {OPD(3, 0b01, 0x39), 1, &OpDispatchBuilder::VEXTRACT128Op},
 
-    {OPD(3, 0b01, 0x40), 1, &OpDispatchBuilder::VDPPOp<4>},
-    {OPD(3, 0b01, 0x41), 1, &OpDispatchBuilder::VDPPOp<8>},
+    {OPD(3, 0b01, 0x40), 1, &OpDispatchBuilder::VDPPOp<OpSize::i32Bit>},
+    {OPD(3, 0b01, 0x41), 1, &OpDispatchBuilder::VDPPOp<OpSize::i64Bit>},
     {OPD(3, 0b01, 0x42), 1, &OpDispatchBuilder::VMPSADBWOp},
 
     {OPD(3, 0b01, 0x46), 1, &OpDispatchBuilder::VPERM2Op},
diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher.h b/FEXCore/Source/Interface/Core/OpcodeDispatcher.h
index ca6650fb4..cbb8361d9 100644
--- a/FEXCore/Source/Interface/Core/OpcodeDispatcher.h
+++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher.h
@@ -578,7 +578,7 @@ public:
 
   void VBROADCASTOp(OpcodeArgs, IR::OpSize ElementSize);
 
-  template<size_t ElementSize>
+  template<IR::OpSize ElementSize>
   void VDPPOp(OpcodeArgs);
 
   void VEXTRACT128Op(OpcodeArgs);
@@ -897,7 +897,7 @@ public:
   void PTestOpImpl(OpSize Size, Ref Dest, Ref Src);
   void PTestOp(OpcodeArgs);
   void PHMINPOSUWOp(OpcodeArgs);
-  template<size_t ElementSize>
+  template<IR::OpSize ElementSize>
   void DPPOp(OpcodeArgs);
 
   void MPSADBWOp(OpcodeArgs);
@@ -1368,7 +1368,7 @@ private:
 
   Ref CVTGPR_To_FPRImpl(OpcodeArgs, size_t DstElementSize, const X86Tables::DecodedOperand& Src1Op, const X86Tables::DecodedOperand& Src2Op);
 
-  Ref DPPOpImpl(size_t DstSize, Ref Src1, Ref Src2, uint8_t Mask, size_t ElementSize);
+  Ref DPPOpImpl(IR::OpSize DstSize, Ref Src1, Ref Src2, uint8_t Mask, size_t ElementSize);
 
   Ref VDPPSOpImpl(OpcodeArgs, const X86Tables::DecodedOperand& Src1, const X86Tables::DecodedOperand& Src2, const X86Tables::DecodedOperand& Imm);
 
@@ -2186,8 +2186,8 @@ private:
   fextl::unordered_map<IndexNamedVectorMapKey, Ref, IndexNamedVectorMapKeyHasher> CachedIndexedNamedVectorConstants;
 
   // Load and cache a named vector constant.
-  Ref LoadAndCacheNamedVectorConstant(uint8_t Size, FEXCore::IR::NamedVectorConstant NamedConstant) {
-    auto log2_size_bytes = FEXCore::ilog2(Size);
+  Ref LoadAndCacheNamedVectorConstant(IR::OpSize Size, FEXCore::IR::NamedVectorConstant NamedConstant) {
+    auto log2_size_bytes = FEXCore::ilog2(IR::OpSizeToSize(Size));
     if (CachedNamedVectorConstants[NamedConstant][log2_size_bytes]) {
       return CachedNamedVectorConstants[NamedConstant][log2_size_bytes];
     }
@@ -2213,11 +2213,11 @@ private:
     return Constant;
   }
 
-  Ref LoadUncachedZeroVector(uint8_t Size) {
+  Ref LoadUncachedZeroVector(IR::OpSize Size) {
     return _LoadNamedVectorConstant(Size, IR::NamedVectorConstant::NAMED_VECTOR_ZERO);
   }
 
-  Ref LoadZeroVector(uint8_t Size) {
+  Ref LoadZeroVector(IR::OpSize Size) {
     return LoadAndCacheNamedVectorConstant(Size, IR::NamedVectorConstant::NAMED_VECTOR_ZERO);
   }
 
diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher/Crypto.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher/Crypto.cpp
index a102f2435..f2317a51c 100644
--- a/FEXCore/Source/Interface/Core/OpcodeDispatcher/Crypto.cpp
+++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher/Crypto.cpp
@@ -315,7 +315,7 @@ void OpDispatchBuilder::AESEncOp(OpcodeArgs) {
 }
 
 void OpDispatchBuilder::VAESEncOp(OpcodeArgs) {
-  const auto DstSize = GetDstSize(Op);
+  const auto DstSize = OpSizeFromDst(Op);
   [[maybe_unused]] const auto Is128Bit = DstSize == Core::CPUState::XMM_SSE_REG_SIZE;
 
   // TODO: Handle 256-bit VAESENC.
@@ -336,7 +336,7 @@ void OpDispatchBuilder::AESEncLastOp(OpcodeArgs) {
 }
 
 void OpDispatchBuilder::VAESEncLastOp(OpcodeArgs) {
-  const auto DstSize = GetDstSize(Op);
+  const auto DstSize = OpSizeFromDst(Op);
   [[maybe_unused]] const auto Is128Bit = DstSize == Core::CPUState::XMM_SSE_REG_SIZE;
 
   // TODO: Handle 256-bit VAESENCLAST.
@@ -357,7 +357,7 @@ void OpDispatchBuilder::AESDecOp(OpcodeArgs) {
 }
 
 void OpDispatchBuilder::VAESDecOp(OpcodeArgs) {
-  const auto DstSize = GetDstSize(Op);
+  const auto DstSize = OpSizeFromDst(Op);
   [[maybe_unused]] const auto Is128Bit = DstSize == Core::CPUState::XMM_SSE_REG_SIZE;
 
   // TODO: Handle 256-bit VAESDEC.
@@ -378,7 +378,7 @@ void OpDispatchBuilder::AESDecLastOp(OpcodeArgs) {
 }
 
 void OpDispatchBuilder::VAESDecLastOp(OpcodeArgs) {
-  const auto DstSize = GetDstSize(Op);
+  const auto DstSize = OpSizeFromDst(Op);
   [[maybe_unused]] const auto Is128Bit = DstSize == Core::CPUState::XMM_SSE_REG_SIZE;
 
   // TODO: Handle 256-bit VAESDECLAST.
diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher/H0F3ATables.h b/FEXCore/Source/Interface/Core/OpcodeDispatcher/H0F3ATables.h
index 3efabe283..5b82b345b 100644
--- a/FEXCore/Source/Interface/Core/OpcodeDispatcher/H0F3ATables.h
+++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher/H0F3ATables.h
@@ -26,8 +26,8 @@ constexpr std::tuple<uint16_t, uint8_t, FEXCore::X86Tables::OpDispatchPtr> OpDis
   {OPD(0, PF_3A_66, 0x20), 1, &OpDispatchBuilder::PINSROp<OpSize::i8Bit>},
   {OPD(0, PF_3A_66, 0x21), 1, &OpDispatchBuilder::InsertPSOp},
   {OPD(0, PF_3A_66, 0x22), 1, &OpDispatchBuilder::PINSROp<OpSize::i32Bit>},
-  {OPD(0, PF_3A_66, 0x40), 1, &OpDispatchBuilder::DPPOp<4>},
-  {OPD(0, PF_3A_66, 0x41), 1, &OpDispatchBuilder::DPPOp<8>},
+  {OPD(0, PF_3A_66, 0x40), 1, &OpDispatchBuilder::DPPOp<OpSize::i32Bit>},
+  {OPD(0, PF_3A_66, 0x41), 1, &OpDispatchBuilder::DPPOp<OpSize::i64Bit>},
   {OPD(0, PF_3A_66, 0x42), 1, &OpDispatchBuilder::MPSADBWOp},
 
   {OPD(0, PF_3A_66, 0x60), 1, &OpDispatchBuilder::VPCMPESTRMOp},
diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp
index eabea2088..238401ad9 100644
--- a/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp
+++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp
@@ -254,7 +254,7 @@ void OpDispatchBuilder::VectorALUOp(OpcodeArgs, IROps IROp, size_t ElementSize)
 }
 
 void OpDispatchBuilder::VectorXOROp(OpcodeArgs) {
-  const auto Size = GetSrcSize(Op);
+  const auto Size = OpSizeFromSrc(Op);
 
   // Special case for vector xor with itself being the optimal way for x86 to zero vector registers.
   if (Op->Dest.IsGPR() && Op->Src[0].IsGPR() && Op->Dest.Data.GPR.GPR == Op->Src[0].Data.GPR.GPR) {
@@ -281,7 +281,7 @@ void OpDispatchBuilder::AVXVectorALUOp(OpcodeArgs, IROps IROp, size_t ElementSiz
 void OpDispatchBuilder::AVXVectorXOROp(OpcodeArgs) {
   // Special case for vector xor with itself being the optimal way for x86 to zero vector registers.
   if (Op->Src[0].IsGPR() && Op->Src[1].IsGPR() && Op->Src[0].Data.GPR.GPR == Op->Src[1].Data.GPR.GPR) {
-    const auto DstSize = GetDstSize(Op);
+    const auto DstSize = OpSizeFromDst(Op);
     const auto ZeroRegister = LoadZeroVector(DstSize);
     StoreResult(FPRClass, Op, ZeroRegister, OpSize::iInvalid);
     return;
@@ -1842,7 +1842,7 @@ void OpDispatchBuilder::PSRLDQ(OpcodeArgs) {
     return;
   }
 
-  const auto Size = GetDstSize(Op);
+  const auto Size = OpSizeFromDst(Op);
 
   Ref Dest = LoadSource(FPRClass, Op, Op->Dest, Op->Flags);
   Ref Result = LoadZeroVector(Size);
@@ -1854,7 +1854,7 @@ void OpDispatchBuilder::PSRLDQ(OpcodeArgs) {
 }
 
 void OpDispatchBuilder::VPSRLDQOp(OpcodeArgs) {
-  const auto DstSize = GetDstSize(Op);
+  const auto DstSize = OpSizeFromDst(Op);
   const auto Is128Bit = DstSize == Core::CPUState::XMM_SSE_REG_SIZE;
   const uint64_t Shift = Op->Src[1].Literal();
 
@@ -1894,7 +1894,7 @@ void OpDispatchBuilder::PSLLDQ(OpcodeArgs) {
     return;
   }
 
-  const auto Size = GetDstSize(Op);
+  const auto Size = OpSizeFromDst(Op);
 
   Ref Dest = LoadSource(FPRClass, Op, Op->Dest, Op->Flags);
   Ref Result = LoadZeroVector(Size);
@@ -1906,7 +1906,7 @@ void OpDispatchBuilder::PSLLDQ(OpcodeArgs) {
 }
 
 void OpDispatchBuilder::VPSLLDQOp(OpcodeArgs) {
-  const auto DstSize = GetDstSize(Op);
+  const auto DstSize = OpSizeFromDst(Op);
   const auto Is128Bit = DstSize == Core::CPUState::XMM_SSE_REG_SIZE;
   const uint64_t Shift = Op->Src[1].Literal();
 
@@ -2784,7 +2784,7 @@ void OpDispatchBuilder::DefaultX87State(OpcodeArgs) {
 
   // On top of resetting the flags to a default state, we also need to clear
   // all of the ST0-7/MM0-7 registers to zero.
-  Ref ZeroVector = LoadZeroVector(Core::CPUState::MM_REG_SIZE);
+  Ref ZeroVector = LoadZeroVector(OpSize::i64Bit);
   for (uint32_t i = 0; i < Core::CPUState::NUM_MMS; ++i) {
     StoreContext(MM0Index + i, ZeroVector);
   }
@@ -2793,7 +2793,7 @@ void OpDispatchBuilder::DefaultX87State(OpcodeArgs) {
 void OpDispatchBuilder::DefaultSSEState() {
   const auto NumRegs = CTX->Config.Is64BitMode ? 16U : 8U;
 
-  Ref ZeroVector = LoadZeroVector(Core::CPUState::XMM_SSE_REG_SIZE);
+  Ref ZeroVector = LoadZeroVector(OpSize::i128Bit);
   for (uint32_t i = 0; i < NumRegs; ++i) {
     StoreXMMRegister(i, ZeroVector);
   }
@@ -2812,8 +2812,8 @@ void OpDispatchBuilder::DefaultAVXState() {
 Ref OpDispatchBuilder::PALIGNROpImpl(OpcodeArgs, const X86Tables::DecodedOperand& Src1, const X86Tables::DecodedOperand& Src2,
                                      const X86Tables::DecodedOperand& Imm, bool IsAVX) {
   // For the 256-bit case we handle it as pairs of 128-bit halves.
-  const auto DstSize = GetDstSize(Op);
-  const auto SanitizedDstSize = std::min<uint8_t>(DstSize, OpSize::i128Bit);
+  const auto DstSize = OpSizeFromDst(Op);
+  const auto SanitizedDstSize = std::min(DstSize, OpSize::i128Bit);
 
   const auto Is256Bit = DstSize == Core::CPUState::XMM_AVX_REG_SIZE;
   const auto Index = Imm.Literal();
@@ -3998,7 +3998,7 @@ template void OpDispatchBuilder::VTESTPOp<OpSize::i32Bit>(OpcodeArgs);
 template void OpDispatchBuilder::VTESTPOp<OpSize::i64Bit>(OpcodeArgs);
 
 Ref OpDispatchBuilder::PHMINPOSUWOpImpl(OpcodeArgs) {
-  const auto Size = GetSrcSize(Op);
+  const auto Size = OpSizeFromSrc(Op);
 
   Ref Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags);
 
@@ -4041,7 +4041,7 @@ void OpDispatchBuilder::PHMINPOSUWOp(OpcodeArgs) {
   StoreResult(FPRClass, Op, Result, OpSize::iInvalid);
 }
 
-Ref OpDispatchBuilder::DPPOpImpl(size_t DstSize, Ref Src1, Ref Src2, uint8_t Mask, size_t ElementSize) {
+Ref OpDispatchBuilder::DPPOpImpl(IR::OpSize DstSize, Ref Src1, Ref Src2, uint8_t Mask, size_t ElementSize) {
   const auto SizeMask = [ElementSize]() {
     if (ElementSize == OpSize::i32Bit) {
       return 0b1111;
@@ -4217,13 +4217,13 @@ Ref OpDispatchBuilder::DPPOpImpl(size_t DstSize, Ref Src1, Ref Src2, uint8_t Mas
   FEX_UNREACHABLE;
 }
 
-template<size_t ElementSize>
+template<IR::OpSize ElementSize>
 void OpDispatchBuilder::DPPOp(OpcodeArgs) {
 
   Ref Dest = LoadSource(FPRClass, Op, Op->Dest, Op->Flags);
   Ref Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags);
 
-  Ref Result = DPPOpImpl(GetDstSize(Op), Dest, Src, Op->Src[1].Literal(), ElementSize);
+  Ref Result = DPPOpImpl(OpSizeFromDst(Op), Dest, Src, Op->Src[1].Literal(), ElementSize);
   StoreResult(FPRClass, Op, Result, OpSize::iInvalid);
 }
 
@@ -4237,7 +4237,7 @@ Ref OpDispatchBuilder::VDPPSOpImpl(OpcodeArgs, const X86Tables::DecodedOperand&
   const uint8_t SrcMask = Mask >> 4;
   const uint8_t DstMask = Mask & 0xF;
 
-  const auto DstSize = GetDstSize(Op);
+  const auto DstSize = OpSizeFromDst(Op);
 
   Ref Src1V = LoadSource(FPRClass, Op, Src1, Op->Flags);
   Ref Src2V = LoadSource(FPRClass, Op, Src2, Op->Flags);
@@ -4280,7 +4280,7 @@ Ref OpDispatchBuilder::VDPPSOpImpl(OpcodeArgs, const X86Tables::DecodedOperand&
   return Result;
 }
 
-template<size_t ElementSize>
+template<IR::OpSize ElementSize>
 void OpDispatchBuilder::VDPPOp(OpcodeArgs) {
   const auto DstSize = GetDstSize(Op);
 
@@ -4292,7 +4292,7 @@ void OpDispatchBuilder::VDPPOp(OpcodeArgs) {
     Ref Src1 = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags);
     Ref Src2 = LoadSource(FPRClass, Op, Op->Src[1], Op->Flags);
 
-    Result = DPPOpImpl(GetDstSize(Op), Src1, Src2, Op->Src[2].Literal(), ElementSize);
+    Result = DPPOpImpl(OpSizeFromDst(Op), Src1, Src2, Op->Src[2].Literal(), ElementSize);
   }
 
   // We don't need to emit a _VMov to clear the upper lane, since DPPOpImpl uses a zero vector
@@ -4468,7 +4468,7 @@ void OpDispatchBuilder::VCVTPS2PHOp(OpcodeArgs) {
 }
 
 void OpDispatchBuilder::VPERM2Op(OpcodeArgs) {
-  const auto DstSize = GetDstSize(Op);
+  const auto DstSize = OpSizeFromDst(Op);
   Ref Src1 = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags);
   Ref Src2 = LoadSource(FPRClass, Op, Op->Src[1], Op->Flags);
 
@@ -4577,7 +4577,7 @@ void OpDispatchBuilder::VPERMDOp(OpcodeArgs) {
 }
 
 void OpDispatchBuilder::VPERMQOp(OpcodeArgs) {
-  const auto DstSize = GetDstSize(Op);
+  const auto DstSize = OpSizeFromDst(Op);
   Ref Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags);
 
   const auto Selector = Op->Src[1].Literal();
@@ -4613,7 +4613,7 @@ Ref OpDispatchBuilder::VBLENDOpImpl(uint32_t VecSize, uint32_t ElementSize, Ref
 }
 
 void OpDispatchBuilder::VBLENDPDOp(OpcodeArgs) {
-  const auto DstSize = GetDstSize(Op);
+  const auto DstSize = OpSizeFromDst(Op);
   const auto Is256Bit = DstSize == Core::CPUState::XMM_AVX_REG_SIZE;
   const auto Selector = Op->Src[2].Literal();
 
@@ -4638,7 +4638,7 @@ void OpDispatchBuilder::VBLENDPDOp(OpcodeArgs) {
 }
 
 void OpDispatchBuilder::VPBLENDDOp(OpcodeArgs) {
-  const auto DstSize = GetDstSize(Op);
+  const auto DstSize = OpSizeFromDst(Op);
   const auto Is256Bit = DstSize == Core::CPUState::XMM_AVX_REG_SIZE;
   const auto Selector = Op->Src[2].Literal();
 
@@ -4682,7 +4682,7 @@ void OpDispatchBuilder::VPBLENDDOp(OpcodeArgs) {
 }
 
 void OpDispatchBuilder::VPBLENDWOp(OpcodeArgs) {
-  const auto DstSize = GetDstSize(Op);
+  const auto DstSize = OpSizeFromDst(Op);
   const auto Is128Bit = DstSize == Core::CPUState::XMM_SSE_REG_SIZE;
   const auto Selector = Op->Src[2].Literal();
 
@@ -4714,7 +4714,7 @@ void OpDispatchBuilder::VPBLENDWOp(OpcodeArgs) {
 }
 
 void OpDispatchBuilder::VZEROOp(OpcodeArgs) {
-  const auto DstSize = GetDstSize(Op);
+  const auto DstSize = OpSizeFromDst(Op);
   const auto IsVZEROALL = DstSize == Core::CPUState::XMM_AVX_REG_SIZE;
   const auto NumRegs = CTX->Config.Is64BitMode ? 16U : 8U;
 
@@ -4739,7 +4739,7 @@ void OpDispatchBuilder::VZEROOp(OpcodeArgs) {
 }
 
 void OpDispatchBuilder::VPERMILImmOp(OpcodeArgs, size_t ElementSize) {
-  const auto DstSize = GetDstSize(Op);
+  const auto DstSize = OpSizeFromDst(Op);
   const auto Is256Bit = DstSize == Core::CPUState::XMM_AVX_REG_SIZE;
   const auto Selector = Op->Src[1].Literal() & 0xFF;
 
@@ -4884,7 +4884,7 @@ void OpDispatchBuilder::PCMPXSTRXOpImpl(OpcodeArgs, bool IsExplicit, bool IsMask
       const auto ElementSize = 1U << (Control & 1);
       const auto NumElements = 16U >> (Control & 1);
 
-      Ref Result = LoadZeroVector(Core::CPUState::XMM_SSE_REG_SIZE);
+      Ref Result = LoadZeroVector(OpSize::i128Bit);
       for (uint32_t i = 0; i < NumElements; i++) {
         Ref SignBit = _Sbfe(OpSize::i64Bit, 1, i, IntermediateResult);
         Result = _VInsGPR(Core::CPUState::XMM_SSE_REG_SIZE, ElementSize, i, Result, SignBit);
@@ -4960,7 +4960,7 @@ void OpDispatchBuilder::VFMAImpl(OpcodeArgs, IROps IROp, bool Scalar, uint8_t Sr
 }
 
 void OpDispatchBuilder::VFMAddSubImpl(OpcodeArgs, bool AddSub, uint8_t Src1Idx, uint8_t Src2Idx, uint8_t AddendIdx) {
-  const auto Size = GetDstSize(Op);
+  const auto Size = OpSizeFromDst(Op);
   const auto Is256Bit = Size == Core::CPUState::XMM_AVX_REG_SIZE;
 
   const OpSize ElementSize = Op->Flags & X86Tables::DecodeFlags::FLAG_OPTION_AVX_W ? OpSize::i64Bit : OpSize::i32Bit;
diff --git a/FEXCore/Source/Interface/IR/IR.json b/FEXCore/Source/Interface/IR/IR.json
index 6161f5049..f1a1e0c97 100644
--- a/FEXCore/Source/Interface/IR/IR.json
+++ b/FEXCore/Source/Interface/IR/IR.json
@@ -1886,7 +1886,7 @@
         "NumElements": "RegisterSize / ElementSize"
       },
 
-      "FPR = LoadNamedVectorConstant u8:#RegisterSize, NamedVectorConstant:$Constant": {
+      "FPR = LoadNamedVectorConstant OpSize:#RegisterSize, NamedVectorConstant:$Constant": {
         "Desc": ["Load a named vector constant.",
                  "The list of vector constants can be found in <FEXCore/IR/IR.h>"
                 ],
diff --git a/FEXCore/Source/Interface/IR/Passes/x87StackOptimizationPass.cpp b/FEXCore/Source/Interface/IR/Passes/x87StackOptimizationPass.cpp
index 2cd3f89bd..aeb5ebf5e 100644
--- a/FEXCore/Source/Interface/IR/Passes/x87StackOptimizationPass.cpp
+++ b/FEXCore/Source/Interface/IR/Passes/x87StackOptimizationPass.cpp
@@ -652,7 +652,7 @@ void X87StackOptimization::Run(IREmitter* Emit) {
         if (ReducedPrecisionMode) {
           OneConst = IREmit->_VCastFromGPR(8, 8, GetConstant(0x3FF0000000000000));
         } else {
-          OneConst = IREmit->_LoadNamedVectorConstant(16, NamedVectorConstant::NAMED_VECTOR_X87_ONE);
+          OneConst = IREmit->_LoadNamedVectorConstant(OpSize::i128Bit, NamedVectorConstant::NAMED_VECTOR_X87_ONE);
         }
 
         if (SlowPath) {