diff --git a/FEXCore/Source/Interface/Core/JIT/Arm64/ALUOps.cpp b/FEXCore/Source/Interface/Core/JIT/Arm64/ALUOps.cpp index 593845449..61cc30469 100644 --- a/FEXCore/Source/Interface/Core/JIT/Arm64/ALUOps.cpp +++ b/FEXCore/Source/Interface/Core/JIT/Arm64/ALUOps.cpp @@ -106,12 +106,18 @@ DEF_OP(AddNZCV) { DEF_OP(TestNZ) { auto Op = IROp->C(); const uint8_t OpSize = Op->Size; - - LOGMAN_THROW_AA_FMT(OpSize == 4 || OpSize == 8, "Unsupported {} size: {}", __func__, OpSize); const auto EmitSize = OpSize == 8 ? ARMEmitter::Size::i64Bit : ARMEmitter::Size::i32Bit; const auto Dst = GetReg(Node); - const auto Src = GetReg(Op->Src1.ID()); + auto Src = GetReg(Op->Src1.ID()); + + // Shift the sign bit into place, clearing out the garbage in upper bits. + // setf+rmif would avoid the scratch register, but higher latency on M1. + if (OpSize < 4) { + lsl(EmitSize, Dst, Src, 32 - (OpSize * 8)); + Src = Dst; + } + tst(EmitSize, Src, Src); // TODO: Optimize this out @@ -1223,7 +1229,9 @@ DEF_OP(Sbfe) { ARMEmitter::Condition MapSelectCC(IR::CondClassType Cond) { switch (Cond.Val) { + case FEXCore::IR::COND_ANDZ: case FEXCore::IR::COND_EQ: return ARMEmitter::Condition::CC_EQ; + case FEXCore::IR::COND_ANDNZ: case FEXCore::IR::COND_NEQ: return ARMEmitter::Condition::CC_NE; case FEXCore::IR::COND_SGE: return ARMEmitter::Condition::CC_GE; case FEXCore::IR::COND_SLT: return ARMEmitter::Condition::CC_LT; @@ -1257,15 +1265,28 @@ DEF_OP(Select) { uint64_t Const; auto cc = MapSelectCC(Op->Cond); + bool tests = Op->Cond == FEXCore::IR::COND_ANDZ || + Op->Cond == FEXCore::IR::COND_ANDNZ; + + LOGMAN_THROW_AA_FMT(!tests || IsGPR(Op->Cmp1.ID()), "Only GPRs can be tested"); if (IsGPR(Op->Cmp1.ID())) { const auto Src1 = GetReg(Op->Cmp1.ID()); - if (IsInlineConstant(Op->Cmp2, &Const)) - cmp(CompareEmitSize, Src1, Const); - else { - const auto Src2 = GetReg(Op->Cmp2.ID()); - cmp(CompareEmitSize, Src1, Src2); + if (tests) { + if (IsInlineConstant(Op->Cmp2, &Const)) + tst(CompareEmitSize, Src1, Const); + else { + const auto Src2 = GetReg(Op->Cmp2.ID()); + tst(CompareEmitSize, Src1, Src2); + } + } else { + if (IsInlineConstant(Op->Cmp2, &Const)) + cmp(CompareEmitSize, Src1, Const); + else { + const auto Src2 = GetReg(Op->Cmp2.ID()); + cmp(CompareEmitSize, Src1, Src2); + } } } else if (IsGPRPair(Op->Cmp1.ID())) { diff --git a/FEXCore/Source/Interface/Core/JIT/Arm64/BranchOps.cpp b/FEXCore/Source/Interface/Core/JIT/Arm64/BranchOps.cpp index ea9ca2fda..34d26fe35 100644 --- a/FEXCore/Source/Interface/Core/JIT/Arm64/BranchOps.cpp +++ b/FEXCore/Source/Interface/Core/JIT/Arm64/BranchOps.cpp @@ -96,7 +96,9 @@ DEF_OP(Jump) { static ARMEmitter::Condition MapBranchCC(IR::CondClassType Cond) { switch (Cond.Val) { + case FEXCore::IR::COND_ANDZ: case FEXCore::IR::COND_EQ: return ARMEmitter::Condition::CC_EQ; + case FEXCore::IR::COND_ANDNZ: case FEXCore::IR::COND_NEQ: return ARMEmitter::Condition::CC_NE; case FEXCore::IR::COND_SGE: return ARMEmitter::Condition::CC_GE; case FEXCore::IR::COND_SLT: return ARMEmitter::Condition::CC_LT; @@ -129,6 +131,8 @@ DEF_OP(CondJump) { uint64_t Const; const bool isConst = IsInlineConstant(Op->Cmp2, &Const); + bool tests = Op->Cond == FEXCore::IR::COND_ANDZ || + Op->Cond == FEXCore::IR::COND_ANDNZ; const auto Size = Op->CompareSize == 4 ? ARMEmitter::Size::i32Bit : ARMEmitter::Size::i64Bit; const auto SubSize = ARMEmitter::ToVectorSizePair(Op->CompareSize == 4 ? ARMEmitter::SubRegSize::i32Bit : ARMEmitter::SubRegSize::i64Bit); @@ -141,10 +145,18 @@ DEF_OP(CondJump) { cbnz(Size, GetReg(Op->Cmp1.ID()), TrueTargetLabel); } else { if (IsGPR(Op->Cmp1.ID())) { - if (isConst) { - cmp(Size, GetReg(Op->Cmp1.ID()), Const); + if (tests) { + if (isConst) { + tst(Size, GetReg(Op->Cmp1.ID()), Const); + } else { + tst(Size, GetReg(Op->Cmp1.ID()), GetReg(Op->Cmp2.ID())); + } } else { - cmp(Size, GetReg(Op->Cmp1.ID()), GetReg(Op->Cmp2.ID())); + if (isConst) { + cmp(Size, GetReg(Op->Cmp1.ID()), Const); + } else { + cmp(Size, GetReg(Op->Cmp1.ID()), GetReg(Op->Cmp2.ID())); + } } } else if (IsFPR(Op->Cmp1.ID())) { fcmp(SubSize.Scalar, GetVReg(Op->Cmp1.ID()), GetVReg(Op->Cmp2.ID())); diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp index acf89a2ad..fd602711b 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp @@ -831,6 +831,17 @@ void OpDispatchBuilder::CALLAbsoluteOp(OpcodeArgs) { _ExitFunction(JMPPCOffset); // If we get here then leave the function now } +OrderedNode *OpDispatchBuilder::SelectMask(OrderedNode *Cmp, uint64_t Mask, bool TrueIsNonzero, IR::OpSize ResultSize, OrderedNode *TrueValue, OrderedNode *FalseValue) { + return _Select(ResultSize, OpSize::i32Bit, + TrueIsNonzero ? CondClassType{COND_ANDNZ} : CondClassType{COND_ANDZ}, + Cmp, _Constant(Mask), + TrueValue, FalseValue); +} + +OrderedNode *OpDispatchBuilder::SelectNZCV(unsigned BitOffset, bool TrueIsNonzero, IR::OpSize ResultSize, OrderedNode *TrueValue, OrderedNode *FalseValue) { + return SelectMask(GetNZCV(), 1u << IndexNZCV(BitOffset), TrueIsNonzero, ResultSize, TrueValue, FalseValue); +} + OrderedNode *OpDispatchBuilder::SelectCC(uint8_t OP, IR::OpSize ResultSize, OrderedNode *TrueValue, OrderedNode *FalseValue) { OrderedNode *SrcCond = nullptr; @@ -839,77 +850,56 @@ OrderedNode *OpDispatchBuilder::SelectCC(uint8_t OP, IR::OpSize ResultSize, Orde switch (OP) { case 0x0: { // JO - Jump if OF == 1 - auto Flag = GetRFLAG(FEXCore::X86State::RFLAG_OF_LOC); - SrcCond = _Select(ResultSize, OpSize::i32Bit, CondClassType{COND_NEQ}, - Flag, ZeroConst, TrueValue, FalseValue); + SrcCond = SelectNZCV(FEXCore::X86State::RFLAG_OF_LOC, true, ResultSize, TrueValue, FalseValue); break; } case 0x1:{ // JNO - Jump if OF == 0 - auto Flag = GetRFLAG(FEXCore::X86State::RFLAG_OF_LOC); - SrcCond = _Select(ResultSize, OpSize::i32Bit, CondClassType{COND_EQ}, - Flag, ZeroConst, TrueValue, FalseValue); + SrcCond = SelectNZCV(FEXCore::X86State::RFLAG_OF_LOC, false, ResultSize, TrueValue, FalseValue); break; } case 0x2: { // JC - Jump if CF == 1 - auto Flag = GetRFLAG(FEXCore::X86State::RFLAG_CF_LOC); - SrcCond = _Select(ResultSize, OpSize::i32Bit, CondClassType{COND_NEQ}, - Flag, ZeroConst, TrueValue, FalseValue); + SrcCond = SelectNZCV(FEXCore::X86State::RFLAG_CF_LOC, true, ResultSize, TrueValue, FalseValue); break; } case 0x3: { // JNC - Jump if CF == 0 - auto Flag = GetRFLAG(FEXCore::X86State::RFLAG_CF_LOC); - SrcCond = _Select(ResultSize, OpSize::i32Bit, CondClassType{COND_EQ}, - Flag, ZeroConst, TrueValue, FalseValue); + SrcCond = SelectNZCV(FEXCore::X86State::RFLAG_CF_LOC, false, ResultSize, TrueValue, FalseValue); break; } case 0x4: { // JE - Jump if ZF == 1 - auto Flag = GetRFLAG(FEXCore::X86State::RFLAG_ZF_LOC); - SrcCond = _Select(ResultSize, OpSize::i32Bit, CondClassType{COND_NEQ}, - Flag, ZeroConst, TrueValue, FalseValue); + SrcCond = SelectNZCV(FEXCore::X86State::RFLAG_ZF_LOC, true, ResultSize, TrueValue, FalseValue); break; } case 0x5: { // JNE - Jump if ZF == 0 - auto Flag = GetRFLAG(FEXCore::X86State::RFLAG_ZF_LOC); - SrcCond = _Select(ResultSize, OpSize::i32Bit, CondClassType{COND_EQ}, - Flag, ZeroConst, TrueValue, FalseValue); + SrcCond = SelectNZCV(FEXCore::X86State::RFLAG_ZF_LOC, false, ResultSize, TrueValue, FalseValue); break; } case 0x6: { // JNA - Jump if CF == 1 || ZC == 1 - auto Flag1 = GetRFLAG(FEXCore::X86State::RFLAG_ZF_LOC); - auto Flag2 = GetRFLAG(FEXCore::X86State::RFLAG_CF_LOC); - auto Check = _Or(OpSize::i32Bit, Flag1, Flag2); - SrcCond = _Select(ResultSize, OpSize::i32Bit, CondClassType{COND_EQ}, - Check, OneConst, TrueValue, FalseValue); + SrcCond = SelectMask(GetNZCV(), (1u << IndexNZCV(FEXCore::X86State::RFLAG_CF_LOC)) | + (1u << IndexNZCV(FEXCore::X86State::RFLAG_ZF_LOC)), + true, ResultSize, TrueValue, FalseValue); break; } case 0x7: { // JA - Jump if CF == 0 && ZF == 0 - auto Flag1 = GetRFLAG(FEXCore::X86State::RFLAG_ZF_LOC); - auto Flag2 = GetRFLAG(FEXCore::X86State::RFLAG_CF_LOC); - auto Check = _Or(OpSize::i32Bit, Flag1, Flag2); - SrcCond = _Select(ResultSize, OpSize::i32Bit, CondClassType{COND_EQ}, - Check, ZeroConst, TrueValue, FalseValue); + SrcCond = SelectMask(GetNZCV(), (1u << IndexNZCV(FEXCore::X86State::RFLAG_CF_LOC)) | + (1u << IndexNZCV(FEXCore::X86State::RFLAG_ZF_LOC)), + false, ResultSize, TrueValue, FalseValue); break; } case 0x8: { // JS - Jump if SF == 1 - auto Flag = GetRFLAG(FEXCore::X86State::RFLAG_SF_LOC); - SrcCond = _Select(ResultSize, OpSize::i32Bit, CondClassType{COND_NEQ}, - Flag, ZeroConst, TrueValue, FalseValue); + SrcCond = SelectNZCV(FEXCore::X86State::RFLAG_SF_LOC, true, ResultSize, TrueValue, FalseValue); break; } case 0x9: { // JNS - Jump if SF == 0 - auto Flag = GetRFLAG(FEXCore::X86State::RFLAG_SF_LOC); - SrcCond = _Select(ResultSize, OpSize::i32Bit, CondClassType{COND_EQ}, - Flag, ZeroConst, TrueValue, FalseValue); + SrcCond = SelectNZCV(FEXCore::X86State::RFLAG_SF_LOC, false, ResultSize, TrueValue, FalseValue); break; } case 0xA: { // JP - Jump if PF == 1 - SrcCond = _Select(ResultSize, OpSize::i32Bit, CondClassType{COND_EQ}, - LoadPFInverted(), ZeroConst, TrueValue, FalseValue); + // Raw value contains inverted PF in bottom bit + SrcCond = SelectMask(LoadPFRaw(), 0x1, false, ResultSize, TrueValue, FalseValue); break; } case 0xB: { // JNP - Jump if PF == 0 - SrcCond = _Select(ResultSize, OpSize::i32Bit, CondClassType{COND_NEQ}, - LoadPFInverted(), ZeroConst, TrueValue, FalseValue); + SrcCond = SelectMask(LoadPFRaw(), 0x1, true, ResultSize, TrueValue, FalseValue); break; } case 0xC: { // SF <> OF @@ -927,13 +917,11 @@ OrderedNode *OpDispatchBuilder::SelectCC(uint8_t OP, IR::OpSize ResultSize, Orde break; } case 0xE: {// ZF = 1 || SF <> OF - auto Flag1 = GetRFLAG(FEXCore::X86State::RFLAG_ZF_LOC); + auto Select1 = SelectNZCV(FEXCore::X86State::RFLAG_ZF_LOC, true, OpSize::i32Bit, + OneConst, ZeroConst); + auto Flag2 = GetRFLAG(FEXCore::X86State::RFLAG_SF_LOC); auto Flag3 = GetRFLAG(FEXCore::X86State::RFLAG_OF_LOC); - - auto Select1 = _Select(OpSize::i32Bit, OpSize::i32Bit, CondClassType{COND_EQ}, - Flag1, OneConst, OneConst, ZeroConst); - auto Select2 = _Select(OpSize::i32Bit, OpSize::i32Bit, CondClassType{COND_NEQ}, Flag2, Flag3, OneConst, ZeroConst); @@ -943,13 +931,11 @@ OrderedNode *OpDispatchBuilder::SelectCC(uint8_t OP, IR::OpSize ResultSize, Orde break; } case 0xF: {// ZF = 0 && SF = OF - auto Flag1 = GetRFLAG(FEXCore::X86State::RFLAG_ZF_LOC); + auto Select1 = SelectNZCV(FEXCore::X86State::RFLAG_ZF_LOC, false, OpSize::i32Bit, + OneConst, ZeroConst); + auto Flag2 = GetRFLAG(FEXCore::X86State::RFLAG_SF_LOC); auto Flag3 = GetRFLAG(FEXCore::X86State::RFLAG_OF_LOC); - - auto Select1 = _Select(OpSize::i32Bit, OpSize::i32Bit, CondClassType{COND_EQ}, - Flag1, ZeroConst, OneConst, ZeroConst); - auto Select2 = _Select(OpSize::i32Bit, OpSize::i32Bit, CondClassType{COND_EQ}, Flag2, Flag3, OneConst, ZeroConst); diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher.h b/FEXCore/Source/Interface/Core/OpcodeDispatcher.h index fc2f370c7..237438263 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher.h +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher.h @@ -1137,45 +1137,10 @@ private: SetNZCV(_And(OpSize::i32Bit, OldNZCV, _Constant(PossiblySetNZCVBits))); } - void SetN_ZeroZCV(unsigned SrcSize, OrderedNode *Res) { - static_assert(IndexNZCV(FEXCore::X86State::RFLAG_SF_LOC) == 31); - - unsigned NBit = 31; - unsigned SignBit = (SrcSize * 8) - 1; - - OrderedNode *Shifted; - - // Shift the sign bit into the N bit - if (SignBit > NBit) - Shifted = _Ashr(OpSize::i64Bit, Res, _Constant(SignBit - NBit)); - else if (SignBit < NBit) - Shifted = _Lshl(OpSize::i32Bit, Res, _Constant(NBit - SignBit)); - else - Shifted = Res; - - // Mask off just the N bit, which now equals the sign bit - CachedNZCV = _And(OpSize::i32Bit, Shifted, _Constant(1u << NBit)); - PossiblySetNZCVBits = (1u << NBit); - NZCVDirty = true; - } - void SetNZ_ZeroCV(unsigned SrcSize, OrderedNode *Res) { - // The TestNZ opcode does this operation natively for 32-bit or 64-bit. - // Otherwise we can implement the functionality ourselves with some bit math. - if (SrcSize >= 4) { - CachedNZCV = _TestNZ(SrcSize, Res); - PossiblySetNZCVBits = (1u << 31) | (1u << 30); - NZCVDirty = true; - } else { - // N - SetN_ZeroZCV(SrcSize, Res); - - // Z - auto Zero = _Constant(0); - auto One = _Constant(1); - auto SelectOp = _Select(FEXCore::IR::COND_EQ, Res, Zero, One, Zero); - SetRFLAG(SelectOp); - } + CachedNZCV = _TestNZ(SrcSize, Res); + PossiblySetNZCVBits = (1u << 31) | (1u << 30); + NZCVDirty = true; } OrderedNode *InsertNZCV(OrderedNode *NZCV, unsigned BitOffset, OrderedNode *Value) { @@ -1280,6 +1245,8 @@ private: CachedIndexedNamedVectorConstants.clear(); } + OrderedNode *SelectMask(OrderedNode *Cmp, uint64_t Mask, bool Invert, IR::OpSize ResultSize, OrderedNode *TrueValue, OrderedNode *FalseValue); + OrderedNode *SelectNZCV(unsigned BitOffset, bool Invert, IR::OpSize ResultSize, OrderedNode *TrueValue, OrderedNode *FalseValue); OrderedNode *SelectCC(uint8_t OP, IR::OpSize ResultSize, OrderedNode *TrueValue, OrderedNode *FalseValue); /** @@ -1386,7 +1353,7 @@ private: * @name These functions are used by the deferred flag handling while it is calculating and storing flags in to RFLAGs. * @{ */ OrderedNode *LoadPF(); - OrderedNode *LoadPFInverted(); + OrderedNode *LoadPFRaw(); OrderedNode *LoadAF(); void FixupAF(); void CalculatePF(OrderedNode *Res, OrderedNode *condition = nullptr); diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher/Flags.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher/Flags.cpp index c91923feb..3f17e37ba 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher/Flags.cpp +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher/Flags.cpp @@ -209,7 +209,7 @@ void OpDispatchBuilder::CalculateOF_Add(uint8_t SrcSize, OrderedNode *Res, Order SetRFLAG(AndOp1); } -OrderedNode *OpDispatchBuilder::LoadPFInverted() { +OrderedNode *OpDispatchBuilder::LoadPFRaw() { // Read the stored byte. This is the original 8-bit result, it needs parity calculated. auto PFByte = GetRFLAG(FEXCore::X86State::RFLAG_PF_LOC); @@ -219,14 +219,15 @@ OrderedNode *OpDispatchBuilder::LoadPFInverted() { // Calculate the popcount. auto Count = _VPopcount(1, 1, InputFPR); - auto Parity = _VExtractToGPR(8, 1, Count, 0); - - // Mask off the bottom bit only. - return _And(OpSize::i64Bit, Parity, _Constant(1)); + return _VExtractToGPR(8, 1, Count, 0); } OrderedNode *OpDispatchBuilder::LoadPF() { - return _Xor(OpSize::i32Bit, LoadPFInverted(), _Constant(1)); + // Mask off the bottom bit only. + OrderedNode *Bit = _And(OpSize::i64Bit, LoadPFRaw(), _Constant(1)); + + // Invert + return _Xor(OpSize::i32Bit, Bit, _Constant(1)); } OrderedNode *OpDispatchBuilder::LoadAF() { @@ -269,6 +270,14 @@ void OpDispatchBuilder::CalculatePF(OrderedNode *Res, OrderedNode *condition) { } void OpDispatchBuilder::CalculateAF(OpSize OpSize, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2) { + // We only care about bit 4 in the subsequent XOR. If we'll XOR with 0, + // there's no sense XOR'ing at all. This affects INC. + uint64_t Const; + if (IsValueConstant(WrapNode(Src2), &Const) && (Const & (1u << 4)) == 0) { + SetRFLAG(Src1); + return; + } + // We store the XOR of the arguments. At read time, we XOR with the // appropriate bit of the result (available as the PF flag) and extract the // appropriate bit. diff --git a/FEXCore/Source/Interface/IR/IR.json b/FEXCore/Source/Interface/IR/IR.json index 2e0e84c49..9ad4d1f49 100644 --- a/FEXCore/Source/Interface/IR/IR.json +++ b/FEXCore/Source/Interface/IR/IR.json @@ -67,6 +67,8 @@ "constexpr uint8_t COND_SLT = 11", "constexpr uint8_t COND_SGT = 12", "constexpr uint8_t COND_SLE = 13", + "constexpr uint8_t COND_ANDZ = 14 /* (a & b) == 0 */", + "constexpr uint8_t COND_ANDNZ = 15 /* (a & b) != 0 */", "constexpr uint8_t COND_FLU = 16 /* float less or unordred */", "constexpr uint8_t COND_FGE = 17 /* float greater or equal */", diff --git a/FEXCore/Source/Interface/IR/IRDumper.cpp b/FEXCore/Source/Interface/IR/IRDumper.cpp index 41fa90c81..a634859f3 100644 --- a/FEXCore/Source/Interface/IR/IRDumper.cpp +++ b/FEXCore/Source/Interface/IR/IRDumper.cpp @@ -59,8 +59,8 @@ static void PrintArg(fextl::stringstream *out, [[maybe_unused]] IRListView const "SLT", "SGT", "SLE", - "Invalid Cond", - "Invalid Cond", + "ANDZ", + "ANDNZ", "FLU", "FGE", "FLEU", diff --git a/FEXCore/Source/Interface/IR/IRParser.cpp b/FEXCore/Source/Interface/IR/IRParser.cpp index bd15e51dd..bb68bdc7d 100644 --- a/FEXCore/Source/Interface/IR/IRParser.cpp +++ b/FEXCore/Source/Interface/IR/IRParser.cpp @@ -210,8 +210,8 @@ class IRParser: public FEXCore::IR::IREmitter { "SLT", "SGT", "SLE", - "Invalid Cond", - "Invalid Cond", + "ANDZ", + "ANDNZ", "FLU", "FGE", "FLEU", diff --git a/FEXCore/Source/Interface/IR/Passes/ConstProp.cpp b/FEXCore/Source/Interface/IR/Passes/ConstProp.cpp index 822d84cc1..2a249d660 100644 --- a/FEXCore/Source/Interface/IR/Passes/ConstProp.cpp +++ b/FEXCore/Source/Interface/IR/Passes/ConstProp.cpp @@ -1087,9 +1087,12 @@ bool ConstProp::ConstantInlining(IREmitter *IREmit, const IRListView& CurrentIR) { auto Op = IROp->C(); + bool Bitwise = Op->Cond == COND_ANDZ || + Op->Cond == COND_ANDNZ; + uint64_t Constant1{}; if (IREmit->IsValueConstant(Op->Header.Args[1], &Constant1)) { - if (IsImmAddSub(Constant1)) { + if (Bitwise ? IsImmLogical(Constant1, IROp->Size * 8) : IsImmAddSub(Constant1)) { IREmit->SetWriteCursor(CurrentIR.GetNode(Op->Header.Args[1])); IREmit->ReplaceNodeArgument(CodeNode, 1, CreateInlineConstant(IREmit, Constant1)); diff --git a/unittests/InstructionCountCI/Primary.json b/unittests/InstructionCountCI/Primary.json index 433e3bcb5..814f2ea34 100644 --- a/unittests/InstructionCountCI/Primary.json +++ b/unittests/InstructionCountCI/Primary.json @@ -9,7 +9,7 @@ }, "Instructions": { "add bl, cl": { - "ExpectedInstructionCount": 22, + "ExpectedInstructionCount": 20, "Optimal": "No", "Comment": "0x00", "ExpectedArm64ASM": [ @@ -22,10 +22,8 @@ "strb w23, [x28, #708]", "strb w22, [x28, #706]", "lsl w23, w22, #24", - "and w23, w23, #0x80000000", - "cmp x22, #0x0 (0)", - "cset x24, eq", - "orr w23, w23, w24, lsl #30", + "tst w23, w23", + "mrs x23, nzcv", "cmp w22, w20", "cset x24, lo", "orr w23, w23, w24, lsl #29", @@ -38,7 +36,7 @@ ] }, "add bx, cx": { - "ExpectedInstructionCount": 22, + "ExpectedInstructionCount": 20, "Optimal": "No", "Comment": "0x01", "ExpectedArm64ASM": [ @@ -51,10 +49,8 @@ "strb w23, [x28, #708]", "strb w22, [x28, #706]", "lsl w23, w22, #16", - "and w23, w23, #0x80000000", - "cmp x22, #0x0 (0)", - "cset x24, eq", - "orr w23, w23, w24, lsl #30", + "tst w23, w23", + "mrs x23, nzcv", "cmp w22, w20", "cset x24, lo", "orr w23, w23, w24, lsl #29", @@ -98,7 +94,7 @@ ] }, "db 0x02, 0xcb": { - "ExpectedInstructionCount": 22, + "ExpectedInstructionCount": 20, "Optimal": "No", "Comment": [ "0x02", @@ -114,10 +110,8 @@ "strb w23, [x28, #708]", "strb w22, [x28, #706]", "lsl w23, w22, #24", - "and w23, w23, #0x80000000", - "cmp x22, #0x0 (0)", - "cset x24, eq", - "orr w23, w23, w24, lsl #30", + "tst w23, w23", + "mrs x23, nzcv", "cmp w22, w20", "cset x24, lo", "orr w23, w23, w24, lsl #29", @@ -130,7 +124,7 @@ ] }, "db 0x66, 0x03, 0xcb": { - "ExpectedInstructionCount": 22, + "ExpectedInstructionCount": 20, "Optimal": "No", "Comment": [ "0x03", @@ -146,10 +140,8 @@ "strb w23, [x28, #708]", "strb w22, [x28, #706]", "lsl w23, w22, #16", - "and w23, w23, #0x80000000", - "cmp x22, #0x0 (0)", - "cset x24, eq", - "orr w23, w23, w24, lsl #30", + "tst w23, w23", + "mrs x23, nzcv", "cmp w22, w20", "cset x24, lo", "orr w23, w23, w24, lsl #29", @@ -199,7 +191,7 @@ ] }, "add al, 1": { - "ExpectedInstructionCount": 21, + "ExpectedInstructionCount": 18, "Optimal": "No", "Comment": "0x04", "ExpectedArm64ASM": [ @@ -207,14 +199,11 @@ "add w21, w20, #0x1 (1)", "bfxil x4, x21, #0, #8", "uxtb w21, w21", - "eor w22, w20, #0x1", - "strb w22, [x28, #708]", + "strb w20, [x28, #708]", "strb w21, [x28, #706]", "lsl w22, w21, #24", - "and w22, w22, #0x80000000", - "cmp x21, #0x0 (0)", - "cset x23, eq", - "orr w22, w22, w23, lsl #30", + "tst w22, w22", + "mrs x22, nzcv", "cmp w21, #0x1 (1)", "cset x23, lo", "orr w22, w22, w23, lsl #29", @@ -227,7 +216,7 @@ ] }, "add ax, 1": { - "ExpectedInstructionCount": 21, + "ExpectedInstructionCount": 18, "Optimal": "No", "Comment": "0x05", "ExpectedArm64ASM": [ @@ -235,14 +224,11 @@ "add w21, w20, #0x1 (1)", "bfxil x4, x21, #0, #16", "uxth w21, w21", - "eor w22, w20, #0x1", - "strb w22, [x28, #708]", + "strb w20, [x28, #708]", "strb w21, [x28, #706]", "lsl w22, w21, #16", - "and w22, w22, #0x80000000", - "cmp x21, #0x0 (0)", - "cset x23, eq", - "orr w22, w22, w23, lsl #30", + "tst w22, w22", + "mrs x22, nzcv", "cmp w21, #0x1 (1)", "cset x23, lo", "orr w22, w22, w23, lsl #29", @@ -255,14 +241,13 @@ ] }, "add eax, 1": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 7, "Optimal": "No", "Comment": "0x05", "ExpectedArm64ASM": [ "mov w20, w4", "add w4, w20, #0x1 (1)", - "eor w21, w20, #0x1", - "strb w21, [x28, #708]", + "strb w20, [x28, #708]", "strb w4, [x28, #706]", "cmn w20, #0x1 (1)", "mrs x20, nzcv", @@ -270,14 +255,13 @@ ] }, "add rax, 1": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 7, "Optimal": "No", "Comment": "0x05", "ExpectedArm64ASM": [ "mov x20, x4", "add x4, x20, #0x1 (1)", - "eor x21, x20, #0x1", - "strb w21, [x28, #708]", + "strb w20, [x28, #708]", "strb w4, [x28, #706]", "cmn x20, #0x1 (1)", "mrs x20, nzcv", @@ -285,7 +269,7 @@ ] }, "or bl, cl": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 9, "Optimal": "No", "Comment": "0x08", "ExpectedArm64ASM": [ @@ -294,16 +278,14 @@ "orr w20, w21, w20", "bfxil x7, x20, #0, #8", "strb w20, [x28, #706]", - "lsl w21, w20, #24", - "and w21, w21, #0x80000000", - "cmp x20, #0x0 (0)", - "cset x20, eq", - "orr w20, w21, w20, lsl #30", + "lsl w20, w20, #24", + "tst w20, w20", + "mrs x20, nzcv", "str w20, [x28, #728]" ] }, "or bx, cx": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 9, "Optimal": "No", "Comment": "0x09", "ExpectedArm64ASM": [ @@ -312,11 +294,9 @@ "orr w20, w21, w20", "bfxil x7, x20, #0, #16", "strb w20, [x28, #706]", - "lsl w21, w20, #16", - "and w21, w21, #0x80000000", - "cmp x20, #0x0 (0)", - "cset x20, eq", - "orr w20, w21, w20, lsl #30", + "lsl w20, w20, #16", + "tst w20, w20", + "mrs x20, nzcv", "str w20, [x28, #728]" ] }, @@ -347,7 +327,7 @@ ] }, "db 0x0A, 0xcb": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 9, "Optimal": "No", "Comment": [ "0x0A", @@ -359,16 +339,14 @@ "orr w20, w21, w20", "bfxil x5, x20, #0, #8", "strb w20, [x28, #706]", - "lsl w21, w20, #24", - "and w21, w21, #0x80000000", - "cmp x20, #0x0 (0)", - "cset x20, eq", - "orr w20, w21, w20, lsl #30", + "lsl w20, w20, #24", + "tst w20, w20", + "mrs x20, nzcv", "str w20, [x28, #728]" ] }, "db 0x66, 0x0B, 0xcb": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 9, "Optimal": "No", "Comment": [ "0x0B", @@ -380,11 +358,9 @@ "orr w20, w21, w20", "bfxil x5, x20, #0, #16", "strb w20, [x28, #706]", - "lsl w21, w20, #16", - "and w21, w21, #0x80000000", - "cmp x20, #0x0 (0)", - "cset x20, eq", - "orr w20, w21, w20, lsl #30", + "lsl w20, w20, #16", + "tst w20, w20", + "mrs x20, nzcv", "str w20, [x28, #728]" ] }, @@ -421,7 +397,7 @@ ] }, "or al, 1": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 8, "Optimal": "No", "Comment": "0x0C", "ExpectedArm64ASM": [ @@ -429,16 +405,14 @@ "orr w20, w20, #0x1", "bfxil x4, x20, #0, #8", "strb w20, [x28, #706]", - "lsl w21, w20, #24", - "and w21, w21, #0x80000000", - "cmp x20, #0x0 (0)", - "cset x20, eq", - "orr w20, w21, w20, lsl #30", + "lsl w20, w20, #24", + "tst w20, w20", + "mrs x20, nzcv", "str w20, [x28, #728]" ] }, "or ax, 1": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 8, "Optimal": "No", "Comment": "0x0D", "ExpectedArm64ASM": [ @@ -446,11 +420,9 @@ "orr w20, w20, #0x1", "bfxil x4, x20, #0, #16", "strb w20, [x28, #706]", - "lsl w21, w20, #16", - "and w21, w21, #0x80000000", - "cmp x20, #0x0 (0)", - "cset x20, eq", - "orr w20, w21, w20, lsl #30", + "lsl w20, w20, #16", + "tst w20, w20", + "mrs x20, nzcv", "str w20, [x28, #728]" ] }, @@ -480,7 +452,7 @@ ] }, "adc bl, cl": { - "ExpectedInstructionCount": 29, + "ExpectedInstructionCount": 27, "Optimal": "No", "Comment": "0x10", "ExpectedArm64ASM": [ @@ -496,10 +468,8 @@ "strb w24, [x28, #708]", "strb w22, [x28, #706]", "lsl w24, w22, #24", - "and w24, w24, #0x80000000", - "cmp x22, #0x0 (0)", - "cset x25, eq", - "orr w24, w24, w25, lsl #30", + "tst w24, w24", + "mrs x24, nzcv", "cmp w22, w20", "cset x25, lo", "cmp w22, w20", @@ -516,7 +486,7 @@ ] }, "adc bx, cx": { - "ExpectedInstructionCount": 29, + "ExpectedInstructionCount": 27, "Optimal": "No", "Comment": "0x11", "ExpectedArm64ASM": [ @@ -532,10 +502,8 @@ "strb w24, [x28, #708]", "strb w22, [x28, #706]", "lsl w24, w22, #16", - "and w24, w24, #0x80000000", - "cmp x22, #0x0 (0)", - "cset x25, eq", - "orr w24, w24, w25, lsl #30", + "tst w24, w24", + "mrs x24, nzcv", "cmp w22, w20", "cset x25, lo", "cmp w22, w20", @@ -613,7 +581,7 @@ ] }, "db 0x12, 0xcb": { - "ExpectedInstructionCount": 29, + "ExpectedInstructionCount": 27, "Optimal": "No", "Comment": [ "0x12", @@ -632,10 +600,8 @@ "strb w24, [x28, #708]", "strb w22, [x28, #706]", "lsl w24, w22, #24", - "and w24, w24, #0x80000000", - "cmp x22, #0x0 (0)", - "cset x25, eq", - "orr w24, w24, w25, lsl #30", + "tst w24, w24", + "mrs x24, nzcv", "cmp w22, w20", "cset x25, lo", "cmp w22, w20", @@ -652,7 +618,7 @@ ] }, "db 0x66, 0x13, 0xcb": { - "ExpectedInstructionCount": 29, + "ExpectedInstructionCount": 27, "Optimal": "No", "Comment": [ "0x13", @@ -671,10 +637,8 @@ "strb w24, [x28, #708]", "strb w22, [x28, #706]", "lsl w24, w22, #16", - "and w24, w24, #0x80000000", - "cmp x22, #0x0 (0)", - "cset x25, eq", - "orr w24, w24, w25, lsl #30", + "tst w24, w24", + "mrs x24, nzcv", "cmp w22, w20", "cset x25, lo", "cmp w22, w20", @@ -758,7 +722,7 @@ ] }, "adc al, 1": { - "ExpectedInstructionCount": 29, + "ExpectedInstructionCount": 26, "Optimal": "No", "Comment": "0x14", "ExpectedArm64ASM": [ @@ -770,14 +734,11 @@ "add w20, w22, w20", "bfxil x4, x20, #0, #8", "uxtb w20, w20", - "eor w23, w22, #0x1", - "strb w23, [x28, #708]", + "strb w22, [x28, #708]", "strb w20, [x28, #706]", "lsl w23, w20, #24", - "and w23, w23, #0x80000000", - "cmp x20, #0x0 (0)", - "cset x24, eq", - "orr w23, w23, w24, lsl #30", + "tst w23, w23", + "mrs x23, nzcv", "cmp w20, #0x1 (1)", "cset x24, lo", "cmp w20, #0x1 (1)", @@ -794,7 +755,7 @@ ] }, "adc ax, 1": { - "ExpectedInstructionCount": 29, + "ExpectedInstructionCount": 26, "Optimal": "No", "Comment": "0x15", "ExpectedArm64ASM": [ @@ -806,14 +767,11 @@ "add w20, w22, w20", "bfxil x4, x20, #0, #16", "uxth w20, w20", - "eor w23, w22, #0x1", - "strb w23, [x28, #708]", + "strb w22, [x28, #708]", "strb w20, [x28, #706]", "lsl w23, w20, #16", - "and w23, w23, #0x80000000", - "cmp x20, #0x0 (0)", - "cset x24, eq", - "orr w23, w23, w24, lsl #30", + "tst w23, w23", + "mrs x23, nzcv", "cmp w20, #0x1 (1)", "cset x24, lo", "cmp w20, #0x1 (1)", @@ -830,7 +788,7 @@ ] }, "adc eax, 1": { - "ExpectedInstructionCount": 24, + "ExpectedInstructionCount": 23, "Optimal": "No", "Comment": "0x15", "ExpectedArm64ASM": [ @@ -840,8 +798,7 @@ "add w20, w20, w21", "mov w22, w4", "add w4, w22, w20", - "eor w20, w22, #0x1", - "strb w20, [x28, #708]", + "strb w22, [x28, #708]", "strb w4, [x28, #706]", "tst w4, w4", "mrs x20, nzcv", @@ -861,7 +818,7 @@ ] }, "adc rax, 1": { - "ExpectedInstructionCount": 24, + "ExpectedInstructionCount": 23, "Optimal": "No", "Comment": "0x15", "ExpectedArm64ASM": [ @@ -871,8 +828,7 @@ "add x20, x20, x21", "mov x22, x4", "add x4, x22, x20", - "eor x20, x22, #0x1", - "strb w20, [x28, #708]", + "strb w22, [x28, #708]", "strb w4, [x28, #706]", "tst x4, x4", "mrs x20, nzcv", @@ -892,7 +848,7 @@ ] }, "sbb bl, cl": { - "ExpectedInstructionCount": 29, + "ExpectedInstructionCount": 27, "Optimal": "No", "Comment": "0x18", "ExpectedArm64ASM": [ @@ -908,10 +864,8 @@ "strb w24, [x28, #708]", "strb w22, [x28, #706]", "lsl w24, w22, #24", - "and w24, w24, #0x80000000", - "cmp x22, #0x0 (0)", - "cset x25, eq", - "orr w24, w24, w25, lsl #30", + "tst w24, w24", + "mrs x24, nzcv", "cmp w22, w23", "cset x25, hi", "cmp w22, w23", @@ -928,7 +882,7 @@ ] }, "sbb bx, cx": { - "ExpectedInstructionCount": 29, + "ExpectedInstructionCount": 27, "Optimal": "No", "Comment": "0x19", "ExpectedArm64ASM": [ @@ -944,10 +898,8 @@ "strb w24, [x28, #708]", "strb w22, [x28, #706]", "lsl w24, w22, #16", - "and w24, w24, #0x80000000", - "cmp x22, #0x0 (0)", - "cset x25, eq", - "orr w24, w24, w25, lsl #30", + "tst w24, w24", + "mrs x24, nzcv", "cmp w22, w23", "cset x25, hi", "cmp w22, w23", @@ -1025,7 +977,7 @@ ] }, "db 0x1A, 0xcb": { - "ExpectedInstructionCount": 29, + "ExpectedInstructionCount": 27, "Optimal": "No", "Comment": [ "0x1A", @@ -1044,10 +996,8 @@ "strb w24, [x28, #708]", "strb w22, [x28, #706]", "lsl w24, w22, #24", - "and w24, w24, #0x80000000", - "cmp x22, #0x0 (0)", - "cset x25, eq", - "orr w24, w24, w25, lsl #30", + "tst w24, w24", + "mrs x24, nzcv", "cmp w22, w23", "cset x25, hi", "cmp w22, w23", @@ -1064,7 +1014,7 @@ ] }, "db 0x66, 0x1B, 0xcb": { - "ExpectedInstructionCount": 29, + "ExpectedInstructionCount": 27, "Optimal": "No", "Comment": [ "0x1B", @@ -1083,10 +1033,8 @@ "strb w24, [x28, #708]", "strb w22, [x28, #706]", "lsl w24, w22, #16", - "and w24, w24, #0x80000000", - "cmp x22, #0x0 (0)", - "cset x25, eq", - "orr w24, w24, w25, lsl #30", + "tst w24, w24", + "mrs x24, nzcv", "cmp w22, w23", "cset x25, hi", "cmp w22, w23", @@ -1170,7 +1118,7 @@ ] }, "sbb al, 1": { - "ExpectedInstructionCount": 29, + "ExpectedInstructionCount": 26, "Optimal": "No", "Comment": "0x1C", "ExpectedArm64ASM": [ @@ -1182,14 +1130,11 @@ "sub w20, w22, w20", "bfxil x4, x20, #0, #8", "uxtb w20, w20", - "eor w23, w22, #0x1", - "strb w23, [x28, #708]", + "strb w22, [x28, #708]", "strb w20, [x28, #706]", "lsl w23, w20, #24", - "and w23, w23, #0x80000000", - "cmp x20, #0x0 (0)", - "cset x24, eq", - "orr w23, w23, w24, lsl #30", + "tst w23, w23", + "mrs x23, nzcv", "cmp w20, w22", "cset x24, hi", "cmp w20, w22", @@ -1206,7 +1151,7 @@ ] }, "sbb ax, 1": { - "ExpectedInstructionCount": 29, + "ExpectedInstructionCount": 26, "Optimal": "No", "Comment": "0x1D", "ExpectedArm64ASM": [ @@ -1218,14 +1163,11 @@ "sub w20, w22, w20", "bfxil x4, x20, #0, #16", "uxth w20, w20", - "eor w23, w22, #0x1", - "strb w23, [x28, #708]", + "strb w22, [x28, #708]", "strb w20, [x28, #706]", "lsl w23, w20, #16", - "and w23, w23, #0x80000000", - "cmp x20, #0x0 (0)", - "cset x24, eq", - "orr w23, w23, w24, lsl #30", + "tst w23, w23", + "mrs x23, nzcv", "cmp w20, w22", "cset x24, hi", "cmp w20, w22", @@ -1242,7 +1184,7 @@ ] }, "sbb eax, 1": { - "ExpectedInstructionCount": 24, + "ExpectedInstructionCount": 23, "Optimal": "No", "Comment": "0x1D", "ExpectedArm64ASM": [ @@ -1252,8 +1194,7 @@ "add w20, w20, w21", "mov w22, w4", "sub w4, w22, w20", - "eor w20, w22, #0x1", - "strb w20, [x28, #708]", + "strb w22, [x28, #708]", "strb w4, [x28, #706]", "tst w4, w4", "mrs x20, nzcv", @@ -1273,7 +1214,7 @@ ] }, "sbb rax, 1": { - "ExpectedInstructionCount": 24, + "ExpectedInstructionCount": 23, "Optimal": "No", "Comment": "0x1D", "ExpectedArm64ASM": [ @@ -1283,8 +1224,7 @@ "add x20, x20, x21", "mov x22, x4", "sub x4, x22, x20", - "eor x20, x22, #0x1", - "strb w20, [x28, #708]", + "strb w22, [x28, #708]", "strb w4, [x28, #706]", "tst x4, x4", "mrs x20, nzcv", @@ -1304,7 +1244,7 @@ ] }, "and bl, cl": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 9, "Optimal": "No", "Comment": "0x20", "ExpectedArm64ASM": [ @@ -1313,16 +1253,14 @@ "and w20, w21, w20", "bfxil x7, x20, #0, #8", "strb w20, [x28, #706]", - "lsl w21, w20, #24", - "and w21, w21, #0x80000000", - "cmp x20, #0x0 (0)", - "cset x20, eq", - "orr w20, w21, w20, lsl #30", + "lsl w20, w20, #24", + "tst w20, w20", + "mrs x20, nzcv", "str w20, [x28, #728]" ] }, "and bx, cx": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 9, "Optimal": "No", "Comment": "0x21", "ExpectedArm64ASM": [ @@ -1331,11 +1269,9 @@ "and w20, w21, w20", "bfxil x7, x20, #0, #16", "strb w20, [x28, #706]", - "lsl w21, w20, #16", - "and w21, w21, #0x80000000", - "cmp x20, #0x0 (0)", - "cset x20, eq", - "orr w20, w21, w20, lsl #30", + "lsl w20, w20, #16", + "tst w20, w20", + "mrs x20, nzcv", "str w20, [x28, #728]" ] }, @@ -1366,7 +1302,7 @@ ] }, "db 0x22, 0xcb": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 9, "Optimal": "No", "Comment": [ "0x22", @@ -1378,16 +1314,14 @@ "and w20, w21, w20", "bfxil x5, x20, #0, #8", "strb w20, [x28, #706]", - "lsl w21, w20, #24", - "and w21, w21, #0x80000000", - "cmp x20, #0x0 (0)", - "cset x20, eq", - "orr w20, w21, w20, lsl #30", + "lsl w20, w20, #24", + "tst w20, w20", + "mrs x20, nzcv", "str w20, [x28, #728]" ] }, "db 0x66, 0x23, 0xcb": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 9, "Optimal": "No", "Comment": [ "0x23", @@ -1399,11 +1333,9 @@ "and w20, w21, w20", "bfxil x5, x20, #0, #16", "strb w20, [x28, #706]", - "lsl w21, w20, #16", - "and w21, w21, #0x80000000", - "cmp x20, #0x0 (0)", - "cset x20, eq", - "orr w20, w21, w20, lsl #30", + "lsl w20, w20, #16", + "tst w20, w20", + "mrs x20, nzcv", "str w20, [x28, #728]" ] }, @@ -1440,7 +1372,7 @@ ] }, "and al, 1": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 8, "Optimal": "No", "Comment": "0x24", "ExpectedArm64ASM": [ @@ -1448,16 +1380,14 @@ "and w20, w20, #0x1", "bfxil x4, x20, #0, #8", "strb w20, [x28, #706]", - "lsl w21, w20, #24", - "and w21, w21, #0x80000000", - "cmp x20, #0x0 (0)", - "cset x20, eq", - "orr w20, w21, w20, lsl #30", + "lsl w20, w20, #24", + "tst w20, w20", + "mrs x20, nzcv", "str w20, [x28, #728]" ] }, "and ax, 1": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 8, "Optimal": "No", "Comment": "0x25", "ExpectedArm64ASM": [ @@ -1465,11 +1395,9 @@ "and w20, w20, #0x1", "bfxil x4, x20, #0, #16", "strb w20, [x28, #706]", - "lsl w21, w20, #16", - "and w21, w21, #0x80000000", - "cmp x20, #0x0 (0)", - "cset x20, eq", - "orr w20, w21, w20, lsl #30", + "lsl w20, w20, #16", + "tst w20, w20", + "mrs x20, nzcv", "str w20, [x28, #728]" ] }, @@ -1499,7 +1427,7 @@ ] }, "sub bl, cl": { - "ExpectedInstructionCount": 22, + "ExpectedInstructionCount": 20, "Optimal": "No", "Comment": "0x28", "ExpectedArm64ASM": [ @@ -1512,10 +1440,8 @@ "strb w23, [x28, #708]", "strb w22, [x28, #706]", "lsl w23, w22, #24", - "and w23, w23, #0x80000000", - "cmp x22, #0x0 (0)", - "cset x24, eq", - "orr w23, w23, w24, lsl #30", + "tst w23, w23", + "mrs x23, nzcv", "cmp w21, w20", "cset x24, lo", "orr w23, w23, w24, lsl #29", @@ -1528,7 +1454,7 @@ ] }, "sub bx, cx": { - "ExpectedInstructionCount": 22, + "ExpectedInstructionCount": 20, "Optimal": "No", "Comment": "0x29", "ExpectedArm64ASM": [ @@ -1541,10 +1467,8 @@ "strb w23, [x28, #708]", "strb w22, [x28, #706]", "lsl w23, w22, #16", - "and w23, w23, #0x80000000", - "cmp x22, #0x0 (0)", - "cset x24, eq", - "orr w23, w23, w24, lsl #30", + "tst w23, w23", + "mrs x23, nzcv", "cmp w21, w20", "cset x24, lo", "orr w23, w23, w24, lsl #29", @@ -1590,7 +1514,7 @@ ] }, "db 0x2A, 0xcb": { - "ExpectedInstructionCount": 22, + "ExpectedInstructionCount": 20, "Optimal": "No", "Comment": [ "0x2A", @@ -1606,10 +1530,8 @@ "strb w23, [x28, #708]", "strb w22, [x28, #706]", "lsl w23, w22, #24", - "and w23, w23, #0x80000000", - "cmp x22, #0x0 (0)", - "cset x24, eq", - "orr w23, w23, w24, lsl #30", + "tst w23, w23", + "mrs x23, nzcv", "cmp w21, w20", "cset x24, lo", "orr w23, w23, w24, lsl #29", @@ -1622,7 +1544,7 @@ ] }, "db 0x66, 0x2B, 0xcb": { - "ExpectedInstructionCount": 22, + "ExpectedInstructionCount": 20, "Optimal": "No", "Comment": [ "0x2B", @@ -1638,10 +1560,8 @@ "strb w23, [x28, #708]", "strb w22, [x28, #706]", "lsl w23, w22, #16", - "and w23, w23, #0x80000000", - "cmp x22, #0x0 (0)", - "cset x24, eq", - "orr w23, w23, w24, lsl #30", + "tst w23, w23", + "mrs x23, nzcv", "cmp w21, w20", "cset x24, lo", "orr w23, w23, w24, lsl #29", @@ -1693,7 +1613,7 @@ ] }, "sub al, 1": { - "ExpectedInstructionCount": 21, + "ExpectedInstructionCount": 18, "Optimal": "No", "Comment": "0x2C", "ExpectedArm64ASM": [ @@ -1701,14 +1621,11 @@ "sub w21, w20, #0x1 (1)", "bfxil x4, x21, #0, #8", "uxtb w21, w21", - "eor w22, w20, #0x1", - "strb w22, [x28, #708]", + "strb w20, [x28, #708]", "strb w21, [x28, #706]", "lsl w22, w21, #24", - "and w22, w22, #0x80000000", - "cmp x21, #0x0 (0)", - "cset x23, eq", - "orr w22, w22, w23, lsl #30", + "tst w22, w22", + "mrs x22, nzcv", "cmp w20, #0x1 (1)", "cset x23, lo", "orr w22, w22, w23, lsl #29", @@ -1721,7 +1638,7 @@ ] }, "sub ax, 1": { - "ExpectedInstructionCount": 21, + "ExpectedInstructionCount": 18, "Optimal": "No", "Comment": "0x2D", "ExpectedArm64ASM": [ @@ -1729,14 +1646,11 @@ "sub w21, w20, #0x1 (1)", "bfxil x4, x21, #0, #16", "uxth w21, w21", - "eor w22, w20, #0x1", - "strb w22, [x28, #708]", + "strb w20, [x28, #708]", "strb w21, [x28, #706]", "lsl w22, w21, #16", - "and w22, w22, #0x80000000", - "cmp x21, #0x0 (0)", - "cset x23, eq", - "orr w22, w22, w23, lsl #30", + "tst w22, w22", + "mrs x22, nzcv", "cmp w20, #0x1 (1)", "cset x23, lo", "orr w22, w22, w23, lsl #29", @@ -1749,14 +1663,13 @@ ] }, "sub eax, 1": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 8, "Optimal": "No", "Comment": "0x2D", "ExpectedArm64ASM": [ "mov w20, w4", "sub w4, w20, #0x1 (1)", - "eor w21, w20, #0x1", - "strb w21, [x28, #708]", + "strb w20, [x28, #708]", "strb w4, [x28, #706]", "cmp w20, #0x1 (1)", "mrs x20, nzcv", @@ -1765,14 +1678,13 @@ ] }, "sub rax, 1": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 8, "Optimal": "No", "Comment": "0x2D", "ExpectedArm64ASM": [ "mov x20, x4", "sub x4, x20, #0x1 (1)", - "eor x21, x20, #0x1", - "strb w21, [x28, #708]", + "strb w20, [x28, #708]", "strb w4, [x28, #706]", "cmp x20, #0x1 (1)", "mrs x20, nzcv", @@ -1781,7 +1693,7 @@ ] }, "xor bl, cl": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 9, "Optimal": "No", "Comment": "0x30", "ExpectedArm64ASM": [ @@ -1790,16 +1702,14 @@ "eor w20, w21, w20", "bfxil x7, x20, #0, #8", "strb w20, [x28, #706]", - "lsl w21, w20, #24", - "and w21, w21, #0x80000000", - "cmp x20, #0x0 (0)", - "cset x20, eq", - "orr w20, w21, w20, lsl #30", + "lsl w20, w20, #24", + "tst w20, w20", + "mrs x20, nzcv", "str w20, [x28, #728]" ] }, "xor bx, cx": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 9, "Optimal": "No", "Comment": "0x31", "ExpectedArm64ASM": [ @@ -1808,11 +1718,9 @@ "eor w20, w21, w20", "bfxil x7, x20, #0, #16", "strb w20, [x28, #706]", - "lsl w21, w20, #16", - "and w21, w21, #0x80000000", - "cmp x20, #0x0 (0)", - "cset x20, eq", - "orr w20, w21, w20, lsl #30", + "lsl w20, w20, #16", + "tst w20, w20", + "mrs x20, nzcv", "str w20, [x28, #728]" ] }, @@ -1843,7 +1751,7 @@ ] }, "db 0x32, 0xcb": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 9, "Optimal": "No", "Comment": [ "0x32", @@ -1855,16 +1763,14 @@ "eor w20, w21, w20", "bfxil x5, x20, #0, #8", "strb w20, [x28, #706]", - "lsl w21, w20, #24", - "and w21, w21, #0x80000000", - "cmp x20, #0x0 (0)", - "cset x20, eq", - "orr w20, w21, w20, lsl #30", + "lsl w20, w20, #24", + "tst w20, w20", + "mrs x20, nzcv", "str w20, [x28, #728]" ] }, "db 0x66, 0x33, 0xcb": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 9, "Optimal": "No", "Comment": [ "0x33", @@ -1876,11 +1782,9 @@ "eor w20, w21, w20", "bfxil x5, x20, #0, #16", "strb w20, [x28, #706]", - "lsl w21, w20, #16", - "and w21, w21, #0x80000000", - "cmp x20, #0x0 (0)", - "cset x20, eq", - "orr w20, w21, w20, lsl #30", + "lsl w20, w20, #16", + "tst w20, w20", + "mrs x20, nzcv", "str w20, [x28, #728]" ] }, @@ -1917,7 +1821,7 @@ ] }, "xor al, 1": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 8, "Optimal": "No", "Comment": "0x34", "ExpectedArm64ASM": [ @@ -1925,16 +1829,14 @@ "eor w20, w20, #0x1", "bfxil x4, x20, #0, #8", "strb w20, [x28, #706]", - "lsl w21, w20, #24", - "and w21, w21, #0x80000000", - "cmp x20, #0x0 (0)", - "cset x20, eq", - "orr w20, w21, w20, lsl #30", + "lsl w20, w20, #24", + "tst w20, w20", + "mrs x20, nzcv", "str w20, [x28, #728]" ] }, "xor ax, 1": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 8, "Optimal": "No", "Comment": "0x35", "ExpectedArm64ASM": [ @@ -1942,11 +1844,9 @@ "eor w20, w20, #0x1", "bfxil x4, x20, #0, #16", "strb w20, [x28, #706]", - "lsl w21, w20, #16", - "and w21, w21, #0x80000000", - "cmp x20, #0x0 (0)", - "cset x20, eq", - "orr w20, w21, w20, lsl #30", + "lsl w20, w20, #16", + "tst w20, w20", + "mrs x20, nzcv", "str w20, [x28, #728]" ] }, @@ -1976,7 +1876,7 @@ ] }, "cmp bl, cl": { - "ExpectedInstructionCount": 21, + "ExpectedInstructionCount": 19, "Optimal": "No", "Comment": "0x38", "ExpectedArm64ASM": [ @@ -1988,10 +1888,8 @@ "strb w23, [x28, #708]", "strb w22, [x28, #706]", "lsl w23, w22, #24", - "and w23, w23, #0x80000000", - "cmp x22, #0x0 (0)", - "cset x24, eq", - "orr w23, w23, w24, lsl #30", + "tst w23, w23", + "mrs x23, nzcv", "cmp w21, w20", "cset x24, lo", "orr w23, w23, w24, lsl #29", @@ -2004,7 +1902,7 @@ ] }, "cmp bx, cx": { - "ExpectedInstructionCount": 21, + "ExpectedInstructionCount": 19, "Optimal": "No", "Comment": "0x39", "ExpectedArm64ASM": [ @@ -2016,10 +1914,8 @@ "strb w23, [x28, #708]", "strb w22, [x28, #706]", "lsl w23, w22, #16", - "and w23, w23, #0x80000000", - "cmp x22, #0x0 (0)", - "cset x24, eq", - "orr w23, w23, w24, lsl #30", + "tst w23, w23", + "mrs x23, nzcv", "cmp w21, w20", "cset x24, lo", "orr w23, w23, w24, lsl #29", @@ -2064,7 +1960,7 @@ ] }, "db 0x3A, 0xcb": { - "ExpectedInstructionCount": 21, + "ExpectedInstructionCount": 19, "Optimal": "No", "Comment": [ "0x3A", @@ -2079,10 +1975,8 @@ "strb w23, [x28, #708]", "strb w22, [x28, #706]", "lsl w23, w22, #24", - "and w23, w23, #0x80000000", - "cmp x22, #0x0 (0)", - "cset x24, eq", - "orr w23, w23, w24, lsl #30", + "tst w23, w23", + "mrs x23, nzcv", "cmp w21, w20", "cset x24, lo", "orr w23, w23, w24, lsl #29", @@ -2095,7 +1989,7 @@ ] }, "db 0x66, 0x3B, 0xcb": { - "ExpectedInstructionCount": 21, + "ExpectedInstructionCount": 19, "Optimal": "No", "Comment": [ "0x3B", @@ -2110,10 +2004,8 @@ "strb w23, [x28, #708]", "strb w22, [x28, #706]", "lsl w23, w22, #16", - "and w23, w23, #0x80000000", - "cmp x22, #0x0 (0)", - "cset x24, eq", - "orr w23, w23, w24, lsl #30", + "tst w23, w23", + "mrs x23, nzcv", "cmp w21, w20", "cset x24, lo", "orr w23, w23, w24, lsl #29", @@ -2164,21 +2056,18 @@ ] }, "cmp al, 1": { - "ExpectedInstructionCount": 20, + "ExpectedInstructionCount": 17, "Optimal": "No", "Comment": "0x3C", "ExpectedArm64ASM": [ "uxtb w20, w4", "sub w21, w20, #0x1 (1)", "uxtb w21, w21", - "eor w22, w20, #0x1", - "strb w22, [x28, #708]", + "strb w20, [x28, #708]", "strb w21, [x28, #706]", "lsl w22, w21, #24", - "and w22, w22, #0x80000000", - "cmp x21, #0x0 (0)", - "cset x23, eq", - "orr w22, w22, w23, lsl #30", + "tst w22, w22", + "mrs x22, nzcv", "cmp w20, #0x1 (1)", "cset x23, lo", "orr w22, w22, w23, lsl #29", @@ -2191,21 +2080,18 @@ ] }, "cmp ax, 1": { - "ExpectedInstructionCount": 20, + "ExpectedInstructionCount": 17, "Optimal": "No", "Comment": "0x3D", "ExpectedArm64ASM": [ "uxth w20, w4", "sub w21, w20, #0x1 (1)", "uxth w21, w21", - "eor w22, w20, #0x1", - "strb w22, [x28, #708]", + "strb w20, [x28, #708]", "strb w21, [x28, #706]", "lsl w22, w21, #16", - "and w22, w22, #0x80000000", - "cmp x21, #0x0 (0)", - "cset x23, eq", - "orr w22, w22, w23, lsl #30", + "tst w22, w22", + "mrs x22, nzcv", "cmp w20, #0x1 (1)", "cset x23, lo", "orr w22, w22, w23, lsl #29", @@ -2218,14 +2104,13 @@ ] }, "cmp eax, 1": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 8, "Optimal": "No", "Comment": "0x3D", "ExpectedArm64ASM": [ "mov w20, w4", "sub w21, w20, #0x1 (1)", - "eor w22, w20, #0x1", - "strb w22, [x28, #708]", + "strb w20, [x28, #708]", "strb w21, [x28, #706]", "cmp w20, #0x1 (1)", "mrs x20, nzcv", @@ -2234,13 +2119,12 @@ ] }, "cmp rax, 1": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 7, "Optimal": "Yes", "Comment": "0x3D", "ExpectedArm64ASM": [ "sub x20, x4, #0x1 (1)", - "eor x21, x4, #0x1", - "strb w21, [x28, #708]", + "strb w4, [x28, #708]", "strb w20, [x28, #706]", "cmp x4, #0x1 (1)", "mrs x20, nzcv", @@ -2447,7 +2331,7 @@ ] }, "test al, bl": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 8, "Optimal": "No", "Comment": "0x84", "ExpectedArm64ASM": [ @@ -2455,16 +2339,14 @@ "uxtb w21, w4", "and w20, w21, w20", "strb w20, [x28, #706]", - "lsl w21, w20, #24", - "and w21, w21, #0x80000000", - "cmp x20, #0x0 (0)", - "cset x20, eq", - "orr w20, w21, w20, lsl #30", + "lsl w20, w20, #24", + "tst w20, w20", + "mrs x20, nzcv", "str w20, [x28, #728]" ] }, "test ax, bx": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 8, "Optimal": "No", "Comment": "0x84", "ExpectedArm64ASM": [ @@ -2472,11 +2354,9 @@ "uxth w21, w4", "and w20, w21, w20", "strb w20, [x28, #706]", - "lsl w21, w20, #16", - "and w21, w21, #0x80000000", - "cmp x20, #0x0 (0)", - "cset x20, eq", - "orr w20, w21, w20, lsl #30", + "lsl w20, w20, #16", + "tst w20, w20", + "mrs x20, nzcv", "str w20, [x28, #728]" ] }, @@ -3573,7 +3453,7 @@ ] }, "cmpsb": { - "ExpectedInstructionCount": 28, + "ExpectedInstructionCount": 26, "Optimal": "No", "Comment": [ "Direction flag increment/decrement location can be made with a single sbfx", @@ -3595,10 +3475,8 @@ "strb w23, [x28, #708]", "strb w22, [x28, #706]", "lsl w23, w22, #24", - "and w23, w23, #0x80000000", - "cmp x22, #0x0 (0)", - "cset x24, eq", - "orr w23, w23, w24, lsl #30", + "tst w23, w23", + "mrs x23, nzcv", "cmp w21, w20", "cset x24, lo", "orr w23, w23, w24, lsl #29", @@ -3611,7 +3489,7 @@ ] }, "cmpsw": { - "ExpectedInstructionCount": 28, + "ExpectedInstructionCount": 26, "Optimal": "No", "Comment": [ "Direction flag increment/decrement location can be made with a tst+mov+csel triple", @@ -3633,10 +3511,8 @@ "strb w23, [x28, #708]", "strb w22, [x28, #706]", "lsl w23, w22, #16", - "and w23, w23, #0x80000000", - "cmp x22, #0x0 (0)", - "cset x24, eq", - "orr w23, w23, w24, lsl #30", + "tst w23, w23", + "mrs x23, nzcv", "cmp w21, w20", "cset x24, lo", "orr w23, w23, w24, lsl #29", @@ -3703,7 +3579,7 @@ ] }, "repz cmpsb": { - "ExpectedInstructionCount": 32, + "ExpectedInstructionCount": 30, "Optimal": "No", "Comment": "0xa6", "ExpectedArm64ASM": [ @@ -3712,7 +3588,7 @@ "mov x22, #0xffffffffffffffff", "cmp x20, #0x0 (0)", "csel x20, x21, x22, eq", - "cbz x5, #+0x6c", + "cbz x5, #+0x64", "ldrb w21, [x11]", "ldrb w22, [x10]", "sub w23, w22, w21", @@ -3721,10 +3597,8 @@ "strb w24, [x28, #708]", "strb w23, [x28, #706]", "lsl w24, w23, #24", - "and w24, w24, #0x80000000", - "cmp x23, #0x0 (0)", - "cset x25, eq", - "orr w24, w24, w25, lsl #30", + "tst w24, w24", + "mrs x24, nzcv", "cmp w22, w21", "cset x25, lo", "orr w24, w24, w25, lsl #29", @@ -3738,11 +3612,11 @@ "add x11, x11, x20", "add x10, x10, x20", "ubfx w21, w21, #30, #1", - "cbnz w21, #-0x68" + "cbnz w21, #-0x60" ] }, "repz cmpsw": { - "ExpectedInstructionCount": 32, + "ExpectedInstructionCount": 30, "Optimal": "No", "Comment": "0xa7", "ExpectedArm64ASM": [ @@ -3751,7 +3625,7 @@ "mov x22, #0xfffffffffffffffe", "cmp x20, #0x0 (0)", "csel x20, x21, x22, eq", - "cbz x5, #+0x6c", + "cbz x5, #+0x64", "ldrh w21, [x11]", "ldrh w22, [x10]", "sub w23, w22, w21", @@ -3760,10 +3634,8 @@ "strb w24, [x28, #708]", "strb w23, [x28, #706]", "lsl w24, w23, #16", - "and w24, w24, #0x80000000", - "cmp x23, #0x0 (0)", - "cset x25, eq", - "orr w24, w24, w25, lsl #30", + "tst w24, w24", + "mrs x24, nzcv", "cmp w22, w21", "cset x25, lo", "orr w24, w24, w25, lsl #29", @@ -3777,7 +3649,7 @@ "add x11, x11, x20", "add x10, x10, x20", "ubfx w21, w21, #30, #1", - "cbnz w21, #-0x68" + "cbnz w21, #-0x60" ] }, "repz cmpsd": { @@ -3837,7 +3709,7 @@ ] }, "repnz cmpsb": { - "ExpectedInstructionCount": 32, + "ExpectedInstructionCount": 30, "Optimal": "No", "Comment": "0xa6", "ExpectedArm64ASM": [ @@ -3846,7 +3718,7 @@ "mov x22, #0xffffffffffffffff", "cmp x20, #0x0 (0)", "csel x20, x21, x22, eq", - "cbz x5, #+0x6c", + "cbz x5, #+0x64", "ldrb w21, [x11]", "ldrb w22, [x10]", "sub w23, w22, w21", @@ -3855,10 +3727,8 @@ "strb w24, [x28, #708]", "strb w23, [x28, #706]", "lsl w24, w23, #24", - "and w24, w24, #0x80000000", - "cmp x23, #0x0 (0)", - "cset x25, eq", - "orr w24, w24, w25, lsl #30", + "tst w24, w24", + "mrs x24, nzcv", "cmp w22, w21", "cset x25, lo", "orr w24, w24, w25, lsl #29", @@ -3872,11 +3742,11 @@ "add x11, x11, x20", "add x10, x10, x20", "ubfx w21, w21, #30, #1", - "cbz w21, #-0x68" + "cbz w21, #-0x60" ] }, "repnz cmpsw": { - "ExpectedInstructionCount": 32, + "ExpectedInstructionCount": 30, "Optimal": "No", "Comment": "0xa7", "ExpectedArm64ASM": [ @@ -3885,7 +3755,7 @@ "mov x22, #0xfffffffffffffffe", "cmp x20, #0x0 (0)", "csel x20, x21, x22, eq", - "cbz x5, #+0x6c", + "cbz x5, #+0x64", "ldrh w21, [x11]", "ldrh w22, [x10]", "sub w23, w22, w21", @@ -3894,10 +3764,8 @@ "strb w24, [x28, #708]", "strb w23, [x28, #706]", "lsl w24, w23, #16", - "and w24, w24, #0x80000000", - "cmp x23, #0x0 (0)", - "cset x25, eq", - "orr w24, w24, w25, lsl #30", + "tst w24, w24", + "mrs x24, nzcv", "cmp w22, w21", "cset x25, lo", "orr w24, w24, w25, lsl #29", @@ -3911,7 +3779,7 @@ "add x11, x11, x20", "add x10, x10, x20", "ubfx w21, w21, #30, #1", - "cbz w21, #-0x68" + "cbz w21, #-0x60" ] }, "repnz cmpsd": { @@ -3971,34 +3839,30 @@ ] }, "test al, 1": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 7, "Optimal": "No", "Comment": "0xa8", "ExpectedArm64ASM": [ "uxtb w20, w4", "and w20, w20, #0x1", "strb w20, [x28, #706]", - "lsl w21, w20, #24", - "and w21, w21, #0x80000000", - "cmp x20, #0x0 (0)", - "cset x20, eq", - "orr w20, w21, w20, lsl #30", + "lsl w20, w20, #24", + "tst w20, w20", + "mrs x20, nzcv", "str w20, [x28, #728]" ] }, "test ax, 1": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 7, "Optimal": "No", "Comment": "0xa9", "ExpectedArm64ASM": [ "uxth w20, w4", "and w20, w20, #0x1", "strb w20, [x28, #706]", - "lsl w21, w20, #16", - "and w21, w21, #0x80000000", - "cmp x20, #0x0 (0)", - "cset x20, eq", - "orr w20, w21, w20, lsl #30", + "lsl w20, w20, #16", + "tst w20, w20", + "mrs x20, nzcv", "str w20, [x28, #728]" ] }, @@ -4314,7 +4178,7 @@ ] }, "scasb": { - "ExpectedInstructionCount": 27, + "ExpectedInstructionCount": 25, "Optimal": "No", "Comment": "0xae", "ExpectedArm64ASM": [ @@ -4332,10 +4196,8 @@ "strb w23, [x28, #708]", "strb w22, [x28, #706]", "lsl w23, w22, #24", - "and w23, w23, #0x80000000", - "cmp x22, #0x0 (0)", - "cset x24, eq", - "orr w23, w23, w24, lsl #30", + "tst w23, w23", + "mrs x23, nzcv", "cmp w20, w21", "cset x24, lo", "orr w23, w23, w24, lsl #29", @@ -4348,7 +4210,7 @@ ] }, "scasw": { - "ExpectedInstructionCount": 27, + "ExpectedInstructionCount": 25, "Optimal": "No", "Comment": "0xaf", "ExpectedArm64ASM": [ @@ -4366,10 +4228,8 @@ "strb w23, [x28, #708]", "strb w22, [x28, #706]", "lsl w23, w22, #16", - "and w23, w23, #0x80000000", - "cmp x22, #0x0 (0)", - "cset x24, eq", - "orr w23, w23, w24, lsl #30", + "tst w23, w23", + "mrs x23, nzcv", "cmp w20, w21", "cset x24, lo", "orr w23, w23, w24, lsl #29", @@ -4427,7 +4287,7 @@ ] }, "repz scasb": { - "ExpectedInstructionCount": 31, + "ExpectedInstructionCount": 29, "Optimal": "No", "Comment": "0xae", "ExpectedArm64ASM": [ @@ -4436,7 +4296,7 @@ "ldrb w22, [x28, #714]", "cmp x22, #0x0 (0)", "csel x20, x20, x21, eq", - "cbz x5, #+0x68", + "cbz x5, #+0x60", "uxtb w21, w4", "ldrb w22, [x11]", "sub w23, w21, w22", @@ -4445,10 +4305,8 @@ "strb w24, [x28, #708]", "strb w23, [x28, #706]", "lsl w24, w23, #24", - "and w24, w24, #0x80000000", - "cmp x23, #0x0 (0)", - "cset x25, eq", - "orr w24, w24, w25, lsl #30", + "tst w24, w24", + "mrs x24, nzcv", "cmp w21, w22", "cset x25, lo", "orr w24, w24, w25, lsl #29", @@ -4461,11 +4319,11 @@ "sub x5, x5, #0x1 (1)", "add x11, x11, x20", "ubfx w21, w21, #30, #1", - "cbnz w21, #-0x64" + "cbnz w21, #-0x5c" ] }, "repz scasw": { - "ExpectedInstructionCount": 31, + "ExpectedInstructionCount": 29, "Optimal": "No", "Comment": "0xaf", "ExpectedArm64ASM": [ @@ -4474,7 +4332,7 @@ "ldrb w22, [x28, #714]", "cmp x22, #0x0 (0)", "csel x20, x20, x21, eq", - "cbz x5, #+0x68", + "cbz x5, #+0x60", "uxth w21, w4", "ldrh w22, [x11]", "sub w23, w21, w22", @@ -4483,10 +4341,8 @@ "strb w24, [x28, #708]", "strb w23, [x28, #706]", "lsl w24, w23, #16", - "and w24, w24, #0x80000000", - "cmp x23, #0x0 (0)", - "cset x25, eq", - "orr w24, w24, w25, lsl #30", + "tst w24, w24", + "mrs x24, nzcv", "cmp w21, w22", "cset x25, lo", "orr w24, w24, w25, lsl #29", @@ -4499,7 +4355,7 @@ "sub x5, x5, #0x1 (1)", "add x11, x11, x20", "ubfx w21, w21, #30, #1", - "cbnz w21, #-0x64" + "cbnz w21, #-0x5c" ] }, "repz scasd": { @@ -4556,7 +4412,7 @@ ] }, "repnz scasb": { - "ExpectedInstructionCount": 31, + "ExpectedInstructionCount": 29, "Optimal": "No", "Comment": "0xae", "ExpectedArm64ASM": [ @@ -4565,7 +4421,7 @@ "ldrb w22, [x28, #714]", "cmp x22, #0x0 (0)", "csel x20, x20, x21, eq", - "cbz x5, #+0x68", + "cbz x5, #+0x60", "uxtb w21, w4", "ldrb w22, [x11]", "sub w23, w21, w22", @@ -4574,10 +4430,8 @@ "strb w24, [x28, #708]", "strb w23, [x28, #706]", "lsl w24, w23, #24", - "and w24, w24, #0x80000000", - "cmp x23, #0x0 (0)", - "cset x25, eq", - "orr w24, w24, w25, lsl #30", + "tst w24, w24", + "mrs x24, nzcv", "cmp w21, w22", "cset x25, lo", "orr w24, w24, w25, lsl #29", @@ -4590,11 +4444,11 @@ "sub x5, x5, #0x1 (1)", "add x11, x11, x20", "ubfx w21, w21, #30, #1", - "cbz w21, #-0x64" + "cbz w21, #-0x5c" ] }, "repnz scasw": { - "ExpectedInstructionCount": 31, + "ExpectedInstructionCount": 29, "Optimal": "No", "Comment": "0xaf", "ExpectedArm64ASM": [ @@ -4603,7 +4457,7 @@ "ldrb w22, [x28, #714]", "cmp x22, #0x0 (0)", "csel x20, x20, x21, eq", - "cbz x5, #+0x68", + "cbz x5, #+0x60", "uxth w21, w4", "ldrh w22, [x11]", "sub w23, w21, w22", @@ -4612,10 +4466,8 @@ "strb w24, [x28, #708]", "strb w23, [x28, #706]", "lsl w24, w23, #16", - "and w24, w24, #0x80000000", - "cmp x23, #0x0 (0)", - "cset x25, eq", - "orr w24, w24, w25, lsl #30", + "tst w24, w24", + "mrs x24, nzcv", "cmp w21, w22", "cset x25, lo", "orr w24, w24, w25, lsl #29", @@ -4628,7 +4480,7 @@ "sub x5, x5, #0x1 (1)", "add x11, x11, x20", "ubfx w21, w21, #30, #1", - "cbz w21, #-0x64" + "cbz w21, #-0x5c" ] }, "repnz scasd": { diff --git a/unittests/InstructionCountCI/PrimaryGroup.json b/unittests/InstructionCountCI/PrimaryGroup.json index 99da8c8a7..b97e8daa2 100644 --- a/unittests/InstructionCountCI/PrimaryGroup.json +++ b/unittests/InstructionCountCI/PrimaryGroup.json @@ -13,7 +13,7 @@ ], "Instructions": { "add al, 1": { - "ExpectedInstructionCount": 21, + "ExpectedInstructionCount": 18, "Optimal": "No", "Comment": "GROUP1 0x80 /0", "ExpectedArm64ASM": [ @@ -21,14 +21,11 @@ "add w21, w20, #0x1 (1)", "bfxil x4, x21, #0, #8", "uxtb w21, w21", - "eor w22, w20, #0x1", - "strb w22, [x28, #708]", + "strb w20, [x28, #708]", "strb w21, [x28, #706]", "lsl w22, w21, #24", - "and w22, w22, #0x80000000", - "cmp x21, #0x0 (0)", - "cset x23, eq", - "orr w22, w22, w23, lsl #30", + "tst w22, w22", + "mrs x22, nzcv", "cmp w21, #0x1 (1)", "cset x23, lo", "orr w22, w22, w23, lsl #29", @@ -41,7 +38,7 @@ ] }, "or al, 1": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 8, "Optimal": "No", "Comment": "GROUP1 0x80 /1", "ExpectedArm64ASM": [ @@ -49,16 +46,14 @@ "orr w20, w20, #0x1", "bfxil x4, x20, #0, #8", "strb w20, [x28, #706]", - "lsl w21, w20, #24", - "and w21, w21, #0x80000000", - "cmp x20, #0x0 (0)", - "cset x20, eq", - "orr w20, w21, w20, lsl #30", + "lsl w20, w20, #24", + "tst w20, w20", + "mrs x20, nzcv", "str w20, [x28, #728]" ] }, "adc al, 1": { - "ExpectedInstructionCount": 29, + "ExpectedInstructionCount": 26, "Optimal": "No", "Comment": "GROUP1 0x80 /2", "ExpectedArm64ASM": [ @@ -70,14 +65,11 @@ "add w20, w22, w20", "bfxil x4, x20, #0, #8", "uxtb w20, w20", - "eor w23, w22, #0x1", - "strb w23, [x28, #708]", + "strb w22, [x28, #708]", "strb w20, [x28, #706]", "lsl w23, w20, #24", - "and w23, w23, #0x80000000", - "cmp x20, #0x0 (0)", - "cset x24, eq", - "orr w23, w23, w24, lsl #30", + "tst w23, w23", + "mrs x23, nzcv", "cmp w20, #0x1 (1)", "cset x24, lo", "cmp w20, #0x1 (1)", @@ -94,7 +86,7 @@ ] }, "sbb al, 1": { - "ExpectedInstructionCount": 29, + "ExpectedInstructionCount": 26, "Optimal": "No", "Comment": "GROUP1 0x80 /3", "ExpectedArm64ASM": [ @@ -106,14 +98,11 @@ "sub w20, w22, w20", "bfxil x4, x20, #0, #8", "uxtb w20, w20", - "eor w23, w22, #0x1", - "strb w23, [x28, #708]", + "strb w22, [x28, #708]", "strb w20, [x28, #706]", "lsl w23, w20, #24", - "and w23, w23, #0x80000000", - "cmp x20, #0x0 (0)", - "cset x24, eq", - "orr w23, w23, w24, lsl #30", + "tst w23, w23", + "mrs x23, nzcv", "cmp w20, w22", "cset x24, hi", "cmp w20, w22", @@ -130,7 +119,7 @@ ] }, "and al, 1": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 8, "Optimal": "No", "Comment": "GROUP1 0x80 /4", "ExpectedArm64ASM": [ @@ -138,16 +127,14 @@ "and w20, w20, #0x1", "bfxil x4, x20, #0, #8", "strb w20, [x28, #706]", - "lsl w21, w20, #24", - "and w21, w21, #0x80000000", - "cmp x20, #0x0 (0)", - "cset x20, eq", - "orr w20, w21, w20, lsl #30", + "lsl w20, w20, #24", + "tst w20, w20", + "mrs x20, nzcv", "str w20, [x28, #728]" ] }, "sub al, 1": { - "ExpectedInstructionCount": 21, + "ExpectedInstructionCount": 18, "Optimal": "No", "Comment": "GROUP1 0x80 /5", "ExpectedArm64ASM": [ @@ -155,14 +142,11 @@ "sub w21, w20, #0x1 (1)", "bfxil x4, x21, #0, #8", "uxtb w21, w21", - "eor w22, w20, #0x1", - "strb w22, [x28, #708]", + "strb w20, [x28, #708]", "strb w21, [x28, #706]", "lsl w22, w21, #24", - "and w22, w22, #0x80000000", - "cmp x21, #0x0 (0)", - "cset x23, eq", - "orr w22, w22, w23, lsl #30", + "tst w22, w22", + "mrs x22, nzcv", "cmp w20, #0x1 (1)", "cset x23, lo", "orr w22, w22, w23, lsl #29", @@ -175,7 +159,7 @@ ] }, "xor al, 1": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 8, "Optimal": "No", "Comment": "GROUP1 0x80 /6", "ExpectedArm64ASM": [ @@ -183,30 +167,25 @@ "eor w20, w20, #0x1", "bfxil x4, x20, #0, #8", "strb w20, [x28, #706]", - "lsl w21, w20, #24", - "and w21, w21, #0x80000000", - "cmp x20, #0x0 (0)", - "cset x20, eq", - "orr w20, w21, w20, lsl #30", + "lsl w20, w20, #24", + "tst w20, w20", + "mrs x20, nzcv", "str w20, [x28, #728]" ] }, "cmp al, 1": { - "ExpectedInstructionCount": 20, + "ExpectedInstructionCount": 17, "Optimal": "No", "Comment": "GROUP1 0x80 /7", "ExpectedArm64ASM": [ "uxtb w20, w4", "sub w21, w20, #0x1 (1)", "uxtb w21, w21", - "eor w22, w20, #0x1", - "strb w22, [x28, #708]", + "strb w20, [x28, #708]", "strb w21, [x28, #706]", "lsl w22, w21, #24", - "and w22, w22, #0x80000000", - "cmp x21, #0x0 (0)", - "cset x23, eq", - "orr w22, w22, w23, lsl #30", + "tst w22, w22", + "mrs x22, nzcv", "cmp w20, #0x1 (1)", "cset x23, lo", "orr w22, w22, w23, lsl #29", @@ -219,7 +198,7 @@ ] }, "add ax, 256": { - "ExpectedInstructionCount": 21, + "ExpectedInstructionCount": 18, "Optimal": "No", "Comment": "GROUP1 0x81 /0", "ExpectedArm64ASM": [ @@ -227,14 +206,11 @@ "add w21, w20, #0x100 (256)", "bfxil x4, x21, #0, #16", "uxth w21, w21", - "eor w22, w20, #0x100", - "strb w22, [x28, #708]", + "strb w20, [x28, #708]", "strb w21, [x28, #706]", "lsl w22, w21, #16", - "and w22, w22, #0x80000000", - "cmp x21, #0x0 (0)", - "cset x23, eq", - "orr w22, w22, w23, lsl #30", + "tst w22, w22", + "mrs x22, nzcv", "cmp w21, #0x100 (256)", "cset x23, lo", "orr w22, w22, w23, lsl #29", @@ -247,14 +223,13 @@ ] }, "add eax, 256": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 7, "Optimal": "No", "Comment": "GROUP1 0x81 /0", "ExpectedArm64ASM": [ "mov w20, w4", "add w4, w20, #0x100 (256)", - "eor w21, w20, #0x100", - "strb w21, [x28, #708]", + "strb w20, [x28, #708]", "strb w4, [x28, #706]", "cmn w20, #0x100 (256)", "mrs x20, nzcv", @@ -262,14 +237,13 @@ ] }, "add rax, 256": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 7, "Optimal": "Yes", "Comment": "GROUP1 0x81 /0", "ExpectedArm64ASM": [ "mov x20, x4", "add x4, x20, #0x100 (256)", - "eor x21, x20, #0x100", - "strb w21, [x28, #708]", + "strb w20, [x28, #708]", "strb w4, [x28, #706]", "cmn x20, #0x100 (256)", "mrs x20, nzcv", @@ -302,7 +276,7 @@ ] }, "adc eax, 256": { - "ExpectedInstructionCount": 24, + "ExpectedInstructionCount": 23, "Optimal": "No", "Comment": "GROUP1 0x81 /2", "ExpectedArm64ASM": [ @@ -312,8 +286,7 @@ "add w20, w20, w21", "mov w22, w4", "add w4, w22, w20", - "eor w20, w22, #0x100", - "strb w20, [x28, #708]", + "strb w22, [x28, #708]", "strb w4, [x28, #706]", "tst w4, w4", "mrs x20, nzcv", @@ -333,7 +306,7 @@ ] }, "adc rax, 256": { - "ExpectedInstructionCount": 24, + "ExpectedInstructionCount": 23, "Optimal": "No", "Comment": "GROUP1 0x81 /2", "ExpectedArm64ASM": [ @@ -343,8 +316,7 @@ "add x20, x20, x21", "mov x22, x4", "add x4, x22, x20", - "eor x20, x22, #0x100", - "strb w20, [x28, #708]", + "strb w22, [x28, #708]", "strb w4, [x28, #706]", "tst x4, x4", "mrs x20, nzcv", @@ -364,7 +336,7 @@ ] }, "sbb eax, 256": { - "ExpectedInstructionCount": 24, + "ExpectedInstructionCount": 23, "Optimal": "No", "Comment": "GROUP1 0x81 /3", "ExpectedArm64ASM": [ @@ -374,8 +346,7 @@ "add w20, w20, w21", "mov w22, w4", "sub w4, w22, w20", - "eor w20, w22, #0x100", - "strb w20, [x28, #708]", + "strb w22, [x28, #708]", "strb w4, [x28, #706]", "tst w4, w4", "mrs x20, nzcv", @@ -395,7 +366,7 @@ ] }, "sbb rax, 256": { - "ExpectedInstructionCount": 24, + "ExpectedInstructionCount": 23, "Optimal": "No", "Comment": "GROUP1 0x81 /3", "ExpectedArm64ASM": [ @@ -405,8 +376,7 @@ "add x20, x20, x21", "mov x22, x4", "sub x4, x22, x20", - "eor x20, x22, #0x100", - "strb w20, [x28, #708]", + "strb w22, [x28, #708]", "strb w4, [x28, #706]", "tst x4, x4", "mrs x20, nzcv", @@ -451,14 +421,13 @@ ] }, "sub eax, 256": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 8, "Optimal": "No", "Comment": "GROUP1 0x81 /5", "ExpectedArm64ASM": [ "mov w20, w4", "sub w4, w20, #0x100 (256)", - "eor w21, w20, #0x100", - "strb w21, [x28, #708]", + "strb w20, [x28, #708]", "strb w4, [x28, #706]", "cmp w20, #0x100 (256)", "mrs x20, nzcv", @@ -467,14 +436,13 @@ ] }, "sub rax, 256": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 8, "Optimal": "Yes", "Comment": "GROUP1 0x81 /5", "ExpectedArm64ASM": [ "mov x20, x4", "sub x4, x20, #0x100 (256)", - "eor x21, x20, #0x100", - "strb w21, [x28, #708]", + "strb w20, [x28, #708]", "strb w4, [x28, #706]", "cmp x20, #0x100 (256)", "mrs x20, nzcv", @@ -508,14 +476,13 @@ ] }, "cmp eax, 256": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 8, "Optimal": "No", "Comment": "GROUP1 0x81 /7", "ExpectedArm64ASM": [ "mov w20, w4", "sub w21, w20, #0x100 (256)", - "eor w22, w20, #0x100", - "strb w22, [x28, #708]", + "strb w20, [x28, #708]", "strb w21, [x28, #706]", "cmp w20, #0x100 (256)", "mrs x20, nzcv", @@ -524,13 +491,12 @@ ] }, "cmp rax, 256": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 7, "Optimal": "Yes", "Comment": "GROUP1 0x81 /7", "ExpectedArm64ASM": [ "sub x20, x4, #0x100 (256)", - "eor x21, x4, #0x100", - "strb w21, [x28, #708]", + "strb w4, [x28, #708]", "strb w20, [x28, #706]", "cmp x4, #0x100 (256)", "mrs x20, nzcv", @@ -539,7 +505,7 @@ ] }, "add ax, 1": { - "ExpectedInstructionCount": 21, + "ExpectedInstructionCount": 18, "Optimal": "No", "Comment": "GROUP1 0x83 /0", "ExpectedArm64ASM": [ @@ -547,14 +513,11 @@ "add w21, w20, #0x1 (1)", "bfxil x4, x21, #0, #16", "uxth w21, w21", - "eor w22, w20, #0x1", - "strb w22, [x28, #708]", + "strb w20, [x28, #708]", "strb w21, [x28, #706]", "lsl w22, w21, #16", - "and w22, w22, #0x80000000", - "cmp x21, #0x0 (0)", - "cset x23, eq", - "orr w22, w22, w23, lsl #30", + "tst w22, w22", + "mrs x22, nzcv", "cmp w21, #0x1 (1)", "cset x23, lo", "orr w22, w22, w23, lsl #29", @@ -567,14 +530,13 @@ ] }, "add eax, 1": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 7, "Optimal": "No", "Comment": "GROUP1 0x83 /0", "ExpectedArm64ASM": [ "mov w20, w4", "add w4, w20, #0x1 (1)", - "eor w21, w20, #0x1", - "strb w21, [x28, #708]", + "strb w20, [x28, #708]", "strb w4, [x28, #706]", "cmn w20, #0x1 (1)", "mrs x20, nzcv", @@ -582,14 +544,13 @@ ] }, "add rax, 1": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 7, "Optimal": "Yes", "Comment": "GROUP1 0x83 /0", "ExpectedArm64ASM": [ "mov x20, x4", "add x4, x20, #0x1 (1)", - "eor x21, x20, #0x1", - "strb w21, [x28, #708]", + "strb w20, [x28, #708]", "strb w4, [x28, #706]", "cmn x20, #0x1 (1)", "mrs x20, nzcv", @@ -622,7 +583,7 @@ ] }, "adc eax, 1": { - "ExpectedInstructionCount": 24, + "ExpectedInstructionCount": 23, "Optimal": "No", "Comment": "GROUP1 0x83 /2", "ExpectedArm64ASM": [ @@ -632,8 +593,7 @@ "add w20, w20, w21", "mov w22, w4", "add w4, w22, w20", - "eor w20, w22, #0x1", - "strb w20, [x28, #708]", + "strb w22, [x28, #708]", "strb w4, [x28, #706]", "tst w4, w4", "mrs x20, nzcv", @@ -653,7 +613,7 @@ ] }, "adc rax, 1": { - "ExpectedInstructionCount": 24, + "ExpectedInstructionCount": 23, "Optimal": "No", "Comment": "GROUP1 0x83 /2", "ExpectedArm64ASM": [ @@ -663,8 +623,7 @@ "add x20, x20, x21", "mov x22, x4", "add x4, x22, x20", - "eor x20, x22, #0x1", - "strb w20, [x28, #708]", + "strb w22, [x28, #708]", "strb w4, [x28, #706]", "tst x4, x4", "mrs x20, nzcv", @@ -684,7 +643,7 @@ ] }, "sbb eax, 1": { - "ExpectedInstructionCount": 24, + "ExpectedInstructionCount": 23, "Optimal": "No", "Comment": "GROUP1 0x83 /3", "ExpectedArm64ASM": [ @@ -694,8 +653,7 @@ "add w20, w20, w21", "mov w22, w4", "sub w4, w22, w20", - "eor w20, w22, #0x1", - "strb w20, [x28, #708]", + "strb w22, [x28, #708]", "strb w4, [x28, #706]", "tst w4, w4", "mrs x20, nzcv", @@ -715,7 +673,7 @@ ] }, "sbb rax, 1": { - "ExpectedInstructionCount": 24, + "ExpectedInstructionCount": 23, "Optimal": "No", "Comment": "GROUP1 0x83 /3", "ExpectedArm64ASM": [ @@ -725,8 +683,7 @@ "add x20, x20, x21", "mov x22, x4", "sub x4, x22, x20", - "eor x20, x22, #0x1", - "strb w20, [x28, #708]", + "strb w22, [x28, #708]", "strb w4, [x28, #706]", "tst x4, x4", "mrs x20, nzcv", @@ -771,14 +728,13 @@ ] }, "sub eax, 1": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 8, "Optimal": "No", "Comment": "GROUP1 0x83 /5", "ExpectedArm64ASM": [ "mov w20, w4", "sub w4, w20, #0x1 (1)", - "eor w21, w20, #0x1", - "strb w21, [x28, #708]", + "strb w20, [x28, #708]", "strb w4, [x28, #706]", "cmp w20, #0x1 (1)", "mrs x20, nzcv", @@ -787,14 +743,13 @@ ] }, "sub rax, 1": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 8, "Optimal": "No", "Comment": "GROUP1 0x83 /5", "ExpectedArm64ASM": [ "mov x20, x4", "sub x4, x20, #0x1 (1)", - "eor x21, x20, #0x1", - "strb w21, [x28, #708]", + "strb w20, [x28, #708]", "strb w4, [x28, #706]", "cmp x20, #0x1 (1)", "mrs x20, nzcv", @@ -828,14 +783,13 @@ ] }, "cmp eax, 1": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 8, "Optimal": "No", "Comment": "GROUP1 0x83 /7", "ExpectedArm64ASM": [ "mov w20, w4", "sub w21, w20, #0x1 (1)", - "eor w22, w20, #0x1", - "strb w22, [x28, #708]", + "strb w20, [x28, #708]", "strb w21, [x28, #706]", "cmp w20, #0x1 (1)", "mrs x20, nzcv", @@ -844,13 +798,12 @@ ] }, "cmp rax, 1": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 7, "Optimal": "No", "Comment": "GROUP1 0x83 /7", "ExpectedArm64ASM": [ "sub x20, x4, #0x1 (1)", - "eor x21, x4, #0x1", - "strb w21, [x28, #708]", + "strb w4, [x28, #708]", "strb w20, [x28, #706]", "cmp x4, #0x1 (1)", "mrs x20, nzcv", @@ -959,7 +912,7 @@ ] }, "shl al, 2": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 11, "Optimal": "No", "Comment": "GROUP2 0xC0 /4", "ExpectedArm64ASM": [ @@ -968,10 +921,8 @@ "bfxil x4, x21, #0, #8", "uxtb w21, w21", "lsl w22, w21, #24", - "and w22, w22, #0x80000000", - "cmp x21, #0x0 (0)", - "cset x23, eq", - "orr w22, w22, w23, lsl #30", + "tst w22, w22", + "mrs x22, nzcv", "ubfx w20, w20, #6, #1", "orr w20, w22, w20, lsl #29", "strb w21, [x28, #706]", @@ -979,7 +930,7 @@ ] }, "shr al, 2": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 13, "Optimal": "No", "Comment": "GROUP2 0xC0 /5", "ExpectedArm64ASM": [ @@ -989,10 +940,8 @@ "ldr w22, [x28, #728]", "ubfx w22, w22, #28, #1", "lsl w23, w21, #24", - "and w23, w23, #0x80000000", - "cmp x21, #0x0 (0)", - "cset x24, eq", - "orr w23, w23, w24, lsl #30", + "tst w23, w23", + "mrs x23, nzcv", "ubfx w20, w20, #1, #1", "orr w20, w23, w20, lsl #29", "strb w21, [x28, #706]", @@ -1001,7 +950,7 @@ ] }, "sar al, 2": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 11, "Optimal": "No", "Comment": "GROUP2 0xC0 /7", "ExpectedArm64ASM": [ @@ -1010,10 +959,8 @@ "asr x21, x20, #2", "bfxil x4, x21, #0, #8", "lsl w22, w21, #24", - "and w22, w22, #0x80000000", - "cmp x21, #0x0 (0)", - "cset x23, eq", - "orr w22, w22, w23, lsl #30", + "tst w22, w22", + "mrs x22, nzcv", "ubfx x20, x20, #1, #1", "orr w20, w22, w20, lsl #29", "strb w21, [x28, #706]", @@ -1299,7 +1246,7 @@ ] }, "shl ax, 2": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 11, "Optimal": "No", "Comment": "GROUP2 0xC1 /4", "ExpectedArm64ASM": [ @@ -1308,10 +1255,8 @@ "bfxil x4, x21, #0, #16", "uxth w21, w21", "lsl w22, w21, #16", - "and w22, w22, #0x80000000", - "cmp x21, #0x0 (0)", - "cset x23, eq", - "orr w22, w22, w23, lsl #30", + "tst w22, w22", + "mrs x22, nzcv", "ubfx w20, w20, #14, #1", "orr w20, w22, w20, lsl #29", "strb w21, [x28, #706]", @@ -1349,7 +1294,7 @@ ] }, "shr ax, 2": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 13, "Optimal": "No", "Comment": "GROUP2 0xC1 /5", "ExpectedArm64ASM": [ @@ -1359,10 +1304,8 @@ "ldr w22, [x28, #728]", "ubfx w22, w22, #28, #1", "lsl w23, w21, #16", - "and w23, w23, #0x80000000", - "cmp x21, #0x0 (0)", - "cset x24, eq", - "orr w23, w23, w24, lsl #30", + "tst w23, w23", + "mrs x23, nzcv", "ubfx w20, w20, #1, #1", "orr w20, w23, w20, lsl #29", "strb w21, [x28, #706]", @@ -1407,7 +1350,7 @@ ] }, "sar ax, 2": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 11, "Optimal": "No", "Comment": "GROUP2 0xC1 /7", "ExpectedArm64ASM": [ @@ -1416,10 +1359,8 @@ "asr x21, x20, #2", "bfxil x4, x21, #0, #16", "lsl w22, w21, #16", - "and w22, w22, #0x80000000", - "cmp x21, #0x0 (0)", - "cset x23, eq", - "orr w22, w22, w23, lsl #30", + "tst w22, w22", + "mrs x22, nzcv", "ubfx x20, x20, #1, #1", "orr w20, w22, w20, lsl #29", "strb w21, [x28, #706]", @@ -1539,7 +1480,7 @@ ] }, "shl al, 1": { - "ExpectedInstructionCount": 16, + "ExpectedInstructionCount": 14, "Optimal": "No", "Comment": "GROUP2 0xd0 /4", "ExpectedArm64ASM": [ @@ -1548,10 +1489,8 @@ "bfxil x4, x21, #0, #8", "uxtb w21, w21", "lsl w22, w21, #24", - "and w22, w22, #0x80000000", - "cmp x21, #0x0 (0)", - "cset x23, eq", - "orr w22, w22, w23, lsl #30", + "tst w22, w22", + "mrs x22, nzcv", "ubfx w23, w20, #7, #1", "orr w22, w22, w23, lsl #29", "strb w21, [x28, #706]", @@ -1562,7 +1501,7 @@ ] }, "shr al, 1": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 12, "Optimal": "No", "Comment": "GROUP2 0xd0 /5", "ExpectedArm64ASM": [ @@ -1570,10 +1509,8 @@ "lsr w21, w20, #1", "bfxil x4, x21, #0, #8", "lsl w22, w21, #24", - "and w22, w22, #0x80000000", - "cmp x21, #0x0 (0)", - "cset x23, eq", - "orr w22, w22, w23, lsl #30", + "tst w22, w22", + "mrs x22, nzcv", "ubfx w23, w20, #0, #1", "orr w22, w22, w23, lsl #29", "strb w21, [x28, #706]", @@ -1583,7 +1520,7 @@ ] }, "sar al, 1": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 11, "Optimal": "No", "Comment": "GROUP2 0xd0 /7", "ExpectedArm64ASM": [ @@ -1592,10 +1529,8 @@ "asr w21, w20, #1", "bfxil x4, x21, #0, #8", "lsl w22, w21, #24", - "and w22, w22, #0x80000000", - "cmp x21, #0x0 (0)", - "cset x23, eq", - "orr w22, w22, w23, lsl #30", + "tst w22, w22", + "mrs x22, nzcv", "ubfx x20, x20, #0, #1", "orr w20, w22, w20, lsl #29", "strb w21, [x28, #706]", @@ -1828,7 +1763,7 @@ ] }, "shl ax, 1": { - "ExpectedInstructionCount": 16, + "ExpectedInstructionCount": 14, "Optimal": "No", "Comment": "GROUP2 0xd1 /4", "ExpectedArm64ASM": [ @@ -1837,10 +1772,8 @@ "bfxil x4, x21, #0, #16", "uxth w21, w21", "lsl w22, w21, #16", - "and w22, w22, #0x80000000", - "cmp x21, #0x0 (0)", - "cset x23, eq", - "orr w22, w22, w23, lsl #30", + "tst w22, w22", + "mrs x22, nzcv", "ubfx w23, w20, #15, #1", "orr w22, w22, w23, lsl #29", "strb w21, [x28, #706]", @@ -1887,7 +1820,7 @@ ] }, "shr ax, 1": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 12, "Optimal": "No", "Comment": "GROUP2 0xd1 /5", "ExpectedArm64ASM": [ @@ -1895,10 +1828,8 @@ "lsr w21, w20, #1", "bfxil x4, x21, #0, #16", "lsl w22, w21, #16", - "and w22, w22, #0x80000000", - "cmp x21, #0x0 (0)", - "cset x23, eq", - "orr w22, w22, w23, lsl #30", + "tst w22, w22", + "mrs x22, nzcv", "ubfx w23, w20, #0, #1", "orr w22, w22, w23, lsl #29", "strb w21, [x28, #706]", @@ -1942,7 +1873,7 @@ ] }, "sar ax, 1": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 11, "Optimal": "No", "Comment": "GROUP2 0xd1 /7", "ExpectedArm64ASM": [ @@ -1951,10 +1882,8 @@ "asr w21, w20, #1", "bfxil x4, x21, #0, #16", "lsl w22, w21, #16", - "and w22, w22, #0x80000000", - "cmp x21, #0x0 (0)", - "cset x23, eq", - "orr w22, w22, w23, lsl #30", + "tst w22, w22", + "mrs x22, nzcv", "ubfx x20, x20, #0, #1", "orr w20, w22, w20, lsl #29", "strb w21, [x28, #706]", @@ -2119,7 +2048,7 @@ ] }, "shl al, cl": { - "ExpectedInstructionCount": 26, + "ExpectedInstructionCount": 24, "Optimal": "No", "Comment": "GROUP2 0xd2 /4", "ExpectedArm64ASM": [ @@ -2130,10 +2059,8 @@ "uxtb w22, w22", "ldr w23, [x28, #728]", "lsl w24, w22, #24", - "and w24, w24, #0x80000000", - "cmp x22, #0x0 (0)", - "cset x25, eq", - "orr w24, w24, w25, lsl #30", + "tst w24, w24", + "mrs x24, nzcv", "mov w25, #0x8", "sub w25, w25, w21", "lsr w25, w20, w25", @@ -2152,7 +2079,7 @@ ] }, "shr al, cl": { - "ExpectedInstructionCount": 24, + "ExpectedInstructionCount": 22, "Optimal": "No", "Comment": "GROUP2 0xd2 /5", "ExpectedArm64ASM": [ @@ -2162,10 +2089,8 @@ "bfxil x4, x22, #0, #8", "ldr w23, [x28, #728]", "lsl w24, w22, #24", - "and w24, w24, #0x80000000", - "cmp x22, #0x0 (0)", - "cset x25, eq", - "orr w24, w24, w25, lsl #30", + "tst w24, w24", + "mrs x24, nzcv", "sub x25, x21, #0x1 (1)", "lsr w25, w20, w25", "ubfx w25, w25, #0, #1", @@ -2183,7 +2108,7 @@ ] }, "sar al, cl": { - "ExpectedInstructionCount": 22, + "ExpectedInstructionCount": 20, "Optimal": "No", "Comment": "GROUP2 0xd2 /7", "ExpectedArm64ASM": [ @@ -2194,10 +2119,8 @@ "bfxil x4, x22, #0, #8", "ldr w23, [x28, #728]", "lsl w24, w22, #24", - "and w24, w24, #0x80000000", - "cmp x22, #0x0 (0)", - "cset x25, eq", - "orr w24, w24, w25, lsl #30", + "tst w24, w24", + "mrs x24, nzcv", "sub x25, x21, #0x1 (1)", "lsr x20, x20, x25", "ubfx x20, x20, #0, #1", @@ -2578,7 +2501,7 @@ ] }, "shl ax, cl": { - "ExpectedInstructionCount": 26, + "ExpectedInstructionCount": 24, "Optimal": "No", "Comment": "GROUP2 0xd3 /4", "ExpectedArm64ASM": [ @@ -2588,16 +2511,14 @@ "bfxil x4, x22, #0, #16", "uxth w22, w22", "ldr w23, [x28, #728]", - "mov w24, #0x10", - "lsl w25, w22, #16", - "and w25, w25, #0x80000000", - "cmp x22, #0x0 (0)", - "cset x26, eq", - "orr w25, w25, w26, lsl #30", - "sub w24, w24, w21", - "lsr w24, w20, w24", - "ubfx w24, w24, #0, #1", - "orr w24, w25, w24, lsl #29", + "lsl w24, w22, #16", + "tst w24, w24", + "mrs x24, nzcv", + "mov w25, #0x10", + "sub w25, w25, w21", + "lsr w25, w20, w25", + "ubfx w25, w25, #0, #1", + "orr w24, w24, w25, lsl #29", "ldrb w25, [x28, #706]", "cmp x21, #0x0 (0)", "csel w25, w25, w22, eq", @@ -2666,7 +2587,7 @@ ] }, "shr ax, cl": { - "ExpectedInstructionCount": 24, + "ExpectedInstructionCount": 22, "Optimal": "No", "Comment": "GROUP2 0xd3 /5", "ExpectedArm64ASM": [ @@ -2676,10 +2597,8 @@ "bfxil x4, x22, #0, #16", "ldr w23, [x28, #728]", "lsl w24, w22, #16", - "and w24, w24, #0x80000000", - "cmp x22, #0x0 (0)", - "cset x25, eq", - "orr w24, w24, w25, lsl #30", + "tst w24, w24", + "mrs x24, nzcv", "sub x25, x21, #0x1 (1)", "lsr w25, w20, w25", "ubfx w25, w25, #0, #1", @@ -2750,7 +2669,7 @@ ] }, "sar ax, cl": { - "ExpectedInstructionCount": 22, + "ExpectedInstructionCount": 20, "Optimal": "No", "Comment": "GROUP2 0xd3 /7", "ExpectedArm64ASM": [ @@ -2761,10 +2680,8 @@ "bfxil x4, x22, #0, #16", "ldr w23, [x28, #728]", "lsl w24, w22, #16", - "and w24, w24, #0x80000000", - "cmp x22, #0x0 (0)", - "cset x25, eq", - "orr w24, w24, w25, lsl #30", + "tst w24, w24", + "mrs x24, nzcv", "sub x25, x21, #0x1 (1)", "lsr x20, x20, x25", "ubfx x20, x20, #0, #1", @@ -2826,18 +2743,16 @@ ] }, "test bl, 1": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 7, "Optimal": "No", "Comment": "GROUP2 0xf6 /0", "ExpectedArm64ASM": [ "uxtb w20, w7", "and w20, w20, #0x1", "strb w20, [x28, #706]", - "lsl w21, w20, #24", - "and w21, w21, #0x80000000", - "cmp x20, #0x0 (0)", - "cset x20, eq", - "orr w20, w21, w20, lsl #30", + "lsl w20, w20, #24", + "tst w20, w20", + "mrs x20, nzcv", "str w20, [x28, #728]" ] }, @@ -2852,7 +2767,7 @@ ] }, "neg bl": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 17, "Optimal": "No", "Comment": "GROUP2 0xf6 /3", "ExpectedArm64ASM": [ @@ -2864,10 +2779,8 @@ "strb w21, [x28, #708]", "strb w22, [x28, #706]", "lsl w23, w22, #24", - "and w23, w23, #0x80000000", - "cmp x22, #0x0 (0)", - "cset x24, eq", - "orr w23, w23, w24, lsl #30", + "tst w23, w23", + "mrs x23, nzcv", "cmp x20, x21", "cset x20, lo", "orr w20, w23, w20, lsl #29", @@ -2952,18 +2865,16 @@ ] }, "test bx, 1": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 7, "Optimal": "No", "Comment": "GROUP2 0xf7 /0", "ExpectedArm64ASM": [ "uxth w20, w7", "and w20, w20, #0x1", "strb w20, [x28, #706]", - "lsl w21, w20, #16", - "and w21, w21, #0x80000000", - "cmp x20, #0x0 (0)", - "cset x20, eq", - "orr w20, w21, w20, lsl #30", + "lsl w20, w20, #16", + "tst w20, w20", + "mrs x20, nzcv", "str w20, [x28, #728]" ] }, @@ -3022,7 +2933,7 @@ ] }, "neg bx": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 17, "Optimal": "No", "Comment": "GROUP2 0xf7 /2", "ExpectedArm64ASM": [ @@ -3034,10 +2945,8 @@ "strb w21, [x28, #708]", "strb w22, [x28, #706]", "lsl w23, w22, #16", - "and w23, w23, #0x80000000", - "cmp x22, #0x0 (0)", - "cset x24, eq", - "orr w23, w23, w24, lsl #30", + "tst w23, w23", + "mrs x23, nzcv", "cmp x20, x21", "cset x20, lo", "orr w20, w23, w20, lsl #29", @@ -3331,7 +3240,7 @@ ] }, "inc al": { - "ExpectedInstructionCount": 21, + "ExpectedInstructionCount": 18, "Optimal": "No", "Comment": "GROUP3 0xfe /0", "ExpectedArm64ASM": [ @@ -3339,16 +3248,13 @@ "add w21, w20, #0x1 (1)", "bfxil x4, x21, #0, #8", "uxtb w21, w21", - "eor w22, w20, #0x1", - "strb w22, [x28, #708]", + "strb w20, [x28, #708]", "strb w21, [x28, #706]", "ldr w22, [x28, #728]", "ubfx w22, w22, #29, #1", "lsl w23, w21, #24", - "and w23, w23, #0x80000000", - "cmp x21, #0x0 (0)", - "cset x24, eq", - "orr w23, w23, w24, lsl #30", + "tst w23, w23", + "mrs x23, nzcv", "eor w24, w20, #0x1", "eor w20, w21, w20", "bic w20, w20, w24", @@ -3359,7 +3265,7 @@ ] }, "dec al": { - "ExpectedInstructionCount": 21, + "ExpectedInstructionCount": 18, "Optimal": "No", "Comment": "GROUP3 0xfe /1", "ExpectedArm64ASM": [ @@ -3367,16 +3273,13 @@ "sub w21, w20, #0x1 (1)", "bfxil x4, x21, #0, #8", "uxtb w21, w21", - "eor w22, w20, #0x1", - "strb w22, [x28, #708]", + "strb w20, [x28, #708]", "strb w21, [x28, #706]", "ldr w22, [x28, #728]", "ubfx w22, w22, #29, #1", "lsl w23, w21, #24", - "and w23, w23, #0x80000000", - "cmp x21, #0x0 (0)", - "cset x24, eq", - "orr w23, w23, w24, lsl #30", + "tst w23, w23", + "mrs x23, nzcv", "eor w24, w20, #0x1", "eor w20, w21, w20", "and w20, w24, w20", @@ -3387,7 +3290,7 @@ ] }, "inc ax": { - "ExpectedInstructionCount": 21, + "ExpectedInstructionCount": 18, "Optimal": "No", "Comment": "GROUP4 0xfe /0", "ExpectedArm64ASM": [ @@ -3395,16 +3298,13 @@ "add w21, w20, #0x1 (1)", "bfxil x4, x21, #0, #16", "uxth w21, w21", - "eor w22, w20, #0x1", - "strb w22, [x28, #708]", + "strb w20, [x28, #708]", "strb w21, [x28, #706]", "ldr w22, [x28, #728]", "ubfx w22, w22, #29, #1", "lsl w23, w21, #16", - "and w23, w23, #0x80000000", - "cmp x21, #0x0 (0)", - "cset x24, eq", - "orr w23, w23, w24, lsl #30", + "tst w23, w23", + "mrs x23, nzcv", "eor w24, w20, #0x1", "eor w20, w21, w20", "bic w20, w20, w24", @@ -3415,14 +3315,13 @@ ] }, "inc eax": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 10, "Optimal": "No", "Comment": "GROUP4 0xfe /0", "ExpectedArm64ASM": [ "mov w20, w4", "add w4, w20, #0x1 (1)", - "eor w21, w20, #0x1", - "strb w21, [x28, #708]", + "strb w20, [x28, #708]", "strb w4, [x28, #706]", "ldr w21, [x28, #728]", "ubfx w21, w21, #29, #1", @@ -3433,14 +3332,13 @@ ] }, "inc rax": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 10, "Optimal": "Yes", "Comment": "GROUP4 0xfe /0", "ExpectedArm64ASM": [ "mov x20, x4", "add x4, x20, #0x1 (1)", - "eor x21, x20, #0x1", - "strb w21, [x28, #708]", + "strb w20, [x28, #708]", "strb w4, [x28, #706]", "ldr w21, [x28, #728]", "ubfx w21, w21, #29, #1", @@ -3451,7 +3349,7 @@ ] }, "dec ax": { - "ExpectedInstructionCount": 21, + "ExpectedInstructionCount": 18, "Optimal": "No", "Comment": "GROUP4 0xfe /1", "ExpectedArm64ASM": [ @@ -3459,16 +3357,13 @@ "sub w21, w20, #0x1 (1)", "bfxil x4, x21, #0, #16", "uxth w21, w21", - "eor w22, w20, #0x1", - "strb w22, [x28, #708]", + "strb w20, [x28, #708]", "strb w21, [x28, #706]", "ldr w22, [x28, #728]", "ubfx w22, w22, #29, #1", "lsl w23, w21, #16", - "and w23, w23, #0x80000000", - "cmp x21, #0x0 (0)", - "cset x24, eq", - "orr w23, w23, w24, lsl #30", + "tst w23, w23", + "mrs x23, nzcv", "eor w24, w20, #0x1", "eor w20, w21, w20", "and w20, w24, w20", @@ -3479,14 +3374,13 @@ ] }, "dec eax": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 10, "Optimal": "No", "Comment": "GROUP4 0xfe /1", "ExpectedArm64ASM": [ "mov w20, w4", "sub w4, w20, #0x1 (1)", - "eor w21, w20, #0x1", - "strb w21, [x28, #708]", + "strb w20, [x28, #708]", "strb w4, [x28, #706]", "ldr w21, [x28, #728]", "ubfx w21, w21, #29, #1", @@ -3497,14 +3391,13 @@ ] }, "dec rax": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 10, "Optimal": "Yes", "Comment": "GROUP4 0xfe /1", "ExpectedArm64ASM": [ "mov x20, x4", "sub x4, x20, #0x1 (1)", - "eor x21, x20, #0x1", - "strb w21, [x28, #708]", + "strb w20, [x28, #708]", "strb w4, [x28, #706]", "ldr w21, [x28, #728]", "ubfx w21, w21, #29, #1", diff --git a/unittests/InstructionCountCI/Primary_32Bit.json b/unittests/InstructionCountCI/Primary_32Bit.json index b9ccae16f..48b0ca4e8 100644 --- a/unittests/InstructionCountCI/Primary_32Bit.json +++ b/unittests/InstructionCountCI/Primary_32Bit.json @@ -286,7 +286,7 @@ ] }, "inc ax": { - "ExpectedInstructionCount": 21, + "ExpectedInstructionCount": 18, "Optimal": "No", "Comment": "0x40", "ExpectedArm64ASM": [ @@ -294,16 +294,13 @@ "add w21, w20, #0x1 (1)", "bfxil w4, w21, #0, #16", "uxth w21, w21", - "eor w22, w20, #0x1", - "strb w22, [x28, #708]", + "strb w20, [x28, #708]", "strb w21, [x28, #706]", "ldr w22, [x28, #728]", "ubfx w22, w22, #29, #1", "lsl w23, w21, #16", - "and w23, w23, #0x80000000", - "cmp x21, #0x0 (0)", - "cset x24, eq", - "orr w23, w23, w24, lsl #30", + "tst w23, w23", + "mrs x23, nzcv", "eor w24, w20, #0x1", "eor w20, w21, w20", "bic w20, w20, w24", @@ -314,14 +311,13 @@ ] }, "inc eax": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 10, "Optimal": "No", "Comment": "0x40", "ExpectedArm64ASM": [ "mov w20, w4", "add w4, w20, #0x1 (1)", - "eor w21, w20, #0x1", - "strb w21, [x28, #708]", + "strb w20, [x28, #708]", "strb w4, [x28, #706]", "ldr w21, [x28, #728]", "ubfx w21, w21, #29, #1", @@ -332,7 +328,7 @@ ] }, "dec ax": { - "ExpectedInstructionCount": 21, + "ExpectedInstructionCount": 18, "Optimal": "No", "Comment": "0x48", "ExpectedArm64ASM": [ @@ -340,16 +336,13 @@ "sub w21, w20, #0x1 (1)", "bfxil w4, w21, #0, #16", "uxth w21, w21", - "eor w22, w20, #0x1", - "strb w22, [x28, #708]", + "strb w20, [x28, #708]", "strb w21, [x28, #706]", "ldr w22, [x28, #728]", "ubfx w22, w22, #29, #1", "lsl w23, w21, #16", - "and w23, w23, #0x80000000", - "cmp x21, #0x0 (0)", - "cset x24, eq", - "orr w23, w23, w24, lsl #30", + "tst w23, w23", + "mrs x23, nzcv", "eor w24, w20, #0x1", "eor w20, w21, w20", "and w20, w24, w20", @@ -360,14 +353,13 @@ ] }, "dec eax": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 10, "Optimal": "No", "Comment": "0x48", "ExpectedArm64ASM": [ "mov w20, w4", "sub w4, w20, #0x1 (1)", - "eor w21, w20, #0x1", - "strb w21, [x28, #708]", + "strb w20, [x28, #708]", "strb w4, [x28, #706]", "ldr w21, [x28, #728]", "ubfx w21, w21, #29, #1", diff --git a/unittests/InstructionCountCI/Secondary.json b/unittests/InstructionCountCI/Secondary.json index 5af25d515..929e69b84 100644 --- a/unittests/InstructionCountCI/Secondary.json +++ b/unittests/InstructionCountCI/Secondary.json @@ -265,359 +265,317 @@ ] }, "cmovo ax, bx": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Optimal": "No", "Comment": "0x0f 0x40", "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "ubfx w20, w20, #28, #1", - "cmp w20, #0x0 (0)", + "tst w20, #0x10000000", "csel w20, w7, w4, ne", "bfxil x4, x20, #0, #16" ] }, "cmovo eax, ebx": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Optimal": "No", "Comment": "0x0f 0x40", "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "ubfx w20, w20, #28, #1", - "cmp w20, #0x0 (0)", + "tst w20, #0x10000000", "csel w4, w7, w4, ne" ] }, "cmovo rax, rbx": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Optimal": "Yes", "Comment": "0x0f 0x40", "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "ubfx w20, w20, #28, #1", - "cmp w20, #0x0 (0)", + "tst w20, #0x10000000", "csel x4, x7, x4, ne" ] }, "cmovno ax, bx": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Optimal": "No", "Comment": "0x0f 0x41", "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "ubfx w20, w20, #28, #1", - "cmp w20, #0x0 (0)", + "tst w20, #0x10000000", "csel w20, w7, w4, eq", "bfxil x4, x20, #0, #16" ] }, "cmovno eax, ebx": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Optimal": "No", "Comment": "0x0f 0x41", "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "ubfx w20, w20, #28, #1", - "cmp w20, #0x0 (0)", + "tst w20, #0x10000000", "csel w4, w7, w4, eq" ] }, "cmovno rax, rbx": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Optimal": "Yes", "Comment": "0x0f 0x41", "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "ubfx w20, w20, #28, #1", - "cmp w20, #0x0 (0)", + "tst w20, #0x10000000", "csel x4, x7, x4, eq" ] }, "cmovb ax, bx": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Optimal": "No", "Comment": "0x0f 0x42", "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "ubfx w20, w20, #29, #1", - "cmp w20, #0x0 (0)", + "tst w20, #0x20000000", "csel w20, w7, w4, ne", "bfxil x4, x20, #0, #16" ] }, "cmovb eax, ebx": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Optimal": "No", "Comment": "0x0f 0x42", "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "ubfx w20, w20, #29, #1", - "cmp w20, #0x0 (0)", + "tst w20, #0x20000000", "csel w4, w7, w4, ne" ] }, "cmovb rax, rbx": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Optimal": "No", "Comment": "0x0f 0x42", "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "ubfx w20, w20, #29, #1", - "cmp w20, #0x0 (0)", + "tst w20, #0x20000000", "csel x4, x7, x4, ne" ] }, "cmovnb ax, bx": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Optimal": "No", "Comment": "0x0f 0x43", "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "ubfx w20, w20, #29, #1", - "cmp w20, #0x0 (0)", + "tst w20, #0x20000000", "csel w20, w7, w4, eq", "bfxil x4, x20, #0, #16" ] }, "cmovnb eax, ebx": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Optimal": "No", "Comment": "0x0f 0x43", "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "ubfx w20, w20, #29, #1", - "cmp w20, #0x0 (0)", + "tst w20, #0x20000000", "csel w4, w7, w4, eq" ] }, "cmovnb rax, rbx": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Optimal": "Yes", "Comment": "0x0f 0x43", "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "ubfx w20, w20, #29, #1", - "cmp w20, #0x0 (0)", + "tst w20, #0x20000000", "csel x4, x7, x4, eq" ] }, "cmovz ax, bx": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Optimal": "No", "Comment": "0x0f 0x44", "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "ubfx w20, w20, #30, #1", - "cmp w20, #0x0 (0)", + "tst w20, #0x40000000", "csel w20, w7, w4, ne", "bfxil x4, x20, #0, #16" ] }, "cmovz eax, ebx": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Optimal": "No", "Comment": "0x0f 0x44", "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "ubfx w20, w20, #30, #1", - "cmp w20, #0x0 (0)", + "tst w20, #0x40000000", "csel w4, w7, w4, ne" ] }, "cmovz rax, rbx": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Optimal": "Yes", "Comment": "0x0f 0x44", "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "ubfx w20, w20, #30, #1", - "cmp w20, #0x0 (0)", + "tst w20, #0x40000000", "csel x4, x7, x4, ne" ] }, "cmovnz ax, bx": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Optimal": "No", "Comment": "0x0f 0x45", "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "ubfx w20, w20, #30, #1", - "cmp w20, #0x0 (0)", + "tst w20, #0x40000000", "csel w20, w7, w4, eq", "bfxil x4, x20, #0, #16" ] }, "cmovnz eax, ebx": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Optimal": "No", "Comment": "0x0f 0x45", "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "ubfx w20, w20, #30, #1", - "cmp w20, #0x0 (0)", + "tst w20, #0x40000000", "csel w4, w7, w4, eq" ] }, "cmovnz rax, rbx": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Optimal": "Yes", "Comment": "0x0f 0x45", "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "ubfx w20, w20, #30, #1", - "cmp w20, #0x0 (0)", + "tst w20, #0x40000000", "csel x4, x7, x4, eq" ] }, "cmovbe ax, bx": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 4, "Optimal": "No", "Comment": "0x0f 0x46", "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "ubfx w21, w20, #30, #1", - "ubfx w20, w20, #29, #1", - "orr w20, w21, w20", - "cmp w20, #0x1 (1)", - "csel w20, w7, w4, eq", + "tst w20, #0x60000000", + "csel w20, w7, w4, ne", "bfxil x4, x20, #0, #16" ] }, "cmovbe eax, ebx": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 3, "Optimal": "No", "Comment": "0x0f 0x46", "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "ubfx w21, w20, #30, #1", - "ubfx w20, w20, #29, #1", - "orr w20, w21, w20", - "cmp w20, #0x1 (1)", - "csel w4, w7, w4, eq" + "tst w20, #0x60000000", + "csel w4, w7, w4, ne" ] }, "cmovbe rax, rbx": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 3, "Optimal": "No", "Comment": "0x0f 0x46", "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "ubfx w21, w20, #30, #1", - "ubfx w20, w20, #29, #1", - "orr w20, w21, w20", - "cmp w20, #0x1 (1)", - "csel x4, x7, x4, eq" + "tst w20, #0x60000000", + "csel x4, x7, x4, ne" ] }, "cmovnbe ax, bx": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 4, "Optimal": "No", "Comment": "0x0f 0x47", "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "ubfx w21, w20, #30, #1", - "ubfx w20, w20, #29, #1", - "orr w20, w21, w20", - "cmp w20, #0x0 (0)", + "tst w20, #0x60000000", "csel w20, w7, w4, eq", "bfxil x4, x20, #0, #16" ] }, "cmovnbe eax, ebx": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 3, "Optimal": "No", "Comment": "0x0f 0x47", "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "ubfx w21, w20, #30, #1", - "ubfx w20, w20, #29, #1", - "orr w20, w21, w20", - "cmp w20, #0x0 (0)", + "tst w20, #0x60000000", "csel w4, w7, w4, eq" ] }, "cmovnbe rax, rbx": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 3, "Optimal": "No", "Comment": "0x0f 0x47", "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "ubfx w21, w20, #30, #1", - "ubfx w20, w20, #29, #1", - "orr w20, w21, w20", - "cmp w20, #0x0 (0)", + "tst w20, #0x60000000", "csel x4, x7, x4, eq" ] }, "cmovs ax, bx": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Optimal": "No", "Comment": "0x0f 0x48", "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "lsr w20, w20, #31", - "cmp w20, #0x0 (0)", + "tst w20, #0x80000000", "csel w20, w7, w4, ne", "bfxil x4, x20, #0, #16" ] }, "cmovs eax, ebx": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Optimal": "No", "Comment": "0x0f 0x48", "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "lsr w20, w20, #31", - "cmp w20, #0x0 (0)", + "tst w20, #0x80000000", "csel w4, w7, w4, ne" ] }, "cmovs rax, rbx": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Optimal": "Yes", "Comment": "0x0f 0x48", "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "lsr w20, w20, #31", - "cmp w20, #0x0 (0)", + "tst w20, #0x80000000", "csel x4, x7, x4, ne" ] }, "cmovns ax, bx": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Optimal": "No", "Comment": "0x0f 0x49", "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "lsr w20, w20, #31", - "cmp w20, #0x0 (0)", + "tst w20, #0x80000000", "csel w20, w7, w4, eq", "bfxil x4, x20, #0, #16" ] }, "cmovns eax, ebx": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Optimal": "No", "Comment": "0x0f 0x49", "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "lsr w20, w20, #31", - "cmp w20, #0x0 (0)", + "tst w20, #0x80000000", "csel w4, w7, w4, eq" ] }, "cmovns rax, rbx": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Optimal": "Yes", "Comment": "0x0f 0x49", "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "lsr w20, w20, #31", - "cmp w20, #0x0 (0)", + "tst w20, #0x80000000", "csel x4, x7, x4, eq" ] }, "cmovpe ax, bx": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 7, "Optimal": "No", "Comment": "0x0f 0x4a", "ExpectedArm64ASM": [ @@ -625,14 +583,13 @@ "fmov s2, w20", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", - "and x20, x20, #0x1", - "cmp w20, #0x0 (0)", + "tst w20, #0x1", "csel w20, w7, w4, eq", "bfxil x4, x20, #0, #16" ] }, "cmovpe eax, ebx": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 6, "Optimal": "No", "Comment": "0x0f 0x4a", "ExpectedArm64ASM": [ @@ -640,13 +597,12 @@ "fmov s2, w20", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", - "and x20, x20, #0x1", - "cmp w20, #0x0 (0)", + "tst w20, #0x1", "csel w4, w7, w4, eq" ] }, "cmovpe rax, rbx": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 6, "Optimal": "No", "Comment": "0x0f 0x4a", "ExpectedArm64ASM": [ @@ -654,13 +610,12 @@ "fmov s2, w20", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", - "and x20, x20, #0x1", - "cmp w20, #0x0 (0)", + "tst w20, #0x1", "csel x4, x7, x4, eq" ] }, "cmovnp ax, bx": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 7, "Optimal": "No", "Comment": "0x0f 0x4b", "ExpectedArm64ASM": [ @@ -668,14 +623,13 @@ "fmov s2, w20", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", - "and x20, x20, #0x1", - "cmp w20, #0x0 (0)", + "tst w20, #0x1", "csel w20, w7, w4, ne", "bfxil x4, x20, #0, #16" ] }, "cmovnp eax, ebx": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 6, "Optimal": "No", "Comment": "0x0f 0x4b", "ExpectedArm64ASM": [ @@ -683,13 +637,12 @@ "fmov s2, w20", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", - "and x20, x20, #0x1", - "cmp w20, #0x0 (0)", + "tst w20, #0x1", "csel w4, w7, w4, ne" ] }, "cmovnp rax, rbx": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 6, "Optimal": "No", "Comment": "0x0f 0x4b", "ExpectedArm64ASM": [ @@ -697,8 +650,7 @@ "fmov s2, w20", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", - "and x20, x20, #0x1", - "cmp w20, #0x0 (0)", + "tst w20, #0x1", "csel x4, x7, x4, ne" ] }, @@ -777,16 +729,15 @@ ] }, "cmovle ax, bx": { - "ExpectedInstructionCount": 12, + "ExpectedInstructionCount": 11, "Optimal": "No", "Comment": "0x0f 0x4e", "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "ubfx w21, w20, #30, #1", + "tst w20, #0x40000000", + "cset w21, ne", "lsr w22, w20, #31", "ubfx w20, w20, #28, #1", - "cmp w21, #0x1 (1)", - "cset w21, eq", "cmp w22, w20", "cset w20, ne", "orr w20, w21, w20", @@ -796,16 +747,15 @@ ] }, "cmovle eax, ebx": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 10, "Optimal": "No", "Comment": "0x0f 0x4e", "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "ubfx w21, w20, #30, #1", + "tst w20, #0x40000000", + "cset w21, ne", "lsr w22, w20, #31", "ubfx w20, w20, #28, #1", - "cmp w21, #0x1 (1)", - "cset w21, eq", "cmp w22, w20", "cset w20, ne", "orr w20, w21, w20", @@ -814,16 +764,15 @@ ] }, "cmovle rax, rbx": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 10, "Optimal": "No", "Comment": "0x0f 0x4e", "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "ubfx w21, w20, #30, #1", + "tst w20, #0x40000000", + "cset w21, ne", "lsr w22, w20, #31", "ubfx w20, w20, #28, #1", - "cmp w21, #0x1 (1)", - "cset w21, eq", "cmp w22, w20", "cset w20, ne", "orr w20, w21, w20", @@ -832,16 +781,15 @@ ] }, "cmovnle ax, bx": { - "ExpectedInstructionCount": 12, + "ExpectedInstructionCount": 11, "Optimal": "No", "Comment": "0x0f 0x4f", "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "ubfx w21, w20, #30, #1", + "tst w20, #0x40000000", + "cset w21, eq", "lsr w22, w20, #31", "ubfx w20, w20, #28, #1", - "cmp w21, #0x0 (0)", - "cset w21, eq", "cmp w22, w20", "cset w20, eq", "and w20, w21, w20", @@ -851,16 +799,15 @@ ] }, "cmovnle eax, ebx": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 10, "Optimal": "No", "Comment": "0x0f 0x4f", "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "ubfx w21, w20, #30, #1", + "tst w20, #0x40000000", + "cset w21, eq", "lsr w22, w20, #31", "ubfx w20, w20, #28, #1", - "cmp w21, #0x0 (0)", - "cset w21, eq", "cmp w22, w20", "cset w20, eq", "and w20, w21, w20", @@ -869,16 +816,15 @@ ] }, "cmovnle rax, rbx": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 10, "Optimal": "No", "Comment": "0x0f 0x4f", "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "ubfx w21, w20, #30, #1", + "tst w20, #0x40000000", + "cset w21, eq", "lsr w22, w20, #31", "ubfx w20, w20, #28, #1", - "cmp w21, #0x0 (0)", - "cset w21, eq", "cmp w22, w20", "cset w20, eq", "and w20, w21, w20", @@ -1456,131 +1402,117 @@ ] }, "seto al": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Optimal": "Yes", "Comment": "0x0f 0x90", "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "ubfx w20, w20, #28, #1", - "cmp w20, #0x0 (0)", + "tst w20, #0x10000000", "cset x20, ne", "bfxil x4, x20, #0, #8" ] }, "setno al": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Optimal": "Yes", "Comment": "0x0f 0x91", "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "ubfx w20, w20, #28, #1", - "cmp w20, #0x0 (0)", + "tst w20, #0x10000000", "cset x20, eq", "bfxil x4, x20, #0, #8" ] }, "setb al": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Optimal": "Yes", "Comment": "0x0f 0x92", "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "ubfx w20, w20, #29, #1", - "cmp w20, #0x0 (0)", + "tst w20, #0x20000000", "cset x20, ne", "bfxil x4, x20, #0, #8" ] }, "setnb al": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Optimal": "Yes", "Comment": "0x0f 0x93", "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "ubfx w20, w20, #29, #1", - "cmp w20, #0x0 (0)", + "tst w20, #0x20000000", "cset x20, eq", "bfxil x4, x20, #0, #8" ] }, "setz al": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Optimal": "Yes", "Comment": "0x0f 0x94", "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "ubfx w20, w20, #30, #1", - "cmp w20, #0x0 (0)", + "tst w20, #0x40000000", "cset x20, ne", "bfxil x4, x20, #0, #8" ] }, "setnz al": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Optimal": "Yes", "Comment": "0x0f 0x95", "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "ubfx w20, w20, #30, #1", - "cmp w20, #0x0 (0)", + "tst w20, #0x40000000", "cset x20, eq", "bfxil x4, x20, #0, #8" ] }, "setbe al": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 4, "Optimal": "No", "Comment": "0x0f 0x96", "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "ubfx w21, w20, #30, #1", - "ubfx w20, w20, #29, #1", - "orr w20, w21, w20", - "cmp w20, #0x1 (1)", - "cset x20, eq", + "tst w20, #0x60000000", + "cset x20, ne", "bfxil x4, x20, #0, #8" ] }, "setnbe al": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 4, "Optimal": "No", "Comment": "0x0f 0x97", "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "ubfx w21, w20, #30, #1", - "ubfx w20, w20, #29, #1", - "orr w20, w21, w20", - "cmp w20, #0x0 (0)", + "tst w20, #0x60000000", "cset x20, eq", "bfxil x4, x20, #0, #8" ] }, "sets al": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Optimal": "Yes", "Comment": "0x0f 0x98", "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "lsr w20, w20, #31", - "cmp w20, #0x0 (0)", + "tst w20, #0x80000000", "cset x20, ne", "bfxil x4, x20, #0, #8" ] }, "setns al": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Optimal": "Yes", "Comment": "0x0f 0x99", "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "lsr w20, w20, #31", - "cmp w20, #0x0 (0)", + "tst w20, #0x80000000", "cset x20, eq", "bfxil x4, x20, #0, #8" ] }, "setpe al": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 7, "Optimal": "Yes", "Comment": "0x0f 0x9a", "ExpectedArm64ASM": [ @@ -1588,14 +1520,13 @@ "fmov s2, w20", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", - "and x20, x20, #0x1", - "cmp w20, #0x0 (0)", + "tst w20, #0x1", "cset x20, eq", "bfxil x4, x20, #0, #8" ] }, "setnp al": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 7, "Optimal": "Yes", "Comment": "0x0f 0x9b", "ExpectedArm64ASM": [ @@ -1603,8 +1534,7 @@ "fmov s2, w20", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", - "and x20, x20, #0x1", - "cmp w20, #0x0 (0)", + "tst w20, #0x1", "cset x20, ne", "bfxil x4, x20, #0, #8" ] @@ -1636,16 +1566,15 @@ ] }, "setle al": { - "ExpectedInstructionCount": 12, + "ExpectedInstructionCount": 11, "Optimal": "No", "Comment": "0x0f 0x9e", "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "ubfx w21, w20, #30, #1", + "tst w20, #0x40000000", + "cset w21, ne", "lsr w22, w20, #31", "ubfx w20, w20, #28, #1", - "cmp w21, #0x1 (1)", - "cset w21, eq", "cmp w22, w20", "cset w20, ne", "orr w20, w21, w20", @@ -1655,16 +1584,15 @@ ] }, "setnle al": { - "ExpectedInstructionCount": 12, + "ExpectedInstructionCount": 11, "Optimal": "No", "Comment": "0x0f 0x9f", "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "ubfx w21, w20, #30, #1", + "tst w20, #0x40000000", + "cset w21, eq", "lsr w22, w20, #31", "ubfx w20, w20, #28, #1", - "cmp w21, #0x0 (0)", - "cset w21, eq", "cmp w22, w20", "cset w20, eq", "and w20, w21, w20", @@ -1785,7 +1713,7 @@ "ExpectedArm64ASM": [] }, "shld ax, bx, 1": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 16, "Optimal": "No", "Comment": "0x0f 0xac", "ExpectedArm64ASM": [ @@ -1796,10 +1724,8 @@ "orr x20, x22, x20", "bfxil x4, x20, #0, #16", "lsl w22, w20, #16", - "and w22, w22, #0x80000000", - "cmp x20, #0x0 (0)", - "cset x23, eq", - "orr w22, w22, w23, lsl #30", + "tst w22, w22", + "mrs x22, nzcv", "ubfx w23, w21, #15, #1", "orr w22, w22, w23, lsl #29", "strb w20, [x28, #706]", @@ -1810,7 +1736,7 @@ ] }, "shld ax, bx, 15": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 13, "Optimal": "No", "Comment": "0x0f 0xac", "ExpectedArm64ASM": [ @@ -1821,10 +1747,8 @@ "orr x20, x22, x20", "bfxil x4, x20, #0, #16", "lsl w22, w20, #16", - "and w22, w22, #0x80000000", - "cmp x20, #0x0 (0)", - "cset x23, eq", - "orr w22, w22, w23, lsl #30", + "tst w22, w22", + "mrs x22, nzcv", "ubfx w21, w21, #1, #1", "orr w21, w22, w21, lsl #29", "strb w20, [x28, #706]", @@ -1832,7 +1756,7 @@ ] }, "shld ax, bx, 16": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 12, "Optimal": "No", "Comment": "0x0f 0xac", "ExpectedArm64ASM": [ @@ -1842,10 +1766,8 @@ "orr x20, x22, x20", "bfxil x4, x20, #0, #16", "lsl w22, w20, #16", - "and w22, w22, #0x80000000", - "cmp x20, #0x0 (0)", - "cset x23, eq", - "orr w22, w22, w23, lsl #30", + "tst w22, w22", + "mrs x22, nzcv", "ubfx w21, w21, #0, #1", "orr w21, w22, w21, lsl #29", "strb w20, [x28, #706]", @@ -1853,7 +1775,7 @@ ] }, "shld ax, bx, 31": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 13, "Optimal": "No", "Comment": "0x0f 0xac", "ExpectedArm64ASM": [ @@ -1864,10 +1786,8 @@ "orr x20, x22, x20", "bfxil x4, x20, #0, #16", "lsl w22, w20, #16", - "and w22, w22, #0x80000000", - "cmp x20, #0x0 (0)", - "cset x23, eq", - "orr w22, w22, w23, lsl #30", + "tst w22, w22", + "mrs x22, nzcv", "ubfx w21, w21, #1, #1", "orr w21, w22, w21, lsl #29", "strb w20, [x28, #706]", @@ -2019,7 +1939,7 @@ ] }, "shld ax, bx, cl": { - "ExpectedInstructionCount": 35, + "ExpectedInstructionCount": 33, "Optimal": "No", "Comment": "0x0f 0xad", "ExpectedArm64ASM": [ @@ -2035,19 +1955,17 @@ "cmp x22, #0x0 (0)", "csel x20, x21, x20, eq", "bfxil x4, x20, #0, #16", - "cbz x22, #+0x5c", + "cbz x22, #+0x54", "uxth x20, w20", "ldr w23, [x28, #728]", - "mov w24, #0x10", - "lsl w25, w20, #16", - "and w25, w25, #0x80000000", - "cmp x20, #0x0 (0)", - "cset x26, eq", - "orr w25, w25, w26, lsl #30", - "sub w24, w24, w22", - "lsr w24, w21, w24", - "ubfx w24, w24, #0, #1", - "orr w24, w25, w24, lsl #29", + "lsl w24, w20, #16", + "tst w24, w24", + "mrs x24, nzcv", + "mov w25, #0x10", + "sub w25, w25, w22", + "lsr w25, w21, w25", + "ubfx w25, w25, #0, #1", + "orr w24, w24, w25, lsl #29", "ldrb w25, [x28, #706]", "cmp x22, #0x0 (0)", "csel x25, x25, x20, eq", @@ -2374,7 +2292,7 @@ ] }, "cmpxchg al, bl": { - "ExpectedInstructionCount": 28, + "ExpectedInstructionCount": 26, "Optimal": "No", "Comment": "0x0f 0xb0", "ExpectedArm64ASM": [ @@ -2393,10 +2311,8 @@ "strb w21, [x28, #708]", "strb w20, [x28, #706]", "lsl w21, w20, #24", - "and w21, w21, #0x80000000", - "cmp x20, #0x0 (0)", - "cset x24, eq", - "orr w21, w21, w24, lsl #30", + "tst w21, w21", + "mrs x21, nzcv", "cmp x22, x23", "cset x24, lo", "orr w21, w21, w24, lsl #29", @@ -2409,7 +2325,7 @@ ] }, "cmpxchg [rax], bl": { - "ExpectedInstructionCount": 25, + "ExpectedInstructionCount": 23, "Optimal": "No", "Comment": "0x0f 0xb0", "ExpectedArm64ASM": [ @@ -2425,10 +2341,8 @@ "strb w23, [x28, #708]", "strb w22, [x28, #706]", "lsl w23, w22, #24", - "and w23, w23, #0x80000000", - "cmp x22, #0x0 (0)", - "cset x24, eq", - "orr w23, w23, w24, lsl #30", + "tst w23, w23", + "mrs x23, nzcv", "cmp w21, w20", "cset x24, lo", "orr w23, w23, w24, lsl #29", @@ -2441,7 +2355,7 @@ ] }, "cmpxchg ax, bx": { - "ExpectedInstructionCount": 28, + "ExpectedInstructionCount": 26, "Optimal": "No", "Comment": "0x0f 0xb1", "ExpectedArm64ASM": [ @@ -2460,10 +2374,8 @@ "strb w21, [x28, #708]", "strb w20, [x28, #706]", "lsl w21, w20, #16", - "and w21, w21, #0x80000000", - "cmp x20, #0x0 (0)", - "cset x24, eq", - "orr w21, w21, w24, lsl #30", + "tst w21, w21", + "mrs x21, nzcv", "cmp x22, x23", "cset x24, lo", "orr w21, w21, w24, lsl #29", @@ -2476,7 +2388,7 @@ ] }, "cmpxchg [rax], bx": { - "ExpectedInstructionCount": 25, + "ExpectedInstructionCount": 23, "Optimal": "No", "Comment": "0x0f 0xb1", "ExpectedArm64ASM": [ @@ -2492,10 +2404,8 @@ "strb w23, [x28, #708]", "strb w22, [x28, #706]", "lsl w23, w22, #16", - "and w23, w23, #0x80000000", - "cmp x22, #0x0 (0)", - "cset x24, eq", - "orr w23, w23, w24, lsl #30", + "tst w23, w23", + "mrs x23, nzcv", "cmp w21, w20", "cset x24, lo", "orr w23, w23, w24, lsl #29", @@ -3202,7 +3112,7 @@ ] }, "xadd al, bl": { - "ExpectedInstructionCount": 23, + "ExpectedInstructionCount": 21, "Optimal": "No", "Comment": "0x0f 0xc0", "ExpectedArm64ASM": [ @@ -3216,10 +3126,8 @@ "strb w23, [x28, #708]", "strb w22, [x28, #706]", "lsl w23, w22, #24", - "and w23, w23, #0x80000000", - "cmp x22, #0x0 (0)", - "cset x24, eq", - "orr w23, w23, w24, lsl #30", + "tst w23, w23", + "mrs x23, nzcv", "cmp w22, w21", "cset x24, lo", "orr w23, w23, w24, lsl #29", @@ -3232,7 +3140,7 @@ ] }, "xadd [rax], bl": { - "ExpectedInstructionCount": 22, + "ExpectedInstructionCount": 20, "Optimal": "No", "Comment": "0x0f 0xc0", "ExpectedArm64ASM": [ @@ -3245,10 +3153,8 @@ "strb w23, [x28, #708]", "strb w22, [x28, #706]", "lsl w23, w22, #24", - "and w23, w23, #0x80000000", - "cmp x22, #0x0 (0)", - "cset x24, eq", - "orr w23, w23, w24, lsl #30", + "tst w23, w23", + "mrs x23, nzcv", "cmp w22, w20", "cset x24, lo", "orr w23, w23, w24, lsl #29", @@ -3261,7 +3167,7 @@ ] }, "xadd ax, bx": { - "ExpectedInstructionCount": 23, + "ExpectedInstructionCount": 21, "Optimal": "No", "Comment": "0x0f 0xc1", "ExpectedArm64ASM": [ @@ -3275,10 +3181,8 @@ "strb w23, [x28, #708]", "strb w22, [x28, #706]", "lsl w23, w22, #16", - "and w23, w23, #0x80000000", - "cmp x22, #0x0 (0)", - "cset x24, eq", - "orr w23, w23, w24, lsl #30", + "tst w23, w23", + "mrs x23, nzcv", "cmp w22, w21", "cset x24, lo", "orr w23, w23, w24, lsl #29", @@ -3291,7 +3195,7 @@ ] }, "xadd [rax], bx": { - "ExpectedInstructionCount": 22, + "ExpectedInstructionCount": 20, "Optimal": "No", "Comment": "0x0f 0xc1", "ExpectedArm64ASM": [ @@ -3304,10 +3208,8 @@ "strb w23, [x28, #708]", "strb w22, [x28, #706]", "lsl w23, w22, #16", - "and w23, w23, #0x80000000", - "cmp x22, #0x0 (0)", - "cset x24, eq", - "orr w23, w23, w24, lsl #30", + "tst w23, w23", + "mrs x23, nzcv", "cmp w22, w20", "cset x24, lo", "orr w23, w23, w24, lsl #29", diff --git a/unittests/InstructionCountCI/x87.json b/unittests/InstructionCountCI/x87.json index 1c1acef3e..97f6808a5 100644 --- a/unittests/InstructionCountCI/x87.json +++ b/unittests/InstructionCountCI/x87.json @@ -8279,15 +8279,14 @@ ] }, "fcmovb st0, st0": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 14, "Optimal": "No", "Comment": [ "0xda 11b 0xc0 /0" ], "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "ubfx w20, w20, #29, #1", - "cmp w20, #0x0 (0)", + "tst w20, #0x20000000", "csetm x20, ne", "dup v2.2d, x20", "ldrb w20, [x28, #747]", @@ -8303,15 +8302,14 @@ ] }, "fcmovb st0, st1": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 14, "Optimal": "No", "Comment": [ "0xda 11b 0xc1 /0" ], "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "ubfx w20, w20, #29, #1", - "cmp w20, #0x0 (0)", + "tst w20, #0x20000000", "csetm x20, ne", "dup v2.2d, x20", "ldrb w20, [x28, #747]", @@ -8327,15 +8325,14 @@ ] }, "fcmovb st0, st2": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 14, "Optimal": "No", "Comment": [ "0xda 11b 0xc2 /0" ], "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "ubfx w20, w20, #29, #1", - "cmp w20, #0x0 (0)", + "tst w20, #0x20000000", "csetm x20, ne", "dup v2.2d, x20", "ldrb w20, [x28, #747]", @@ -8351,15 +8348,14 @@ ] }, "fcmovb st0, st3": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 14, "Optimal": "No", "Comment": [ "0xda 11b 0xc3 /0" ], "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "ubfx w20, w20, #29, #1", - "cmp w20, #0x0 (0)", + "tst w20, #0x20000000", "csetm x20, ne", "dup v2.2d, x20", "ldrb w20, [x28, #747]", @@ -8375,15 +8371,14 @@ ] }, "fcmovb st0, st4": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 14, "Optimal": "No", "Comment": [ "0xda 11b 0xc4 /0" ], "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "ubfx w20, w20, #29, #1", - "cmp w20, #0x0 (0)", + "tst w20, #0x20000000", "csetm x20, ne", "dup v2.2d, x20", "ldrb w20, [x28, #747]", @@ -8399,15 +8394,14 @@ ] }, "fcmovb st0, st5": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 14, "Optimal": "No", "Comment": [ "0xda 11b 0xc5 /0" ], "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "ubfx w20, w20, #29, #1", - "cmp w20, #0x0 (0)", + "tst w20, #0x20000000", "csetm x20, ne", "dup v2.2d, x20", "ldrb w20, [x28, #747]", @@ -8423,15 +8417,14 @@ ] }, "fcmovb st0, st6": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 14, "Optimal": "No", "Comment": [ "0xda 11b 0xc6 /0" ], "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "ubfx w20, w20, #29, #1", - "cmp w20, #0x0 (0)", + "tst w20, #0x20000000", "csetm x20, ne", "dup v2.2d, x20", "ldrb w20, [x28, #747]", @@ -8447,15 +8440,14 @@ ] }, "fcmovb st0, st7": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 14, "Optimal": "No", "Comment": [ "0xda 11b 0xc7 /0" ], "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "ubfx w20, w20, #29, #1", - "cmp w20, #0x0 (0)", + "tst w20, #0x20000000", "csetm x20, ne", "dup v2.2d, x20", "ldrb w20, [x28, #747]", @@ -8471,15 +8463,14 @@ ] }, "fcmove st0, st0": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 14, "Optimal": "No", "Comment": [ "0xda 11b 0xc8 /1" ], "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "ubfx w20, w20, #30, #1", - "cmp w20, #0x0 (0)", + "tst w20, #0x40000000", "csetm x20, ne", "dup v2.2d, x20", "ldrb w20, [x28, #747]", @@ -8495,15 +8486,14 @@ ] }, "fcmove st0, st1": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 14, "Optimal": "No", "Comment": [ "0xda 11b 0xc9 /1" ], "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "ubfx w20, w20, #30, #1", - "cmp w20, #0x0 (0)", + "tst w20, #0x40000000", "csetm x20, ne", "dup v2.2d, x20", "ldrb w20, [x28, #747]", @@ -8519,15 +8509,14 @@ ] }, "fcmove st0, st2": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 14, "Optimal": "No", "Comment": [ "0xda 11b 0xca /1" ], "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "ubfx w20, w20, #30, #1", - "cmp w20, #0x0 (0)", + "tst w20, #0x40000000", "csetm x20, ne", "dup v2.2d, x20", "ldrb w20, [x28, #747]", @@ -8543,15 +8532,14 @@ ] }, "fcmove st0, st3": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 14, "Optimal": "No", "Comment": [ "0xda 11b 0xcb /1" ], "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "ubfx w20, w20, #30, #1", - "cmp w20, #0x0 (0)", + "tst w20, #0x40000000", "csetm x20, ne", "dup v2.2d, x20", "ldrb w20, [x28, #747]", @@ -8567,15 +8555,14 @@ ] }, "fcmove st0, st4": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 14, "Optimal": "No", "Comment": [ "0xda 11b 0xcc /1" ], "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "ubfx w20, w20, #30, #1", - "cmp w20, #0x0 (0)", + "tst w20, #0x40000000", "csetm x20, ne", "dup v2.2d, x20", "ldrb w20, [x28, #747]", @@ -8591,15 +8578,14 @@ ] }, "fcmove st0, st5": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 14, "Optimal": "No", "Comment": [ "0xda 11b 0xcd /1" ], "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "ubfx w20, w20, #30, #1", - "cmp w20, #0x0 (0)", + "tst w20, #0x40000000", "csetm x20, ne", "dup v2.2d, x20", "ldrb w20, [x28, #747]", @@ -8615,15 +8601,14 @@ ] }, "fcmove st0, st6": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 14, "Optimal": "No", "Comment": [ "0xda 11b 0xce /1" ], "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "ubfx w20, w20, #30, #1", - "cmp w20, #0x0 (0)", + "tst w20, #0x40000000", "csetm x20, ne", "dup v2.2d, x20", "ldrb w20, [x28, #747]", @@ -8639,15 +8624,14 @@ ] }, "fcmove st0, st7": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 14, "Optimal": "No", "Comment": [ "0xda 11b 0xcf /1" ], "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "ubfx w20, w20, #30, #1", - "cmp w20, #0x0 (0)", + "tst w20, #0x40000000", "csetm x20, ne", "dup v2.2d, x20", "ldrb w20, [x28, #747]", @@ -8663,18 +8647,15 @@ ] }, "fcmovbe st0, st0": { - "ExpectedInstructionCount": 17, + "ExpectedInstructionCount": 14, "Optimal": "No", "Comment": [ "0xda 11b 0xd0 /0" ], "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "ubfx w21, w20, #30, #1", - "ubfx w20, w20, #29, #1", - "orr w20, w21, w20", - "cmp w20, #0x1 (1)", - "csetm x20, eq", + "tst w20, #0x60000000", + "csetm x20, ne", "dup v2.2d, x20", "ldrb w20, [x28, #747]", "add w21, w20, #0x0 (0)", @@ -8689,18 +8670,15 @@ ] }, "fcmovbe st0, st1": { - "ExpectedInstructionCount": 17, + "ExpectedInstructionCount": 14, "Optimal": "No", "Comment": [ "0xda 11b 0xd1 /0" ], "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "ubfx w21, w20, #30, #1", - "ubfx w20, w20, #29, #1", - "orr w20, w21, w20", - "cmp w20, #0x1 (1)", - "csetm x20, eq", + "tst w20, #0x60000000", + "csetm x20, ne", "dup v2.2d, x20", "ldrb w20, [x28, #747]", "add w21, w20, #0x1 (1)", @@ -8715,18 +8693,15 @@ ] }, "fcmovbe st0, st2": { - "ExpectedInstructionCount": 17, + "ExpectedInstructionCount": 14, "Optimal": "No", "Comment": [ "0xda 11b 0xd2 /0" ], "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "ubfx w21, w20, #30, #1", - "ubfx w20, w20, #29, #1", - "orr w20, w21, w20", - "cmp w20, #0x1 (1)", - "csetm x20, eq", + "tst w20, #0x60000000", + "csetm x20, ne", "dup v2.2d, x20", "ldrb w20, [x28, #747]", "add w21, w20, #0x2 (2)", @@ -8741,18 +8716,15 @@ ] }, "fcmovbe st0, st3": { - "ExpectedInstructionCount": 17, + "ExpectedInstructionCount": 14, "Optimal": "No", "Comment": [ "0xda 11b 0xd3 /0" ], "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "ubfx w21, w20, #30, #1", - "ubfx w20, w20, #29, #1", - "orr w20, w21, w20", - "cmp w20, #0x1 (1)", - "csetm x20, eq", + "tst w20, #0x60000000", + "csetm x20, ne", "dup v2.2d, x20", "ldrb w20, [x28, #747]", "add w21, w20, #0x3 (3)", @@ -8767,18 +8739,15 @@ ] }, "fcmovbe st0, st4": { - "ExpectedInstructionCount": 17, + "ExpectedInstructionCount": 14, "Optimal": "No", "Comment": [ "0xda 11b 0xd4 /0" ], "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "ubfx w21, w20, #30, #1", - "ubfx w20, w20, #29, #1", - "orr w20, w21, w20", - "cmp w20, #0x1 (1)", - "csetm x20, eq", + "tst w20, #0x60000000", + "csetm x20, ne", "dup v2.2d, x20", "ldrb w20, [x28, #747]", "add w21, w20, #0x4 (4)", @@ -8793,18 +8762,15 @@ ] }, "fcmovbe st0, st5": { - "ExpectedInstructionCount": 17, + "ExpectedInstructionCount": 14, "Optimal": "No", "Comment": [ "0xda 11b 0xd5 /0" ], "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "ubfx w21, w20, #30, #1", - "ubfx w20, w20, #29, #1", - "orr w20, w21, w20", - "cmp w20, #0x1 (1)", - "csetm x20, eq", + "tst w20, #0x60000000", + "csetm x20, ne", "dup v2.2d, x20", "ldrb w20, [x28, #747]", "add w21, w20, #0x5 (5)", @@ -8819,18 +8785,15 @@ ] }, "fcmovbe st0, st6": { - "ExpectedInstructionCount": 17, + "ExpectedInstructionCount": 14, "Optimal": "No", "Comment": [ "0xda 11b 0xd6 /0" ], "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "ubfx w21, w20, #30, #1", - "ubfx w20, w20, #29, #1", - "orr w20, w21, w20", - "cmp w20, #0x1 (1)", - "csetm x20, eq", + "tst w20, #0x60000000", + "csetm x20, ne", "dup v2.2d, x20", "ldrb w20, [x28, #747]", "add w21, w20, #0x6 (6)", @@ -8845,18 +8808,15 @@ ] }, "fcmovbe st0, st7": { - "ExpectedInstructionCount": 17, + "ExpectedInstructionCount": 14, "Optimal": "No", "Comment": [ "0xda 11b 0xd7 /0" ], "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "ubfx w21, w20, #30, #1", - "ubfx w20, w20, #29, #1", - "orr w20, w21, w20", - "cmp w20, #0x1 (1)", - "csetm x20, eq", + "tst w20, #0x60000000", + "csetm x20, ne", "dup v2.2d, x20", "ldrb w20, [x28, #747]", "add w21, w20, #0x7 (7)", @@ -8871,7 +8831,7 @@ ] }, "fcmovu st0, st0": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 17, "Optimal": "No", "Comment": [ "0xda 11b 0xd8 /1" @@ -8881,8 +8841,7 @@ "fmov s2, w20", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", - "and x20, x20, #0x1", - "cmp w20, #0x0 (0)", + "tst w20, #0x1", "csetm x20, eq", "dup v2.2d, x20", "ldrb w20, [x28, #747]", @@ -8898,7 +8857,7 @@ ] }, "fcmovu st0, st1": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 17, "Optimal": "No", "Comment": [ "0xda 11b 0xd9 /1" @@ -8908,8 +8867,7 @@ "fmov s2, w20", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", - "and x20, x20, #0x1", - "cmp w20, #0x0 (0)", + "tst w20, #0x1", "csetm x20, eq", "dup v2.2d, x20", "ldrb w20, [x28, #747]", @@ -8925,7 +8883,7 @@ ] }, "fcmovu st0, st2": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 17, "Optimal": "No", "Comment": [ "0xda 11b 0xda /1" @@ -8935,8 +8893,7 @@ "fmov s2, w20", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", - "and x20, x20, #0x1", - "cmp w20, #0x0 (0)", + "tst w20, #0x1", "csetm x20, eq", "dup v2.2d, x20", "ldrb w20, [x28, #747]", @@ -8952,7 +8909,7 @@ ] }, "fcmovu st0, st3": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 17, "Optimal": "No", "Comment": [ "0xda 11b 0xdb /1" @@ -8962,8 +8919,7 @@ "fmov s2, w20", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", - "and x20, x20, #0x1", - "cmp w20, #0x0 (0)", + "tst w20, #0x1", "csetm x20, eq", "dup v2.2d, x20", "ldrb w20, [x28, #747]", @@ -8979,7 +8935,7 @@ ] }, "fcmovu st0, st4": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 17, "Optimal": "No", "Comment": [ "0xda 11b 0xdc /1" @@ -8989,8 +8945,7 @@ "fmov s2, w20", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", - "and x20, x20, #0x1", - "cmp w20, #0x0 (0)", + "tst w20, #0x1", "csetm x20, eq", "dup v2.2d, x20", "ldrb w20, [x28, #747]", @@ -9006,7 +8961,7 @@ ] }, "fcmovu st0, st5": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 17, "Optimal": "No", "Comment": [ "0xda 11b 0xdd /1" @@ -9016,8 +8971,7 @@ "fmov s2, w20", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", - "and x20, x20, #0x1", - "cmp w20, #0x0 (0)", + "tst w20, #0x1", "csetm x20, eq", "dup v2.2d, x20", "ldrb w20, [x28, #747]", @@ -9033,7 +8987,7 @@ ] }, "fcmovu st0, st6": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 17, "Optimal": "No", "Comment": [ "0xda 11b 0xde /1" @@ -9043,8 +8997,7 @@ "fmov s2, w20", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", - "and x20, x20, #0x1", - "cmp w20, #0x0 (0)", + "tst w20, #0x1", "csetm x20, eq", "dup v2.2d, x20", "ldrb w20, [x28, #747]", @@ -9060,7 +9013,7 @@ ] }, "fcmovu st0, st7": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 17, "Optimal": "No", "Comment": [ "0xda 11b 0xdf /1" @@ -9070,8 +9023,7 @@ "fmov s2, w20", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", - "and x20, x20, #0x1", - "cmp w20, #0x0 (0)", + "tst w20, #0x1", "csetm x20, eq", "dup v2.2d, x20", "ldrb w20, [x28, #747]", @@ -9446,15 +9398,14 @@ ] }, "fcmovnb st0, st0": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 14, "Optimal": "No", "Comment": [ "0xdb 11b 0xc0 /0" ], "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "ubfx w20, w20, #29, #1", - "cmp w20, #0x0 (0)", + "tst w20, #0x20000000", "csetm x20, eq", "dup v2.2d, x20", "ldrb w20, [x28, #747]", @@ -9470,15 +9421,14 @@ ] }, "fcmovnb st0, st1": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 14, "Optimal": "No", "Comment": [ "0xdb 11b 0xc1 /0" ], "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "ubfx w20, w20, #29, #1", - "cmp w20, #0x0 (0)", + "tst w20, #0x20000000", "csetm x20, eq", "dup v2.2d, x20", "ldrb w20, [x28, #747]", @@ -9494,15 +9444,14 @@ ] }, "fcmovnb st0, st2": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 14, "Optimal": "No", "Comment": [ "0xdb 11b 0xc2 /0" ], "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "ubfx w20, w20, #29, #1", - "cmp w20, #0x0 (0)", + "tst w20, #0x20000000", "csetm x20, eq", "dup v2.2d, x20", "ldrb w20, [x28, #747]", @@ -9518,15 +9467,14 @@ ] }, "fcmovnb st0, st3": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 14, "Optimal": "No", "Comment": [ "0xdb 11b 0xc3 /0" ], "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "ubfx w20, w20, #29, #1", - "cmp w20, #0x0 (0)", + "tst w20, #0x20000000", "csetm x20, eq", "dup v2.2d, x20", "ldrb w20, [x28, #747]", @@ -9542,15 +9490,14 @@ ] }, "fcmovnb st0, st4": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 14, "Optimal": "No", "Comment": [ "0xdb 11b 0xc4 /0" ], "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "ubfx w20, w20, #29, #1", - "cmp w20, #0x0 (0)", + "tst w20, #0x20000000", "csetm x20, eq", "dup v2.2d, x20", "ldrb w20, [x28, #747]", @@ -9566,15 +9513,14 @@ ] }, "fcmovnb st0, st5": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 14, "Optimal": "No", "Comment": [ "0xdb 11b 0xc5 /0" ], "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "ubfx w20, w20, #29, #1", - "cmp w20, #0x0 (0)", + "tst w20, #0x20000000", "csetm x20, eq", "dup v2.2d, x20", "ldrb w20, [x28, #747]", @@ -9590,15 +9536,14 @@ ] }, "fcmovnb st0, st6": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 14, "Optimal": "No", "Comment": [ "0xdb 11b 0xc6 /0" ], "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "ubfx w20, w20, #29, #1", - "cmp w20, #0x0 (0)", + "tst w20, #0x20000000", "csetm x20, eq", "dup v2.2d, x20", "ldrb w20, [x28, #747]", @@ -9614,15 +9559,14 @@ ] }, "fcmovnb st0, st7": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 14, "Optimal": "No", "Comment": [ "0xdb 11b 0xc7 /0" ], "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "ubfx w20, w20, #29, #1", - "cmp w20, #0x0 (0)", + "tst w20, #0x20000000", "csetm x20, eq", "dup v2.2d, x20", "ldrb w20, [x28, #747]", @@ -9638,15 +9582,14 @@ ] }, "fcmovne st0, st0": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 14, "Optimal": "No", "Comment": [ "0xdb 11b 0xc8 /1" ], "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "ubfx w20, w20, #30, #1", - "cmp w20, #0x0 (0)", + "tst w20, #0x40000000", "csetm x20, eq", "dup v2.2d, x20", "ldrb w20, [x28, #747]", @@ -9662,15 +9605,14 @@ ] }, "fcmovne st0, st1": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 14, "Optimal": "No", "Comment": [ "0xdb 11b 0xc9 /1" ], "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "ubfx w20, w20, #30, #1", - "cmp w20, #0x0 (0)", + "tst w20, #0x40000000", "csetm x20, eq", "dup v2.2d, x20", "ldrb w20, [x28, #747]", @@ -9686,15 +9628,14 @@ ] }, "fcmovne st0, st2": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 14, "Optimal": "No", "Comment": [ "0xdb 11b 0xca /1" ], "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "ubfx w20, w20, #30, #1", - "cmp w20, #0x0 (0)", + "tst w20, #0x40000000", "csetm x20, eq", "dup v2.2d, x20", "ldrb w20, [x28, #747]", @@ -9710,15 +9651,14 @@ ] }, "fcmovne st0, st3": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 14, "Optimal": "No", "Comment": [ "0xdb 11b 0xcb /1" ], "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "ubfx w20, w20, #30, #1", - "cmp w20, #0x0 (0)", + "tst w20, #0x40000000", "csetm x20, eq", "dup v2.2d, x20", "ldrb w20, [x28, #747]", @@ -9734,15 +9674,14 @@ ] }, "fcmovne st0, st4": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 14, "Optimal": "No", "Comment": [ "0xdb 11b 0xcc /1" ], "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "ubfx w20, w20, #30, #1", - "cmp w20, #0x0 (0)", + "tst w20, #0x40000000", "csetm x20, eq", "dup v2.2d, x20", "ldrb w20, [x28, #747]", @@ -9758,15 +9697,14 @@ ] }, "fcmovne st0, st5": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 14, "Optimal": "No", "Comment": [ "0xdb 11b 0xcd /1" ], "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "ubfx w20, w20, #30, #1", - "cmp w20, #0x0 (0)", + "tst w20, #0x40000000", "csetm x20, eq", "dup v2.2d, x20", "ldrb w20, [x28, #747]", @@ -9782,15 +9720,14 @@ ] }, "fcmovne st0, st6": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 14, "Optimal": "No", "Comment": [ "0xdb 11b 0xce /1" ], "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "ubfx w20, w20, #30, #1", - "cmp w20, #0x0 (0)", + "tst w20, #0x40000000", "csetm x20, eq", "dup v2.2d, x20", "ldrb w20, [x28, #747]", @@ -9806,15 +9743,14 @@ ] }, "fcmovne st0, st7": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 14, "Optimal": "No", "Comment": [ "0xdb 11b 0xcf /1" ], "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "ubfx w20, w20, #30, #1", - "cmp w20, #0x0 (0)", + "tst w20, #0x40000000", "csetm x20, eq", "dup v2.2d, x20", "ldrb w20, [x28, #747]", @@ -9830,17 +9766,14 @@ ] }, "fcmovnbe st0, st0": { - "ExpectedInstructionCount": 17, + "ExpectedInstructionCount": 14, "Optimal": "No", "Comment": [ "0xdb 11b 0xd0 /2" ], "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "ubfx w21, w20, #30, #1", - "ubfx w20, w20, #29, #1", - "orr w20, w21, w20", - "cmp w20, #0x0 (0)", + "tst w20, #0x60000000", "csetm x20, eq", "dup v2.2d, x20", "ldrb w20, [x28, #747]", @@ -9856,17 +9789,14 @@ ] }, "fcmovnbe st0, st1": { - "ExpectedInstructionCount": 17, + "ExpectedInstructionCount": 14, "Optimal": "No", "Comment": [ "0xdb 11b 0xd1 /2" ], "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "ubfx w21, w20, #30, #1", - "ubfx w20, w20, #29, #1", - "orr w20, w21, w20", - "cmp w20, #0x0 (0)", + "tst w20, #0x60000000", "csetm x20, eq", "dup v2.2d, x20", "ldrb w20, [x28, #747]", @@ -9882,17 +9812,14 @@ ] }, "fcmovnbe st0, st2": { - "ExpectedInstructionCount": 17, + "ExpectedInstructionCount": 14, "Optimal": "No", "Comment": [ "0xdb 11b 0xd2 /2" ], "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "ubfx w21, w20, #30, #1", - "ubfx w20, w20, #29, #1", - "orr w20, w21, w20", - "cmp w20, #0x0 (0)", + "tst w20, #0x60000000", "csetm x20, eq", "dup v2.2d, x20", "ldrb w20, [x28, #747]", @@ -9908,17 +9835,14 @@ ] }, "fcmovnbe st0, st3": { - "ExpectedInstructionCount": 17, + "ExpectedInstructionCount": 14, "Optimal": "No", "Comment": [ "0xdb 11b 0xd3 /2" ], "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "ubfx w21, w20, #30, #1", - "ubfx w20, w20, #29, #1", - "orr w20, w21, w20", - "cmp w20, #0x0 (0)", + "tst w20, #0x60000000", "csetm x20, eq", "dup v2.2d, x20", "ldrb w20, [x28, #747]", @@ -9934,17 +9858,14 @@ ] }, "fcmovnbe st0, st4": { - "ExpectedInstructionCount": 17, + "ExpectedInstructionCount": 14, "Optimal": "No", "Comment": [ "0xdb 11b 0xd4 /2" ], "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "ubfx w21, w20, #30, #1", - "ubfx w20, w20, #29, #1", - "orr w20, w21, w20", - "cmp w20, #0x0 (0)", + "tst w20, #0x60000000", "csetm x20, eq", "dup v2.2d, x20", "ldrb w20, [x28, #747]", @@ -9960,17 +9881,14 @@ ] }, "fcmovnbe st0, st5": { - "ExpectedInstructionCount": 17, + "ExpectedInstructionCount": 14, "Optimal": "No", "Comment": [ "0xdb 11b 0xd5 /2" ], "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "ubfx w21, w20, #30, #1", - "ubfx w20, w20, #29, #1", - "orr w20, w21, w20", - "cmp w20, #0x0 (0)", + "tst w20, #0x60000000", "csetm x20, eq", "dup v2.2d, x20", "ldrb w20, [x28, #747]", @@ -9986,17 +9904,14 @@ ] }, "fcmovnbe st0, st6": { - "ExpectedInstructionCount": 17, + "ExpectedInstructionCount": 14, "Optimal": "No", "Comment": [ "0xdb 11b 0xd6 /2" ], "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "ubfx w21, w20, #30, #1", - "ubfx w20, w20, #29, #1", - "orr w20, w21, w20", - "cmp w20, #0x0 (0)", + "tst w20, #0x60000000", "csetm x20, eq", "dup v2.2d, x20", "ldrb w20, [x28, #747]", @@ -10012,17 +9927,14 @@ ] }, "fcmovnbe st0, st7": { - "ExpectedInstructionCount": 17, + "ExpectedInstructionCount": 14, "Optimal": "No", "Comment": [ "0xdb 11b 0xd7 /2" ], "ExpectedArm64ASM": [ "ldr w20, [x28, #728]", - "ubfx w21, w20, #30, #1", - "ubfx w20, w20, #29, #1", - "orr w20, w21, w20", - "cmp w20, #0x0 (0)", + "tst w20, #0x60000000", "csetm x20, eq", "dup v2.2d, x20", "ldrb w20, [x28, #747]", @@ -10038,7 +9950,7 @@ ] }, "fcmovnu st0, st0": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 17, "Optimal": "No", "Comment": [ "0xdb 11b 0xd8 /3" @@ -10048,8 +9960,7 @@ "fmov s2, w20", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", - "and x20, x20, #0x1", - "cmp w20, #0x0 (0)", + "tst w20, #0x1", "csetm x20, ne", "dup v2.2d, x20", "ldrb w20, [x28, #747]", @@ -10065,7 +9976,7 @@ ] }, "fcmovnu st0, st1": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 17, "Optimal": "No", "Comment": [ "0xdb 11b 0xd9 /3" @@ -10075,8 +9986,7 @@ "fmov s2, w20", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", - "and x20, x20, #0x1", - "cmp w20, #0x0 (0)", + "tst w20, #0x1", "csetm x20, ne", "dup v2.2d, x20", "ldrb w20, [x28, #747]", @@ -10092,7 +10002,7 @@ ] }, "fcmovnu st0, st2": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 17, "Optimal": "No", "Comment": [ "0xdb 11b 0xda /3" @@ -10102,8 +10012,7 @@ "fmov s2, w20", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", - "and x20, x20, #0x1", - "cmp w20, #0x0 (0)", + "tst w20, #0x1", "csetm x20, ne", "dup v2.2d, x20", "ldrb w20, [x28, #747]", @@ -10119,7 +10028,7 @@ ] }, "fcmovnu st0, st3": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 17, "Optimal": "No", "Comment": [ "0xdb 11b 0xdb /3" @@ -10129,8 +10038,7 @@ "fmov s2, w20", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", - "and x20, x20, #0x1", - "cmp w20, #0x0 (0)", + "tst w20, #0x1", "csetm x20, ne", "dup v2.2d, x20", "ldrb w20, [x28, #747]", @@ -10146,7 +10054,7 @@ ] }, "fcmovnu st0, st4": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 17, "Optimal": "No", "Comment": [ "0xdb 11b 0xdc /3" @@ -10156,8 +10064,7 @@ "fmov s2, w20", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", - "and x20, x20, #0x1", - "cmp w20, #0x0 (0)", + "tst w20, #0x1", "csetm x20, ne", "dup v2.2d, x20", "ldrb w20, [x28, #747]", @@ -10173,7 +10080,7 @@ ] }, "fcmovnu st0, st5": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 17, "Optimal": "No", "Comment": [ "0xdb 11b 0xdd /3" @@ -10183,8 +10090,7 @@ "fmov s2, w20", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", - "and x20, x20, #0x1", - "cmp w20, #0x0 (0)", + "tst w20, #0x1", "csetm x20, ne", "dup v2.2d, x20", "ldrb w20, [x28, #747]", @@ -10200,7 +10106,7 @@ ] }, "fcmovnu st0, st6": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 17, "Optimal": "No", "Comment": [ "0xdb 11b 0xde /3" @@ -10210,8 +10116,7 @@ "fmov s2, w20", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", - "and x20, x20, #0x1", - "cmp w20, #0x0 (0)", + "tst w20, #0x1", "csetm x20, ne", "dup v2.2d, x20", "ldrb w20, [x28, #747]", @@ -10227,7 +10132,7 @@ ] }, "fcmovnu st0, st7": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 17, "Optimal": "No", "Comment": [ "0xdb 11b 0xdf /3" @@ -10237,8 +10142,7 @@ "fmov s2, w20", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", - "and x20, x20, #0x1", - "cmp w20, #0x0 (0)", + "tst w20, #0x1", "csetm x20, ne", "dup v2.2d, x20", "ldrb w20, [x28, #747]",