diff --git a/FEXCore/Source/Interface/Core/JIT/MiscOps.cpp b/FEXCore/Source/Interface/Core/JIT/MiscOps.cpp
index f382595bd..34e731b24 100644
--- a/FEXCore/Source/Interface/Core/JIT/MiscOps.cpp
+++ b/FEXCore/Source/Interface/Core/JIT/MiscOps.cpp
@@ -47,10 +47,10 @@ DEF_OP(GuestOpcode) {
 DEF_OP(Fence) {
   auto Op = IROp->C<IR::IROp_Fence>();
   switch (Op->Fence) {
-  case IR::Fence_Load.Val: dmb(ARMEmitter::BarrierScope::LD); break;
-  case IR::Fence_LoadStore.Val: dmb(ARMEmitter::BarrierScope::SY); break;
-  case IR::Fence_Store.Val: dmb(ARMEmitter::BarrierScope::ST); break;
-  case IR::Fence_Inst.Val: isb(); break;
+  case IR::FenceType::Load: dmb(ARMEmitter::BarrierScope::LD); break;
+  case IR::FenceType::LoadStore: dmb(ARMEmitter::BarrierScope::SY); break;
+  case IR::FenceType::Store: dmb(ARMEmitter::BarrierScope::ST); break;
+  case IR::FenceType::Inst: isb(); break;
   default: LOGMAN_MSG_A_FMT("Unknown Fence: {}", Op->Fence); break;
   }
 }
diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
index 82dcef7a5..506b85e53 100644
--- a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
+++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
@@ -4793,7 +4793,7 @@ void OpDispatchBuilder::CLFLUSHOPT(OpcodeArgs) {
 void OpDispatchBuilder::LoadFenceOrXRSTOR(OpcodeArgs) {
   // 0xE8 signifies LFENCE
   if (Op->ModRM == 0xE8) {
-    _Fence(IR::Fence_Load);
+    _Fence(FenceType::Load);
   } else {
     XRstorOpImpl(Op);
   }
@@ -4802,7 +4802,7 @@ void OpDispatchBuilder::LoadFenceOrXRSTOR(OpcodeArgs) {
 void OpDispatchBuilder::MemFenceOrXSAVEOPT(OpcodeArgs) {
   if (Op->ModRM == 0xF0) {
     // 0xF0 is MFENCE
-    _Fence(FEXCore::IR::Fence_LoadStore);
+    _Fence(FenceType::LoadStore);
   } else {
     XSaveOp(Op);
   }
@@ -4811,7 +4811,7 @@ void OpDispatchBuilder::MemFenceOrXSAVEOPT(OpcodeArgs) {
 void OpDispatchBuilder::StoreFenceOrCLFlush(OpcodeArgs) {
   if (Op->ModRM == 0xF8) {
     // 0xF8 is SFENCE
-    _Fence({FEXCore::IR::Fence_Store});
+    _Fence(FenceType::Store);
   } else {
     // This is a CLFlush
     Ref DestMem = MakeSegmentAddress(Op, Op->Dest);
diff --git a/FEXCore/Source/Interface/IR/IR.h b/FEXCore/Source/Interface/IR/IR.h
index 56ad2266b..96c92e6b6 100644
--- a/FEXCore/Source/Interface/IR/IR.h
+++ b/FEXCore/Source/Interface/IR/IR.h
@@ -488,17 +488,6 @@ struct FEX_PACKED TypeDefinition final {
 
 static_assert(std::is_trivially_copyable_v<TypeDefinition>);
 
-struct FEX_PACKED FenceType final {
-  using value_type = uint8_t;
-
-  value_type Val;
-  [[nodiscard]] constexpr operator value_type() const {
-    return Val;
-  }
-  [[nodiscard]]
-  friend constexpr bool operator==(const FenceType&, const FenceType&) = default;
-};
-
 struct FEX_PACKED RoundType final {
   uint8_t Val;
   [[nodiscard]] constexpr operator uint8_t() const {
@@ -805,12 +794,12 @@ struct fmt::formatter<FEXCore::IR::RegisterClassType> : fmt::formatter<FEXCore::
 };
 
 template<>
-struct fmt::formatter<FEXCore::IR::FenceType> : fmt::formatter<FEXCore::IR::FenceType::value_type> {
-  using Base = fmt::formatter<FEXCore::IR::FenceType::value_type>;
+struct fmt::formatter<FEXCore::IR::FenceType> : fmt::formatter<std::underlying_type_t<FEXCore::IR::FenceType>> {
+  using Base = fmt::formatter<std::underlying_type_t<FEXCore::IR::FenceType>>;
 
   template<typename FormatContext>
   auto format(const FEXCore::IR::FenceType& Fence, FormatContext& ctx) const {
-    return Base::format(Fence.Val, ctx);
+    return Base::format(FEXCore::ToUnderlying(Fence), ctx);
   }
 };
 
diff --git a/FEXCore/Source/Interface/IR/IR.json b/FEXCore/Source/Interface/IR/IR.json
index 406f22949..bbf69e348 100644
--- a/FEXCore/Source/Interface/IR/IR.json
+++ b/FEXCore/Source/Interface/IR/IR.json
@@ -79,6 +79,12 @@
       "FNU   = 21, /* float not unordered */",
       "",
       "AL    = 32, /* always */"
+    ],
+    "class FenceType : uint8_t": [
+      "Load      = 0,",
+      "Store     = 1,",
+      "LoadStore = 2,",
+      "Inst      = 3,"
     ]
   },
   "Defines": [
@@ -108,11 +114,6 @@
     "constexpr uint8_t FCMP_FLAG_LT        = 1",
     "constexpr uint8_t FCMP_FLAG_UNORDERED = 2",
 
-    "constexpr FEXCore::IR::FenceType Fence_Load      {0}",
-    "constexpr FEXCore::IR::FenceType Fence_Store     {1}",
-    "constexpr FEXCore::IR::FenceType Fence_LoadStore {2}",
-    "constexpr FEXCore::IR::FenceType Fence_Inst      {3}",
-
     "constexpr uint8_t ROUND_MODE_NEAREST           = 0",
     "constexpr uint8_t ROUND_MODE_NEGATIVE_INFINITY = 1",
     "constexpr uint8_t ROUND_MODE_POSITIVE_INFINITY = 2",
@@ -764,9 +765,9 @@
       },
       "Fence FenceType:$Fence": {
         "Desc": ["Does a memory fence operation of the desired type",
-                 "Fence_Load: Ensures load memory operations are serialized",
-                 "Fence_Store: Ensures store memory operations are serialized",
-                 "Fence_LoadStore: Ensures loads and store memory operations are serialized",
+                 "FenceType::Load: Ensures load memory operations are serialized",
+                 "FenceType::Store: Ensures store memory operations are serialized",
+                 "FenceType::LoadStore: Ensures loads and store memory operations are serialized",
                  "Ensures the memory operations are globally visible"
                 ],
         "HasSideEffects": true
diff --git a/FEXCore/Source/Interface/IR/IRDumper.cpp b/FEXCore/Source/Interface/IR/IRDumper.cpp
index 8150c33f6..2130f8881 100644
--- a/FEXCore/Source/Interface/IR/IRDumper.cpp
+++ b/FEXCore/Source/Interface/IR/IRDumper.cpp
@@ -124,12 +124,12 @@ static void PrintArg(fextl::stringstream* out, const IRListView* IR, OrderedNode
   }
 }
 
-static void PrintArg(fextl::stringstream* out, const IRListView*, FEXCore::IR::FenceType Arg) {
-  if (Arg == IR::Fence_Load) {
+static void PrintArg(fextl::stringstream* out, const IRListView*, FenceType Arg) {
+  if (Arg == FenceType::Load) {
     *out << "Loads";
-  } else if (Arg == IR::Fence_Store) {
+  } else if (Arg == FenceType::Store) {
     *out << "Stores";
-  } else if (Arg == IR::Fence_LoadStore) {
+  } else if (Arg == FenceType::LoadStore) {
     *out << "LoadStores";
   } else {
     *out << "<Unknown Fence Type>";
diff --git a/FEXCore/Source/Interface/IR/Passes/RegisterAllocationPass.cpp b/FEXCore/Source/Interface/IR/Passes/RegisterAllocationPass.cpp
index 1a50f2eb8..80ef39c0c 100644
--- a/FEXCore/Source/Interface/IR/Passes/RegisterAllocationPass.cpp
+++ b/FEXCore/Source/Interface/IR/Passes/RegisterAllocationPass.cpp
@@ -530,7 +530,7 @@ bool ConstrainedRAPass::TryPostRAMerge(Ref LastNode, Ref CodeNode, IROp_Header*
       const auto Result = CPUID->RunFunction(ConstantFunction, 0 /* leaf */);
 
       IREmit->SetWriteCursorBefore(CodeNode);
-      IREmit->_Fence({FEXCore::IR::Fence_Inst});
+      IREmit->_Fence(IR::FenceType::Inst);
       IREmit->_Constant(Result.eax).Node->Reg = PhysicalRegister(Op->OutEAX).Raw;
       IREmit->_Constant(Result.ebx).Node->Reg = PhysicalRegister(Op->OutEBX).Raw;
       IREmit->_Constant(Result.ecx).Node->Reg = PhysicalRegister(Op->OutECX).Raw;