diff --git a/FEXCore/Source/Interface/Core/JIT/Arm64/VectorOps.cpp b/FEXCore/Source/Interface/Core/JIT/Arm64/VectorOps.cpp
index cc8a6aa3d..75024ddd9 100644
--- a/FEXCore/Source/Interface/Core/JIT/Arm64/VectorOps.cpp
+++ b/FEXCore/Source/Interface/Core/JIT/Arm64/VectorOps.cpp
@@ -1262,10 +1262,15 @@ DEF_OP(VSMin) {
   if (HostSupportsSVE256 && Is256Bit) {
     const auto Pred = PRED_TMP_32B.Merging();
 
-    // SVE SMIN is a destructive operation, so we need a temporary.
-    movprfx(VTMP1.Z(), Vector1.Z());
-    smin(SubRegSize, VTMP1.Z(), Pred, VTMP1.Z(), Vector2.Z());
-    mov(Dst.Z(), VTMP1.Z());
+    if (Dst == Vector1) {
+      // Trivial case where we can perform the operation in place.
+      smin(SubRegSize, Dst.Z(), Pred, Dst.Z(), Vector2.Z());
+    } else {
+      // SVE SMIN is a destructive operation, so we need a temporary.
+      movprfx(VTMP1.Z(), Vector1.Z());
+      smin(SubRegSize, VTMP1.Z(), Pred, VTMP1.Z(), Vector2.Z());
+      mov(Dst.Z(), VTMP1.Z());
+    }
   } else {
     switch (ElementSize) {
       case 1:
diff --git a/unittests/InstructionCountCI/VEX_map1.json b/unittests/InstructionCountCI/VEX_map1.json
index 31ac7d985..26a9b7f12 100644
--- a/unittests/InstructionCountCI/VEX_map1.json
+++ b/unittests/InstructionCountCI/VEX_map1.json
@@ -5959,7 +5959,7 @@
       ]
     },
     "vpminsw ymm0, ymm1, ymm2": {
-      "ExpectedInstructionCount": 6,
+      "ExpectedInstructionCount": 4,
       "Optimal": "No",
       "Comment": [
         "Map 1 0b01 0xea 256-bit"
@@ -5967,9 +5967,7 @@
       "ExpectedArm64ASM": [
         "mov z4.d, p7/m, z17.d",
         "mov z5.d, p7/m, z18.d",
-        "movprfx z0, z4",
-        "smin z0.h, p7/m, z0.h, z5.h",
-        "mov z4.d, z0.d",
+        "smin z4.h, p7/m, z4.h, z5.h",
         "mov z16.d, p7/m, z4.d"
       ]
     },
diff --git a/unittests/InstructionCountCI/VEX_map2.json b/unittests/InstructionCountCI/VEX_map2.json
index 3b002a406..27da7d621 100644
--- a/unittests/InstructionCountCI/VEX_map2.json
+++ b/unittests/InstructionCountCI/VEX_map2.json
@@ -1625,7 +1625,7 @@
       ]
     },
     "vpminsb ymm0, ymm1, ymm2": {
-      "ExpectedInstructionCount": 6,
+      "ExpectedInstructionCount": 4,
       "Optimal": "No",
       "Comment": [
         "Map 2 0b01 0x38 256-bit"
@@ -1633,9 +1633,7 @@
       "ExpectedArm64ASM": [
         "mov z4.d, p7/m, z17.d",
         "mov z5.d, p7/m, z18.d",
-        "movprfx z0, z4",
-        "smin z0.b, p7/m, z0.b, z5.b",
-        "mov z4.d, z0.d",
+        "smin z4.b, p7/m, z4.b, z5.b",
         "mov z16.d, p7/m, z4.d"
       ]
     },
@@ -1654,7 +1652,7 @@
       ]
     },
     "vpminsd ymm0, ymm1, ymm2": {
-      "ExpectedInstructionCount": 6,
+      "ExpectedInstructionCount": 4,
       "Optimal": "No",
       "Comment": [
         "Map 2 0b01 0x39 256-bit"
@@ -1662,9 +1660,7 @@
       "ExpectedArm64ASM": [
         "mov z4.d, p7/m, z17.d",
         "mov z5.d, p7/m, z18.d",
-        "movprfx z0, z4",
-        "smin z0.s, p7/m, z0.s, z5.s",
-        "mov z4.d, z0.d",
+        "smin z4.s, p7/m, z4.s, z5.s",
         "mov z16.d, p7/m, z4.d"
       ]
     },