From 764c844225c40e6e1400ae7832bf3ffbfcf5603e Mon Sep 17 00:00:00 2001 From: Lioncache Date: Thu, 17 Aug 2023 16:51:44 -0400 Subject: [PATCH] OpcodeDispatcher: Improve output of {V}MOVSHDUP --- .../Interface/Core/OpcodeDispatcher.cpp | 2 +- .../Source/Interface/Core/OpcodeDispatcher.h | 1 - .../Core/OpcodeDispatcher/Vector.cpp | 22 +--------- .../InstructionCountCI/Secondary_REP.json | 22 +++------- unittests/InstructionCountCI/VEX_map1.json | 41 ++----------------- 5 files changed, 13 insertions(+), 75 deletions(-) diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp index 3bd656645..e34b85f65 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp @@ -6534,7 +6534,7 @@ void InstallOpcodeHandlers(Context::OperatingMode Mode) { constexpr std::tuple RepModOpTable[] = { {0x10, 2, &OpDispatchBuilder::MOVSSOp}, {0x12, 1, &OpDispatchBuilder::VMOVSLDUPOp}, - {0x16, 1, &OpDispatchBuilder::MOVSHDUPOp}, + {0x16, 1, &OpDispatchBuilder::VMOVSHDUPOp}, {0x19, 7, &OpDispatchBuilder::NOPOp}, {0x2A, 1, &OpDispatchBuilder::CVTGPR_To_FPR<4>}, {0x2B, 1, &OpDispatchBuilder::MOVVectorOp}, diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher.h b/FEXCore/Source/Interface/Core/OpcodeDispatcher.h index a8242c6f7..a39aff41d 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher.h +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher.h @@ -316,7 +316,6 @@ public: void MOVAPSOp(OpcodeArgs); void MOVUPSOp(OpcodeArgs); void MOVLPOp(OpcodeArgs); - void MOVSHDUPOp(OpcodeArgs); void MOVHPDOp(OpcodeArgs); void MOVSDOp(OpcodeArgs); template diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp index 788eaa109..0ab2d57a7 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp @@ -151,28 +151,10 @@ void OpDispatchBuilder::VMOVLPOp(OpcodeArgs) { } } -void OpDispatchBuilder::MOVSHDUPOp(OpcodeArgs) { - OrderedNode *Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags, 8); - OrderedNode *Result = _VInsElement(16, 4, 2, 3, Src, Src); - Result = _VInsElement(16, 4, 0, 1, Result, Src); - StoreResult(FPRClass, Op, Result, -1); -} - void OpDispatchBuilder::VMOVSHDUPOp(OpcodeArgs) { - OrderedNode *Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags, -1); const auto SrcSize = GetSrcSize(Op); - const auto Is256Bit = SrcSize == Core::CPUState::XMM_AVX_REG_SIZE; - - OrderedNode *Result = _VInsElement(SrcSize, 4, 2, 3, Src, Src); - Result = _VInsElement(SrcSize, 4, 0, 1, Result, Src); - if (Is256Bit) { - Result = _VInsElement(SrcSize, 4, 4, 5, Result, Src); - Result = _VInsElement(SrcSize, 4, 6, 7, Result, Src); - } else { - // Clear upper lane - Result = _VMov(16, Result); - } - + OrderedNode *Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags, -1); + OrderedNode *Result = _VTrn2(SrcSize, 4, Src, Src); StoreResult(FPRClass, Op, Result, -1); } diff --git a/unittests/InstructionCountCI/Secondary_REP.json b/unittests/InstructionCountCI/Secondary_REP.json index 5a4dc97d1..c6bfa9634 100644 --- a/unittests/InstructionCountCI/Secondary_REP.json +++ b/unittests/InstructionCountCI/Secondary_REP.json @@ -50,30 +50,20 @@ ] }, "movshdup xmm0, xmm1": { - "ExpectedInstructionCount": 6, - "Optimal": "No", + "ExpectedInstructionCount": 1, + "Optimal": "Yes", "Comment": "0xf3 0x0f 0x16", "ExpectedArm64ASM": [ - "mov v0.16b, v17.16b", - "mov v0.s[2], v17.s[3]", - "mov v4.16b, v0.16b", - "mov v0.16b, v4.16b", - "mov v0.s[0], v17.s[1]", - "mov v16.16b, v0.16b" + "trn2 v16.4s, v17.4s, v17.4s" ] }, "movshdup xmm0, [rax]": { - "ExpectedInstructionCount": 7, - "Optimal": "No", + "ExpectedInstructionCount": 2, + "Optimal": "Yes", "Comment": "0xf3 0x0f 0x16", "ExpectedArm64ASM": [ "ldr q4, [x4]", - "mov v0.16b, v4.16b", - "mov v0.s[2], v4.s[3]", - "mov v5.16b, v0.16b", - "mov v0.16b, v5.16b", - "mov v0.s[0], v4.s[1]", - "mov v16.16b, v0.16b" + "trn2 v16.4s, v4.4s, v4.4s" ] }, "cvtsi2ss xmm0, eax": { diff --git a/unittests/InstructionCountCI/VEX_map1.json b/unittests/InstructionCountCI/VEX_map1.json index 30788f0f6..675fc03da 100644 --- a/unittests/InstructionCountCI/VEX_map1.json +++ b/unittests/InstructionCountCI/VEX_map1.json @@ -516,60 +516,27 @@ ] }, "vmovshdup xmm0, [rax]": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 4, "Optimal": "No", "Comment": [ "Map 1 0b10 0x16 128-bit" ], "ExpectedArm64ASM": [ "ldr q4, [x4]", - "mov v0.16b, v4.16b", - "mov v0.s[2], v4.s[3]", - "mov v5.16b, v0.16b", - "mov v0.16b, v5.16b", - "mov v0.s[0], v4.s[1]", - "mov v4.16b, v0.16b", - "mov v4.16b, v4.16b", + "trn2 v4.4s, v4.4s, v4.4s", "mov v4.16b, v4.16b", "mov z16.d, p7/m, z4.d" ] }, "vmovshdup ymm0, [rax]": { - "ExpectedInstructionCount": 30, + "ExpectedInstructionCount": 3, "Optimal": "No", "Comment": [ "Map 1 0b10 0x16 256-bit" ], "ExpectedArm64ASM": [ "ld1b {z4.b}, p7/z, [x4]", - "adr x0, #+0x18", - "ldr p0, [x0]", - "mov z1.s, z4.s[3]", - "mov z5.d, z4.d", - "mov z5.s, p0/m, z1.s", - "b #+0x8", - "udf #0x100", - "adr x0, #+0x18", - "ldr p0, [x0]", - "mov z1.s, z4.s[1]", - "mov z5.d, z5.d", - "mov z5.s, p0/m, z1.s", - "b #+0x8", - "udf #0x1", - "adr x0, #+0x18", - "ldr p0, [x0]", - "mov z1.s, z4.s[5]", - "mov z5.d, z5.d", - "mov z5.s, p0/m, z1.s", - "b #+0x8", - "unallocated (Unallocated)", - "adr x0, #+0x18", - "ldr p0, [x0]", - "mov z1.s, z4.s[7]", - "mov z4.d, z5.d", - "mov z4.s, p0/m, z1.s", - "b #+0x8", - "unallocated (Unallocated)", + "trn2 z4.s, z4.s, z4.s", "mov z16.d, p7/m, z4.d" ] },