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Merge pull request #3082 from Sonicadvance1/minor_storeregsra_opt

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FEXCore: Minor optimization to StoreRegisterSRA
This commit is contained in:
Ryan Houdek authored and GitHub committed 2023-09-14 14:54:39 -07:00
2 parents e1eb151051 b2e61d2deb
commit 6fdf2f963b
3 files changed
+57 -121
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FEXCore/Source/Interface/Core/JIT/Arm64/MemoryOps.cpp
+3 -21
View File
@@ -302,16 +302,6 @@ DEF_OP(LoadRegisterSRA) {
const auto reg = StaticRegisters[regId]; const auto reg = StaticRegisters[regId];
switch (OpSize) { switch (OpSize) {
case 1:
LOGMAN_THROW_AA_FMT(regOffs == 0 || regOffs == 1, "unexpected regOffs");
ubfx(ARMEmitter::Size::i64Bit, GetReg(Node), reg, regOffs * 8, 8);
break;
case 2:
LOGMAN_THROW_AA_FMT(regOffs == 0, "unexpected regOffs");
ubfx(ARMEmitter::Size::i64Bit, GetReg(Node), reg, 0, 16);
break;
case 4: case 4:
LOGMAN_THROW_AA_FMT(regOffs == 0, "unexpected regOffs"); LOGMAN_THROW_AA_FMT(regOffs == 0, "unexpected regOffs");
if (GetReg(Node).Idx() != reg.Idx()) if (GetReg(Node).Idx() != reg.Idx())
@@ -491,19 +481,11 @@ DEF_OP(StoreRegisterSRA) {
const auto Src = GetReg(Op->Value.ID()); const auto Src = GetReg(Op->Value.ID());
switch (OpSize) { switch (OpSize) {
case 1:
LOGMAN_THROW_AA_FMT(regOffs == 0 || regOffs == 1, "unexpected regOffs");
bfi(ARMEmitter::Size::i64Bit, reg, Src, regOffs * 8, 8);
break;
case 2:
LOGMAN_THROW_AA_FMT(regOffs == 0, "unexpected regOffs");
bfi(ARMEmitter::Size::i64Bit, reg, Src, 0, 16);
break;
case 4: case 4:
LOGMAN_THROW_AA_FMT(regOffs == 0, "unexpected regOffs"); LOGMAN_THROW_AA_FMT(regOffs == 0, "unexpected regOffs");
bfi(ARMEmitter::Size::i64Bit, reg, Src, 0, 32); if (Src.Idx() != reg.Idx()) {
mov(ARMEmitter::Size::i32Bit, reg, Src);
}
break; break;
case 8: case 8:
LOGMAN_THROW_AA_FMT(regOffs == 0, "unexpected regOffs"); LOGMAN_THROW_AA_FMT(regOffs == 0, "unexpected regOffs");
unittests/InstructionCountCI/Primary_32Bit.json
+46 -88
View File
@@ -9,23 +9,21 @@
}, },
"Instructions": { "Instructions": {
"push es": { "push es": {
"ExpectedInstructionCount": 3, "ExpectedInstructionCount": 2,
"Optimal": "No", "Optimal": "Yes",
"Comment": "0x06", "Comment": "0x06",
"ExpectedArm64ASM": [ "ExpectedArm64ASM": [
"ldrh w20, [x28, #136]", "ldrh w20, [x28, #136]",
"str w20, [x8, #-4]!", "str w20, [x8, #-4]!"
"bfxil x8, x8, #0, #32"
] ]
}, },
"pop es": { "pop es": {
"ExpectedInstructionCount": 8, "ExpectedInstructionCount": 7,
"Optimal": "No", "Optimal": "No",
"Comment": "0x07", "Comment": "0x07",
"ExpectedArm64ASM": [ "ExpectedArm64ASM": [
"ldr w20, [x8]", "ldr w20, [x8]",
"add x8, x8, #0x4 (4)", "add x8, x8, #0x4 (4)",
"bfxil x8, x8, #0, #32",
"strh w20, [x28, #136]", "strh w20, [x28, #136]",
"ubfx w20, w20, #3, #13", "ubfx w20, w20, #3, #13",
"add x0, x28, x20, lsl #2", "add x0, x28, x20, lsl #2",
@@ -34,33 +32,30 @@
] ]
}, },
"push cs": { "push cs": {
"ExpectedInstructionCount": 3, "ExpectedInstructionCount": 2,
"Optimal": "No", "Optimal": "Yes",
"Comment": "0x0e", "Comment": "0x0e",
"ExpectedArm64ASM": [ "ExpectedArm64ASM": [
"ldrh w20, [x28, #138]", "ldrh w20, [x28, #138]",
"str w20, [x8, #-4]!", "str w20, [x8, #-4]!"
"bfxil x8, x8, #0, #32"
] ]
}, },
"push ss": { "push ss": {
"ExpectedInstructionCount": 3, "ExpectedInstructionCount": 2,
"Optimal": "No", "Optimal": "Yes",
"Comment": "0x16", "Comment": "0x16",
"ExpectedArm64ASM": [ "ExpectedArm64ASM": [
"ldrh w20, [x28, #140]", "ldrh w20, [x28, #140]",
"str w20, [x8, #-4]!", "str w20, [x8, #-4]!"
"bfxil x8, x8, #0, #32"
] ]
}, },
"pop ss": { "pop ss": {
"ExpectedInstructionCount": 8, "ExpectedInstructionCount": 7,
"Optimal": "No", "Optimal": "No",
"Comment": "0x17", "Comment": "0x17",
"ExpectedArm64ASM": [ "ExpectedArm64ASM": [
"ldr w20, [x8]", "ldr w20, [x8]",
"add x8, x8, #0x4 (4)", "add x8, x8, #0x4 (4)",
"bfxil x8, x8, #0, #32",
"strh w20, [x28, #140]", "strh w20, [x28, #140]",
"ubfx w20, w20, #3, #13", "ubfx w20, w20, #3, #13",
"add x0, x28, x20, lsl #2", "add x0, x28, x20, lsl #2",
@@ -69,23 +64,21 @@
] ]
}, },
"push ds": { "push ds": {
"ExpectedInstructionCount": 3, "ExpectedInstructionCount": 2,
"Optimal": "No", "Optimal": "Yes",
"Comment": "0x1e", "Comment": "0x1e",
"ExpectedArm64ASM": [ "ExpectedArm64ASM": [
"ldrh w20, [x28, #142]", "ldrh w20, [x28, #142]",
"str w20, [x8, #-4]!", "str w20, [x8, #-4]!"
"bfxil x8, x8, #0, #32"
] ]
}, },
"pop ds": { "pop ds": {
"ExpectedInstructionCount": 8, "ExpectedInstructionCount": 7,
"Optimal": "No", "Optimal": "No",
"Comment": "0x1f", "Comment": "0x1f",
"ExpectedArm64ASM": [ "ExpectedArm64ASM": [
"ldr w20, [x8]", "ldr w20, [x8]",
"add x8, x8, #0x4 (4)", "add x8, x8, #0x4 (4)",
"bfxil x8, x8, #0, #32",
"strh w20, [x28, #142]", "strh w20, [x28, #142]",
"ubfx w20, w20, #3, #13", "ubfx w20, w20, #3, #13",
"add x0, x28, x20, lsl #2", "add x0, x28, x20, lsl #2",
@@ -94,7 +87,7 @@
] ]
}, },
"daa": { "daa": {
"ExpectedInstructionCount": 59, "ExpectedInstructionCount": 57,
"Optimal": "No", "Optimal": "No",
"Comment": "0x27", "Comment": "0x27",
"ExpectedArm64ASM": [ "ExpectedArm64ASM": [
@@ -114,10 +107,9 @@
"cbnz x20, #+0x10", "cbnz x20, #+0x10",
"mov w20, #0x0", "mov w20, #0x0",
"strb w20, [x28, #708]", "strb w20, [x28, #708]",
"b #+0x2c", "b #+0x28",
"add x20, x23, #0x6 (6)", "add x20, x23, #0x6 (6)",
"bfxil w4, w20, #0, #8", "bfxil w4, w20, #0, #8",
"bfxil x4, x4, #0, #32",
"ldr w20, [x28, #728]", "ldr w20, [x28, #728]",
"ubfx w22, w20, #29, #1", "ubfx w22, w20, #29, #1",
"orr x22, x21, x22", "orr x22, x21, x22",
@@ -132,11 +124,10 @@
"ldr w20, [x28, #728]", "ldr w20, [x28, #728]",
"and w20, w20, #0xdfffffff", "and w20, w20, #0xdfffffff",
"str w20, [x28, #728]", "str w20, [x28, #728]",
"b #+0x20", "b #+0x1c",
"uxtb w20, w4", "uxtb w20, w4",
"add x20, x20, #0x60 (96)", "add x20, x20, #0x60 (96)",
"bfxil w4, w20, #0, #8", "bfxil w4, w20, #0, #8",
"bfxil x4, x4, #0, #32",
"ldr w20, [x28, #728]", "ldr w20, [x28, #728]",
"orr w20, w20, #0x20000000", "orr w20, w20, #0x20000000",
"str w20, [x28, #728]", "str w20, [x28, #728]",
@@ -160,7 +151,7 @@
] ]
}, },
"das": { "das": {
"ExpectedInstructionCount": 59, "ExpectedInstructionCount": 57,
"Optimal": "No", "Optimal": "No",
"Comment": "0x2f", "Comment": "0x2f",
"ExpectedArm64ASM": [ "ExpectedArm64ASM": [
@@ -180,10 +171,9 @@
"cbnz x20, #+0x10", "cbnz x20, #+0x10",
"mov w20, #0x0", "mov w20, #0x0",
"strb w20, [x28, #708]", "strb w20, [x28, #708]",
"b #+0x2c", "b #+0x28",
"sub x20, x23, #0x6 (6)", "sub x20, x23, #0x6 (6)",
"bfxil w4, w20, #0, #8", "bfxil w4, w20, #0, #8",
"bfxil x4, x4, #0, #32",
"ldr w20, [x28, #728]", "ldr w20, [x28, #728]",
"ubfx w22, w20, #29, #1", "ubfx w22, w20, #29, #1",
"orr x22, x21, x22", "orr x22, x21, x22",
@@ -198,11 +188,10 @@
"ldr w20, [x28, #728]", "ldr w20, [x28, #728]",
"and w20, w20, #0xdfffffff", "and w20, w20, #0xdfffffff",
"str w20, [x28, #728]", "str w20, [x28, #728]",
"b #+0x20", "b #+0x1c",
"uxtb w20, w4", "uxtb w20, w4",
"sub x20, x20, #0x60 (96)", "sub x20, x20, #0x60 (96)",
"bfxil w4, w20, #0, #8", "bfxil w4, w20, #0, #8",
"bfxil x4, x4, #0, #32",
"ldr w20, [x28, #728]", "ldr w20, [x28, #728]",
"orr w20, w20, #0x20000000", "orr w20, w20, #0x20000000",
"str w20, [x28, #728]", "str w20, [x28, #728]",
@@ -226,7 +215,7 @@
] ]
}, },
"aaa": { "aaa": {
"ExpectedInstructionCount": 30, "ExpectedInstructionCount": 28,
"Optimal": "No", "Optimal": "No",
"Comment": "0x37", "Comment": "0x37",
"ExpectedArm64ASM": [ "ExpectedArm64ASM": [
@@ -240,21 +229,19 @@
"cmp x21, #0x9 (9)", "cmp x21, #0x9 (9)",
"cset x21, hi", "cset x21, hi",
"orr x20, x20, x21", "orr x20, x20, x21",
"cbnz x20, #+0x28", "cbnz x20, #+0x24",
"mov w20, #0xff0f", "mov w20, #0xff0f",
"and x20, x22, x20", "and x20, x22, x20",
"bfxil w4, w20, #0, #16", "bfxil w4, w20, #0, #16",
"bfxil x4, x4, #0, #32",
"mov w20, #0x0", "mov w20, #0x0",
"mov w21, #0x0", "mov w21, #0x0",
"strb w20, [x28, #708]", "strb w20, [x28, #708]",
"str w21, [x28, #728]", "str w21, [x28, #728]",
"b #+0x2c", "b #+0x28",
"add x20, x22, #0x106 (262)", "add x20, x22, #0x106 (262)",
"mov w21, #0xff0f", "mov w21, #0xff0f",
"and x20, x20, x21", "and x20, x20, x21",
"bfxil w4, w20, #0, #16", "bfxil w4, w20, #0, #16",
"bfxil x4, x4, #0, #32",
"ldr w20, [x28, #728]", "ldr w20, [x28, #728]",
"orr w20, w20, #0x20000000", "orr w20, w20, #0x20000000",
"mov w21, #0x10", "mov w21, #0x10",
@@ -263,7 +250,7 @@
] ]
}, },
"aas": { "aas": {
"ExpectedInstructionCount": 31, "ExpectedInstructionCount": 29,
"Optimal": "No", "Optimal": "No",
"Comment": "0x3f", "Comment": "0x3f",
"ExpectedArm64ASM": [ "ExpectedArm64ASM": [
@@ -277,22 +264,20 @@
"cmp x21, #0x9 (9)", "cmp x21, #0x9 (9)",
"cset x21, hi", "cset x21, hi",
"orr x20, x20, x21", "orr x20, x20, x21",
"cbnz x20, #+0x28", "cbnz x20, #+0x24",
"mov w20, #0xff0f", "mov w20, #0xff0f",
"and x20, x22, x20", "and x20, x22, x20",
"bfxil w4, w20, #0, #16", "bfxil w4, w20, #0, #16",
"bfxil x4, x4, #0, #32",
"mov w20, #0x0", "mov w20, #0x0",
"mov w21, #0x0", "mov w21, #0x0",
"strb w20, [x28, #708]", "strb w20, [x28, #708]",
"str w21, [x28, #728]", "str w21, [x28, #728]",
"b #+0x30", "b #+0x2c",
"sub x20, x22, #0x6 (6)", "sub x20, x22, #0x6 (6)",
"sub x20, x20, #0x100 (256)", "sub x20, x20, #0x100 (256)",
"mov w21, #0xff0f", "mov w21, #0xff0f",
"and x20, x20, x21", "and x20, x20, x21",
"bfxil w4, w20, #0, #16", "bfxil w4, w20, #0, #16",
"bfxil x4, x4, #0, #32",
"ldr w20, [x28, #728]", "ldr w20, [x28, #728]",
"orr w20, w20, #0x20000000", "orr w20, w20, #0x20000000",
"mov w21, #0x10", "mov w21, #0x10",
@@ -301,14 +286,13 @@
] ]
}, },
"inc ax": { "inc ax": {
"ExpectedInstructionCount": 22, "ExpectedInstructionCount": 21,
"Optimal": "No", "Optimal": "No",
"Comment": "0x40", "Comment": "0x40",
"ExpectedArm64ASM": [ "ExpectedArm64ASM": [
"uxth w20, w4", "uxth w20, w4",
"add w21, w20, #0x1 (1)", "add w21, w20, #0x1 (1)",
"bfxil w4, w21, #0, #16", "bfxil w4, w21, #0, #16",
"bfxil x4, x4, #0, #32",
"uxth w21, w21", "uxth w21, w21",
"eor w22, w20, #0x1", "eor w22, w20, #0x1",
"strb w22, [x28, #708]", "strb w22, [x28, #708]",
@@ -330,13 +314,12 @@
] ]
}, },
"inc eax": { "inc eax": {
"ExpectedInstructionCount": 12, "ExpectedInstructionCount": 11,
"Optimal": "No", "Optimal": "No",
"Comment": "0x40", "Comment": "0x40",
"ExpectedArm64ASM": [ "ExpectedArm64ASM": [
"mov w20, w4", "mov w20, w4",
"add w4, w20, #0x1 (1)", "add w4, w20, #0x1 (1)",
"bfxil x4, x4, #0, #32",
"eor w21, w20, #0x1", "eor w21, w20, #0x1",
"strb w21, [x28, #708]", "strb w21, [x28, #708]",
"strb w4, [x28, #706]", "strb w4, [x28, #706]",
@@ -349,14 +332,13 @@
] ]
}, },
"dec ax": { "dec ax": {
"ExpectedInstructionCount": 22, "ExpectedInstructionCount": 21,
"Optimal": "No", "Optimal": "No",
"Comment": "0x48", "Comment": "0x48",
"ExpectedArm64ASM": [ "ExpectedArm64ASM": [
"uxth w20, w4", "uxth w20, w4",
"sub w21, w20, #0x1 (1)", "sub w21, w20, #0x1 (1)",
"bfxil w4, w21, #0, #16", "bfxil w4, w21, #0, #16",
"bfxil x4, x4, #0, #32",
"uxth w21, w21", "uxth w21, w21",
"eor w22, w20, #0x1", "eor w22, w20, #0x1",
"strb w22, [x28, #708]", "strb w22, [x28, #708]",
@@ -378,13 +360,12 @@
] ]
}, },
"dec eax": { "dec eax": {
"ExpectedInstructionCount": 13, "ExpectedInstructionCount": 12,
"Optimal": "No", "Optimal": "No",
"Comment": "0x48", "Comment": "0x48",
"ExpectedArm64ASM": [ "ExpectedArm64ASM": [
"mov w20, w4", "mov w20, w4",
"sub w4, w20, #0x1 (1)", "sub w4, w20, #0x1 (1)",
"bfxil x4, x4, #0, #32",
"eor w21, w20, #0x1", "eor w21, w20, #0x1",
"strb w21, [x28, #708]", "strb w21, [x28, #708]",
"strb w4, [x28, #706]", "strb w4, [x28, #706]",
@@ -398,8 +379,8 @@
] ]
}, },
"pusha": { "pusha": {
"ExpectedInstructionCount": 11, "ExpectedInstructionCount": 10,
"Optimal": "No", "Optimal": "Yes",
"Comment": "0x60", "Comment": "0x60",
"ExpectedArm64ASM": [ "ExpectedArm64ASM": [
"mov w20, w8", "mov w20, w8",
@@ -411,13 +392,12 @@
"str w9, [x20, #-4]!", "str w9, [x20, #-4]!",
"str w10, [x20, #-4]!", "str w10, [x20, #-4]!",
"mov w8, w20", "mov w8, w20",
"str w11, [x8, #-4]!", "str w11, [x8, #-4]!"
"bfxil x8, x8, #0, #32"
] ]
}, },
"pushad": { "pushad": {
"ExpectedInstructionCount": 11, "ExpectedInstructionCount": 10,
"Optimal": "No", "Optimal": "Yes",
"Comment": "0x60", "Comment": "0x60",
"ExpectedArm64ASM": [ "ExpectedArm64ASM": [
"mov w20, w8", "mov w20, w8",
@@ -429,70 +409,53 @@
"str w9, [x20, #-4]!", "str w9, [x20, #-4]!",
"str w10, [x20, #-4]!", "str w10, [x20, #-4]!",
"mov w8, w20", "mov w8, w20",
"str w11, [x8, #-4]!", "str w11, [x8, #-4]!"
"bfxil x8, x8, #0, #32"
] ]
}, },
"popa": { "popa": {
"ExpectedInstructionCount": 22, "ExpectedInstructionCount": 14,
"Optimal": "No", "Optimal": "No",
"Comment": "0x61", "Comment": "0x61",
"ExpectedArm64ASM": [ "ExpectedArm64ASM": [
"ldr w11, [x8]", "ldr w11, [x8]",
"bfxil x11, x11, #0, #32",
"add x20, x8, #0x4 (4)", "add x20, x8, #0x4 (4)",
"ldr w10, [x8, #4]", "ldr w10, [x8, #4]",
"bfxil x10, x10, #0, #32",
"add x21, x20, #0x4 (4)", "add x21, x20, #0x4 (4)",
"ldr w9, [x20, #4]", "ldr w9, [x20, #4]",
"bfxil x9, x9, #0, #32",
"add x20, x21, #0x8 (8)", "add x20, x21, #0x8 (8)",
"ldr w7, [x21, #8]", "ldr w7, [x21, #8]",
"bfxil x7, x7, #0, #32",
"add x21, x20, #0x4 (4)", "add x21, x20, #0x4 (4)",
"ldr w6, [x20, #4]", "ldr w6, [x20, #4]",
"bfxil x6, x6, #0, #32",
"add x20, x21, #0x4 (4)", "add x20, x21, #0x4 (4)",
"ldr w5, [x21, #4]", "ldr w5, [x21, #4]",
"bfxil x5, x5, #0, #32",
"add x21, x20, #0x4 (4)", "add x21, x20, #0x4 (4)",
"ldr w4, [x20, #4]", "ldr w4, [x20, #4]",
"bfxil x4, x4, #0, #32", "add x8, x21, #0x4 (4)"
"add x8, x21, #0x4 (4)",
"bfxil x8, x8, #0, #32"
] ]
}, },
"popad": { "popad": {
"ExpectedInstructionCount": 22, "ExpectedInstructionCount": 14,
"Optimal": "No", "Optimal": "No",
"Comment": "0x61", "Comment": "0x61",
"ExpectedArm64ASM": [ "ExpectedArm64ASM": [
"ldr w11, [x8]", "ldr w11, [x8]",
"bfxil x11, x11, #0, #32",
"add x20, x8, #0x4 (4)", "add x20, x8, #0x4 (4)",
"ldr w10, [x8, #4]", "ldr w10, [x8, #4]",
"bfxil x10, x10, #0, #32",
"add x21, x20, #0x4 (4)", "add x21, x20, #0x4 (4)",
"ldr w9, [x20, #4]", "ldr w9, [x20, #4]",
"bfxil x9, x9, #0, #32",
"add x20, x21, #0x8 (8)", "add x20, x21, #0x8 (8)",
"ldr w7, [x21, #8]", "ldr w7, [x21, #8]",
"bfxil x7, x7, #0, #32",
"add x21, x20, #0x4 (4)", "add x21, x20, #0x4 (4)",
"ldr w6, [x20, #4]", "ldr w6, [x20, #4]",
"bfxil x6, x6, #0, #32",
"add x20, x21, #0x4 (4)", "add x20, x21, #0x4 (4)",
"ldr w5, [x21, #4]", "ldr w5, [x21, #4]",
"bfxil x5, x5, #0, #32",
"add x21, x20, #0x4 (4)", "add x21, x20, #0x4 (4)",
"ldr w4, [x20, #4]", "ldr w4, [x20, #4]",
"bfxil x4, x4, #0, #32", "add x8, x21, #0x4 (4)"
"add x8, x21, #0x4 (4)",
"bfxil x8, x8, #0, #32"
] ]
}, },
"aam": { "aam": {
"ExpectedInstructionCount": 20, "ExpectedInstructionCount": 19,
"Optimal": "No", "Optimal": "No",
"Comment": "0xd4", "Comment": "0xd4",
"ExpectedArm64ASM": [ "ExpectedArm64ASM": [
@@ -504,7 +467,6 @@
"lsl x21, x22, #8", "lsl x21, x22, #8",
"add x20, x21, x20", "add x20, x21, x20",
"bfxil w4, w20, #0, #16", "bfxil w4, w20, #0, #16",
"bfxil x4, x4, #0, #32",
"uxtb w20, w4", "uxtb w20, w4",
"and x21, x20, #0x80", "and x21, x20, #0x80",
"cmp x21, #0x0 (0)", "cmp x21, #0x0 (0)",
@@ -519,7 +481,7 @@
] ]
}, },
"aad": { "aad": {
"ExpectedInstructionCount": 20, "ExpectedInstructionCount": 19,
"Optimal": "No", "Optimal": "No",
"Comment": "0xd5", "Comment": "0xd5",
"ExpectedArm64ASM": [ "ExpectedArm64ASM": [
@@ -531,7 +493,6 @@
"add x20, x20, x21", "add x20, x20, x21",
"and x20, x20, #0xff", "and x20, x20, #0xff",
"bfxil w4, w20, #0, #16", "bfxil w4, w20, #0, #16",
"bfxil x4, x4, #0, #32",
"uxtb w20, w4", "uxtb w20, w4",
"and x21, x20, #0x80", "and x21, x20, #0x80",
"cmp x21, #0x0 (0)", "cmp x21, #0x0 (0)",
@@ -546,7 +507,7 @@
] ]
}, },
"db 0xd4, 0x40": { "db 0xd4, 0x40": {
"ExpectedInstructionCount": 20, "ExpectedInstructionCount": 19,
"Optimal": "No", "Optimal": "No",
"Comment": [ "Comment": [
"aam with a different immediate byte base", "aam with a different immediate byte base",
@@ -561,7 +522,6 @@
"lsl x21, x22, #8", "lsl x21, x22, #8",
"add x20, x21, x20", "add x20, x21, x20",
"bfxil w4, w20, #0, #16", "bfxil w4, w20, #0, #16",
"bfxil x4, x4, #0, #32",
"uxtb w20, w4", "uxtb w20, w4",
"and x21, x20, #0x80", "and x21, x20, #0x80",
"cmp x21, #0x0 (0)", "cmp x21, #0x0 (0)",
@@ -576,7 +536,7 @@
] ]
}, },
"db 0xd5, 0x40": { "db 0xd5, 0x40": {
"ExpectedInstructionCount": 19, "ExpectedInstructionCount": 18,
"Optimal": "No", "Optimal": "No",
"Comment": [ "Comment": [
"aad with a different immediate byte base", "aad with a different immediate byte base",
@@ -590,7 +550,6 @@
"add x20, x20, x21", "add x20, x20, x21",
"and x20, x20, #0xff", "and x20, x20, #0xff",
"bfxil w4, w20, #0, #16", "bfxil w4, w20, #0, #16",
"bfxil x4, x4, #0, #32",
"uxtb w20, w4", "uxtb w20, w4",
"and x21, x20, #0x80", "and x21, x20, #0x80",
"cmp x21, #0x0 (0)", "cmp x21, #0x0 (0)",
@@ -605,7 +564,7 @@
] ]
}, },
"salc": { "salc": {
"ExpectedInstructionCount": 9, "ExpectedInstructionCount": 8,
"Optimal": "No", "Optimal": "No",
"Comment": "0xd6", "Comment": "0xd6",
"ExpectedArm64ASM": [ "ExpectedArm64ASM": [
@@ -616,7 +575,6 @@
"uxtb w22, w4", "uxtb w22, w4",
"sub w20, w22, w20", "sub w20, w22, w20",
"bfxil w4, w20, #0, #8", "bfxil w4, w20, #0, #8",
"bfxil x4, x4, #0, #32",
"str w21, [x28, #728]" "str w21, [x28, #728]"
] ]
} }
unittests/InstructionCountCI/Secondary_32Bit.json
+8 -12
View File
@@ -9,23 +9,21 @@
}, },
"Instructions": { "Instructions": {
"push fs": { "push fs": {
"ExpectedInstructionCount": 3, "ExpectedInstructionCount": 2,
"Optimal": "No", "Optimal": "Yes",
"Comment": "0x0f 0xa0", "Comment": "0x0f 0xa0",
"ExpectedArm64ASM": [ "ExpectedArm64ASM": [
"ldrh w20, [x28, #146]", "ldrh w20, [x28, #146]",
"str w20, [x8, #-4]!", "str w20, [x8, #-4]!"
"bfxil x8, x8, #0, #32"
] ]
}, },
"pop fs": { "pop fs": {
"ExpectedInstructionCount": 8, "ExpectedInstructionCount": 7,
"Optimal": "No", "Optimal": "No",
"Comment": "0x0f 0xa1", "Comment": "0x0f 0xa1",
"ExpectedArm64ASM": [ "ExpectedArm64ASM": [
"ldr w20, [x8]", "ldr w20, [x8]",
"add x8, x8, #0x4 (4)", "add x8, x8, #0x4 (4)",
"bfxil x8, x8, #0, #32",
"strh w20, [x28, #146]", "strh w20, [x28, #146]",
"ubfx w20, w20, #3, #13", "ubfx w20, w20, #3, #13",
"add x0, x28, x20, lsl #2", "add x0, x28, x20, lsl #2",
@@ -34,23 +32,21 @@
] ]
}, },
"push gs": { "push gs": {
"ExpectedInstructionCount": 3, "ExpectedInstructionCount": 2,
"Optimal": "No", "Optimal": "Yes",
"Comment": "0x0f 0xa8", "Comment": "0x0f 0xa8",
"ExpectedArm64ASM": [ "ExpectedArm64ASM": [
"ldrh w20, [x28, #144]", "ldrh w20, [x28, #144]",
"str w20, [x8, #-4]!", "str w20, [x8, #-4]!"
"bfxil x8, x8, #0, #32"
] ]
}, },
"pop gs": { "pop gs": {
"ExpectedInstructionCount": 8, "ExpectedInstructionCount": 7,
"Optimal": "No", "Optimal": "No",
"Comment": "0x0f 0xa9", "Comment": "0x0f 0xa9",
"ExpectedArm64ASM": [ "ExpectedArm64ASM": [
"ldr w20, [x8]", "ldr w20, [x8]",
"add x8, x8, #0x4 (4)", "add x8, x8, #0x4 (4)",
"bfxil x8, x8, #0, #32",
"strh w20, [x28, #144]", "strh w20, [x28, #144]",
"ubfx w20, w20, #3, #13", "ubfx w20, w20, #3, #13",
"add x0, x28, x20, lsl #2", "add x0, x28, x20, lsl #2",