mirror of
https://github.com/FEX-Emu/FEX.git
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Merge pull request #3082 from Sonicadvance1/minor_storeregsra_opt
FEXCore: Minor optimization to StoreRegisterSRA
This commit is contained in:
3 files changed
+57
-121
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@@ -302,16 +302,6 @@ DEF_OP(LoadRegisterSRA) {
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const auto reg = StaticRegisters[regId];
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switch (OpSize) {
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case 1:
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LOGMAN_THROW_AA_FMT(regOffs == 0 || regOffs == 1, "unexpected regOffs");
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ubfx(ARMEmitter::Size::i64Bit, GetReg(Node), reg, regOffs * 8, 8);
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break;
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case 2:
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LOGMAN_THROW_AA_FMT(regOffs == 0, "unexpected regOffs");
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ubfx(ARMEmitter::Size::i64Bit, GetReg(Node), reg, 0, 16);
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break;
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case 4:
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LOGMAN_THROW_AA_FMT(regOffs == 0, "unexpected regOffs");
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if (GetReg(Node).Idx() != reg.Idx())
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@@ -491,19 +481,11 @@ DEF_OP(StoreRegisterSRA) {
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const auto Src = GetReg(Op->Value.ID());
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switch (OpSize) {
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case 1:
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LOGMAN_THROW_AA_FMT(regOffs == 0 || regOffs == 1, "unexpected regOffs");
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bfi(ARMEmitter::Size::i64Bit, reg, Src, regOffs * 8, 8);
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break;
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case 2:
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LOGMAN_THROW_AA_FMT(regOffs == 0, "unexpected regOffs");
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bfi(ARMEmitter::Size::i64Bit, reg, Src, 0, 16);
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break;
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case 4:
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LOGMAN_THROW_AA_FMT(regOffs == 0, "unexpected regOffs");
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bfi(ARMEmitter::Size::i64Bit, reg, Src, 0, 32);
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if (Src.Idx() != reg.Idx()) {
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mov(ARMEmitter::Size::i32Bit, reg, Src);
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}
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break;
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case 8:
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LOGMAN_THROW_AA_FMT(regOffs == 0, "unexpected regOffs");
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@@ -9,23 +9,21 @@
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},
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"Instructions": {
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"push es": {
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"ExpectedInstructionCount": 3,
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"Optimal": "No",
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"ExpectedInstructionCount": 2,
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"Optimal": "Yes",
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"Comment": "0x06",
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"ExpectedArm64ASM": [
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"ldrh w20, [x28, #136]",
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"str w20, [x8, #-4]!",
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"bfxil x8, x8, #0, #32"
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"str w20, [x8, #-4]!"
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]
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},
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"pop es": {
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"ExpectedInstructionCount": 8,
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"ExpectedInstructionCount": 7,
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"Optimal": "No",
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"Comment": "0x07",
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"ExpectedArm64ASM": [
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"ldr w20, [x8]",
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"add x8, x8, #0x4 (4)",
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"bfxil x8, x8, #0, #32",
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"strh w20, [x28, #136]",
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"ubfx w20, w20, #3, #13",
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"add x0, x28, x20, lsl #2",
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@@ -34,33 +32,30 @@
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]
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},
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"push cs": {
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"ExpectedInstructionCount": 3,
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"Optimal": "No",
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"ExpectedInstructionCount": 2,
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"Optimal": "Yes",
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"Comment": "0x0e",
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"ExpectedArm64ASM": [
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"ldrh w20, [x28, #138]",
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"str w20, [x8, #-4]!",
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"bfxil x8, x8, #0, #32"
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"str w20, [x8, #-4]!"
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]
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},
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"push ss": {
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"ExpectedInstructionCount": 3,
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"Optimal": "No",
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"ExpectedInstructionCount": 2,
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"Optimal": "Yes",
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"Comment": "0x16",
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"ExpectedArm64ASM": [
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"ldrh w20, [x28, #140]",
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"str w20, [x8, #-4]!",
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"bfxil x8, x8, #0, #32"
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"str w20, [x8, #-4]!"
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]
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},
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"pop ss": {
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"ExpectedInstructionCount": 8,
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"ExpectedInstructionCount": 7,
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"Optimal": "No",
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"Comment": "0x17",
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"ExpectedArm64ASM": [
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"ldr w20, [x8]",
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"add x8, x8, #0x4 (4)",
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"bfxil x8, x8, #0, #32",
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"strh w20, [x28, #140]",
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"ubfx w20, w20, #3, #13",
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"add x0, x28, x20, lsl #2",
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@@ -69,23 +64,21 @@
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]
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},
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"push ds": {
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"ExpectedInstructionCount": 3,
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"Optimal": "No",
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"ExpectedInstructionCount": 2,
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"Optimal": "Yes",
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"Comment": "0x1e",
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"ExpectedArm64ASM": [
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"ldrh w20, [x28, #142]",
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"str w20, [x8, #-4]!",
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"bfxil x8, x8, #0, #32"
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"str w20, [x8, #-4]!"
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]
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},
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"pop ds": {
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"ExpectedInstructionCount": 8,
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"ExpectedInstructionCount": 7,
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"Optimal": "No",
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"Comment": "0x1f",
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"ExpectedArm64ASM": [
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"ldr w20, [x8]",
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"add x8, x8, #0x4 (4)",
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"bfxil x8, x8, #0, #32",
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"strh w20, [x28, #142]",
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"ubfx w20, w20, #3, #13",
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"add x0, x28, x20, lsl #2",
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@@ -94,7 +87,7 @@
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]
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},
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"daa": {
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"ExpectedInstructionCount": 59,
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"ExpectedInstructionCount": 57,
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"Optimal": "No",
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"Comment": "0x27",
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"ExpectedArm64ASM": [
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@@ -114,10 +107,9 @@
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"cbnz x20, #+0x10",
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"mov w20, #0x0",
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"strb w20, [x28, #708]",
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"b #+0x2c",
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"b #+0x28",
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"add x20, x23, #0x6 (6)",
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"bfxil w4, w20, #0, #8",
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"bfxil x4, x4, #0, #32",
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"ldr w20, [x28, #728]",
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"ubfx w22, w20, #29, #1",
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"orr x22, x21, x22",
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@@ -132,11 +124,10 @@
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"ldr w20, [x28, #728]",
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"and w20, w20, #0xdfffffff",
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"str w20, [x28, #728]",
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"b #+0x20",
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"b #+0x1c",
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"uxtb w20, w4",
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"add x20, x20, #0x60 (96)",
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"bfxil w4, w20, #0, #8",
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"bfxil x4, x4, #0, #32",
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"ldr w20, [x28, #728]",
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"orr w20, w20, #0x20000000",
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"str w20, [x28, #728]",
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@@ -160,7 +151,7 @@
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]
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},
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"das": {
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"ExpectedInstructionCount": 59,
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"ExpectedInstructionCount": 57,
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"Optimal": "No",
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"Comment": "0x2f",
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"ExpectedArm64ASM": [
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@@ -180,10 +171,9 @@
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"cbnz x20, #+0x10",
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"mov w20, #0x0",
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"strb w20, [x28, #708]",
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"b #+0x2c",
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"b #+0x28",
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"sub x20, x23, #0x6 (6)",
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"bfxil w4, w20, #0, #8",
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"bfxil x4, x4, #0, #32",
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"ldr w20, [x28, #728]",
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"ubfx w22, w20, #29, #1",
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"orr x22, x21, x22",
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@@ -198,11 +188,10 @@
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"ldr w20, [x28, #728]",
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"and w20, w20, #0xdfffffff",
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"str w20, [x28, #728]",
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"b #+0x20",
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"b #+0x1c",
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"uxtb w20, w4",
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"sub x20, x20, #0x60 (96)",
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"bfxil w4, w20, #0, #8",
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"bfxil x4, x4, #0, #32",
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"ldr w20, [x28, #728]",
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"orr w20, w20, #0x20000000",
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"str w20, [x28, #728]",
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@@ -226,7 +215,7 @@
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]
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},
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"aaa": {
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"ExpectedInstructionCount": 30,
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"ExpectedInstructionCount": 28,
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"Optimal": "No",
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"Comment": "0x37",
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"ExpectedArm64ASM": [
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@@ -240,21 +229,19 @@
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"cmp x21, #0x9 (9)",
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"cset x21, hi",
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"orr x20, x20, x21",
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"cbnz x20, #+0x28",
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"cbnz x20, #+0x24",
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"mov w20, #0xff0f",
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"and x20, x22, x20",
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"bfxil w4, w20, #0, #16",
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"bfxil x4, x4, #0, #32",
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"mov w20, #0x0",
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"mov w21, #0x0",
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"strb w20, [x28, #708]",
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"str w21, [x28, #728]",
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"b #+0x2c",
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"b #+0x28",
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"add x20, x22, #0x106 (262)",
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"mov w21, #0xff0f",
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"and x20, x20, x21",
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"bfxil w4, w20, #0, #16",
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"bfxil x4, x4, #0, #32",
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"ldr w20, [x28, #728]",
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"orr w20, w20, #0x20000000",
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"mov w21, #0x10",
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@@ -263,7 +250,7 @@
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]
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},
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"aas": {
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"ExpectedInstructionCount": 31,
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||||
"ExpectedInstructionCount": 29,
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||||
"Optimal": "No",
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||||
"Comment": "0x3f",
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||||
"ExpectedArm64ASM": [
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@@ -277,22 +264,20 @@
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"cmp x21, #0x9 (9)",
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"cset x21, hi",
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"orr x20, x20, x21",
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"cbnz x20, #+0x28",
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"cbnz x20, #+0x24",
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"mov w20, #0xff0f",
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"and x20, x22, x20",
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"bfxil w4, w20, #0, #16",
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"bfxil x4, x4, #0, #32",
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"mov w20, #0x0",
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"mov w21, #0x0",
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"strb w20, [x28, #708]",
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"str w21, [x28, #728]",
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"b #+0x30",
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"b #+0x2c",
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"sub x20, x22, #0x6 (6)",
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"sub x20, x20, #0x100 (256)",
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"mov w21, #0xff0f",
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"and x20, x20, x21",
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"bfxil w4, w20, #0, #16",
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"bfxil x4, x4, #0, #32",
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"ldr w20, [x28, #728]",
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"orr w20, w20, #0x20000000",
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"mov w21, #0x10",
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@@ -301,14 +286,13 @@
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||||
]
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||||
},
|
||||
"inc ax": {
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||||
"ExpectedInstructionCount": 22,
|
||||
"ExpectedInstructionCount": 21,
|
||||
"Optimal": "No",
|
||||
"Comment": "0x40",
|
||||
"ExpectedArm64ASM": [
|
||||
"uxth w20, w4",
|
||||
"add w21, w20, #0x1 (1)",
|
||||
"bfxil w4, w21, #0, #16",
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||||
"bfxil x4, x4, #0, #32",
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||||
"uxth w21, w21",
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||||
"eor w22, w20, #0x1",
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||||
"strb w22, [x28, #708]",
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||||
@@ -330,13 +314,12 @@
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||||
]
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||||
},
|
||||
"inc eax": {
|
||||
"ExpectedInstructionCount": 12,
|
||||
"ExpectedInstructionCount": 11,
|
||||
"Optimal": "No",
|
||||
"Comment": "0x40",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov w20, w4",
|
||||
"add w4, w20, #0x1 (1)",
|
||||
"bfxil x4, x4, #0, #32",
|
||||
"eor w21, w20, #0x1",
|
||||
"strb w21, [x28, #708]",
|
||||
"strb w4, [x28, #706]",
|
||||
@@ -349,14 +332,13 @@
|
||||
]
|
||||
},
|
||||
"dec ax": {
|
||||
"ExpectedInstructionCount": 22,
|
||||
"ExpectedInstructionCount": 21,
|
||||
"Optimal": "No",
|
||||
"Comment": "0x48",
|
||||
"ExpectedArm64ASM": [
|
||||
"uxth w20, w4",
|
||||
"sub w21, w20, #0x1 (1)",
|
||||
"bfxil w4, w21, #0, #16",
|
||||
"bfxil x4, x4, #0, #32",
|
||||
"uxth w21, w21",
|
||||
"eor w22, w20, #0x1",
|
||||
"strb w22, [x28, #708]",
|
||||
@@ -378,13 +360,12 @@
|
||||
]
|
||||
},
|
||||
"dec eax": {
|
||||
"ExpectedInstructionCount": 13,
|
||||
"ExpectedInstructionCount": 12,
|
||||
"Optimal": "No",
|
||||
"Comment": "0x48",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov w20, w4",
|
||||
"sub w4, w20, #0x1 (1)",
|
||||
"bfxil x4, x4, #0, #32",
|
||||
"eor w21, w20, #0x1",
|
||||
"strb w21, [x28, #708]",
|
||||
"strb w4, [x28, #706]",
|
||||
@@ -398,8 +379,8 @@
|
||||
]
|
||||
},
|
||||
"pusha": {
|
||||
"ExpectedInstructionCount": 11,
|
||||
"Optimal": "No",
|
||||
"ExpectedInstructionCount": 10,
|
||||
"Optimal": "Yes",
|
||||
"Comment": "0x60",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov w20, w8",
|
||||
@@ -411,13 +392,12 @@
|
||||
"str w9, [x20, #-4]!",
|
||||
"str w10, [x20, #-4]!",
|
||||
"mov w8, w20",
|
||||
"str w11, [x8, #-4]!",
|
||||
"bfxil x8, x8, #0, #32"
|
||||
"str w11, [x8, #-4]!"
|
||||
]
|
||||
},
|
||||
"pushad": {
|
||||
"ExpectedInstructionCount": 11,
|
||||
"Optimal": "No",
|
||||
"ExpectedInstructionCount": 10,
|
||||
"Optimal": "Yes",
|
||||
"Comment": "0x60",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov w20, w8",
|
||||
@@ -429,70 +409,53 @@
|
||||
"str w9, [x20, #-4]!",
|
||||
"str w10, [x20, #-4]!",
|
||||
"mov w8, w20",
|
||||
"str w11, [x8, #-4]!",
|
||||
"bfxil x8, x8, #0, #32"
|
||||
"str w11, [x8, #-4]!"
|
||||
]
|
||||
},
|
||||
"popa": {
|
||||
"ExpectedInstructionCount": 22,
|
||||
"ExpectedInstructionCount": 14,
|
||||
"Optimal": "No",
|
||||
"Comment": "0x61",
|
||||
"ExpectedArm64ASM": [
|
||||
"ldr w11, [x8]",
|
||||
"bfxil x11, x11, #0, #32",
|
||||
"add x20, x8, #0x4 (4)",
|
||||
"ldr w10, [x8, #4]",
|
||||
"bfxil x10, x10, #0, #32",
|
||||
"add x21, x20, #0x4 (4)",
|
||||
"ldr w9, [x20, #4]",
|
||||
"bfxil x9, x9, #0, #32",
|
||||
"add x20, x21, #0x8 (8)",
|
||||
"ldr w7, [x21, #8]",
|
||||
"bfxil x7, x7, #0, #32",
|
||||
"add x21, x20, #0x4 (4)",
|
||||
"ldr w6, [x20, #4]",
|
||||
"bfxil x6, x6, #0, #32",
|
||||
"add x20, x21, #0x4 (4)",
|
||||
"ldr w5, [x21, #4]",
|
||||
"bfxil x5, x5, #0, #32",
|
||||
"add x21, x20, #0x4 (4)",
|
||||
"ldr w4, [x20, #4]",
|
||||
"bfxil x4, x4, #0, #32",
|
||||
"add x8, x21, #0x4 (4)",
|
||||
"bfxil x8, x8, #0, #32"
|
||||
"add x8, x21, #0x4 (4)"
|
||||
]
|
||||
},
|
||||
"popad": {
|
||||
"ExpectedInstructionCount": 22,
|
||||
"ExpectedInstructionCount": 14,
|
||||
"Optimal": "No",
|
||||
"Comment": "0x61",
|
||||
"ExpectedArm64ASM": [
|
||||
"ldr w11, [x8]",
|
||||
"bfxil x11, x11, #0, #32",
|
||||
"add x20, x8, #0x4 (4)",
|
||||
"ldr w10, [x8, #4]",
|
||||
"bfxil x10, x10, #0, #32",
|
||||
"add x21, x20, #0x4 (4)",
|
||||
"ldr w9, [x20, #4]",
|
||||
"bfxil x9, x9, #0, #32",
|
||||
"add x20, x21, #0x8 (8)",
|
||||
"ldr w7, [x21, #8]",
|
||||
"bfxil x7, x7, #0, #32",
|
||||
"add x21, x20, #0x4 (4)",
|
||||
"ldr w6, [x20, #4]",
|
||||
"bfxil x6, x6, #0, #32",
|
||||
"add x20, x21, #0x4 (4)",
|
||||
"ldr w5, [x21, #4]",
|
||||
"bfxil x5, x5, #0, #32",
|
||||
"add x21, x20, #0x4 (4)",
|
||||
"ldr w4, [x20, #4]",
|
||||
"bfxil x4, x4, #0, #32",
|
||||
"add x8, x21, #0x4 (4)",
|
||||
"bfxil x8, x8, #0, #32"
|
||||
"add x8, x21, #0x4 (4)"
|
||||
]
|
||||
},
|
||||
"aam": {
|
||||
"ExpectedInstructionCount": 20,
|
||||
"ExpectedInstructionCount": 19,
|
||||
"Optimal": "No",
|
||||
"Comment": "0xd4",
|
||||
"ExpectedArm64ASM": [
|
||||
@@ -504,7 +467,6 @@
|
||||
"lsl x21, x22, #8",
|
||||
"add x20, x21, x20",
|
||||
"bfxil w4, w20, #0, #16",
|
||||
"bfxil x4, x4, #0, #32",
|
||||
"uxtb w20, w4",
|
||||
"and x21, x20, #0x80",
|
||||
"cmp x21, #0x0 (0)",
|
||||
@@ -519,7 +481,7 @@
|
||||
]
|
||||
},
|
||||
"aad": {
|
||||
"ExpectedInstructionCount": 20,
|
||||
"ExpectedInstructionCount": 19,
|
||||
"Optimal": "No",
|
||||
"Comment": "0xd5",
|
||||
"ExpectedArm64ASM": [
|
||||
@@ -531,7 +493,6 @@
|
||||
"add x20, x20, x21",
|
||||
"and x20, x20, #0xff",
|
||||
"bfxil w4, w20, #0, #16",
|
||||
"bfxil x4, x4, #0, #32",
|
||||
"uxtb w20, w4",
|
||||
"and x21, x20, #0x80",
|
||||
"cmp x21, #0x0 (0)",
|
||||
@@ -546,7 +507,7 @@
|
||||
]
|
||||
},
|
||||
"db 0xd4, 0x40": {
|
||||
"ExpectedInstructionCount": 20,
|
||||
"ExpectedInstructionCount": 19,
|
||||
"Optimal": "No",
|
||||
"Comment": [
|
||||
"aam with a different immediate byte base",
|
||||
@@ -561,7 +522,6 @@
|
||||
"lsl x21, x22, #8",
|
||||
"add x20, x21, x20",
|
||||
"bfxil w4, w20, #0, #16",
|
||||
"bfxil x4, x4, #0, #32",
|
||||
"uxtb w20, w4",
|
||||
"and x21, x20, #0x80",
|
||||
"cmp x21, #0x0 (0)",
|
||||
@@ -576,7 +536,7 @@
|
||||
]
|
||||
},
|
||||
"db 0xd5, 0x40": {
|
||||
"ExpectedInstructionCount": 19,
|
||||
"ExpectedInstructionCount": 18,
|
||||
"Optimal": "No",
|
||||
"Comment": [
|
||||
"aad with a different immediate byte base",
|
||||
@@ -590,7 +550,6 @@
|
||||
"add x20, x20, x21",
|
||||
"and x20, x20, #0xff",
|
||||
"bfxil w4, w20, #0, #16",
|
||||
"bfxil x4, x4, #0, #32",
|
||||
"uxtb w20, w4",
|
||||
"and x21, x20, #0x80",
|
||||
"cmp x21, #0x0 (0)",
|
||||
@@ -605,7 +564,7 @@
|
||||
]
|
||||
},
|
||||
"salc": {
|
||||
"ExpectedInstructionCount": 9,
|
||||
"ExpectedInstructionCount": 8,
|
||||
"Optimal": "No",
|
||||
"Comment": "0xd6",
|
||||
"ExpectedArm64ASM": [
|
||||
@@ -616,7 +575,6 @@
|
||||
"uxtb w22, w4",
|
||||
"sub w20, w22, w20",
|
||||
"bfxil w4, w20, #0, #8",
|
||||
"bfxil x4, x4, #0, #32",
|
||||
"str w21, [x28, #728]"
|
||||
]
|
||||
}
|
||||
|
||||
@@ -9,23 +9,21 @@
|
||||
},
|
||||
"Instructions": {
|
||||
"push fs": {
|
||||
"ExpectedInstructionCount": 3,
|
||||
"Optimal": "No",
|
||||
"ExpectedInstructionCount": 2,
|
||||
"Optimal": "Yes",
|
||||
"Comment": "0x0f 0xa0",
|
||||
"ExpectedArm64ASM": [
|
||||
"ldrh w20, [x28, #146]",
|
||||
"str w20, [x8, #-4]!",
|
||||
"bfxil x8, x8, #0, #32"
|
||||
"str w20, [x8, #-4]!"
|
||||
]
|
||||
},
|
||||
"pop fs": {
|
||||
"ExpectedInstructionCount": 8,
|
||||
"ExpectedInstructionCount": 7,
|
||||
"Optimal": "No",
|
||||
"Comment": "0x0f 0xa1",
|
||||
"ExpectedArm64ASM": [
|
||||
"ldr w20, [x8]",
|
||||
"add x8, x8, #0x4 (4)",
|
||||
"bfxil x8, x8, #0, #32",
|
||||
"strh w20, [x28, #146]",
|
||||
"ubfx w20, w20, #3, #13",
|
||||
"add x0, x28, x20, lsl #2",
|
||||
@@ -34,23 +32,21 @@
|
||||
]
|
||||
},
|
||||
"push gs": {
|
||||
"ExpectedInstructionCount": 3,
|
||||
"Optimal": "No",
|
||||
"ExpectedInstructionCount": 2,
|
||||
"Optimal": "Yes",
|
||||
"Comment": "0x0f 0xa8",
|
||||
"ExpectedArm64ASM": [
|
||||
"ldrh w20, [x28, #144]",
|
||||
"str w20, [x8, #-4]!",
|
||||
"bfxil x8, x8, #0, #32"
|
||||
"str w20, [x8, #-4]!"
|
||||
]
|
||||
},
|
||||
"pop gs": {
|
||||
"ExpectedInstructionCount": 8,
|
||||
"ExpectedInstructionCount": 7,
|
||||
"Optimal": "No",
|
||||
"Comment": "0x0f 0xa9",
|
||||
"ExpectedArm64ASM": [
|
||||
"ldr w20, [x8]",
|
||||
"add x8, x8, #0x4 (4)",
|
||||
"bfxil x8, x8, #0, #32",
|
||||
"strh w20, [x28, #144]",
|
||||
"ubfx w20, w20, #3, #13",
|
||||
"add x0, x28, x20, lsl #2",
|
||||
|
||||
Reference in new issue
Block a user