diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
index 4ff689957..30a8ff648 100644
--- a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
+++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
@@ -1044,9 +1044,9 @@ void OpDispatchBuilder::CMPOp(OpcodeArgs, uint32_t SrcIndex) {
 }
 
 void OpDispatchBuilder::CQOOp(OpcodeArgs) {
-  Ref Src = LoadSource(GPRClass, Op, Op->Src[0], Op->Flags);
-  auto Size = GetSrcSize(Op);
-  Ref Upper = _Sbfe(OpSize::i64Bit, 1, Size * 8 - 1, Src);
+  Ref Src = LoadSource(GPRClass, Op, Op->Src[0], Op->Flags, {.AllowUpperGarbage = true});
+  auto Size = OpSizeFromSrc(Op);
+  Ref Upper = _Sbfe(std::max(OpSize::i32Bit, Size), 1, GetSrcBitSize(Op) - 1, Src);
 
   StoreResult(GPRClass, Op, Upper, OpSize::iInvalid);
 }
diff --git a/unittests/InstructionCountCI/FEXOpt/MultiInst.json b/unittests/InstructionCountCI/FEXOpt/MultiInst.json
index 1c5fb1ddf..b042b36df 100644
--- a/unittests/InstructionCountCI/FEXOpt/MultiInst.json
+++ b/unittests/InstructionCountCI/FEXOpt/MultiInst.json
@@ -153,7 +153,7 @@
     },
     "signed div narrow": {
       "x86InstructionCount": 2,
-      "ExpectedInstructionCount": 31,
+      "ExpectedInstructionCount": 29,
       "Comment": [
         "div narrowing with known smaller sources",
         "dividend in rdx:rax"
@@ -163,9 +163,7 @@
         "idiv rcx"
       ],
       "ExpectedArm64ASM": [
-        "mov w20, w4",
-        "sbfx x20, x20, #31, #1",
-        "mov w5, w20",
+        "asr w5, w4, #31",
         "asr x0, x4, #63",
         "eor x0, x0, x5",
         "cbz x0, #+0x28",
diff --git a/unittests/InstructionCountCI/Primary.json b/unittests/InstructionCountCI/Primary.json
index 2544d7923..dd743ce9b 100644
--- a/unittests/InstructionCountCI/Primary.json
+++ b/unittests/InstructionCountCI/Primary.json
@@ -2598,21 +2598,18 @@
       ]
     },
     "cwd": {
-      "ExpectedInstructionCount": 3,
+      "ExpectedInstructionCount": 2,
       "Comment": "0x98",
       "ExpectedArm64ASM": [
-        "uxth w20, w4",
-        "sbfx x20, x20, #15, #1",
+        "sbfx w20, w4, #15, #1",
         "bfxil x5, x20, #0, #16"
       ]
     },
     "cdq": {
-      "ExpectedInstructionCount": 3,
+      "ExpectedInstructionCount": 1,
       "Comment": "0x99",
       "ExpectedArm64ASM": [
-        "mov w20, w4",
-        "sbfx x20, x20, #31, #1",
-        "mov w5, w20"
+        "asr w5, w4, #31"
       ]
     },
     "cqo": {