diff --git a/FEXCore/Source/Interface/Core/DiskCache.h b/FEXCore/Source/Interface/Core/DiskCache.h
index 35d51cd0a..3784e4768 100644
--- a/FEXCore/Source/Interface/Core/DiskCache.h
+++ b/FEXCore/Source/Interface/Core/DiskCache.h
@@ -244,7 +244,7 @@ namespace DiskCache {
   // The current version of the diskcache.
   // This must be changed any time codegen changes occur!
   // Be aware of the impact of changing this frequently!
-  static constexpr uint16_t FormatVersion = 25;
+  static constexpr uint16_t FormatVersion = 26;
 
   static constexpr uint32_t LOOKUP_KEY_MAX_BUCKET_DEPTH = 20;
 
diff --git a/FEXCore/Source/Interface/Core/Dispatcher/Dispatcher.cpp b/FEXCore/Source/Interface/Core/Dispatcher/Dispatcher.cpp
index b174dab3c..62b5940fe 100644
--- a/FEXCore/Source/Interface/Core/Dispatcher/Dispatcher.cpp
+++ b/FEXCore/Source/Interface/Core/Dispatcher/Dispatcher.cpp
@@ -276,8 +276,15 @@ void Dispatcher::EmitDispatcher() {
     str(TMP2, STATE, offsetof(FEXCore::Core::CPUState, DeferredSignalRefCount));
 
     // Trigger segfault if any deferred signals are pending
-    strb(ARMEmitter::XReg::zr, STATE,
-         offsetof(FEXCore::Core::InternalThreadState, InterruptFaultPage) - offsetof(FEXCore::Core::InternalThreadState, BaseFrameState));
+    constexpr size_t InterruptPageOffset =
+      offsetof(FEXCore::Core::InternalThreadState, InterruptFaultPage) - offsetof(FEXCore::Core::InternalThreadState, BaseFrameState);
+    if constexpr (InterruptPageOffset <= 32760) {
+      str(ARMEmitter::XReg::zr, STATE, InterruptPageOffset);
+    } else {
+      // Need to use vector 128-bit store for this range.
+      // Doesn't matter which register we use to store.
+      str(ARMEmitter::QReg::q0, STATE, InterruptPageOffset);
+    }
 #endif
   };
 
@@ -507,6 +514,42 @@ void Dispatcher::EmitDispatcher() {
     (void)b(&LoopTop);
   }
 
+  {
+    // All dynamic and static registers are spilled coming in to this handler.
+    // It's also the end of block and RIP might have changed, so we jump directly to the top of the loop.
+    ThreadDispatchSyscallHandler = GetCursorAddress<uint64_t>();
+
+    // Store in the state that we are in a syscall
+    // 16bit LoadConstant to be a single instruction
+    // This gives the signal handler a value to check to see if we are in a syscall at all
+    LoadConstant(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r0, 0xFFFF);
+    str(ARMEmitter::XReg::x0, STATE, offsetof(FEXCore::Core::CpuStateFrame, InSyscallInfo));
+
+    ldr(ARMEmitter::XReg::x0, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.SyscallHandlerObj));
+    ldr(ARMEmitter::XReg::x3, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.SyscallHandlerFunc));
+    mov(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r1, STATE.R());
+
+    if (!CTX->Config.DisableVixlIndirectCalls) [[unlikely]] {
+      GenerateIndirectRuntimeCall<uint64_t, void*, void*, void*>(ARMEmitter::Reg::r3);
+    } else {
+      blr(ARMEmitter::Reg::r3);
+    }
+
+    // Fix the stack and any values that were stepped on
+    // Syscall result is in any static register that the frontend desired.
+    FillStaticRegs({
+      .OptionalReg = ARMEmitter::Reg::r1,
+      .OptionalReg2 = ARMEmitter::Reg::r2,
+    });
+
+    // Now the registers we've spilled are back in their original host registers
+    // We can safely claim we are no longer in a syscall
+    str(ARMEmitter::XReg::zr, STATE, offsetof(FEXCore::Core::CpuStateFrame, InSyscallInfo));
+
+    // Now go back to the regular dispatcher loop
+    (void)b(&LoopTop);
+  }
+
   auto EmitLongALUOpHandler = [&](auto R, auto Offset) {
     auto Address = GetCursorAddress<uint64_t>();
 
@@ -2620,6 +2663,7 @@ void Dispatcher::InitThreadPointers(FEXCore::Core::InternalThreadState* Thread)
     Ptrs.ExitFunctionLinker = ExitFunctionLinkerAddress;
     Ptrs.ThreadStopHandlerSpillSRA = ThreadStopHandlerAddressSpillSRA;
     Ptrs.ThreadPauseHandlerSpillSRA = ThreadPauseHandlerAddressSpillSRA;
+    Ptrs.ThreadDispatchSyscallHandler = ThreadDispatchSyscallHandler;
     Ptrs.GuestSignal_SIGILL = GuestSignal_SIGILL;
     Ptrs.GuestSignal_SIGTRAP = GuestSignal_SIGTRAP;
     Ptrs.GuestSignal_SIGSEGV = GuestSignal_SIGSEGV;
diff --git a/FEXCore/Source/Interface/Core/Dispatcher/Dispatcher.h b/FEXCore/Source/Interface/Core/Dispatcher/Dispatcher.h
index b0f3d7a47..b2f979212 100644
--- a/FEXCore/Source/Interface/Core/Dispatcher/Dispatcher.h
+++ b/FEXCore/Source/Interface/Core/Dispatcher/Dispatcher.h
@@ -81,6 +81,7 @@ private:
   uint64_t AbsoluteLoopTopAddressEnterECFillSRA {};
   uint64_t ThreadPauseHandlerAddress {};
   uint64_t ThreadPauseHandlerAddressSpillSRA {};
+  uint64_t ThreadDispatchSyscallHandler {};
   uint64_t ExitFunctionLinkerAddress {};
   uint64_t SignalHandlerReturnAddress {};
   uint64_t SignalHandlerReturnAddressRT {};
diff --git a/FEXCore/Source/Interface/Core/JIT/BranchOps.cpp b/FEXCore/Source/Interface/Core/JIT/BranchOps.cpp
index 5852d1e8f..2d90c7291 100644
--- a/FEXCore/Source/Interface/Core/JIT/BranchOps.cpp
+++ b/FEXCore/Source/Interface/Core/JIT/BranchOps.cpp
@@ -283,51 +283,11 @@ DEF_OP(CondJump) {
 }
 
 DEF_OP(Syscall) {
-  // Arguments are passed as follows:
-  // X0: SyscallHandler
-  // X1: ThreadState
+  SpillStaticRegs(TMP1);
 
-  PushDynamicRegs(TMP1);
-
-  uint32_t GPRSpillMask = ~0U;
-  uint32_t FPRSpillMask = ~0U;
-
-  SpillStaticRegs(TMP1, {
-                          .GPRSpillMask = GPRSpillMask,
-                          .FPRSpillMask = FPRSpillMask,
-                        });
-
-  // Now that we are spilled, store in the state that we are in a syscall
-  // Still without overwriting registers that matter
-  // 16bit LoadConstant to be a single instruction
-  // This gives the signal handler a value to check to see if we are in a syscall at all
-  LoadConstant(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r0, GPRSpillMask & 0xFFFF);
-  str(ARMEmitter::XReg::x0, STATE, offsetof(FEXCore::Core::CpuStateFrame, InSyscallInfo));
-
-  ldr(ARMEmitter::XReg::x0, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.SyscallHandlerObj));
-  ldr(ARMEmitter::XReg::x3, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.SyscallHandlerFunc));
-  mov(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r1, STATE.R());
-
-  if (!CTX->Config.DisableVixlIndirectCalls) [[unlikely]] {
-    GenerateIndirectRuntimeCall<uint64_t, void*, void*, void*>(ARMEmitter::Reg::r3);
-  } else {
-    blr(ARMEmitter::Reg::r3);
-  }
-
-  // Fix the stack and any values that were stepped on
-  // Syscall result is in any static register that the frontend desired.
-  FillStaticRegs({
-    .OptionalReg = ARMEmitter::Reg::r1,
-    .OptionalReg2 = ARMEmitter::Reg::r2,
-    .GPRFillMask = GPRSpillMask,
-    .FPRFillMask = FPRSpillMask,
-  });
-
-  // Now the registers we've spilled are back in their original host registers
-  // We can safely claim we are no longer in a syscall
-  str(ARMEmitter::XReg::zr, STATE, offsetof(FEXCore::Core::CpuStateFrame, InSyscallInfo));
-
-  PopDynamicRegs();
+  // Jump to the syscall dispatch handler. We won't return after this.
+  ldr(TMP1, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.ThreadDispatchSyscallHandler));
+  br(TMP1);
 }
 
 DEF_OP(Thunk) {
diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
index 5ee618981..8dc605ca7 100644
--- a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
+++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
@@ -59,12 +59,6 @@ void OpDispatchBuilder::SyscallOp(OpcodeArgs, bool IsSyscallInst) {
 
   FlushRegisterCache();
   _Syscall();
-
-  if (Op->TableInfo->Flags & X86Tables::InstFlags::FLAGS_BLOCK_END) {
-    // RIP could have been updated after coming back from the Syscall.
-    NewRIP = _LoadContextGPR(GPRSize, offsetof(FEXCore::Core::CPUState, rip));
-    ExitFunction(NewRIP);
-  }
 }
 
 void OpDispatchBuilder::ThunkOp(OpcodeArgs) {
diff --git a/FEXCore/Source/Interface/IR/IREmitter.cpp b/FEXCore/Source/Interface/IR/IREmitter.cpp
index a0b265166..ac187de31 100644
--- a/FEXCore/Source/Interface/IR/IREmitter.cpp
+++ b/FEXCore/Source/Interface/IR/IREmitter.cpp
@@ -19,6 +19,7 @@ namespace FEXCore::IR {
 
 static bool IsFragmentExit(FEXCore::IR::IROps Op) {
   switch (Op) {
+  case OP_SYSCALL:
   case OP_EXITFUNCTION:
   case OP_BREAK: return true;
   default: return false;
diff --git a/FEXCore/include/FEXCore/Core/CoreState.h b/FEXCore/include/FEXCore/Core/CoreState.h
index 0ac202eed..b62a46715 100644
--- a/FEXCore/include/FEXCore/Core/CoreState.h
+++ b/FEXCore/include/FEXCore/Core/CoreState.h
@@ -371,6 +371,7 @@ struct JITPointers {
   uint64_t ExitFunctionLinker {};
   uint64_t ThreadStopHandlerSpillSRA {};
   uint64_t ThreadPauseHandlerSpillSRA {};
+  uint64_t ThreadDispatchSyscallHandler {};
   uint64_t GuestSignal_SIGILL {};
   uint64_t GuestSignal_SIGTRAP {};
   uint64_t GuestSignal_SIGSEGV {};
diff --git a/unittests/InstructionCountCI/AFP/H0F3A.json b/unittests/InstructionCountCI/AFP/H0F3A.json
index 656ab3b81..712b64b84 100644
--- a/unittests/InstructionCountCI/AFP/H0F3A.json
+++ b/unittests/InstructionCountCI/AFP/H0F3A.json
@@ -8,7 +8,7 @@
       "SVE128",
       "SVE256"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Instructions": {
     "roundss xmm0, xmm1, 00000000b": {
diff --git a/unittests/InstructionCountCI/AFP/SVE256/Secondary.json b/unittests/InstructionCountCI/AFP/SVE256/Secondary.json
index a60ea29b5..90873b741 100644
--- a/unittests/InstructionCountCI/AFP/SVE256/Secondary.json
+++ b/unittests/InstructionCountCI/AFP/SVE256/Secondary.json
@@ -7,7 +7,7 @@
       "AFP"
     ],
     "DisabledHostFeatures": [],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Instructions": {
     "cvtpi2ps xmm0, [rax]": {
diff --git a/unittests/InstructionCountCI/AFP/SVE256/Secondary_REP.json b/unittests/InstructionCountCI/AFP/SVE256/Secondary_REP.json
index ee12225ea..1158e9974 100644
--- a/unittests/InstructionCountCI/AFP/SVE256/Secondary_REP.json
+++ b/unittests/InstructionCountCI/AFP/SVE256/Secondary_REP.json
@@ -9,7 +9,7 @@
     "DisabledHostFeatures": [
       "RPRES"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Instructions": {
     "cvtsi2ss xmm0, eax": {
diff --git a/unittests/InstructionCountCI/AFP/SVE256/Secondary_REPNE.json b/unittests/InstructionCountCI/AFP/SVE256/Secondary_REPNE.json
index 8ff0de096..780c31932 100644
--- a/unittests/InstructionCountCI/AFP/SVE256/Secondary_REPNE.json
+++ b/unittests/InstructionCountCI/AFP/SVE256/Secondary_REPNE.json
@@ -7,7 +7,7 @@
       "AFP"
     ],
     "DisabledHostFeatures": [],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Instructions": {
     "cvtsi2sd xmm0, eax": {
diff --git a/unittests/InstructionCountCI/AFP/Secondary.json b/unittests/InstructionCountCI/AFP/Secondary.json
index 2a85bf4e9..9e42f0d0d 100644
--- a/unittests/InstructionCountCI/AFP/Secondary.json
+++ b/unittests/InstructionCountCI/AFP/Secondary.json
@@ -8,7 +8,7 @@
       "SVE128",
       "SVE256"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Instructions": {
     "cvtpi2ps xmm0, [rax]": {
diff --git a/unittests/InstructionCountCI/AFP/Secondary_REP.json b/unittests/InstructionCountCI/AFP/Secondary_REP.json
index 8c2206cc2..e07a01313 100644
--- a/unittests/InstructionCountCI/AFP/Secondary_REP.json
+++ b/unittests/InstructionCountCI/AFP/Secondary_REP.json
@@ -9,7 +9,7 @@
       "SVE256",
       "RPRES"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Instructions": {
     "cvtsi2ss xmm0, eax": {
diff --git a/unittests/InstructionCountCI/AFP/Secondary_REPNE.json b/unittests/InstructionCountCI/AFP/Secondary_REPNE.json
index 9ac11520e..36cad44ec 100644
--- a/unittests/InstructionCountCI/AFP/Secondary_REPNE.json
+++ b/unittests/InstructionCountCI/AFP/Secondary_REPNE.json
@@ -8,7 +8,7 @@
       "SVE128",
       "SVE256"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Instructions": {
     "cvtsi2sd xmm0, eax": {
diff --git a/unittests/InstructionCountCI/AFP/VEX_map1.json b/unittests/InstructionCountCI/AFP/VEX_map1.json
index a657be492..0fafeccf3 100644
--- a/unittests/InstructionCountCI/AFP/VEX_map1.json
+++ b/unittests/InstructionCountCI/AFP/VEX_map1.json
@@ -9,7 +9,7 @@
     "DisabledHostFeatures": [
       "RPRES"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Instructions": {
     "vsqrtss xmm0, xmm1, xmm2": {
diff --git a/unittests/InstructionCountCI/AFP/VEX_map3.json b/unittests/InstructionCountCI/AFP/VEX_map3.json
index 6dea99dc3..23cdf312a 100644
--- a/unittests/InstructionCountCI/AFP/VEX_map3.json
+++ b/unittests/InstructionCountCI/AFP/VEX_map3.json
@@ -7,7 +7,7 @@
       "AFP"
     ],
     "DisabledHostFeatures": [],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Instructions": {
     "vroundss xmm0, xmm1, 00000000b": {
diff --git a/unittests/InstructionCountCI/AVX128/FMA4.json b/unittests/InstructionCountCI/AVX128/FMA4.json
index 52f096720..52e785b44 100644
--- a/unittests/InstructionCountCI/AVX128/FMA4.json
+++ b/unittests/InstructionCountCI/AVX128/FMA4.json
@@ -7,7 +7,7 @@
       "SVE256",
       "SVE128"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Instructions": {
     "vfmaddsubps xmm0, xmm1, xmm2, xmm3": {
@@ -20,7 +20,7 @@
         "str x20, [x28, #24]",
         "mov w0, #0x401",
         "str x0, [x28, #1496]",
-        "ldr x0, [x28, #2976]",
+        "ldr x0, [x28, #2984]",
         "br x0"
       ]
     },
@@ -34,7 +34,7 @@
         "str x20, [x28, #24]",
         "mov w0, #0x401",
         "str x0, [x28, #1496]",
-        "ldr x0, [x28, #2976]",
+        "ldr x0, [x28, #2984]",
         "br x0"
       ]
     },
@@ -48,7 +48,7 @@
         "str x20, [x28, #24]",
         "mov w0, #0x401",
         "str x0, [x28, #1496]",
-        "ldr x0, [x28, #2976]",
+        "ldr x0, [x28, #2984]",
         "br x0"
       ]
     },
@@ -62,7 +62,7 @@
         "str x20, [x28, #24]",
         "mov w0, #0x401",
         "str x0, [x28, #1496]",
-        "ldr x0, [x28, #2976]",
+        "ldr x0, [x28, #2984]",
         "br x0"
       ]
     },
@@ -76,7 +76,7 @@
         "str x20, [x28, #24]",
         "mov w0, #0x401",
         "str x0, [x28, #1496]",
-        "ldr x0, [x28, #2976]",
+        "ldr x0, [x28, #2984]",
         "br x0"
       ]
     },
@@ -90,7 +90,7 @@
         "str x20, [x28, #24]",
         "mov w0, #0x401",
         "str x0, [x28, #1496]",
-        "ldr x0, [x28, #2976]",
+        "ldr x0, [x28, #2984]",
         "br x0"
       ]
     },
@@ -104,7 +104,7 @@
         "str x20, [x28, #24]",
         "mov w0, #0x401",
         "str x0, [x28, #1496]",
-        "ldr x0, [x28, #2976]",
+        "ldr x0, [x28, #2984]",
         "br x0"
       ]
     },
@@ -118,7 +118,7 @@
         "str x20, [x28, #24]",
         "mov w0, #0x401",
         "str x0, [x28, #1496]",
-        "ldr x0, [x28, #2976]",
+        "ldr x0, [x28, #2984]",
         "br x0"
       ]
     },
@@ -132,7 +132,7 @@
         "str x20, [x28, #24]",
         "mov w0, #0x401",
         "str x0, [x28, #1496]",
-        "ldr x0, [x28, #2976]",
+        "ldr x0, [x28, #2984]",
         "br x0"
       ]
     },
@@ -146,7 +146,7 @@
         "str x20, [x28, #24]",
         "mov w0, #0x401",
         "str x0, [x28, #1496]",
-        "ldr x0, [x28, #2976]",
+        "ldr x0, [x28, #2984]",
         "br x0"
       ]
     },
@@ -160,7 +160,7 @@
         "str x20, [x28, #24]",
         "mov w0, #0x401",
         "str x0, [x28, #1496]",
-        "ldr x0, [x28, #2976]",
+        "ldr x0, [x28, #2984]",
         "br x0"
       ]
     },
@@ -174,7 +174,7 @@
         "str x20, [x28, #24]",
         "mov w0, #0x401",
         "str x0, [x28, #1496]",
-        "ldr x0, [x28, #2976]",
+        "ldr x0, [x28, #2984]",
         "br x0"
       ]
     },
@@ -188,7 +188,7 @@
         "str x20, [x28, #24]",
         "mov w0, #0x401",
         "str x0, [x28, #1496]",
-        "ldr x0, [x28, #2976]",
+        "ldr x0, [x28, #2984]",
         "br x0"
       ]
     },
@@ -202,7 +202,7 @@
         "str x20, [x28, #24]",
         "mov w0, #0x401",
         "str x0, [x28, #1496]",
-        "ldr x0, [x28, #2976]",
+        "ldr x0, [x28, #2984]",
         "br x0"
       ]
     },
@@ -216,7 +216,7 @@
         "str x20, [x28, #24]",
         "mov w0, #0x401",
         "str x0, [x28, #1496]",
-        "ldr x0, [x28, #2976]",
+        "ldr x0, [x28, #2984]",
         "br x0"
       ]
     },
@@ -230,7 +230,7 @@
         "str x20, [x28, #24]",
         "mov w0, #0x401",
         "str x0, [x28, #1496]",
-        "ldr x0, [x28, #2976]",
+        "ldr x0, [x28, #2984]",
         "br x0"
       ]
     },
@@ -244,7 +244,7 @@
         "str x20, [x28, #24]",
         "mov w0, #0x401",
         "str x0, [x28, #1496]",
-        "ldr x0, [x28, #2976]",
+        "ldr x0, [x28, #2984]",
         "br x0"
       ]
     },
@@ -258,7 +258,7 @@
         "str x20, [x28, #24]",
         "mov w0, #0x401",
         "str x0, [x28, #1496]",
-        "ldr x0, [x28, #2976]",
+        "ldr x0, [x28, #2984]",
         "br x0"
       ]
     },
@@ -272,7 +272,7 @@
         "str x20, [x28, #24]",
         "mov w0, #0x401",
         "str x0, [x28, #1496]",
-        "ldr x0, [x28, #2976]",
+        "ldr x0, [x28, #2984]",
         "br x0"
       ]
     },
@@ -286,7 +286,7 @@
         "str x20, [x28, #24]",
         "mov w0, #0x401",
         "str x0, [x28, #1496]",
-        "ldr x0, [x28, #2976]",
+        "ldr x0, [x28, #2984]",
         "br x0"
       ]
     },
@@ -300,7 +300,7 @@
         "str x20, [x28, #24]",
         "mov w0, #0x401",
         "str x0, [x28, #1496]",
-        "ldr x0, [x28, #2976]",
+        "ldr x0, [x28, #2984]",
         "br x0"
       ]
     },
@@ -314,7 +314,7 @@
         "str x20, [x28, #24]",
         "mov w0, #0x401",
         "str x0, [x28, #1496]",
-        "ldr x0, [x28, #2976]",
+        "ldr x0, [x28, #2984]",
         "br x0"
       ]
     },
@@ -328,7 +328,7 @@
         "str x20, [x28, #24]",
         "mov w0, #0x401",
         "str x0, [x28, #1496]",
-        "ldr x0, [x28, #2976]",
+        "ldr x0, [x28, #2984]",
         "br x0"
       ]
     },
@@ -342,7 +342,7 @@
         "str x20, [x28, #24]",
         "mov w0, #0x401",
         "str x0, [x28, #1496]",
-        "ldr x0, [x28, #2976]",
+        "ldr x0, [x28, #2984]",
         "br x0"
       ]
     },
@@ -356,7 +356,7 @@
         "str x20, [x28, #24]",
         "mov w0, #0x401",
         "str x0, [x28, #1496]",
-        "ldr x0, [x28, #2976]",
+        "ldr x0, [x28, #2984]",
         "br x0"
       ]
     },
@@ -370,7 +370,7 @@
         "str x20, [x28, #24]",
         "mov w0, #0x401",
         "str x0, [x28, #1496]",
-        "ldr x0, [x28, #2976]",
+        "ldr x0, [x28, #2984]",
         "br x0"
       ]
     },
@@ -384,7 +384,7 @@
         "str x20, [x28, #24]",
         "mov w0, #0x401",
         "str x0, [x28, #1496]",
-        "ldr x0, [x28, #2976]",
+        "ldr x0, [x28, #2984]",
         "br x0"
       ]
     },
@@ -398,7 +398,7 @@
         "str x20, [x28, #24]",
         "mov w0, #0x401",
         "str x0, [x28, #1496]",
-        "ldr x0, [x28, #2976]",
+        "ldr x0, [x28, #2984]",
         "br x0"
       ]
     },
@@ -412,7 +412,7 @@
         "str x20, [x28, #24]",
         "mov w0, #0x401",
         "str x0, [x28, #1496]",
-        "ldr x0, [x28, #2976]",
+        "ldr x0, [x28, #2984]",
         "br x0"
       ]
     },
@@ -426,7 +426,7 @@
         "str x20, [x28, #24]",
         "mov w0, #0x401",
         "str x0, [x28, #1496]",
-        "ldr x0, [x28, #2976]",
+        "ldr x0, [x28, #2984]",
         "br x0"
       ]
     }
diff --git a/unittests/InstructionCountCI/AVX128/VEX_map1.json b/unittests/InstructionCountCI/AVX128/VEX_map1.json
index 724ea9eba..c5c10819c 100644
--- a/unittests/InstructionCountCI/AVX128/VEX_map1.json
+++ b/unittests/InstructionCountCI/AVX128/VEX_map1.json
@@ -13,7 +13,7 @@
       "SVE256",
       "SVE128"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Instructions": {
     "vmovups xmm0, xmm0": {
@@ -486,7 +486,7 @@
       ],
       "ExpectedArm64ASM": [
         "ushr v2.4s, v16.4s, #31",
-        "ldr q3, [x28, #3280]",
+        "ldr q3, [x28, #3296]",
         "ushl v2.4s, v2.4s, v3.4s",
         "addv s2, v2.4s",
         "mov w4, v2.s[0]"
@@ -501,7 +501,7 @@
         "ldr q2, [x28, #192]",
         "uzp2 v2.8h, v16.8h, v2.8h",
         "ushr v2.8h, v2.8h, #15",
-        "ldr q3, [x28, #3120]",
+        "ldr q3, [x28, #3136]",
         "ushl v2.8h, v2.8h, v3.8h",
         "addv h2, v2.8h",
         "umov w4, v2.h[0]"
@@ -528,7 +528,7 @@
         "ldr q2, [x28, #192]",
         "uzp2 v2.4s, v16.4s, v2.4s",
         "ushr v2.4s, v2.4s, #31",
-        "ldr q3, [x28, #3280]",
+        "ldr q3, [x28, #3296]",
         "ushl v2.4s, v2.4s, v3.4s",
         "addv s2, v2.4s",
         "mov w4, v2.s[0]"
@@ -3936,7 +3936,7 @@
         "Map 1 0b01 0xd0 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3184]",
+        "ldr q2, [x28, #3200]",
         "eor v2.16b, v18.16b, v2.16b",
         "fadd v16.2d, v17.2d, v2.2d",
         "stp xzr, xzr, [x28, #192]"
@@ -3950,7 +3950,7 @@
       "ExpectedArm64ASM": [
         "ldr q2, [x28, #208]",
         "ldr q3, [x28, #224]",
-        "ldr q4, [x28, #3184]",
+        "ldr q4, [x28, #3200]",
         "eor v5.16b, v18.16b, v4.16b",
         "fadd v16.2d, v17.2d, v5.2d",
         "eor v3.16b, v3.16b, v4.16b",
@@ -3964,7 +3964,7 @@
         "Map 1 0b11 0xd0 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3152]",
+        "ldr q2, [x28, #3168]",
         "eor v2.16b, v18.16b, v2.16b",
         "fadd v16.4s, v17.4s, v2.4s",
         "stp xzr, xzr, [x28, #192]"
@@ -3978,7 +3978,7 @@
       "ExpectedArm64ASM": [
         "ldr q2, [x28, #208]",
         "ldr q3, [x28, #224]",
-        "ldr q4, [x28, #3152]",
+        "ldr q4, [x28, #3168]",
         "eor v5.16b, v18.16b, v4.16b",
         "fadd v16.4s, v17.4s, v5.4s",
         "eor v3.16b, v3.16b, v4.16b",
@@ -4149,7 +4149,7 @@
         "Map 1 0b01 0xd7 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3408]",
+        "ldr q2, [x28, #3424]",
         "cmlt v3.16b, v16.16b, #0",
         "and v2.16b, v3.16b, v2.16b",
         "addp v2.16b, v2.16b, v2.16b",
@@ -4165,7 +4165,7 @@
       ],
       "ExpectedArm64ASM": [
         "ldr q2, [x28, #192]",
-        "ldr q3, [x28, #3408]",
+        "ldr q3, [x28, #3424]",
         "cmlt v4.16b, v16.16b, #0",
         "and v4.16b, v4.16b, v3.16b",
         "addp v4.16b, v4.16b, v4.16b",
diff --git a/unittests/InstructionCountCI/AVX128/VEX_map1_FCMA.json b/unittests/InstructionCountCI/AVX128/VEX_map1_FCMA.json
index b0fbba218..8ab3d042b 100644
--- a/unittests/InstructionCountCI/AVX128/VEX_map1_FCMA.json
+++ b/unittests/InstructionCountCI/AVX128/VEX_map1_FCMA.json
@@ -9,7 +9,7 @@
       "SVE256",
       "SVE128"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Instructions": {
     "vaddsubpd xmm0, xmm1, xmm2": {
diff --git a/unittests/InstructionCountCI/AVX128/VEX_map1_SVE128.json b/unittests/InstructionCountCI/AVX128/VEX_map1_SVE128.json
index 89728fbee..495d331a6 100644
--- a/unittests/InstructionCountCI/AVX128/VEX_map1_SVE128.json
+++ b/unittests/InstructionCountCI/AVX128/VEX_map1_SVE128.json
@@ -10,7 +10,7 @@
       "FLAGM2",
       "SVE256"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Instructions": {
     "vmovntps [rax], xmm0": {
diff --git a/unittests/InstructionCountCI/AVX128/VEX_map1_flagm.json b/unittests/InstructionCountCI/AVX128/VEX_map1_flagm.json
index aff670f3f..d9aedc1ea 100644
--- a/unittests/InstructionCountCI/AVX128/VEX_map1_flagm.json
+++ b/unittests/InstructionCountCI/AVX128/VEX_map1_flagm.json
@@ -10,7 +10,7 @@
       "SVE128",
       "SVE256"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Instructions": {
     "vucomiss xmm0, xmm1": {
diff --git a/unittests/InstructionCountCI/AVX128/VEX_map2.json b/unittests/InstructionCountCI/AVX128/VEX_map2.json
index 0ea97c813..435cafc63 100644
--- a/unittests/InstructionCountCI/AVX128/VEX_map2.json
+++ b/unittests/InstructionCountCI/AVX128/VEX_map2.json
@@ -11,7 +11,7 @@
       "I8MM",
       "DOTPROD"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Instructions": {
     "vpshufb xmm0, xmm1, xmm2": {
@@ -1902,7 +1902,7 @@
         "Map 2 0b01 0x41 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3120]",
+        "ldr q2, [x28, #3136]",
         "zip1 v3.8h, v2.8h, v17.8h",
         "zip2 v2.8h, v2.8h, v17.8h",
         "umin v2.4s, v3.4s, v2.4s",
@@ -4695,7 +4695,7 @@
         "Map 2 0b01 0x96 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3152]",
+        "ldr q2, [x28, #3168]",
         "eor v2.16b, v17.16b, v2.16b",
         "mov v0.16b, v2.16b",
         "fmla v0.4s, v16.4s, v18.4s",
@@ -4712,7 +4712,7 @@
         "ldr q2, [x28, #192]",
         "ldr q3, [x28, #208]",
         "ldr q4, [x28, #224]",
-        "ldr q5, [x28, #3152]",
+        "ldr q5, [x28, #3168]",
         "eor v6.16b, v17.16b, v5.16b",
         "mov v0.16b, v6.16b",
         "fmla v0.4s, v16.4s, v18.4s",
@@ -4728,7 +4728,7 @@
         "Map 2 0b01 0x96 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3184]",
+        "ldr q2, [x28, #3200]",
         "eor v2.16b, v17.16b, v2.16b",
         "mov v0.16b, v2.16b",
         "fmla v0.2d, v16.2d, v18.2d",
@@ -4745,7 +4745,7 @@
         "ldr q2, [x28, #192]",
         "ldr q3, [x28, #208]",
         "ldr q4, [x28, #224]",
-        "ldr q5, [x28, #3184]",
+        "ldr q5, [x28, #3200]",
         "eor v6.16b, v17.16b, v5.16b",
         "mov v0.16b, v6.16b",
         "fmla v0.2d, v16.2d, v18.2d",
@@ -4761,7 +4761,7 @@
         "Map 2 0b01 0x97 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3216]",
+        "ldr q2, [x28, #3232]",
         "eor v2.16b, v17.16b, v2.16b",
         "mov v0.16b, v2.16b",
         "fmla v0.4s, v16.4s, v18.4s",
@@ -4778,7 +4778,7 @@
         "ldr q2, [x28, #192]",
         "ldr q3, [x28, #208]",
         "ldr q4, [x28, #224]",
-        "ldr q5, [x28, #3216]",
+        "ldr q5, [x28, #3232]",
         "eor v6.16b, v17.16b, v5.16b",
         "mov v0.16b, v6.16b",
         "fmla v0.4s, v16.4s, v18.4s",
@@ -4794,7 +4794,7 @@
         "Map 2 0b01 0x97 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3248]",
+        "ldr q2, [x28, #3264]",
         "eor v2.16b, v17.16b, v2.16b",
         "mov v0.16b, v2.16b",
         "fmla v0.2d, v16.2d, v18.2d",
@@ -4811,7 +4811,7 @@
         "ldr q2, [x28, #192]",
         "ldr q3, [x28, #208]",
         "ldr q4, [x28, #224]",
-        "ldr q5, [x28, #3248]",
+        "ldr q5, [x28, #3264]",
         "eor v6.16b, v17.16b, v5.16b",
         "mov v0.16b, v6.16b",
         "fmla v0.2d, v16.2d, v18.2d",
@@ -5751,7 +5751,7 @@
         "Map 2 0b01 0xa6 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3152]",
+        "ldr q2, [x28, #3168]",
         "eor v2.16b, v18.16b, v2.16b",
         "mov v0.16b, v2.16b",
         "fmla v0.4s, v17.4s, v16.4s",
@@ -5768,7 +5768,7 @@
         "ldr q2, [x28, #192]",
         "ldr q3, [x28, #208]",
         "ldr q4, [x28, #224]",
-        "ldr q5, [x28, #3152]",
+        "ldr q5, [x28, #3168]",
         "eor v6.16b, v18.16b, v5.16b",
         "mov v0.16b, v6.16b",
         "fmla v0.4s, v17.4s, v16.4s",
@@ -5784,7 +5784,7 @@
         "Map 2 0b01 0xa6 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3184]",
+        "ldr q2, [x28, #3200]",
         "eor v2.16b, v18.16b, v2.16b",
         "mov v0.16b, v2.16b",
         "fmla v0.2d, v17.2d, v16.2d",
@@ -5801,7 +5801,7 @@
         "ldr q2, [x28, #192]",
         "ldr q3, [x28, #208]",
         "ldr q4, [x28, #224]",
-        "ldr q5, [x28, #3184]",
+        "ldr q5, [x28, #3200]",
         "eor v6.16b, v18.16b, v5.16b",
         "mov v0.16b, v6.16b",
         "fmla v0.2d, v17.2d, v16.2d",
@@ -5817,7 +5817,7 @@
         "Map 2 0b01 0xa7 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3216]",
+        "ldr q2, [x28, #3232]",
         "eor v2.16b, v18.16b, v2.16b",
         "mov v0.16b, v2.16b",
         "fmla v0.4s, v17.4s, v16.4s",
@@ -5834,7 +5834,7 @@
         "ldr q2, [x28, #192]",
         "ldr q3, [x28, #208]",
         "ldr q4, [x28, #224]",
-        "ldr q5, [x28, #3216]",
+        "ldr q5, [x28, #3232]",
         "eor v6.16b, v18.16b, v5.16b",
         "mov v0.16b, v6.16b",
         "fmla v0.4s, v17.4s, v16.4s",
@@ -5850,7 +5850,7 @@
         "Map 2 0b01 0xa7 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3248]",
+        "ldr q2, [x28, #3264]",
         "eor v2.16b, v18.16b, v2.16b",
         "mov v0.16b, v2.16b",
         "fmla v0.2d, v17.2d, v16.2d",
@@ -5867,7 +5867,7 @@
         "ldr q2, [x28, #192]",
         "ldr q3, [x28, #208]",
         "ldr q4, [x28, #224]",
-        "ldr q5, [x28, #3248]",
+        "ldr q5, [x28, #3264]",
         "eor v6.16b, v18.16b, v5.16b",
         "mov v0.16b, v6.16b",
         "fmla v0.2d, v17.2d, v16.2d",
@@ -5883,7 +5883,7 @@
         "Map 2 0b01 0xb6 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3152]",
+        "ldr q2, [x28, #3168]",
         "eor v2.16b, v16.16b, v2.16b",
         "mov v16.16b, v2.16b",
         "fmla v16.4s, v17.4s, v18.4s",
@@ -5899,7 +5899,7 @@
         "ldr q2, [x28, #192]",
         "ldr q3, [x28, #208]",
         "ldr q4, [x28, #224]",
-        "ldr q5, [x28, #3152]",
+        "ldr q5, [x28, #3168]",
         "eor v6.16b, v16.16b, v5.16b",
         "mov v16.16b, v6.16b",
         "fmla v16.4s, v17.4s, v18.4s",
@@ -5914,7 +5914,7 @@
         "Map 2 0b01 0xb6 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3184]",
+        "ldr q2, [x28, #3200]",
         "eor v2.16b, v16.16b, v2.16b",
         "mov v16.16b, v2.16b",
         "fmla v16.2d, v17.2d, v18.2d",
@@ -5930,7 +5930,7 @@
         "ldr q2, [x28, #192]",
         "ldr q3, [x28, #208]",
         "ldr q4, [x28, #224]",
-        "ldr q5, [x28, #3184]",
+        "ldr q5, [x28, #3200]",
         "eor v6.16b, v16.16b, v5.16b",
         "mov v16.16b, v6.16b",
         "fmla v16.2d, v17.2d, v18.2d",
@@ -5945,7 +5945,7 @@
         "Map 2 0b01 0xb7 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3216]",
+        "ldr q2, [x28, #3232]",
         "eor v2.16b, v16.16b, v2.16b",
         "mov v16.16b, v2.16b",
         "fmla v16.4s, v17.4s, v18.4s",
@@ -5961,7 +5961,7 @@
         "ldr q2, [x28, #192]",
         "ldr q3, [x28, #208]",
         "ldr q4, [x28, #224]",
-        "ldr q5, [x28, #3216]",
+        "ldr q5, [x28, #3232]",
         "eor v6.16b, v16.16b, v5.16b",
         "mov v16.16b, v6.16b",
         "fmla v16.4s, v17.4s, v18.4s",
@@ -5976,7 +5976,7 @@
         "Map 2 0b01 0xb7 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3248]",
+        "ldr q2, [x28, #3264]",
         "eor v2.16b, v16.16b, v2.16b",
         "mov v16.16b, v2.16b",
         "fmla v16.2d, v17.2d, v18.2d",
@@ -5992,7 +5992,7 @@
         "ldr q2, [x28, #192]",
         "ldr q3, [x28, #208]",
         "ldr q4, [x28, #224]",
-        "ldr q5, [x28, #3248]",
+        "ldr q5, [x28, #3264]",
         "eor v6.16b, v16.16b, v5.16b",
         "mov v16.16b, v6.16b",
         "fmla v16.2d, v17.2d, v18.2d",
diff --git a/unittests/InstructionCountCI/AVX128/VEX_map2_AFP.json b/unittests/InstructionCountCI/AVX128/VEX_map2_AFP.json
index 964c98013..d47f65d53 100644
--- a/unittests/InstructionCountCI/AVX128/VEX_map2_AFP.json
+++ b/unittests/InstructionCountCI/AVX128/VEX_map2_AFP.json
@@ -8,7 +8,7 @@
       "SVE256",
       "SVE128"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Instructions": {
     "vfmadd132ss xmm0, xmm1, xmm2": {
diff --git a/unittests/InstructionCountCI/AVX128/VEX_map2_DOTPROD.json b/unittests/InstructionCountCI/AVX128/VEX_map2_DOTPROD.json
index 457c36f5f..54ff0330a 100644
--- a/unittests/InstructionCountCI/AVX128/VEX_map2_DOTPROD.json
+++ b/unittests/InstructionCountCI/AVX128/VEX_map2_DOTPROD.json
@@ -12,7 +12,7 @@
       "SVE256",
       "I8MM"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Instructions": {
     "vpdpbusd xmm0, xmm1, xmm2": {
diff --git a/unittests/InstructionCountCI/AVX128/VEX_map2_I8MM.json b/unittests/InstructionCountCI/AVX128/VEX_map2_I8MM.json
index b85505f2f..01ee94bd6 100644
--- a/unittests/InstructionCountCI/AVX128/VEX_map2_I8MM.json
+++ b/unittests/InstructionCountCI/AVX128/VEX_map2_I8MM.json
@@ -11,7 +11,7 @@
       "SVE128",
       "SVE256"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Instructions": {
     "vpdpbusd xmm0, xmm1, xmm2": {
diff --git a/unittests/InstructionCountCI/AVX128/VEX_map2_SVE128.json b/unittests/InstructionCountCI/AVX128/VEX_map2_SVE128.json
index 5a4132983..c0f486c5c 100644
--- a/unittests/InstructionCountCI/AVX128/VEX_map2_SVE128.json
+++ b/unittests/InstructionCountCI/AVX128/VEX_map2_SVE128.json
@@ -10,7 +10,7 @@
       "FLAGM2",
       "SVE256"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Instructions": {
     "vmovntdqa xmm0, [rax]": {
@@ -2844,7 +2844,7 @@
         "Map 2 0b01 0x96 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3152]",
+        "ldr q2, [x28, #3168]",
         "eor v2.16b, v17.16b, v2.16b",
         "mov v0.16b, v2.16b",
         "fmla v0.4s, v16.4s, v18.4s",
@@ -2861,7 +2861,7 @@
         "ldr q2, [x28, #192]",
         "ldr q3, [x28, #208]",
         "ldr q4, [x28, #224]",
-        "ldr q5, [x28, #3152]",
+        "ldr q5, [x28, #3168]",
         "eor v6.16b, v17.16b, v5.16b",
         "mov v0.16b, v6.16b",
         "fmla v0.4s, v16.4s, v18.4s",
@@ -2877,7 +2877,7 @@
         "Map 2 0b01 0x96 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3184]",
+        "ldr q2, [x28, #3200]",
         "eor v2.16b, v17.16b, v2.16b",
         "mov v0.16b, v2.16b",
         "fmla v0.2d, v16.2d, v18.2d",
@@ -2894,7 +2894,7 @@
         "ldr q2, [x28, #192]",
         "ldr q3, [x28, #208]",
         "ldr q4, [x28, #224]",
-        "ldr q5, [x28, #3184]",
+        "ldr q5, [x28, #3200]",
         "eor v6.16b, v17.16b, v5.16b",
         "mov v0.16b, v6.16b",
         "fmla v0.2d, v16.2d, v18.2d",
@@ -2910,7 +2910,7 @@
         "Map 2 0b01 0x97 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3216]",
+        "ldr q2, [x28, #3232]",
         "eor v2.16b, v17.16b, v2.16b",
         "mov v0.16b, v2.16b",
         "fmla v0.4s, v16.4s, v18.4s",
@@ -2927,7 +2927,7 @@
         "ldr q2, [x28, #192]",
         "ldr q3, [x28, #208]",
         "ldr q4, [x28, #224]",
-        "ldr q5, [x28, #3216]",
+        "ldr q5, [x28, #3232]",
         "eor v6.16b, v17.16b, v5.16b",
         "mov v0.16b, v6.16b",
         "fmla v0.4s, v16.4s, v18.4s",
@@ -2943,7 +2943,7 @@
         "Map 2 0b01 0x97 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3248]",
+        "ldr q2, [x28, #3264]",
         "eor v2.16b, v17.16b, v2.16b",
         "mov v0.16b, v2.16b",
         "fmla v0.2d, v16.2d, v18.2d",
@@ -2960,7 +2960,7 @@
         "ldr q2, [x28, #192]",
         "ldr q3, [x28, #208]",
         "ldr q4, [x28, #224]",
-        "ldr q5, [x28, #3248]",
+        "ldr q5, [x28, #3264]",
         "eor v6.16b, v17.16b, v5.16b",
         "mov v0.16b, v6.16b",
         "fmla v0.2d, v16.2d, v18.2d",
@@ -3880,7 +3880,7 @@
         "Map 2 0b01 0xa6 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3152]",
+        "ldr q2, [x28, #3168]",
         "eor v2.16b, v18.16b, v2.16b",
         "mov v0.16b, v2.16b",
         "fmla v0.4s, v17.4s, v16.4s",
@@ -3897,7 +3897,7 @@
         "ldr q2, [x28, #192]",
         "ldr q3, [x28, #208]",
         "ldr q4, [x28, #224]",
-        "ldr q5, [x28, #3152]",
+        "ldr q5, [x28, #3168]",
         "eor v6.16b, v18.16b, v5.16b",
         "mov v0.16b, v6.16b",
         "fmla v0.4s, v17.4s, v16.4s",
@@ -3913,7 +3913,7 @@
         "Map 2 0b01 0xa6 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3184]",
+        "ldr q2, [x28, #3200]",
         "eor v2.16b, v18.16b, v2.16b",
         "mov v0.16b, v2.16b",
         "fmla v0.2d, v17.2d, v16.2d",
@@ -3930,7 +3930,7 @@
         "ldr q2, [x28, #192]",
         "ldr q3, [x28, #208]",
         "ldr q4, [x28, #224]",
-        "ldr q5, [x28, #3184]",
+        "ldr q5, [x28, #3200]",
         "eor v6.16b, v18.16b, v5.16b",
         "mov v0.16b, v6.16b",
         "fmla v0.2d, v17.2d, v16.2d",
@@ -3946,7 +3946,7 @@
         "Map 2 0b01 0xa7 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3216]",
+        "ldr q2, [x28, #3232]",
         "eor v2.16b, v18.16b, v2.16b",
         "mov v0.16b, v2.16b",
         "fmla v0.4s, v17.4s, v16.4s",
@@ -3963,7 +3963,7 @@
         "ldr q2, [x28, #192]",
         "ldr q3, [x28, #208]",
         "ldr q4, [x28, #224]",
-        "ldr q5, [x28, #3216]",
+        "ldr q5, [x28, #3232]",
         "eor v6.16b, v18.16b, v5.16b",
         "mov v0.16b, v6.16b",
         "fmla v0.4s, v17.4s, v16.4s",
@@ -3979,7 +3979,7 @@
         "Map 2 0b01 0xa7 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3248]",
+        "ldr q2, [x28, #3264]",
         "eor v2.16b, v18.16b, v2.16b",
         "mov v0.16b, v2.16b",
         "fmla v0.2d, v17.2d, v16.2d",
@@ -3996,7 +3996,7 @@
         "ldr q2, [x28, #192]",
         "ldr q3, [x28, #208]",
         "ldr q4, [x28, #224]",
-        "ldr q5, [x28, #3248]",
+        "ldr q5, [x28, #3264]",
         "eor v6.16b, v18.16b, v5.16b",
         "mov v0.16b, v6.16b",
         "fmla v0.2d, v17.2d, v16.2d",
@@ -4012,7 +4012,7 @@
         "Map 2 0b01 0xb6 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3152]",
+        "ldr q2, [x28, #3168]",
         "eor v2.16b, v16.16b, v2.16b",
         "mov v16.16b, v2.16b",
         "fmla v16.4s, v17.4s, v18.4s",
@@ -4028,7 +4028,7 @@
         "ldr q2, [x28, #192]",
         "ldr q3, [x28, #208]",
         "ldr q4, [x28, #224]",
-        "ldr q5, [x28, #3152]",
+        "ldr q5, [x28, #3168]",
         "eor v6.16b, v16.16b, v5.16b",
         "mov v16.16b, v6.16b",
         "fmla v16.4s, v17.4s, v18.4s",
@@ -4043,7 +4043,7 @@
         "Map 2 0b01 0xb6 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3184]",
+        "ldr q2, [x28, #3200]",
         "eor v2.16b, v16.16b, v2.16b",
         "mov v16.16b, v2.16b",
         "fmla v16.2d, v17.2d, v18.2d",
@@ -4059,7 +4059,7 @@
         "ldr q2, [x28, #192]",
         "ldr q3, [x28, #208]",
         "ldr q4, [x28, #224]",
-        "ldr q5, [x28, #3184]",
+        "ldr q5, [x28, #3200]",
         "eor v6.16b, v16.16b, v5.16b",
         "mov v16.16b, v6.16b",
         "fmla v16.2d, v17.2d, v18.2d",
@@ -4074,7 +4074,7 @@
         "Map 2 0b01 0xb7 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3216]",
+        "ldr q2, [x28, #3232]",
         "eor v2.16b, v16.16b, v2.16b",
         "mov v16.16b, v2.16b",
         "fmla v16.4s, v17.4s, v18.4s",
@@ -4090,7 +4090,7 @@
         "ldr q2, [x28, #192]",
         "ldr q3, [x28, #208]",
         "ldr q4, [x28, #224]",
-        "ldr q5, [x28, #3216]",
+        "ldr q5, [x28, #3232]",
         "eor v6.16b, v16.16b, v5.16b",
         "mov v16.16b, v6.16b",
         "fmla v16.4s, v17.4s, v18.4s",
@@ -4105,7 +4105,7 @@
         "Map 2 0b01 0xb7 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3248]",
+        "ldr q2, [x28, #3264]",
         "eor v2.16b, v16.16b, v2.16b",
         "mov v16.16b, v2.16b",
         "fmla v16.2d, v17.2d, v18.2d",
@@ -4121,7 +4121,7 @@
         "ldr q2, [x28, #192]",
         "ldr q3, [x28, #208]",
         "ldr q4, [x28, #224]",
-        "ldr q5, [x28, #3248]",
+        "ldr q5, [x28, #3264]",
         "eor v6.16b, v16.16b, v5.16b",
         "mov v16.16b, v6.16b",
         "fmla v16.2d, v17.2d, v18.2d",
diff --git a/unittests/InstructionCountCI/AVX128/VEX_map2_flagm.json b/unittests/InstructionCountCI/AVX128/VEX_map2_flagm.json
index 00f66a265..3c8e47234 100644
--- a/unittests/InstructionCountCI/AVX128/VEX_map2_flagm.json
+++ b/unittests/InstructionCountCI/AVX128/VEX_map2_flagm.json
@@ -11,7 +11,7 @@
       "SVE256",
       "SVEBITPERM"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Instructions": {
     "vtestps xmm0, xmm1": {
diff --git a/unittests/InstructionCountCI/AVX128/VEX_map3.json b/unittests/InstructionCountCI/AVX128/VEX_map3.json
index f6464bb12..ff4aab9ee 100644
--- a/unittests/InstructionCountCI/AVX128/VEX_map3.json
+++ b/unittests/InstructionCountCI/AVX128/VEX_map3.json
@@ -7,7 +7,7 @@
       "SVE256",
       "SVE128"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Instructions": {
     "vpermq ymm0, ymm1, 1": {
@@ -338,7 +338,7 @@
         "Map 3 0b01 0x02 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3312]",
+        "ldr q2, [x28, #3328]",
         "tbx v16.16b, {v17.16b}, v2.16b",
         "stp xzr, xzr, [x28, #192]"
       ]
@@ -349,7 +349,7 @@
         "Map 3 0b01 0x02 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3328]",
+        "ldr q2, [x28, #3344]",
         "tbx v16.16b, {v17.16b}, v2.16b",
         "stp xzr, xzr, [x28, #192]"
       ]
@@ -370,7 +370,7 @@
         "Map 3 0b01 0x02 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3344]",
+        "ldr q2, [x28, #3360]",
         "tbx v16.16b, {v17.16b}, v2.16b",
         "stp xzr, xzr, [x28, #192]"
       ]
@@ -392,7 +392,7 @@
         "Map 3 0b01 0x02 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3360]",
+        "ldr q2, [x28, #3376]",
         "tbx v16.16b, {v17.16b}, v2.16b",
         "stp xzr, xzr, [x28, #192]"
       ]
@@ -413,7 +413,7 @@
         "Map 3 0b01 0x02 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3376]",
+        "ldr q2, [x28, #3392]",
         "tbx v16.16b, {v17.16b}, v2.16b",
         "stp xzr, xzr, [x28, #192]"
       ]
@@ -424,7 +424,7 @@
         "Map 3 0b01 0x02 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3392]",
+        "ldr q2, [x28, #3408]",
         "tbx v16.16b, {v17.16b}, v2.16b",
         "stp xzr, xzr, [x28, #192]"
       ]
@@ -3494,7 +3494,7 @@
       ],
       "ExpectedArm64ASM": [
         "movi v2.2d, #0x0",
-        "ldr q3, [x28, #3296]",
+        "ldr q3, [x28, #3312]",
         "mov v16.16b, v17.16b",
         "aese v16.16b, v2.16b",
         "tbl v16.16b, {v16.16b}, v3.16b",
@@ -3508,7 +3508,7 @@
       ],
       "ExpectedArm64ASM": [
         "movi v2.2d, #0x0",
-        "ldr q3, [x28, #3296]",
+        "ldr q3, [x28, #3312]",
         "mov v16.16b, v17.16b",
         "aese v16.16b, v2.16b",
         "tbl v16.16b, {v16.16b}, v3.16b",
diff --git a/unittests/InstructionCountCI/AVX128/VEX_map3_SVE128.json b/unittests/InstructionCountCI/AVX128/VEX_map3_SVE128.json
index b3724791d..0fb8c6c58 100644
--- a/unittests/InstructionCountCI/AVX128/VEX_map3_SVE128.json
+++ b/unittests/InstructionCountCI/AVX128/VEX_map3_SVE128.json
@@ -8,7 +8,7 @@
       "AFP",
       "SVE256"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Instructions": {
     "vblendvps xmm0, xmm1, xmm2, xmm3": {
diff --git a/unittests/InstructionCountCI/AVX128/VEX_map_group.json b/unittests/InstructionCountCI/AVX128/VEX_map_group.json
index 00be64981..e8da7eefb 100644
--- a/unittests/InstructionCountCI/AVX128/VEX_map_group.json
+++ b/unittests/InstructionCountCI/AVX128/VEX_map_group.json
@@ -9,7 +9,7 @@
       "SVE256",
       "SVE128"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Instructions": {
     "vpsrlw xmm0, xmm1, 0": {
diff --git a/unittests/InstructionCountCI/Atomics.json b/unittests/InstructionCountCI/Atomics.json
index 2107dcc7c..2ffb6cb14 100644
--- a/unittests/InstructionCountCI/Atomics.json
+++ b/unittests/InstructionCountCI/Atomics.json
@@ -9,7 +9,7 @@
       "FLAGM",
       "FLAGM2"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Instructions": {
     "lock add byte [rax], cl": {
diff --git a/unittests/InstructionCountCI/Crypto/H0F38.json b/unittests/InstructionCountCI/Crypto/H0F38.json
index a6d45c2b6..37a1c7078 100644
--- a/unittests/InstructionCountCI/Crypto/H0F38.json
+++ b/unittests/InstructionCountCI/Crypto/H0F38.json
@@ -9,7 +9,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Instructions": {
     "sha1nexte xmm0, xmm1": {
diff --git a/unittests/InstructionCountCI/Crypto/H0F38_SVE128.json b/unittests/InstructionCountCI/Crypto/H0F38_SVE128.json
index e37439d06..3d597daff 100644
--- a/unittests/InstructionCountCI/Crypto/H0F38_SVE128.json
+++ b/unittests/InstructionCountCI/Crypto/H0F38_SVE128.json
@@ -9,7 +9,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Instructions": {
     "sha1nexte xmm0, xmm1": {
diff --git a/unittests/InstructionCountCI/Crypto/H0F3A.json b/unittests/InstructionCountCI/Crypto/H0F3A.json
index 90045c2fd..0b01fbc9b 100644
--- a/unittests/InstructionCountCI/Crypto/H0F3A.json
+++ b/unittests/InstructionCountCI/Crypto/H0F3A.json
@@ -9,7 +9,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Instructions": {
     "pclmulqdq xmm0, xmm1, 00000b": {
@@ -56,7 +56,7 @@
         "0x66 0x0f 0x3a 0xdf"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3296]",
+        "ldr q2, [x28, #3312]",
         "movi v3.2d, #0x0",
         "mov v16.16b, v17.16b",
         "aese v16.16b, v3.16b",
@@ -69,7 +69,7 @@
         "0x66 0x0f 0x3a 0xdf"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3296]",
+        "ldr q2, [x28, #3312]",
         "movi v3.2d, #0x0",
         "mov v16.16b, v17.16b",
         "aese v16.16b, v3.16b",
@@ -85,7 +85,7 @@
         "0x66 0x0f 0x3a 0xcc"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3712]",
+        "ldr q2, [x28, #3728]",
         "movi v3.2d, #0x0",
         "ldr x0, [x28, #2744]",
         "ldr q4, [x0, #432]",
@@ -102,7 +102,7 @@
         "0x66 0x0f 0x3a 0xcc"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3728]",
+        "ldr q2, [x28, #3744]",
         "movi v3.2d, #0x0",
         "ldr x0, [x28, #2744]",
         "ldr q4, [x0, #432]",
@@ -119,7 +119,7 @@
         "0x66 0x0f 0x3a 0xcc"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3744]",
+        "ldr q2, [x28, #3760]",
         "movi v3.2d, #0x0",
         "ldr x0, [x28, #2744]",
         "ldr q4, [x0, #432]",
@@ -136,7 +136,7 @@
         "0x66 0x0f 0x3a 0xcc"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3760]",
+        "ldr q2, [x28, #3776]",
         "movi v3.2d, #0x0",
         "ldr x0, [x28, #2744]",
         "ldr q4, [x0, #432]",
diff --git a/unittests/InstructionCountCI/DDD.json b/unittests/InstructionCountCI/DDD.json
index 09a34f837..f79abde80 100644
--- a/unittests/InstructionCountCI/DDD.json
+++ b/unittests/InstructionCountCI/DDD.json
@@ -10,7 +10,7 @@
       "AFP",
       "RPRES"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Comment": [
     "These 3DNow! instructions are optimal assuming that FEX doesn't SRA MMX registers",
diff --git a/unittests/InstructionCountCI/FEXOpt/AddressingLimitations.json b/unittests/InstructionCountCI/FEXOpt/AddressingLimitations.json
index 92fdad633..0c594e334 100644
--- a/unittests/InstructionCountCI/FEXOpt/AddressingLimitations.json
+++ b/unittests/InstructionCountCI/FEXOpt/AddressingLimitations.json
@@ -8,7 +8,7 @@
       "RPRES",
       "AFP"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Comment": [
     "Instructions that explicitly push against the limits of ARM's loadstore instructions"
diff --git a/unittests/InstructionCountCI/FEXOpt/AddressingLimitations_32Bit.json b/unittests/InstructionCountCI/FEXOpt/AddressingLimitations_32Bit.json
index 3cd69b63a..8dc5ee889 100644
--- a/unittests/InstructionCountCI/FEXOpt/AddressingLimitations_32Bit.json
+++ b/unittests/InstructionCountCI/FEXOpt/AddressingLimitations_32Bit.json
@@ -8,7 +8,7 @@
       "RPRES",
       "AFP"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Comment": [
     "Instructions that explicitly push against the limits of ARM's loadstore instructions"
diff --git a/unittests/InstructionCountCI/FEXOpt/MultiInst.json b/unittests/InstructionCountCI/FEXOpt/MultiInst.json
index a58833143..9f6d78c80 100644
--- a/unittests/InstructionCountCI/FEXOpt/MultiInst.json
+++ b/unittests/InstructionCountCI/FEXOpt/MultiInst.json
@@ -13,7 +13,7 @@
       "RPRES",
       "AFP"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Comment": [
     "These are instruction combinations that could be more optimal if FEX optimized for them"
diff --git a/unittests/InstructionCountCI/FEXOpt/MultiInst_32bit.json b/unittests/InstructionCountCI/FEXOpt/MultiInst_32bit.json
index 055718469..5b82dcc69 100644
--- a/unittests/InstructionCountCI/FEXOpt/MultiInst_32bit.json
+++ b/unittests/InstructionCountCI/FEXOpt/MultiInst_32bit.json
@@ -11,7 +11,7 @@
       "RPRES",
       "AFP"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Comment": [
     "These are instruction combinations that could be more optimal if FEX optimized for them"
diff --git a/unittests/InstructionCountCI/FEXOpt/MultiInst_AFP.json b/unittests/InstructionCountCI/FEXOpt/MultiInst_AFP.json
index 460010e8b..ec69b9355 100644
--- a/unittests/InstructionCountCI/FEXOpt/MultiInst_AFP.json
+++ b/unittests/InstructionCountCI/FEXOpt/MultiInst_AFP.json
@@ -9,7 +9,7 @@
       "SVE256",
       "RPRES"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Comment": [
     "These are instruction combinations that could be more optimal if FEX optimized for them"
diff --git a/unittests/InstructionCountCI/FEXOpt/MultiInst_TSO.json b/unittests/InstructionCountCI/FEXOpt/MultiInst_TSO.json
index 1b23462be..bb1cb0a0c 100644
--- a/unittests/InstructionCountCI/FEXOpt/MultiInst_TSO.json
+++ b/unittests/InstructionCountCI/FEXOpt/MultiInst_TSO.json
@@ -14,7 +14,7 @@
       "RPRES",
       "AFP"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Comment": [
     "These are instruction combinations that could be more optimal if FEX optimized for them"
diff --git a/unittests/InstructionCountCI/FEXOpt/MultiInst_TSO_32bit.json b/unittests/InstructionCountCI/FEXOpt/MultiInst_TSO_32bit.json
index f9f562c93..a144b95de 100644
--- a/unittests/InstructionCountCI/FEXOpt/MultiInst_TSO_32bit.json
+++ b/unittests/InstructionCountCI/FEXOpt/MultiInst_TSO_32bit.json
@@ -14,7 +14,7 @@
       "RPRES",
       "AFP"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Comment": [
     "These are instruction combinations that could be more optimal if FEX optimized for them"
diff --git a/unittests/InstructionCountCI/FEXOpt/libnss.json b/unittests/InstructionCountCI/FEXOpt/libnss.json
index ee95c9dfd..54e940ad5 100644
--- a/unittests/InstructionCountCI/FEXOpt/libnss.json
+++ b/unittests/InstructionCountCI/FEXOpt/libnss.json
@@ -12,7 +12,7 @@
       "RPRES",
       "AFP"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Comment": [],
   "Instructions": {
diff --git a/unittests/InstructionCountCI/FlagM/Atomics.json b/unittests/InstructionCountCI/FlagM/Atomics.json
index db351663a..3540390bd 100644
--- a/unittests/InstructionCountCI/FlagM/Atomics.json
+++ b/unittests/InstructionCountCI/FlagM/Atomics.json
@@ -10,7 +10,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Instructions": {
     "lock add byte [rax], cl": {
diff --git a/unittests/InstructionCountCI/FlagM/FlagOpts.json b/unittests/InstructionCountCI/FlagM/FlagOpts.json
index 821ddcc0e..ab91c3a08 100644
--- a/unittests/InstructionCountCI/FlagM/FlagOpts.json
+++ b/unittests/InstructionCountCI/FlagM/FlagOpts.json
@@ -9,7 +9,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Instructions": {
     "Chained add": {
diff --git a/unittests/InstructionCountCI/FlagM/H0F38.json b/unittests/InstructionCountCI/FlagM/H0F38.json
index ea331ddca..bd5afe5a1 100644
--- a/unittests/InstructionCountCI/FlagM/H0F38.json
+++ b/unittests/InstructionCountCI/FlagM/H0F38.json
@@ -10,7 +10,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Instructions": {
     "ptest xmm0, xmm1": {
diff --git a/unittests/InstructionCountCI/FlagM/HotBlocks.json b/unittests/InstructionCountCI/FlagM/HotBlocks.json
index d4266ab14..4b6c2cdd1 100644
--- a/unittests/InstructionCountCI/FlagM/HotBlocks.json
+++ b/unittests/InstructionCountCI/FlagM/HotBlocks.json
@@ -10,7 +10,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Instructions": {
     "The Witcher 3": {
diff --git a/unittests/InstructionCountCI/FlagM/HotBlocks_32Bit.json b/unittests/InstructionCountCI/FlagM/HotBlocks_32Bit.json
index c277a34e9..5b7c7c06c 100644
--- a/unittests/InstructionCountCI/FlagM/HotBlocks_32Bit.json
+++ b/unittests/InstructionCountCI/FlagM/HotBlocks_32Bit.json
@@ -10,7 +10,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Instructions": {
     "Sonic Mania movie player": {
diff --git a/unittests/InstructionCountCI/FlagM/HotBlocks_AFP.json b/unittests/InstructionCountCI/FlagM/HotBlocks_AFP.json
index 1a17dfd87..ef3579830 100644
--- a/unittests/InstructionCountCI/FlagM/HotBlocks_AFP.json
+++ b/unittests/InstructionCountCI/FlagM/HotBlocks_AFP.json
@@ -10,7 +10,7 @@
       "SVE128",
       "SVE256"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Instructions": {
     "FMOD scalar loop": {
diff --git a/unittests/InstructionCountCI/FlagM/HotBlocks_TSO_32Bit.json b/unittests/InstructionCountCI/FlagM/HotBlocks_TSO_32Bit.json
index 3bea6e338..96ddd975d 100644
--- a/unittests/InstructionCountCI/FlagM/HotBlocks_TSO_32Bit.json
+++ b/unittests/InstructionCountCI/FlagM/HotBlocks_TSO_32Bit.json
@@ -13,7 +13,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Instructions": {
     "The Sims 1 hot block": {
diff --git a/unittests/InstructionCountCI/FlagM/Primary.json b/unittests/InstructionCountCI/FlagM/Primary.json
index c53b68b1b..49dc0bd3f 100644
--- a/unittests/InstructionCountCI/FlagM/Primary.json
+++ b/unittests/InstructionCountCI/FlagM/Primary.json
@@ -10,7 +10,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Instructions": {
     "add bl, cl": {
diff --git a/unittests/InstructionCountCI/FlagM/PrimaryGroup.json b/unittests/InstructionCountCI/FlagM/PrimaryGroup.json
index 73b5fc0de..fb731a7ca 100644
--- a/unittests/InstructionCountCI/FlagM/PrimaryGroup.json
+++ b/unittests/InstructionCountCI/FlagM/PrimaryGroup.json
@@ -10,7 +10,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Instructions": {
     "add al, 1": {
diff --git a/unittests/InstructionCountCI/FlagM/Primary_32Bit.json b/unittests/InstructionCountCI/FlagM/Primary_32Bit.json
index 53b62106f..89c9f0b8c 100644
--- a/unittests/InstructionCountCI/FlagM/Primary_32Bit.json
+++ b/unittests/InstructionCountCI/FlagM/Primary_32Bit.json
@@ -10,7 +10,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Instructions": {
     "push es": {
diff --git a/unittests/InstructionCountCI/FlagM/Secondary.json b/unittests/InstructionCountCI/FlagM/Secondary.json
index 130c1b55e..399ca9df8 100644
--- a/unittests/InstructionCountCI/FlagM/Secondary.json
+++ b/unittests/InstructionCountCI/FlagM/Secondary.json
@@ -11,7 +11,7 @@
       "RPRES",
       "AFP"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Instructions": {
     "ucomiss xmm0, xmm1": {
@@ -1610,7 +1610,7 @@
         "mov w20, #0xffff",
         "strb w20, [x28, #1202]",
         "ldr d2, [x28, #1056]",
-        "ldr d3, [x28, #3408]",
+        "ldr d3, [x28, #3424]",
         "cmlt v2.16b, v2.16b, #0",
         "and v2.8b, v2.8b, v3.8b",
         "addp v2.16b, v2.16b, v2.16b",
diff --git a/unittests/InstructionCountCI/FlagM/SecondaryGroup.json b/unittests/InstructionCountCI/FlagM/SecondaryGroup.json
index 114f88013..7d759ed82 100644
--- a/unittests/InstructionCountCI/FlagM/SecondaryGroup.json
+++ b/unittests/InstructionCountCI/FlagM/SecondaryGroup.json
@@ -11,7 +11,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Instructions": {
     "sgdt [rax]": {
diff --git a/unittests/InstructionCountCI/FlagM/SecondaryModRM.json b/unittests/InstructionCountCI/FlagM/SecondaryModRM.json
index 278e779ba..42a38a1a4 100644
--- a/unittests/InstructionCountCI/FlagM/SecondaryModRM.json
+++ b/unittests/InstructionCountCI/FlagM/SecondaryModRM.json
@@ -11,7 +11,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Instructions": {
     "xgetbv": {
diff --git a/unittests/InstructionCountCI/FlagM/Secondary_OpSize.json b/unittests/InstructionCountCI/FlagM/Secondary_OpSize.json
index cb3c331bd..22e571423 100644
--- a/unittests/InstructionCountCI/FlagM/Secondary_OpSize.json
+++ b/unittests/InstructionCountCI/FlagM/Secondary_OpSize.json
@@ -11,7 +11,7 @@
       "AFP",
       "FCMA"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Instructions": {
     "ucomisd xmm0, xmm1": {
@@ -38,7 +38,7 @@
       "ExpectedInstructionCount": 7,
       "Comment": "0x66 0x0f 0xd7",
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3408]",
+        "ldr q2, [x28, #3424]",
         "cmlt v3.16b, v16.16b, #0",
         "and v2.16b, v3.16b, v2.16b",
         "addp v2.16b, v2.16b, v2.16b",
diff --git a/unittests/InstructionCountCI/FlagM/Secondary_REP.json b/unittests/InstructionCountCI/FlagM/Secondary_REP.json
index 86bf26ab4..ff97be708 100644
--- a/unittests/InstructionCountCI/FlagM/Secondary_REP.json
+++ b/unittests/InstructionCountCI/FlagM/Secondary_REP.json
@@ -12,7 +12,7 @@
       "AFP",
       "CSSC"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Instructions": {
     "popcnt ax, bx": {
diff --git a/unittests/InstructionCountCI/FlagM/Secondary_REP_CSSC.json b/unittests/InstructionCountCI/FlagM/Secondary_REP_CSSC.json
index 3aebd1f20..950062c2b 100644
--- a/unittests/InstructionCountCI/FlagM/Secondary_REP_CSSC.json
+++ b/unittests/InstructionCountCI/FlagM/Secondary_REP_CSSC.json
@@ -12,7 +12,7 @@
       "RPRES",
       "AFP"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Instructions": {
     "popcnt ax, bx": {
diff --git a/unittests/InstructionCountCI/FlagM/VEX_map1.json b/unittests/InstructionCountCI/FlagM/VEX_map1.json
index e0d355bd5..500878cb2 100644
--- a/unittests/InstructionCountCI/FlagM/VEX_map1.json
+++ b/unittests/InstructionCountCI/FlagM/VEX_map1.json
@@ -12,7 +12,7 @@
       "RPRES",
       "AFP"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Instructions": {
     "vucomiss xmm0, xmm1": {
@@ -69,7 +69,7 @@
         "Map 1 0b01 0xd7 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3408]",
+        "ldr q2, [x28, #3424]",
         "cmlt v3.16b, v16.16b, #0",
         "and v2.16b, v3.16b, v2.16b",
         "addp v2.16b, v2.16b, v2.16b",
diff --git a/unittests/InstructionCountCI/FlagM/VEX_map2.json b/unittests/InstructionCountCI/FlagM/VEX_map2.json
index 63ed55372..81dd18ee1 100644
--- a/unittests/InstructionCountCI/FlagM/VEX_map2.json
+++ b/unittests/InstructionCountCI/FlagM/VEX_map2.json
@@ -10,7 +10,7 @@
       "AFP",
       "SVEBITPERM"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Instructions": {
     "vtestps xmm0, xmm1": {
diff --git a/unittests/InstructionCountCI/FlagM/VEX_map_group.json b/unittests/InstructionCountCI/FlagM/VEX_map_group.json
index dfa71035b..e177160e3 100644
--- a/unittests/InstructionCountCI/FlagM/VEX_map_group.json
+++ b/unittests/InstructionCountCI/FlagM/VEX_map_group.json
@@ -9,7 +9,7 @@
     "DisabledHostFeatures": [
       "AFP"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Instructions": {
     "blsr eax, ebx": {
diff --git a/unittests/InstructionCountCI/FlagM/x87-Crysis2Max-fmodel.json b/unittests/InstructionCountCI/FlagM/x87-Crysis2Max-fmodel.json
index ff4c76b3f..deebb3c5e 100644
--- a/unittests/InstructionCountCI/FlagM/x87-Crysis2Max-fmodel.json
+++ b/unittests/InstructionCountCI/FlagM/x87-Crysis2Max-fmodel.json
@@ -10,7 +10,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Instructions": {
     "Block1": {
diff --git a/unittests/InstructionCountCI/FlagM/x87-HalfLife.json b/unittests/InstructionCountCI/FlagM/x87-HalfLife.json
index dc63b687e..b03e8d6b2 100644
--- a/unittests/InstructionCountCI/FlagM/x87-HalfLife.json
+++ b/unittests/InstructionCountCI/FlagM/x87-HalfLife.json
@@ -10,7 +10,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Instructions": {
     "Block1": {
@@ -560,7 +560,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v2.16b, v0.16b",
-        "ldr q3, [x28, #3696]",
+        "ldr q3, [x28, #3712]",
         "bic v2.16b, v2.16b, v3.16b",
         "ldr s3, [x4]",
         "str x30, [sp, #-16]!",
@@ -570,7 +570,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v3.16b, v0.16b",
-        "ldr q4, [x28, #3696]",
+        "ldr q4, [x28, #3712]",
         "bic v3.16b, v3.16b, v4.16b",
         "mov w27, #0x0",
         "strb wzr, [x28, #1049]",
@@ -604,7 +604,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v2.16b, v0.16b",
-        "ldr q3, [x28, #3696]",
+        "ldr q3, [x28, #3712]",
         "bic v2.16b, v2.16b, v3.16b",
         "ldr s3, [x4, #4]",
         "str x30, [sp, #-16]!",
@@ -614,7 +614,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v3.16b, v0.16b",
-        "ldr q5, [x28, #3696]",
+        "ldr q5, [x28, #3712]",
         "bic v3.16b, v3.16b, v5.16b",
         "strb wzr, [x28, #1049]",
         "str x30, [sp, #-16]!",
@@ -647,7 +647,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v2.16b, v0.16b",
-        "ldr q3, [x28, #3696]",
+        "ldr q3, [x28, #3712]",
         "bic v2.16b, v2.16b, v3.16b",
         "ldr s3, [x4, #8]",
         "str x30, [sp, #-16]!",
@@ -657,7 +657,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v3.16b, v0.16b",
-        "ldr q6, [x28, #3696]",
+        "ldr q6, [x28, #3712]",
         "bic v3.16b, v3.16b, v6.16b",
         "strb wzr, [x28, #1049]",
         "str x30, [sp, #-16]!",
diff --git a/unittests/InstructionCountCI/FlagM/x87-Oblivion.json b/unittests/InstructionCountCI/FlagM/x87-Oblivion.json
index 1736b7dfe..10f5db618 100644
--- a/unittests/InstructionCountCI/FlagM/x87-Oblivion.json
+++ b/unittests/InstructionCountCI/FlagM/x87-Oblivion.json
@@ -10,7 +10,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Instructions": {
     "Block1": {
@@ -3790,7 +3790,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v2.16b, v0.16b",
-        "ldr q9, [x28, #3696]",
+        "ldr q9, [x28, #3712]",
         "eor v2.16b, v2.16b, v9.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v2.16b",
@@ -3840,7 +3840,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v2.16b, v0.16b",
-        "ldr q9, [x28, #3696]",
+        "ldr q9, [x28, #3712]",
         "eor v2.16b, v2.16b, v9.16b",
         "ldr s9, [x8, #28]",
         "str x30, [sp, #-16]!",
@@ -4003,7 +4003,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v2.16b, v0.16b",
-        "ldr q9, [x28, #3696]",
+        "ldr q9, [x28, #3712]",
         "eor v2.16b, v2.16b, v9.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v2.16b",
@@ -4053,7 +4053,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v2.16b, v0.16b",
-        "ldr q9, [x28, #3696]",
+        "ldr q9, [x28, #3712]",
         "eor v2.16b, v2.16b, v9.16b",
         "ldr s9, [x8, #60]",
         "str x30, [sp, #-16]!",
@@ -4239,7 +4239,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v2.16b, v0.16b",
-        "ldr q9, [x28, #3696]",
+        "ldr q9, [x28, #3712]",
         "eor v2.16b, v2.16b, v9.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v2.16b",
@@ -4260,7 +4260,7 @@
         "ldr x30, [sp], #16",
         "mov v9.16b, v0.16b",
         "str s2, [x8, #176]",
-        "ldr q2, [x28, #3696]",
+        "ldr q2, [x28, #3712]",
         "eor v2.16b, v9.16b, v2.16b",
         "ldr s9, [x8, #8]",
         "str x30, [sp, #-16]!",
@@ -7531,7 +7531,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v8.16b, v0.16b",
-        "ldr q10, [x28, #3696]",
+        "ldr q10, [x28, #3712]",
         "eor v8.16b, v8.16b, v10.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v8.16b",
@@ -7622,7 +7622,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v8.16b, v0.16b",
-        "ldr q11, [x28, #3696]",
+        "ldr q11, [x28, #3712]",
         "eor v8.16b, v8.16b, v11.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v8.16b",
@@ -7680,7 +7680,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v8.16b, v0.16b",
-        "ldr q11, [x28, #3696]",
+        "ldr q11, [x28, #3712]",
         "eor v8.16b, v8.16b, v11.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v8.16b",
@@ -7953,7 +7953,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v7.16b, v0.16b",
-        "ldr q9, [x28, #3696]",
+        "ldr q9, [x28, #3712]",
         "eor v7.16b, v7.16b, v9.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v7.16b",
@@ -8113,7 +8113,7 @@
         "ldr x30, [sp], #16",
         "fmov s2, s0",
         "str s2, [x4, #1024]",
-        "ldr q2, [x28, #3696]",
+        "ldr q2, [x28, #3712]",
         "eor v2.16b, v3.16b, v2.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v2.16b",
@@ -8131,7 +8131,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v2.16b, v0.16b",
-        "ldr q3, [x28, #3696]",
+        "ldr q3, [x28, #3712]",
         "eor v2.16b, v2.16b, v3.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v2.16b",
@@ -8142,7 +8142,7 @@
         "fmov s2, s0",
         "str s2, [x4, #1152]",
         "strb wzr, [x28, #1049]",
-        "ldr q2, [x28, #3696]",
+        "ldr q2, [x28, #3712]",
         "eor v2.16b, v6.16b, v2.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v2.16b",
@@ -8160,7 +8160,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v2.16b, v0.16b",
-        "ldr q3, [x28, #3696]",
+        "ldr q3, [x28, #3712]",
         "eor v2.16b, v2.16b, v3.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v2.16b",
@@ -8178,7 +8178,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v2.16b, v0.16b",
-        "ldr q3, [x28, #3696]",
+        "ldr q3, [x28, #3712]",
         "eor v2.16b, v2.16b, v3.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v2.16b",
@@ -8189,7 +8189,7 @@
         "fmov s2, s0",
         "str s2, [x4, #1344]",
         "strb wzr, [x28, #1049]",
-        "ldr q2, [x28, #3696]",
+        "ldr q2, [x28, #3712]",
         "eor v2.16b, v11.16b, v2.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v2.16b",
@@ -8207,7 +8207,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v2.16b, v0.16b",
-        "ldr q3, [x28, #3696]",
+        "ldr q3, [x28, #3712]",
         "eor v2.16b, v2.16b, v3.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v2.16b",
@@ -8218,7 +8218,7 @@
         "fmov s2, s0",
         "str s2, [x4, #1472]",
         "strb wzr, [x28, #1049]",
-        "ldr q2, [x28, #3696]",
+        "ldr q2, [x28, #3712]",
         "eor v2.16b, v10.16b, v2.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v2.16b",
@@ -8229,7 +8229,7 @@
         "fmov s2, s0",
         "str s2, [x4, #1536]",
         "strb wzr, [x28, #1049]",
-        "ldr q2, [x28, #3696]",
+        "ldr q2, [x28, #3712]",
         "eor v2.16b, v9.16b, v2.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v2.16b",
@@ -8240,7 +8240,7 @@
         "fmov s2, s0",
         "str s2, [x4, #1600]",
         "strb wzr, [x28, #1049]",
-        "ldr q2, [x28, #3696]",
+        "ldr q2, [x28, #3712]",
         "eor v2.16b, v8.16b, v2.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v2.16b",
@@ -8250,7 +8250,7 @@
         "ldr x30, [sp], #16",
         "fmov s2, s0",
         "str s2, [x4, #1664]",
-        "ldr q2, [x28, #3696]",
+        "ldr q2, [x28, #3712]",
         "eor v2.16b, v7.16b, v2.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v2.16b",
@@ -12539,7 +12539,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v2.16b, v0.16b",
-        "ldr q3, [x28, #3696]",
+        "ldr q3, [x28, #3712]",
         "eor v3.16b, v2.16b, v3.16b",
         "ldr s4, [x4]",
         "str x30, [sp, #-16]!",
@@ -12581,7 +12581,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v4.16b, v0.16b",
-        "ldr q5, [x28, #3696]",
+        "ldr q5, [x28, #3712]",
         "eor v5.16b, v4.16b, v5.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v3.16b",
@@ -12616,7 +12616,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v5.16b, v0.16b",
-        "ldr q6, [x28, #3696]",
+        "ldr q6, [x28, #3712]",
         "eor v6.16b, v5.16b, v6.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v3.16b",
@@ -12651,7 +12651,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v6.16b, v0.16b",
-        "ldr q7, [x28, #3696]",
+        "ldr q7, [x28, #3712]",
         "eor v7.16b, v6.16b, v7.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v3.16b",
@@ -12686,7 +12686,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v7.16b, v0.16b",
-        "ldr q8, [x28, #3696]",
+        "ldr q8, [x28, #3712]",
         "eor v8.16b, v7.16b, v8.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v3.16b",
@@ -12721,7 +12721,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v8.16b, v0.16b",
-        "ldr q9, [x28, #3696]",
+        "ldr q9, [x28, #3712]",
         "eor v9.16b, v8.16b, v9.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v3.16b",
@@ -12756,7 +12756,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v9.16b, v0.16b",
-        "ldr q10, [x28, #3696]",
+        "ldr q10, [x28, #3712]",
         "eor v9.16b, v9.16b, v10.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v3.16b",
@@ -12790,7 +12790,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v9.16b, v0.16b",
-        "ldr q10, [x28, #3696]",
+        "ldr q10, [x28, #3712]",
         "eor v9.16b, v9.16b, v10.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v3.16b",
@@ -12824,7 +12824,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v9.16b, v0.16b",
-        "ldr q10, [x28, #3696]",
+        "ldr q10, [x28, #3712]",
         "eor v9.16b, v9.16b, v10.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v3.16b",
@@ -20013,7 +20013,7 @@
         "mov x8, x26",
         "str s2, [x8, #16]",
         "uxtb w7, w4",
-        "ldr q2, [x28, #3472]",
+        "ldr q2, [x28, #3488]",
         "str w7, [x8, #56]",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v2.16b",
@@ -21709,7 +21709,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v2.16b, v0.16b",
-        "ldr q3, [x28, #3696]",
+        "ldr q3, [x28, #3712]",
         "eor v2.16b, v2.16b, v3.16b",
         "add x14, x28, x20, lsl #4",
         "ldr q3, [x14, #1056]",
@@ -21764,7 +21764,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v2.16b, v0.16b",
-        "ldr q5, [x28, #3696]",
+        "ldr q5, [x28, #3712]",
         "eor v2.16b, v2.16b, v5.16b",
         "mov w14, #0x7b90",
         "movk w14, #0xa7, lsl #16",
@@ -21828,7 +21828,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v2.16b, v0.16b",
-        "ldr q6, [x28, #3696]",
+        "ldr q6, [x28, #3712]",
         "eor v2.16b, v2.16b, v6.16b",
         "mov w15, #0x7b80",
         "movk w15, #0xa7, lsl #16",
@@ -21956,7 +21956,7 @@
         "fmov s7, s0",
         "str s7, [x8, #64]",
         "strb wzr, [x28, #1049]",
-        "ldr q7, [x28, #3696]",
+        "ldr q7, [x28, #3712]",
         "eor v7.16b, v6.16b, v7.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v7.16b",
@@ -21980,7 +21980,7 @@
         "fmov s7, s0",
         "str s7, [x8, #68]",
         "strb wzr, [x28, #1049]",
-        "ldr q7, [x28, #3696]",
+        "ldr q7, [x28, #3712]",
         "eor v2.16b, v2.16b, v7.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v5.16b",
@@ -22006,7 +22006,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v2.16b, v0.16b",
-        "ldr q5, [x28, #3696]",
+        "ldr q5, [x28, #3712]",
         "eor v5.16b, v2.16b, v5.16b",
         "ldr d7, [x15]",
         "str x30, [sp, #-16]!",
diff --git a/unittests/InstructionCountCI/FlagM/x87-Psychonauts.json b/unittests/InstructionCountCI/FlagM/x87-Psychonauts.json
index 347398814..c1e6fa9fb 100644
--- a/unittests/InstructionCountCI/FlagM/x87-Psychonauts.json
+++ b/unittests/InstructionCountCI/FlagM/x87-Psychonauts.json
@@ -10,7 +10,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Instructions": {
     "Block1": {
@@ -10859,7 +10859,7 @@
         "add w22, w20, #0x7 (7)",
         "and w22, w22, #0x7",
         "add x23, x28, x22, lsl #4",
-        "ldr q4, [x28, #3696]",
+        "ldr q4, [x28, #3712]",
         "eor v3.16b, v3.16b, v4.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v3.16b",
@@ -10904,7 +10904,7 @@
         "add w22, w22, #0x7 (7)",
         "and w22, w22, #0x7",
         "add x12, x28, x22, lsl #4",
-        "ldr q5, [x28, #3696]",
+        "ldr q5, [x28, #3712]",
         "eor v4.16b, v4.16b, v5.16b",
         "ldur s5, [x5, #-4]",
         "str x30, [sp, #-16]!",
@@ -11029,7 +11029,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v5.16b, v0.16b",
-        "ldr q6, [x28, #3696]",
+        "ldr q6, [x28, #3712]",
         "eor v5.16b, v5.16b, v6.16b",
         "ldr s6, [x5, #4]",
         "str x30, [sp, #-16]!",
@@ -12175,7 +12175,7 @@
         "ldr x30, [sp], #16",
         "mov v4.16b, v0.16b",
         "ldr w9, [x8, #48]",
-        "ldr q5, [x28, #3696]",
+        "ldr q5, [x28, #3712]",
         "eor v4.16b, v4.16b, v5.16b",
         "ldr s5, [x9, #12]",
         "str x30, [sp, #-16]!",
@@ -12303,7 +12303,7 @@
         "ldr x30, [sp], #16",
         "mov v5.16b, v0.16b",
         "ldr w9, [x8, #48]",
-        "ldr q6, [x28, #3696]",
+        "ldr q6, [x28, #3712]",
         "eor v5.16b, v5.16b, v6.16b",
         "ldr s6, [x9, #4]",
         "str x30, [sp, #-16]!",
@@ -14022,7 +14022,7 @@
         "add w22, w20, #0x7 (7)",
         "and w22, w22, #0x7",
         "add x23, x28, x22, lsl #4",
-        "ldr q4, [x28, #3696]",
+        "ldr q4, [x28, #3712]",
         "eor v3.16b, v3.16b, v4.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v3.16b",
@@ -22327,7 +22327,7 @@
         "add w22, w22, #0x7 (7)",
         "and w22, w22, #0x7",
         "add x13, x28, x22, lsl #4",
-        "ldr q6, [x28, #3696]",
+        "ldr q6, [x28, #3712]",
         "eor v5.16b, v5.16b, v6.16b",
         "add w14, w4, w10, lsl #2",
         "ldur s6, [x14, #-4]",
@@ -22928,7 +22928,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v5.16b, v0.16b",
-        "ldr q6, [x28, #3696]",
+        "ldr q6, [x28, #3712]",
         "eor v5.16b, v5.16b, v6.16b",
         "add w15, w4, w10, lsl #2",
         "ldr s6, [x15, #4]",
@@ -23398,7 +23398,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v6.16b, v0.16b",
-        "ldr q7, [x28, #3696]",
+        "ldr q7, [x28, #3712]",
         "eor v6.16b, v6.16b, v7.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v5.16b",
@@ -23486,7 +23486,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v5.16b, v0.16b",
-        "ldr q6, [x28, #3696]",
+        "ldr q6, [x28, #3712]",
         "eor v5.16b, v5.16b, v6.16b",
         "add w15, w4, w10, lsl #2",
         "ldr s6, [x15, #12]",
@@ -25587,7 +25587,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v6.16b, v0.16b",
-        "ldr q7, [x28, #3696]",
+        "ldr q7, [x28, #3712]",
         "eor v6.16b, v6.16b, v7.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v5.16b",
diff --git a/unittests/InstructionCountCI/FlagM/x87.json b/unittests/InstructionCountCI/FlagM/x87.json
index c6e2b4f8f..5270b5fe9 100644
--- a/unittests/InstructionCountCI/FlagM/x87.json
+++ b/unittests/InstructionCountCI/FlagM/x87.json
@@ -11,7 +11,7 @@
       "CSSC",
       "AFP"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Instructions": {
     "fadd dword [rax]": {
@@ -2554,7 +2554,7 @@
         "ldrb w20, [x28, #1051]",
         "add x20, x28, x20, lsl #4",
         "ldr q2, [x20, #1056]",
-        "ldr q3, [x28, #3696]",
+        "ldr q3, [x28, #3712]",
         "eor v2.16b, v2.16b, v3.16b",
         "str q2, [x20, #1056]"
       ]
@@ -2568,7 +2568,7 @@
         "ldrb w20, [x28, #1051]",
         "add x20, x28, x20, lsl #4",
         "ldr q2, [x20, #1056]",
-        "ldr q3, [x28, #3696]",
+        "ldr q3, [x28, #3712]",
         "bic v2.16b, v2.16b, v3.16b",
         "str q2, [x20, #1056]"
       ]
@@ -2636,7 +2636,7 @@
         "0xd9 11b 0xe8 /5"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3472]",
+        "ldr q2, [x28, #3488]",
         "ldrb w20, [x28, #1051]",
         "add w20, w20, #0x7 (7)",
         "and w20, w20, #0x7",
@@ -2656,7 +2656,7 @@
         "0xd9 11b 0xe9 /5"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3488]",
+        "ldr q2, [x28, #3504]",
         "ldrb w20, [x28, #1051]",
         "add w20, w20, #0x7 (7)",
         "and w20, w20, #0x7",
@@ -2676,7 +2676,7 @@
         "0xd9 11b 0xea /5"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3504]",
+        "ldr q2, [x28, #3520]",
         "ldrb w20, [x28, #1051]",
         "add w20, w20, #0x7 (7)",
         "and w20, w20, #0x7",
@@ -2696,7 +2696,7 @@
         "0xd9 11b 0xeb /5"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3520]",
+        "ldr q2, [x28, #3536]",
         "ldrb w20, [x28, #1051]",
         "add w20, w20, #0x7 (7)",
         "and w20, w20, #0x7",
@@ -2716,7 +2716,7 @@
         "0xd9 11b 0xec /5"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3536]",
+        "ldr q2, [x28, #3552]",
         "ldrb w20, [x28, #1051]",
         "add w20, w20, #0x7 (7)",
         "and w20, w20, #0x7",
@@ -2736,7 +2736,7 @@
         "0xd9 11b 0xed /5"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3552]",
+        "ldr q2, [x28, #3568]",
         "ldrb w20, [x28, #1051]",
         "add w20, w20, #0x7 (7)",
         "and w20, w20, #0x7",
@@ -2835,7 +2835,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v2.16b, v0.16b",
-        "ldr q3, [x28, #3472]",
+        "ldr q3, [x28, #3488]",
         "add w20, w20, #0x7 (7)",
         "and w20, w20, #0x7",
         "strb wzr, [x28, #1050]",
diff --git a/unittests/InstructionCountCI/FlagM/x87_f64-Crysis2Max-fmodel.json b/unittests/InstructionCountCI/FlagM/x87_f64-Crysis2Max-fmodel.json
index 7042c5e52..3b4355008 100644
--- a/unittests/InstructionCountCI/FlagM/x87_f64-Crysis2Max-fmodel.json
+++ b/unittests/InstructionCountCI/FlagM/x87_f64-Crysis2Max-fmodel.json
@@ -13,7 +13,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Instructions": {
     "Block1": {
diff --git a/unittests/InstructionCountCI/FlagM/x87_f64-HalfLife.json b/unittests/InstructionCountCI/FlagM/x87_f64-HalfLife.json
index 950e24722..569779221 100644
--- a/unittests/InstructionCountCI/FlagM/x87_f64-HalfLife.json
+++ b/unittests/InstructionCountCI/FlagM/x87_f64-HalfLife.json
@@ -13,7 +13,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Instructions": {
     "Block1": {
diff --git a/unittests/InstructionCountCI/FlagM/x87_f64-Oblivion.json b/unittests/InstructionCountCI/FlagM/x87_f64-Oblivion.json
index 18dec360c..31529243d 100644
--- a/unittests/InstructionCountCI/FlagM/x87_f64-Oblivion.json
+++ b/unittests/InstructionCountCI/FlagM/x87_f64-Oblivion.json
@@ -13,7 +13,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Instructions": {
     "Block1": {
diff --git a/unittests/InstructionCountCI/FlagM/x87_f64-Psychonauts.json b/unittests/InstructionCountCI/FlagM/x87_f64-Psychonauts.json
index b030fe333..8d9ed4702 100644
--- a/unittests/InstructionCountCI/FlagM/x87_f64-Psychonauts.json
+++ b/unittests/InstructionCountCI/FlagM/x87_f64-Psychonauts.json
@@ -13,7 +13,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Instructions": {
     "Block1": {
diff --git a/unittests/InstructionCountCI/FlagM/x87_f64.json b/unittests/InstructionCountCI/FlagM/x87_f64.json
index d7d7d8490..13ef3b150 100644
--- a/unittests/InstructionCountCI/FlagM/x87_f64.json
+++ b/unittests/InstructionCountCI/FlagM/x87_f64.json
@@ -13,7 +13,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Instructions": {
     "fadd dword [rax]": {
@@ -2201,7 +2201,7 @@
         "add x20, x28, x20, lsl #4",
         "ldr d2, [x20, #1056]",
         "fmov d0, d2",
-        "ldr x0, [x28, #3064]",
+        "ldr x0, [x28, #3072]",
         "str x30, [sp, #-16]!",
         "blr x0",
         "ldr x30, [sp], #16",
@@ -2224,7 +2224,7 @@
         "ldr d3, [x23, #1056]",
         "fmov d0, d3",
         "fmov d1, d2",
-        "ldr x0, [x28, #3088]",
+        "ldr x0, [x28, #3096]",
         "str x30, [sp, #-16]!",
         "blr x0",
         "ldr x30, [sp], #16",
@@ -2248,7 +2248,7 @@
         "add x21, x28, x20, lsl #4",
         "ldr d2, [x21, #1056]",
         "fmov d0, d2",
-        "ldr x0, [x28, #3056]",
+        "ldr x0, [x28, #3064]",
         "str x30, [sp, #-16]!",
         "blr x0",
         "ldr x30, [sp], #16",
@@ -2284,7 +2284,7 @@
         "ldr d3, [x22, #1056]",
         "fmov d0, d3",
         "fmov d1, d2",
-        "ldr x0, [x28, #3080]",
+        "ldr x0, [x28, #3088]",
         "str x30, [sp, #-16]!",
         "blr x0",
         "ldr x30, [sp], #16",
@@ -2361,7 +2361,7 @@
         "ldr d3, [x20, #1056]",
         "fmov d0, d3",
         "fmov d1, d2",
-        "ldr x0, [x28, #3112]",
+        "ldr x0, [x28, #3120]",
         "str x30, [sp, #-16]!",
         "blr x0",
         "ldr x30, [sp], #16",
@@ -2411,7 +2411,7 @@
         "ldr d3, [x20, #1056]",
         "fmov d0, d3",
         "fmov d1, d2",
-        "ldr x0, [x28, #3104]",
+        "ldr x0, [x28, #3112]",
         "str x30, [sp, #-16]!",
         "blr x0",
         "ldr x30, [sp], #16",
@@ -2435,7 +2435,7 @@
         "ldr d3, [x23, #1056]",
         "fmov d0, d3",
         "fmov d1, d2",
-        "ldr x0, [x28, #3096]",
+        "ldr x0, [x28, #3104]",
         "str x30, [sp, #-16]!",
         "blr x0",
         "ldr x30, [sp], #16",
@@ -2472,13 +2472,13 @@
         "add x21, x28, x20, lsl #4",
         "ldr d2, [x21, #1056]",
         "fmov d0, d2",
-        "ldr x0, [x28, #3040]",
+        "ldr x0, [x28, #3048]",
         "str x30, [sp, #-16]!",
         "blr x0",
         "ldr x30, [sp], #16",
         "fmov d3, d0",
         "fmov d0, d2",
-        "ldr x0, [x28, #3048]",
+        "ldr x0, [x28, #3056]",
         "str x30, [sp, #-16]!",
         "blr x0",
         "ldr x30, [sp], #16",
@@ -2525,7 +2525,7 @@
         "ldr d3, [x20, #1056]",
         "fmov d0, d3",
         "fmov d1, d2",
-        "ldr x0, [x28, #3072]",
+        "ldr x0, [x28, #3080]",
         "str x30, [sp, #-16]!",
         "blr x0",
         "ldr x30, [sp], #16",
@@ -2543,7 +2543,7 @@
         "add x20, x28, x20, lsl #4",
         "ldr d2, [x20, #1056]",
         "fmov d0, d2",
-        "ldr x0, [x28, #3040]",
+        "ldr x0, [x28, #3048]",
         "str x30, [sp, #-16]!",
         "blr x0",
         "ldr x30, [sp], #16",
@@ -2562,7 +2562,7 @@
         "add x20, x28, x20, lsl #4",
         "ldr d2, [x20, #1056]",
         "fmov d0, d2",
-        "ldr x0, [x28, #3048]",
+        "ldr x0, [x28, #3056]",
         "str x30, [sp, #-16]!",
         "blr x0",
         "ldr x30, [sp], #16",
diff --git a/unittests/InstructionCountCI/H0F38.json b/unittests/InstructionCountCI/H0F38.json
index 64353bfd1..d7cf512a2 100644
--- a/unittests/InstructionCountCI/H0F38.json
+++ b/unittests/InstructionCountCI/H0F38.json
@@ -10,7 +10,7 @@
       "FLAGM2",
       "CRYPTO"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Instructions": {
     "pshufb mm0, mm1": {
@@ -674,7 +674,7 @@
         "0x66 0x0f 0x38 0x41"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3120]",
+        "ldr q2, [x28, #3136]",
         "zip1 v3.8h, v2.8h, v17.8h",
         "zip2 v2.8h, v2.8h, v17.8h",
         "umin v2.4s, v3.4s, v2.4s",
diff --git a/unittests/InstructionCountCI/H0F3A.json b/unittests/InstructionCountCI/H0F3A.json
index 9b9b02c84..def8149fa 100644
--- a/unittests/InstructionCountCI/H0F3A.json
+++ b/unittests/InstructionCountCI/H0F3A.json
@@ -8,7 +8,7 @@
       "AFP",
       "CRYPTO"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Comment": [
     "SSE4.2 string instructions are skipped here.",
@@ -328,7 +328,7 @@
         "0x66 0x0f 0x3a 0x0c"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3312]",
+        "ldr q2, [x28, #3328]",
         "tbx v16.16b, {v17.16b}, v2.16b"
       ]
     },
@@ -338,7 +338,7 @@
         "0x66 0x0f 0x3a 0x0c"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3328]",
+        "ldr q2, [x28, #3344]",
         "tbx v16.16b, {v17.16b}, v2.16b"
       ]
     },
@@ -357,7 +357,7 @@
         "0x66 0x0f 0x3a 0x0c"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3344]",
+        "ldr q2, [x28, #3360]",
         "tbx v16.16b, {v17.16b}, v2.16b"
       ]
     },
@@ -377,7 +377,7 @@
         "0x66 0x0f 0x3a 0x0c"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3360]",
+        "ldr q2, [x28, #3376]",
         "tbx v16.16b, {v17.16b}, v2.16b"
       ]
     },
@@ -396,7 +396,7 @@
         "0x66 0x0f 0x3a 0x0c"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3376]",
+        "ldr q2, [x28, #3392]",
         "tbx v16.16b, {v17.16b}, v2.16b"
       ]
     },
@@ -406,7 +406,7 @@
         "0x66 0x0f 0x3a 0x0c"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3392]",
+        "ldr q2, [x28, #3408]",
         "tbx v16.16b, {v17.16b}, v2.16b"
       ]
     },
diff --git a/unittests/InstructionCountCI/H0F3A_SVE128.json b/unittests/InstructionCountCI/H0F3A_SVE128.json
index 4795cb844..1bd9f597c 100644
--- a/unittests/InstructionCountCI/H0F3A_SVE128.json
+++ b/unittests/InstructionCountCI/H0F3A_SVE128.json
@@ -8,7 +8,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Instructions": {
     "dpps xmm0, xmm1, 00000000b": {
diff --git a/unittests/InstructionCountCI/MOPS/Primary.json b/unittests/InstructionCountCI/MOPS/Primary.json
index 026df4528..ef5f32c17 100644
--- a/unittests/InstructionCountCI/MOPS/Primary.json
+++ b/unittests/InstructionCountCI/MOPS/Primary.json
@@ -11,7 +11,7 @@
       "FLAGM",
       "FLAGM2"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Instructions": {
     "rep movsb": {
diff --git a/unittests/InstructionCountCI/Primary.json b/unittests/InstructionCountCI/Primary.json
index 268de0088..aa26b7209 100644
--- a/unittests/InstructionCountCI/Primary.json
+++ b/unittests/InstructionCountCI/Primary.json
@@ -10,7 +10,7 @@
       "FLAGM2",
       "MOPS"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Instructions": {
     "add bl, cl": {
@@ -2473,7 +2473,7 @@
         "str x20, [x28, #24]",
         "mov w0, #0x401",
         "str x0, [x28, #1496]",
-        "ldr x0, [x28, #2976]",
+        "ldr x0, [x28, #2984]",
         "br x0"
       ]
     },
@@ -2488,7 +2488,7 @@
         "str x20, [x28, #24]",
         "mov w0, #0x401",
         "str x0, [x28, #1496]",
-        "ldr x0, [x28, #2976]",
+        "ldr x0, [x28, #2984]",
         "br x0"
       ]
     },
@@ -2503,7 +2503,7 @@
         "str x20, [x28, #24]",
         "mov w0, #0x401",
         "str x0, [x28, #1496]",
-        "ldr x0, [x28, #2976]",
+        "ldr x0, [x28, #2984]",
         "br x0"
       ]
     },
diff --git a/unittests/InstructionCountCI/PrimaryGroup.json b/unittests/InstructionCountCI/PrimaryGroup.json
index 0e73641df..d8f4be814 100644
--- a/unittests/InstructionCountCI/PrimaryGroup.json
+++ b/unittests/InstructionCountCI/PrimaryGroup.json
@@ -9,7 +9,7 @@
       "FLAGM",
       "FLAGM2"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Comment": [
     "Instructions in this table that are marked optimal don't have their flag calculation part of this assumption",
@@ -2787,7 +2787,7 @@
         "mov x0, x5",
         "mov x1, x4",
         "mov x2, x6",
-        "ldr x3, [x28, #3024]",
+        "ldr x3, [x28, #3032]",
         "str x30, [sp, #-16]!",
         "blr x3",
         "ldr x30, [sp], #16",
@@ -2838,7 +2838,7 @@
         "mov x0, x5",
         "mov x1, x4",
         "mov x2, x6",
-        "ldr x3, [x28, #3032]",
+        "ldr x3, [x28, #3040]",
         "str x30, [sp, #-16]!",
         "blr x3",
         "ldr x30, [sp], #16",
diff --git a/unittests/InstructionCountCI/Primary_32Bit.json b/unittests/InstructionCountCI/Primary_32Bit.json
index 9c26456e7..b20f142dd 100644
--- a/unittests/InstructionCountCI/Primary_32Bit.json
+++ b/unittests/InstructionCountCI/Primary_32Bit.json
@@ -9,7 +9,7 @@
       "FlagM",
       "FlagM2"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Instructions": {
     "push es": {
diff --git a/unittests/InstructionCountCI/RPRES/DDD.json b/unittests/InstructionCountCI/RPRES/DDD.json
index af982ab41..d5289e27c 100644
--- a/unittests/InstructionCountCI/RPRES/DDD.json
+++ b/unittests/InstructionCountCI/RPRES/DDD.json
@@ -9,7 +9,7 @@
       "SVE128",
       "SVE256"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Instructions": {
     "pfrcpv mm0, mm1": {
diff --git a/unittests/InstructionCountCI/RPRES/Secondary.json b/unittests/InstructionCountCI/RPRES/Secondary.json
index 4956b7224..497790607 100644
--- a/unittests/InstructionCountCI/RPRES/Secondary.json
+++ b/unittests/InstructionCountCI/RPRES/Secondary.json
@@ -9,7 +9,7 @@
       "SVE128",
       "SVE256"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Instructions": {
     "rsqrtps xmm0, xmm1": {
diff --git a/unittests/InstructionCountCI/RPRES/Secondary_REP_AFP.json b/unittests/InstructionCountCI/RPRES/Secondary_REP_AFP.json
index 4d85efb8d..3d4dabf74 100644
--- a/unittests/InstructionCountCI/RPRES/Secondary_REP_AFP.json
+++ b/unittests/InstructionCountCI/RPRES/Secondary_REP_AFP.json
@@ -9,7 +9,7 @@
       "SVE128",
       "SVE256"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Instructions": {
     "rsqrtss xmm0, xmm1": {
diff --git a/unittests/InstructionCountCI/RPRES/VEX_map1_AFP.json b/unittests/InstructionCountCI/RPRES/VEX_map1_AFP.json
index 767e451b4..70537a70e 100644
--- a/unittests/InstructionCountCI/RPRES/VEX_map1_AFP.json
+++ b/unittests/InstructionCountCI/RPRES/VEX_map1_AFP.json
@@ -8,7 +8,7 @@
       "AFP"
     ],
     "DisabledHostFeatures": [],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Instructions": {
     "vrsqrtps xmm0, xmm1": {
diff --git a/unittests/InstructionCountCI/Repeat.json b/unittests/InstructionCountCI/Repeat.json
index f52b54dd5..af5e63b9a 100644
--- a/unittests/InstructionCountCI/Repeat.json
+++ b/unittests/InstructionCountCI/Repeat.json
@@ -6,7 +6,7 @@
       "SVE128",
       "SVE256"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Instructions": {}
 }
diff --git a/unittests/InstructionCountCI/SSE42_Strings.json b/unittests/InstructionCountCI/SSE42_Strings.json
index cb00f6e59..dc86d0470 100644
--- a/unittests/InstructionCountCI/SSE42_Strings.json
+++ b/unittests/InstructionCountCI/SSE42_Strings.json
@@ -33,7 +33,7 @@
       "      - 1b: ECX = MSB",
       "[7]   - Reserved"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Instructions": {
     "pcmpestrm xmm0, xmm1, 0_0_00_00_00b": {
diff --git a/unittests/InstructionCountCI/Secondary.json b/unittests/InstructionCountCI/Secondary.json
index 131782bbd..832e9a7cb 100644
--- a/unittests/InstructionCountCI/Secondary.json
+++ b/unittests/InstructionCountCI/Secondary.json
@@ -12,7 +12,7 @@
       "FLAGM",
       "FLAGM2"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Comment": [
     "MMX instructions are defined as optimal without SRA being used for these instructions.",
@@ -652,7 +652,7 @@
       "Comment": "0x0f 0x50",
       "ExpectedArm64ASM": [
         "ushr v2.4s, v16.4s, #31",
-        "ldr q3, [x28, #3280]",
+        "ldr q3, [x28, #3296]",
         "ushl v2.4s, v2.4s, v3.4s",
         "addv s2, v2.4s",
         "mov w4, v2.s[0]"
@@ -663,7 +663,7 @@
       "Comment": "0x0f 0x50",
       "ExpectedArm64ASM": [
         "ushr v2.4s, v16.4s, #31",
-        "ldr q3, [x28, #3280]",
+        "ldr q3, [x28, #3296]",
         "ushl v2.4s, v2.4s, v3.4s",
         "addv s2, v2.4s",
         "mov w4, v2.s[0]"
@@ -3698,7 +3698,7 @@
         "mov w20, #0xffff",
         "strb w20, [x28, #1202]",
         "ldr d2, [x28, #1056]",
-        "ldr d3, [x28, #3408]",
+        "ldr d3, [x28, #3424]",
         "cmlt v2.16b, v2.16b, #0",
         "and v2.8b, v2.8b, v3.8b",
         "addp v2.16b, v2.16b, v2.16b",
diff --git a/unittests/InstructionCountCI/SecondaryGroup.json b/unittests/InstructionCountCI/SecondaryGroup.json
index ba6c1f691..dd5fd3625 100644
--- a/unittests/InstructionCountCI/SecondaryGroup.json
+++ b/unittests/InstructionCountCI/SecondaryGroup.json
@@ -11,7 +11,7 @@
       "FLAGM",
       "FLAGM2"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Instructions": {
     "sgdt [rax]": {
diff --git a/unittests/InstructionCountCI/SecondaryModRM.json b/unittests/InstructionCountCI/SecondaryModRM.json
index f98cf402e..0eac75349 100644
--- a/unittests/InstructionCountCI/SecondaryModRM.json
+++ b/unittests/InstructionCountCI/SecondaryModRM.json
@@ -11,7 +11,7 @@
       "FLAGM",
       "FLAGM2"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Instructions": {
     "xgetbv": {
diff --git a/unittests/InstructionCountCI/Secondary_32Bit.json b/unittests/InstructionCountCI/Secondary_32Bit.json
index 29de8a3f2..0863531b1 100644
--- a/unittests/InstructionCountCI/Secondary_32Bit.json
+++ b/unittests/InstructionCountCI/Secondary_32Bit.json
@@ -7,7 +7,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Instructions": {
     "push fs": {
diff --git a/unittests/InstructionCountCI/Secondary_OpSize.json b/unittests/InstructionCountCI/Secondary_OpSize.json
index 46e86cd39..fd9f921b5 100644
--- a/unittests/InstructionCountCI/Secondary_OpSize.json
+++ b/unittests/InstructionCountCI/Secondary_OpSize.json
@@ -12,7 +12,7 @@
       "FLAGM",
       "FLAGM2"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Instructions": {
     "movupd xmm0, xmm0": {
@@ -1260,7 +1260,7 @@
       "ExpectedInstructionCount": 3,
       "Comment": "0x66 0x0f 0xd0",
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3184]",
+        "ldr q2, [x28, #3200]",
         "eor v2.16b, v17.16b, v2.16b",
         "fadd v16.2d, v16.2d, v2.2d"
       ]
@@ -1316,7 +1316,7 @@
       "ExpectedInstructionCount": 7,
       "Comment": "0x66 0x0f 0xd7",
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3408]",
+        "ldr q2, [x28, #3424]",
         "cmlt v3.16b, v16.16b, #0",
         "and v2.16b, v3.16b, v2.16b",
         "addp v2.16b, v2.16b, v2.16b",
diff --git a/unittests/InstructionCountCI/Secondary_OpSize_FCMA.json b/unittests/InstructionCountCI/Secondary_OpSize_FCMA.json
index da035472d..e63d5f896 100644
--- a/unittests/InstructionCountCI/Secondary_OpSize_FCMA.json
+++ b/unittests/InstructionCountCI/Secondary_OpSize_FCMA.json
@@ -9,7 +9,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Instructions": {
     "addsubpd xmm0, xmm1": {
diff --git a/unittests/InstructionCountCI/Secondary_OpSize_SVE128.json b/unittests/InstructionCountCI/Secondary_OpSize_SVE128.json
index 693fb1747..95061c931 100644
--- a/unittests/InstructionCountCI/Secondary_OpSize_SVE128.json
+++ b/unittests/InstructionCountCI/Secondary_OpSize_SVE128.json
@@ -8,7 +8,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Instructions": {
     "psrlw xmm0, xmm1": {
diff --git a/unittests/InstructionCountCI/Secondary_OpSize_SVE256.json b/unittests/InstructionCountCI/Secondary_OpSize_SVE256.json
index 80d90cc32..c84dd7849 100644
--- a/unittests/InstructionCountCI/Secondary_OpSize_SVE256.json
+++ b/unittests/InstructionCountCI/Secondary_OpSize_SVE256.json
@@ -7,7 +7,7 @@
       "AFP"
     ],
     "DisabledHostFeatures": [],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Instructions": {
     "pmulhuw xmm0, xmm1": {
diff --git a/unittests/InstructionCountCI/Secondary_REP.json b/unittests/InstructionCountCI/Secondary_REP.json
index 9235e1965..816e801bd 100644
--- a/unittests/InstructionCountCI/Secondary_REP.json
+++ b/unittests/InstructionCountCI/Secondary_REP.json
@@ -12,7 +12,7 @@
       "FRINTTS",
       "CSSC"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Instructions": {
     "movss xmm0, xmm1": {
@@ -119,7 +119,7 @@
       "ExpectedArm64ASM": [
         "fcvtzs w20, s16",
         "mov w21, #0x80000000",
-        "ldr s2, [x28, #3568]",
+        "ldr s2, [x28, #3584]",
         "mrs x22, nzcv",
         "fcmp s2, s16",
         "csel w4, w20, w21, gt",
@@ -133,7 +133,7 @@
         "ldr s2, [x6]",
         "fcvtzs w20, s2",
         "mov w21, #0x80000000",
-        "ldr s3, [x28, #3568]",
+        "ldr s3, [x28, #3584]",
         "mrs x22, nzcv",
         "fcmp s3, s2",
         "csel w4, w20, w21, gt",
@@ -146,7 +146,7 @@
       "ExpectedArm64ASM": [
         "fcvtzs x20, s16",
         "mov x21, #0x8000000000000000",
-        "ldr s2, [x28, #3600]",
+        "ldr s2, [x28, #3616]",
         "mrs x22, nzcv",
         "fcmp s2, s16",
         "csel x4, x20, x21, gt",
@@ -160,7 +160,7 @@
         "ldr s2, [x6]",
         "fcvtzs x20, s2",
         "mov x21, #0x8000000000000000",
-        "ldr s3, [x28, #3600]",
+        "ldr s3, [x28, #3616]",
         "mrs x22, nzcv",
         "fcmp s3, s2",
         "csel x4, x20, x21, gt",
@@ -174,7 +174,7 @@
         "frinti s2, s16",
         "fcvtzs w20, s2",
         "mov w21, #0x80000000",
-        "ldr s3, [x28, #3568]",
+        "ldr s3, [x28, #3584]",
         "mrs x22, nzcv",
         "fcmp s3, s2",
         "csel w4, w20, w21, gt",
@@ -189,7 +189,7 @@
         "frinti s2, s2",
         "fcvtzs w20, s2",
         "mov w21, #0x80000000",
-        "ldr s3, [x28, #3568]",
+        "ldr s3, [x28, #3584]",
         "mrs x22, nzcv",
         "fcmp s3, s2",
         "csel w4, w20, w21, gt",
@@ -203,7 +203,7 @@
         "frinti s2, s16",
         "fcvtzs x20, s2",
         "mov x21, #0x8000000000000000",
-        "ldr s3, [x28, #3600]",
+        "ldr s3, [x28, #3616]",
         "mrs x22, nzcv",
         "fcmp s3, s2",
         "csel x4, x20, x21, gt",
@@ -218,7 +218,7 @@
         "frinti s2, s2",
         "fcvtzs x20, s2",
         "mov x21, #0x8000000000000000",
-        "ldr s3, [x28, #3600]",
+        "ldr s3, [x28, #3616]",
         "mrs x22, nzcv",
         "fcmp s3, s2",
         "csel x4, x20, x21, gt",
@@ -297,8 +297,8 @@
       "ExpectedInstructionCount": 6,
       "Comment": "0xf3 0x0f 0x5b",
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3664]",
-        "ldr q3, [x28, #3568]",
+        "ldr q2, [x28, #3680]",
+        "ldr q3, [x28, #3584]",
         "fcvtzs v4.4s, v17.4s",
         "fcmgt v3.4s, v3.4s, v17.4s",
         "mov v16.16b, v3.16b",
diff --git a/unittests/InstructionCountCI/Secondary_REPNE.json b/unittests/InstructionCountCI/Secondary_REPNE.json
index b79b30479..31516d9c8 100644
--- a/unittests/InstructionCountCI/Secondary_REPNE.json
+++ b/unittests/InstructionCountCI/Secondary_REPNE.json
@@ -10,7 +10,7 @@
       "FCMA",
       "AFP"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Instructions": {
     "movsd xmm0, xmm1": {
@@ -500,7 +500,7 @@
       "ExpectedInstructionCount": 3,
       "Comment": "0xf2 0x0f 0xd0",
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3152]",
+        "ldr q2, [x28, #3168]",
         "eor v2.16b, v17.16b, v2.16b",
         "fadd v16.4s, v16.4s, v2.4s"
       ]
diff --git a/unittests/InstructionCountCI/Secondary_REPNE_FCMA.json b/unittests/InstructionCountCI/Secondary_REPNE_FCMA.json
index ed7af0648..18175fb50 100644
--- a/unittests/InstructionCountCI/Secondary_REPNE_FCMA.json
+++ b/unittests/InstructionCountCI/Secondary_REPNE_FCMA.json
@@ -9,7 +9,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Instructions": {
     "addsubps xmm0, xmm1": {
diff --git a/unittests/InstructionCountCI/Secondary_REPNE_SVE128.json b/unittests/InstructionCountCI/Secondary_REPNE_SVE128.json
index 2b27b1e1d..32aa347cb 100644
--- a/unittests/InstructionCountCI/Secondary_REPNE_SVE128.json
+++ b/unittests/InstructionCountCI/Secondary_REPNE_SVE128.json
@@ -10,7 +10,7 @@
       "FCMA",
       "AFP"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Instructions": {
     "cvtpd2dq xmm0, xmm1": {
diff --git a/unittests/InstructionCountCI/Secondary_REP_FRINTTS.json b/unittests/InstructionCountCI/Secondary_REP_FRINTTS.json
index 0b6027e23..ba2d5e1a9 100644
--- a/unittests/InstructionCountCI/Secondary_REP_FRINTTS.json
+++ b/unittests/InstructionCountCI/Secondary_REP_FRINTTS.json
@@ -12,7 +12,7 @@
       "FLAGM",
       "FLAGM2"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Instructions": {
     "cvttss2si eax, xmm0": {
diff --git a/unittests/InstructionCountCI/Secondary_SVE128.json b/unittests/InstructionCountCI/Secondary_SVE128.json
index 3619d0772..027ae9d33 100644
--- a/unittests/InstructionCountCI/Secondary_SVE128.json
+++ b/unittests/InstructionCountCI/Secondary_SVE128.json
@@ -8,7 +8,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Instructions": {
     "movmskps eax, xmm0": {
diff --git a/unittests/InstructionCountCI/VEX_map1.json b/unittests/InstructionCountCI/VEX_map1.json
index 82a8e698d..992a42634 100644
--- a/unittests/InstructionCountCI/VEX_map1.json
+++ b/unittests/InstructionCountCI/VEX_map1.json
@@ -13,7 +13,7 @@
       "FLAGM2",
       "FRINTTS"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Instructions": {
     "vmovups xmm0, xmm0": {
@@ -3168,7 +3168,7 @@
       "ExpectedArm64ASM": [
         "fcvtzs w20, s16",
         "mov w21, #0x80000000",
-        "ldr s2, [x28, #3568]",
+        "ldr s2, [x28, #3584]",
         "mrs x22, nzcv",
         "fcmp s2, s16",
         "csel w4, w20, w21, gt",
@@ -3183,7 +3183,7 @@
       "ExpectedArm64ASM": [
         "fcvtzs x20, s16",
         "mov x21, #0x8000000000000000",
-        "ldr s2, [x28, #3600]",
+        "ldr s2, [x28, #3616]",
         "mrs x22, nzcv",
         "fcmp s2, s16",
         "csel x4, x20, x21, gt",
@@ -3198,7 +3198,7 @@
       "ExpectedArm64ASM": [
         "fcvtzs w20, d16",
         "mov w21, #0x80000000",
-        "ldr d2, [x28, #3616]",
+        "ldr d2, [x28, #3632]",
         "mrs x22, nzcv",
         "fcmp d2, d16",
         "csel w4, w20, w21, gt",
@@ -3213,7 +3213,7 @@
       "ExpectedArm64ASM": [
         "fcvtzs x20, d16",
         "mov x21, #0x8000000000000000",
-        "ldr d2, [x28, #3648]",
+        "ldr d2, [x28, #3664]",
         "mrs x22, nzcv",
         "fcmp d2, d16",
         "csel x4, x20, x21, gt",
@@ -3229,7 +3229,7 @@
         "frinti s2, s16",
         "fcvtzs w20, s2",
         "mov w21, #0x80000000",
-        "ldr s3, [x28, #3568]",
+        "ldr s3, [x28, #3584]",
         "mrs x22, nzcv",
         "fcmp s3, s2",
         "csel w4, w20, w21, gt",
@@ -3245,7 +3245,7 @@
         "frinti s2, s16",
         "fcvtzs x20, s2",
         "mov x21, #0x8000000000000000",
-        "ldr s3, [x28, #3600]",
+        "ldr s3, [x28, #3616]",
         "mrs x22, nzcv",
         "fcmp s3, s2",
         "csel x4, x20, x21, gt",
@@ -3261,7 +3261,7 @@
         "frinti d2, d16",
         "fcvtzs w20, d2",
         "mov w21, #0x80000000",
-        "ldr d3, [x28, #3616]",
+        "ldr d3, [x28, #3632]",
         "mrs x22, nzcv",
         "fcmp d3, d2",
         "csel w4, w20, w21, gt",
@@ -3277,7 +3277,7 @@
         "frinti d2, d16",
         "fcvtzs x20, d2",
         "mov x21, #0x8000000000000000",
-        "ldr d3, [x28, #3648]",
+        "ldr d3, [x28, #3664]",
         "mrs x22, nzcv",
         "fcmp d3, d2",
         "csel x4, x20, x21, gt",
@@ -3626,8 +3626,8 @@
       ],
       "ExpectedArm64ASM": [
         "frinti v2.4s, v17.4s",
-        "ldr q3, [x28, #3664]",
-        "ldr q4, [x28, #3568]",
+        "ldr q3, [x28, #3680]",
+        "ldr q4, [x28, #3584]",
         "fcvtzs v5.4s, v2.4s",
         "fcmgt v2.4s, v4.4s, v2.4s",
         "mov v16.16b, v2.16b",
@@ -3661,8 +3661,8 @@
         "Map 1 0b10 0x5b 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3664]",
-        "ldr q3, [x28, #3568]",
+        "ldr q2, [x28, #3680]",
+        "ldr q3, [x28, #3584]",
         "fcvtzs v4.4s, v17.4s",
         "fcmgt v3.4s, v3.4s, v17.4s",
         "mov v16.16b, v3.16b",
@@ -4356,7 +4356,7 @@
         "Map 1 0b01 0xd0 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3184]",
+        "ldr q2, [x28, #3200]",
         "eor v2.16b, v18.16b, v2.16b",
         "fadd v16.2d, v17.2d, v2.2d"
       ]
@@ -4379,7 +4379,7 @@
         "Map 1 0b11 0xd0 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3152]",
+        "ldr q2, [x28, #3168]",
         "eor v2.16b, v18.16b, v2.16b",
         "fadd v16.4s, v17.4s, v2.4s"
       ]
@@ -4514,7 +4514,7 @@
         "Map 1 0b01 0xd7 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3408]",
+        "ldr q2, [x28, #3424]",
         "cmlt v3.16b, v16.16b, #0",
         "and v2.16b, v3.16b, v2.16b",
         "addp v2.16b, v2.16b, v2.16b",
@@ -4903,8 +4903,8 @@
         "Map 1 0b01 0xe6 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr d2, [x28, #3664]",
-        "ldr q3, [x28, #3616]",
+        "ldr d2, [x28, #3680]",
+        "ldr q3, [x28, #3632]",
         "fcvtzs z4.s, p6/m, z17.d",
         "uzp1 z4.s, z4.s, z4.s",
         "mov v4.8b, v4.8b",
@@ -4920,7 +4920,7 @@
         "Map 1 0b01 0xe6 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3664]",
+        "ldr q2, [x28, #3680]",
         "ldr x0, [x28, #2648]",
         "ld1b {z3.b}, p7/z, [x0]",
         "fcvtzs z4.s, p7/m, z17.d",
@@ -4964,8 +4964,8 @@
       ],
       "ExpectedArm64ASM": [
         "frinti v2.2d, v17.2d",
-        "ldr d3, [x28, #3664]",
-        "ldr q4, [x28, #3616]",
+        "ldr d3, [x28, #3680]",
+        "ldr q4, [x28, #3632]",
         "fcvtzs z5.s, p6/m, z2.d",
         "uzp1 z5.s, z5.s, z5.s",
         "mov v5.8b, v5.8b",
@@ -4982,7 +4982,7 @@
       ],
       "ExpectedArm64ASM": [
         "frinti z2.d, p7/m, z17.d",
-        "ldr q3, [x28, #3664]",
+        "ldr q3, [x28, #3680]",
         "ldr x0, [x28, #2648]",
         "ld1b {z4.b}, p7/z, [x0]",
         "fcvtzs z5.s, p7/m, z2.d",
diff --git a/unittests/InstructionCountCI/VEX_map1_FCMA.json b/unittests/InstructionCountCI/VEX_map1_FCMA.json
index 35c6e964a..69b1f0093 100644
--- a/unittests/InstructionCountCI/VEX_map1_FCMA.json
+++ b/unittests/InstructionCountCI/VEX_map1_FCMA.json
@@ -8,7 +8,7 @@
       "FCMA"
     ],
     "DisabledHostFeatures": [],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Instructions": {
     "vaddsubpd xmm0, xmm1, xmm2": {
diff --git a/unittests/InstructionCountCI/VEX_map1_FRINTTS.json b/unittests/InstructionCountCI/VEX_map1_FRINTTS.json
index de25e679a..999b1e449 100644
--- a/unittests/InstructionCountCI/VEX_map1_FRINTTS.json
+++ b/unittests/InstructionCountCI/VEX_map1_FRINTTS.json
@@ -13,7 +13,7 @@
       "FLAGM",
       "FLAGM2"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Instructions": {
     "vcvttss2si eax, xmm0": {
@@ -174,7 +174,7 @@
         "Map 1 0b01 0xe6 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3664]",
+        "ldr q2, [x28, #3680]",
         "ldr x0, [x28, #2648]",
         "ld1b {z3.b}, p7/z, [x0]",
         "fcvtzs z4.s, p7/m, z17.d",
@@ -209,7 +209,7 @@
       ],
       "ExpectedArm64ASM": [
         "frinti z2.d, p7/m, z17.d",
-        "ldr q3, [x28, #3664]",
+        "ldr q3, [x28, #3680]",
         "ldr x0, [x28, #2648]",
         "ld1b {z4.b}, p7/z, [x0]",
         "fcvtzs z5.s, p7/m, z2.d",
diff --git a/unittests/InstructionCountCI/VEX_map2.json b/unittests/InstructionCountCI/VEX_map2.json
index 76711a729..a83af2327 100644
--- a/unittests/InstructionCountCI/VEX_map2.json
+++ b/unittests/InstructionCountCI/VEX_map2.json
@@ -13,7 +13,7 @@
       "I8MM",
       "DOTPROD"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Instructions": {
     "vpshufb xmm0, xmm1, xmm2": {
@@ -1511,7 +1511,7 @@
         "Map 2 0b01 0x41 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3120]",
+        "ldr q2, [x28, #3136]",
         "zip1 v3.8h, v2.8h, v17.8h",
         "zip2 v2.8h, v2.8h, v17.8h",
         "umin v2.4s, v3.4s, v2.4s",
@@ -3757,7 +3757,7 @@
         "Map 2 0b01 0x96 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3152]",
+        "ldr q2, [x28, #3168]",
         "eor v2.16b, v17.16b, v2.16b",
         "fmla v2.4s, v16.4s, v18.4s",
         "mov v16.16b, v2.16b"
@@ -3783,7 +3783,7 @@
         "Map 2 0b01 0x96 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3184]",
+        "ldr q2, [x28, #3200]",
         "eor v2.16b, v17.16b, v2.16b",
         "fmla v2.2d, v16.2d, v18.2d",
         "mov v16.16b, v2.16b"
@@ -3809,7 +3809,7 @@
         "Map 2 0b01 0x97 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3216]",
+        "ldr q2, [x28, #3232]",
         "eor v2.16b, v17.16b, v2.16b",
         "fmla v2.4s, v16.4s, v18.4s",
         "mov v16.16b, v2.16b"
@@ -3835,7 +3835,7 @@
         "Map 2 0b01 0x97 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3248]",
+        "ldr q2, [x28, #3264]",
         "eor v2.16b, v17.16b, v2.16b",
         "fmla v2.2d, v16.2d, v18.2d",
         "mov v16.16b, v2.16b"
@@ -4709,7 +4709,7 @@
         "Map 2 0b01 0xa6 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3152]",
+        "ldr q2, [x28, #3168]",
         "eor v2.16b, v18.16b, v2.16b",
         "fmla v2.4s, v17.4s, v16.4s",
         "mov v16.16b, v2.16b"
@@ -4735,7 +4735,7 @@
         "Map 2 0b01 0xa6 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3184]",
+        "ldr q2, [x28, #3200]",
         "eor v2.16b, v18.16b, v2.16b",
         "fmla v2.2d, v17.2d, v16.2d",
         "mov v16.16b, v2.16b"
@@ -4761,7 +4761,7 @@
         "Map 2 0b01 0xa7 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3216]",
+        "ldr q2, [x28, #3232]",
         "eor v2.16b, v18.16b, v2.16b",
         "fmla v2.4s, v17.4s, v16.4s",
         "mov v16.16b, v2.16b"
@@ -4787,7 +4787,7 @@
         "Map 2 0b01 0xa7 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3248]",
+        "ldr q2, [x28, #3264]",
         "eor v2.16b, v18.16b, v2.16b",
         "fmla v2.2d, v17.2d, v16.2d",
         "mov v16.16b, v2.16b"
@@ -4813,7 +4813,7 @@
         "Map 2 0b01 0xb6 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3152]",
+        "ldr q2, [x28, #3168]",
         "eor v2.16b, v16.16b, v2.16b",
         "fmla v2.4s, v17.4s, v18.4s",
         "mov v16.16b, v2.16b"
@@ -4838,7 +4838,7 @@
         "Map 2 0b01 0xb6 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3184]",
+        "ldr q2, [x28, #3200]",
         "eor v2.16b, v16.16b, v2.16b",
         "fmla v2.2d, v17.2d, v18.2d",
         "mov v16.16b, v2.16b"
@@ -4863,7 +4863,7 @@
         "Map 2 0b01 0xb7 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3216]",
+        "ldr q2, [x28, #3232]",
         "eor v2.16b, v16.16b, v2.16b",
         "fmla v2.4s, v17.4s, v18.4s",
         "mov v16.16b, v2.16b"
@@ -4888,7 +4888,7 @@
         "Map 2 0b01 0xb7 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3248]",
+        "ldr q2, [x28, #3264]",
         "eor v2.16b, v16.16b, v2.16b",
         "fmla v2.2d, v17.2d, v18.2d",
         "mov v16.16b, v2.16b"
diff --git a/unittests/InstructionCountCI/VEX_map2_DOTPROD.json b/unittests/InstructionCountCI/VEX_map2_DOTPROD.json
index 38648b753..0d60b65e1 100644
--- a/unittests/InstructionCountCI/VEX_map2_DOTPROD.json
+++ b/unittests/InstructionCountCI/VEX_map2_DOTPROD.json
@@ -13,7 +13,7 @@
       "SVEBITPERM",
       "I8MM"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Instructions": {
     "vpdpbusd xmm0, xmm1, xmm2": {
diff --git a/unittests/InstructionCountCI/VEX_map2_I8MM.json b/unittests/InstructionCountCI/VEX_map2_I8MM.json
index d45e6d642..da47fab5d 100644
--- a/unittests/InstructionCountCI/VEX_map2_I8MM.json
+++ b/unittests/InstructionCountCI/VEX_map2_I8MM.json
@@ -12,7 +12,7 @@
       "FLAGM2",
       "SVEBITPERM"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Instructions": {
     "vpdpbusd xmm0, xmm1, xmm2": {
diff --git a/unittests/InstructionCountCI/VEX_map2_svebitperm.json b/unittests/InstructionCountCI/VEX_map2_svebitperm.json
index 1247e79b4..81732b114 100644
--- a/unittests/InstructionCountCI/VEX_map2_svebitperm.json
+++ b/unittests/InstructionCountCI/VEX_map2_svebitperm.json
@@ -11,7 +11,7 @@
       "FLAGM",
       "FLAGM2"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Instructions": {
     "pext eax, ebx, ecx": {
diff --git a/unittests/InstructionCountCI/VEX_map3.json b/unittests/InstructionCountCI/VEX_map3.json
index 3520f103e..f9ff4a75f 100644
--- a/unittests/InstructionCountCI/VEX_map3.json
+++ b/unittests/InstructionCountCI/VEX_map3.json
@@ -8,7 +8,7 @@
     "DisabledHostFeatures": [
       "AFP"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Instructions": {
     "vpermq ymm0, ymm1, 1": {
@@ -4199,7 +4199,7 @@
         "Map 3 0b01 0xdf 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3296]",
+        "ldr q2, [x28, #3312]",
         "movi v3.2d, #0x0",
         "mov v16.16b, v17.16b",
         "aese v16.16b, v3.16b",
@@ -4212,7 +4212,7 @@
         "Map 3 0b01 0xdf 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3296]",
+        "ldr q2, [x28, #3312]",
         "movi v3.2d, #0x0",
         "mov v16.16b, v17.16b",
         "aese v16.16b, v3.16b",
diff --git a/unittests/InstructionCountCI/VEX_map_group.json b/unittests/InstructionCountCI/VEX_map_group.json
index fef54963a..7b10c5c45 100644
--- a/unittests/InstructionCountCI/VEX_map_group.json
+++ b/unittests/InstructionCountCI/VEX_map_group.json
@@ -9,7 +9,7 @@
       "FLAGM",
       "FLAGM2"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Instructions": {
     "vpsrlw xmm0, xmm1, 0": {
diff --git a/unittests/InstructionCountCI/X87ldst-SVE.json b/unittests/InstructionCountCI/X87ldst-SVE.json
index 9ee2ca5d6..940bc6f2b 100644
--- a/unittests/InstructionCountCI/X87ldst-SVE.json
+++ b/unittests/InstructionCountCI/X87ldst-SVE.json
@@ -11,7 +11,7 @@
       "FLAGM2",
       "RPRES"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Instructions": {
     "fstp tword [rax]": {
diff --git a/unittests/InstructionCountCI/x87.json b/unittests/InstructionCountCI/x87.json
index dafe12d34..4ec37fc9c 100644
--- a/unittests/InstructionCountCI/x87.json
+++ b/unittests/InstructionCountCI/x87.json
@@ -10,7 +10,7 @@
       "FLAGM",
       "FLAGM2"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Instructions": {
     "fadd dword [rax]": {
@@ -2553,7 +2553,7 @@
         "ldrb w20, [x28, #1051]",
         "add x20, x28, x20, lsl #4",
         "ldr q2, [x20, #1056]",
-        "ldr q3, [x28, #3696]",
+        "ldr q3, [x28, #3712]",
         "eor v2.16b, v2.16b, v3.16b",
         "str q2, [x20, #1056]"
       ]
@@ -2567,7 +2567,7 @@
         "ldrb w20, [x28, #1051]",
         "add x20, x28, x20, lsl #4",
         "ldr q2, [x20, #1056]",
-        "ldr q3, [x28, #3696]",
+        "ldr q3, [x28, #3712]",
         "bic v2.16b, v2.16b, v3.16b",
         "str q2, [x20, #1056]"
       ]
@@ -2635,7 +2635,7 @@
         "0xd9 11b 0xe8 /5"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3472]",
+        "ldr q2, [x28, #3488]",
         "ldrb w20, [x28, #1051]",
         "add w20, w20, #0x7 (7)",
         "and w20, w20, #0x7",
@@ -2655,7 +2655,7 @@
         "0xd9 11b 0xe9 /5"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3488]",
+        "ldr q2, [x28, #3504]",
         "ldrb w20, [x28, #1051]",
         "add w20, w20, #0x7 (7)",
         "and w20, w20, #0x7",
@@ -2675,7 +2675,7 @@
         "0xd9 11b 0xea /5"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3504]",
+        "ldr q2, [x28, #3520]",
         "ldrb w20, [x28, #1051]",
         "add w20, w20, #0x7 (7)",
         "and w20, w20, #0x7",
@@ -2695,7 +2695,7 @@
         "0xd9 11b 0xeb /5"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3520]",
+        "ldr q2, [x28, #3536]",
         "ldrb w20, [x28, #1051]",
         "add w20, w20, #0x7 (7)",
         "and w20, w20, #0x7",
@@ -2715,7 +2715,7 @@
         "0xd9 11b 0xec /5"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3536]",
+        "ldr q2, [x28, #3552]",
         "ldrb w20, [x28, #1051]",
         "add w20, w20, #0x7 (7)",
         "and w20, w20, #0x7",
@@ -2735,7 +2735,7 @@
         "0xd9 11b 0xed /5"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3552]",
+        "ldr q2, [x28, #3568]",
         "ldrb w20, [x28, #1051]",
         "add w20, w20, #0x7 (7)",
         "and w20, w20, #0x7",
@@ -2834,7 +2834,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v2.16b, v0.16b",
-        "ldr q3, [x28, #3472]",
+        "ldr q3, [x28, #3488]",
         "add w20, w20, #0x7 (7)",
         "and w20, w20, #0x7",
         "strb wzr, [x28, #1050]",
diff --git a/unittests/InstructionCountCI/x87_32Bit.json b/unittests/InstructionCountCI/x87_32Bit.json
index d43a67dba..8d74e74b4 100644
--- a/unittests/InstructionCountCI/x87_32Bit.json
+++ b/unittests/InstructionCountCI/x87_32Bit.json
@@ -10,7 +10,7 @@
       "FLAGM",
       "FLAGM2"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Instructions": {
     "Multiple fld/fst": {
diff --git a/unittests/InstructionCountCI/x87_f64.json b/unittests/InstructionCountCI/x87_f64.json
index 080cff5da..a65916a4f 100644
--- a/unittests/InstructionCountCI/x87_f64.json
+++ b/unittests/InstructionCountCI/x87_f64.json
@@ -12,7 +12,7 @@
       "FLAGM",
       "FLAGM2"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Instructions": {
     "fadd dword [rax]": {
@@ -2219,7 +2219,7 @@
         "add x20, x28, x20, lsl #4",
         "ldr d2, [x20, #1056]",
         "fmov d0, d2",
-        "ldr x0, [x28, #3064]",
+        "ldr x0, [x28, #3072]",
         "str x30, [sp, #-16]!",
         "blr x0",
         "ldr x30, [sp], #16",
@@ -2242,7 +2242,7 @@
         "ldr d3, [x23, #1056]",
         "fmov d0, d3",
         "fmov d1, d2",
-        "ldr x0, [x28, #3088]",
+        "ldr x0, [x28, #3096]",
         "str x30, [sp, #-16]!",
         "blr x0",
         "ldr x30, [sp], #16",
@@ -2266,7 +2266,7 @@
         "add x21, x28, x20, lsl #4",
         "ldr d2, [x21, #1056]",
         "fmov d0, d2",
-        "ldr x0, [x28, #3056]",
+        "ldr x0, [x28, #3064]",
         "str x30, [sp, #-16]!",
         "blr x0",
         "ldr x30, [sp], #16",
@@ -2302,7 +2302,7 @@
         "ldr d3, [x22, #1056]",
         "fmov d0, d3",
         "fmov d1, d2",
-        "ldr x0, [x28, #3080]",
+        "ldr x0, [x28, #3088]",
         "str x30, [sp, #-16]!",
         "blr x0",
         "ldr x30, [sp], #16",
@@ -2379,7 +2379,7 @@
         "ldr d3, [x20, #1056]",
         "fmov d0, d3",
         "fmov d1, d2",
-        "ldr x0, [x28, #3112]",
+        "ldr x0, [x28, #3120]",
         "str x30, [sp, #-16]!",
         "blr x0",
         "ldr x30, [sp], #16",
@@ -2429,7 +2429,7 @@
         "ldr d3, [x20, #1056]",
         "fmov d0, d3",
         "fmov d1, d2",
-        "ldr x0, [x28, #3104]",
+        "ldr x0, [x28, #3112]",
         "str x30, [sp, #-16]!",
         "blr x0",
         "ldr x30, [sp], #16",
@@ -2453,7 +2453,7 @@
         "ldr d3, [x23, #1056]",
         "fmov d0, d3",
         "fmov d1, d2",
-        "ldr x0, [x28, #3096]",
+        "ldr x0, [x28, #3104]",
         "str x30, [sp, #-16]!",
         "blr x0",
         "ldr x30, [sp], #16",
@@ -2490,13 +2490,13 @@
         "add x21, x28, x20, lsl #4",
         "ldr d2, [x21, #1056]",
         "fmov d0, d2",
-        "ldr x0, [x28, #3040]",
+        "ldr x0, [x28, #3048]",
         "str x30, [sp, #-16]!",
         "blr x0",
         "ldr x30, [sp], #16",
         "fmov d3, d0",
         "fmov d0, d2",
-        "ldr x0, [x28, #3048]",
+        "ldr x0, [x28, #3056]",
         "str x30, [sp, #-16]!",
         "blr x0",
         "ldr x30, [sp], #16",
@@ -2543,7 +2543,7 @@
         "ldr d3, [x20, #1056]",
         "fmov d0, d3",
         "fmov d1, d2",
-        "ldr x0, [x28, #3072]",
+        "ldr x0, [x28, #3080]",
         "str x30, [sp, #-16]!",
         "blr x0",
         "ldr x30, [sp], #16",
@@ -2561,7 +2561,7 @@
         "add x20, x28, x20, lsl #4",
         "ldr d2, [x20, #1056]",
         "fmov d0, d2",
-        "ldr x0, [x28, #3040]",
+        "ldr x0, [x28, #3048]",
         "str x30, [sp, #-16]!",
         "blr x0",
         "ldr x30, [sp], #16",
@@ -2580,7 +2580,7 @@
         "add x20, x28, x20, lsl #4",
         "ldr d2, [x20, #1056]",
         "fmov d0, d2",
-        "ldr x0, [x28, #3048]",
+        "ldr x0, [x28, #3056]",
         "str x30, [sp, #-16]!",
         "blr x0",
         "ldr x30, [sp], #16",
diff --git a/unittests/InstructionCountCI/x87_f64_32Bit.json b/unittests/InstructionCountCI/x87_f64_32Bit.json
index f74e3531f..d05ae2ad7 100644
--- a/unittests/InstructionCountCI/x87_f64_32Bit.json
+++ b/unittests/InstructionCountCI/x87_f64_32Bit.json
@@ -15,7 +15,7 @@
       "SVE256",
       "CSSC"
     ],
-    "BinaryCacheVersion": 25
+    "BinaryCacheVersion": 26
   },
   "Instructions": {
     "fstp dword [ebx*4+0x204a20]": {