From 60da70b07e3f26f50bf09acd057ed76200978ccf Mon Sep 17 00:00:00 2001 From: Ryan Houdek Date: Sat, 10 Jul 2021 23:15:49 -0700 Subject: [PATCH] ARMv8.0: Adds some NOPs around CASPair loadstore exclusive pair The unaligned signal handler will backpatch these with DMBs. Previously generating corrupted code. This will fix that corruption but not the atomicity problem --- .../FEXCore/Source/Interface/Core/JIT/Arm64/AtomicOps.cpp | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/External/FEXCore/Source/Interface/Core/JIT/Arm64/AtomicOps.cpp b/External/FEXCore/Source/Interface/Core/JIT/Arm64/AtomicOps.cpp index 4dfae45b6..d12fb598c 100644 --- a/External/FEXCore/Source/Interface/Core/JIT/Arm64/AtomicOps.cpp +++ b/External/FEXCore/Source/Interface/Core/JIT/Arm64/AtomicOps.cpp @@ -44,11 +44,15 @@ DEF_OP(CASPair) { aarch64::Label LoopNotExpected; aarch64::Label LoopExpected; bind(&LoopTop); + nop(); ldaxp(TMP2.W(), TMP3.W(), MemOperand(MemSrc)); + nop(); cmp(TMP2.W(), Expected.first.W()); ccmp(TMP3.W(), Expected.second.W(), NoFlag, Condition::eq); b(&LoopNotExpected, Condition::ne); + nop(); stlxp(TMP2.W(), Desired.first.W(), Desired.second.W(), MemOperand(MemSrc)); + nop(); cbnz(TMP2.W(), &LoopTop); mov(Dst.first.W(), Expected.first.W()); mov(Dst.second.W(), Expected.second.W()); @@ -69,11 +73,15 @@ DEF_OP(CASPair) { aarch64::Label LoopNotExpected; aarch64::Label LoopExpected; bind(&LoopTop); + nop(); ldaxp(TMP2.X(), TMP3.X(), MemOperand(MemSrc)); + nop(); cmp(TMP2.X(), Expected.first.X()); ccmp(TMP3.X(), Expected.second.X(), NoFlag, Condition::eq); b(&LoopNotExpected, Condition::ne); + nop(); stlxp(TMP2.X(), Desired.first.X(), Desired.second.X(), MemOperand(MemSrc)); + nop(); cbnz(TMP2.X(), &LoopTop); mov(Dst.first.X(), Expected.first.X()); mov(Dst.second.X(), Expected.second.X());