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ARM64EC: Emulate unaligned atomic access in non-JIT EC code
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@@ -349,15 +349,11 @@ struct alignas(16) KiUserExceptionDispatcherStackLayout {
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uint64_t Redzone[2];
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};
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static bool HandleUnalignedAccess(ARM64_NT_CONTEXT& Context) {
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static bool HandleUnalignedAccess(ARM64_NT_CONTEXT& Context, bool IsJIT) {
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auto Thread = GetCPUArea().ThreadState();
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if (!CTX->IsAddressInCodeBuffer(Thread, Context.Pc)) {
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return false;
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}
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FEXCORE_PROFILE_INSTANT_INCREMENT(Thread, AccumulatedSIGBUSCount, 1);
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const auto Result =
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FEXCore::ArchHelpers::Arm64::HandleUnalignedAccess(Thread, HandlerConfig->GetUnalignedHandlerType(), Context.Pc, &Context.X0);
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FEXCore::ArchHelpers::Arm64::HandleUnalignedAccess(Thread, HandlerConfig->GetUnalignedHandlerType(), Context.Pc, &Context.X0, IsJIT);
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Context.Pc += Result.value_or(0);
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return Result.has_value();
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}
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@@ -761,16 +757,17 @@ bool ResetToConsistentStateImpl(EXCEPTION_RECORD* Exception, CONTEXT* GuestConte
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}
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}
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if (!CTX->IsAddressInCodeBuffer(Thread, NativeContext->Pc) && !IsDispatcherAddress(NativeContext->Pc)) {
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LogMan::Msg::DFmt("Passing through exception");
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return false;
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}
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if (Exception->ExceptionCode == EXCEPTION_DATATYPE_MISALIGNMENT && Exception::HandleUnalignedAccess(*NativeContext)) {
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bool IsJIT = CTX->IsAddressInCodeBuffer(Thread, NativeContext->Pc);
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if (Exception->ExceptionCode == EXCEPTION_DATATYPE_MISALIGNMENT && Exception::HandleUnalignedAccess(*NativeContext, IsJIT)) {
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LogMan::Msg::DFmt("Handled unaligned atomic: new pc: {:X}", NativeContext->Pc);
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return true;
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}
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if (!IsJIT && !IsDispatcherAddress(NativeContext->Pc)) {
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LogMan::Msg::DFmt("Passing through exception");
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return false;
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}
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// The JIT (in CompileBlock) emits code to check the suspend doorbell at the start of every block, and run the following instruction if it is set:
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static constexpr uint32_t SuspendTrapMagic {0xD4395FC0}; // brk #0xCAFE
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if (Exception->ExceptionCode == EXCEPTION_ILLEGAL_INSTRUCTION && *reinterpret_cast<uint32_t*>(NativeContext->Pc) == SuspendTrapMagic) {
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