From 5664195e49701b71eda1e729d3a5c8b57a2cd8cc Mon Sep 17 00:00:00 2001 From: Ryan Houdek Date: Thu, 21 Sep 2023 02:07:27 -0700 Subject: [PATCH 1/2] OpcodeDispatcher: Optimize reconstructing FSW Minor optimization using Bfi to insert C0, C1, C2, & C3 --- .../Source/Interface/Core/OpcodeDispatcher/X87.cpp | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher/X87.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher/X87.cpp index cae62d90b..9f70408ff 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher/X87.cpp +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher/X87.cpp @@ -91,20 +91,19 @@ void OpDispatchBuilder::SetX87Top(OrderedNode *Value) { OrderedNode *OpDispatchBuilder::ReconstructFSW() { // We must construct the FSW from our various bits - // TODO: These should use BFI OrderedNode *FSW = _Constant(0); auto Top = GetX87Top(); - FSW = _Or(OpSize::i64Bit, FSW, _Lshl(OpSize::i32Bit, Top, _Constant(11))); + FSW = _Bfi(OpSize::i64Bit, 3, 11, FSW, Top); auto C0 = GetRFLAG(FEXCore::X86State::X87FLAG_C0_LOC); auto C1 = GetRFLAG(FEXCore::X86State::X87FLAG_C1_LOC); auto C2 = GetRFLAG(FEXCore::X86State::X87FLAG_C2_LOC); auto C3 = GetRFLAG(FEXCore::X86State::X87FLAG_C3_LOC); - FSW = _Or(OpSize::i64Bit, FSW, _Lshl(OpSize::i32Bit, C0, _Constant(8))); - FSW = _Or(OpSize::i64Bit, FSW, _Lshl(OpSize::i32Bit, C1, _Constant(9))); - FSW = _Or(OpSize::i64Bit, FSW, _Lshl(OpSize::i32Bit, C2, _Constant(10))); - FSW = _Or(OpSize::i64Bit, FSW, _Lshl(OpSize::i32Bit, C3, _Constant(14))); + FSW = _Bfi(OpSize::i64Bit, 1, 8, FSW, C0); + FSW = _Bfi(OpSize::i64Bit, 1, 9, FSW, C1); + FSW = _Bfi(OpSize::i64Bit, 1, 10, FSW, C2); + FSW = _Bfi(OpSize::i64Bit, 1, 14, FSW, C3); return FSW; } From 758820ca867d0b612aaec759960a6dc14f617b1a Mon Sep 17 00:00:00 2001 From: Ryan Houdek Date: Thu, 21 Sep 2023 02:08:36 -0700 Subject: [PATCH 2/2] InstCountCI: Update for optimized FSW reconstruction --- .../InstructionCountCI/SecondaryGroup.json | 36 ++++------ unittests/InstructionCountCI/x87.json | 72 ++++++++----------- 2 files changed, 41 insertions(+), 67 deletions(-) diff --git a/unittests/InstructionCountCI/SecondaryGroup.json b/unittests/InstructionCountCI/SecondaryGroup.json index b2e8d9a75..86b55952a 100644 --- a/unittests/InstructionCountCI/SecondaryGroup.json +++ b/unittests/InstructionCountCI/SecondaryGroup.json @@ -943,7 +943,7 @@ ] }, "fxsave [rax]": { - "ExpectedInstructionCount": 73, + "ExpectedInstructionCount": 68, "Optimal": "No", "Comment": "GROUP15 0x0F 0xAE /0", "ExpectedArm64ASM": [ @@ -951,20 +951,15 @@ "strh w20, [x4]", "mov w20, #0x0", "ldrb w21, [x28, #747]", - "lsl w21, w21, #11", - "orr x20, x20, x21", + "bfi x20, x21, #11, #3", "ldrb w21, [x28, #744]", "ldrb w22, [x28, #745]", "ldrb w23, [x28, #746]", "ldrb w24, [x28, #750]", - "lsl w21, w21, #8", - "orr x20, x20, x21", - "lsl w21, w22, #9", - "orr x20, x20, x21", - "lsl w21, w23, #10", - "orr x20, x20, x21", - "lsl w21, w24, #14", - "orr x20, x20, x21", + "bfi x20, x21, #8, #1", + "bfi x20, x22, #9, #1", + "bfi x20, x23, #10, #1", + "bfi x20, x24, #14, #1", "strh w20, [x4, #2]", "ldrb w20, [x28, #1010]", "strb w20, [x4, #4]", @@ -1208,7 +1203,7 @@ ] }, "xsave [rax]": { - "ExpectedInstructionCount": 86, + "ExpectedInstructionCount": 81, "Optimal": "No", "Comment": "GROUP15 0x0F 0xAE /4", "ExpectedArm64ASM": [ @@ -1216,25 +1211,20 @@ "mov x21, x4", "ubfx x22, x20, #0, #1", "cbnz x22, #+0x8", - "b #+0x98", + "b #+0x84", "ldrh w22, [x28, #1008]", "strh w22, [x21]", "mov w22, #0x0", "ldrb w23, [x28, #747]", - "lsl w23, w23, #11", - "orr x22, x22, x23", + "bfi x22, x23, #11, #3", "ldrb w23, [x28, #744]", "ldrb w24, [x28, #745]", "ldrb w25, [x28, #746]", "ldrb w26, [x28, #750]", - "lsl w23, w23, #8", - "orr x22, x22, x23", - "lsl w23, w24, #9", - "orr x22, x22, x23", - "lsl w23, w25, #10", - "orr x22, x22, x23", - "lsl w23, w26, #14", - "orr x22, x22, x23", + "bfi x22, x23, #8, #1", + "bfi x22, x24, #9, #1", + "bfi x22, x25, #10, #1", + "bfi x22, x26, #14, #1", "strh w22, [x21, #2]", "ldrb w22, [x28, #1010]", "strb w22, [x21, #4]", diff --git a/unittests/InstructionCountCI/x87.json b/unittests/InstructionCountCI/x87.json index 41ef1e8a7..7c64be6c6 100644 --- a/unittests/InstructionCountCI/x87.json +++ b/unittests/InstructionCountCI/x87.json @@ -5548,7 +5548,7 @@ ] }, "fnstenv [rax]": { - "ExpectedInstructionCount": 72, + "ExpectedInstructionCount": 69, "Optimal": "No", "Comment": [ "0xd9 !11b /6" @@ -5558,20 +5558,17 @@ "str w20, [x4]", "mov w20, #0x0", "ldrb w21, [x28, #747]", - "lsl w21, w21, #11", - "orr x21, x20, x21", + "mov x0, x20", + "bfi x0, x21, #11, #3", + "mov x21, x0", "ldrb w22, [x28, #744]", "ldrb w23, [x28, #745]", "ldrb w24, [x28, #746]", "ldrb w25, [x28, #750]", - "lsl w22, w22, #8", - "orr x21, x21, x22", - "lsl w22, w23, #9", - "orr x21, x21, x22", - "lsl w22, w24, #10", - "orr x21, x21, x22", - "lsl w22, w25, #14", - "orr x21, x21, x22", + "bfi x21, x22, #8, #1", + "bfi x21, x23, #9, #1", + "bfi x21, x24, #10, #1", + "bfi x21, x25, #14, #1", "str w21, [x4, #4]", "ldrb w21, [x28, #1010]", "and w22, w21, #0x1", @@ -15909,7 +15906,7 @@ ] }, "fnsave [rax]": { - "ExpectedInstructionCount": 128, + "ExpectedInstructionCount": 125, "Optimal": "No", "Comment": [ "0xdd !11b /6" @@ -15919,20 +15916,17 @@ "ldrh w21, [x28, #1008]", "str w21, [x4]", "mov w21, #0x0", - "lsl w22, w20, #11", - "orr x22, x21, x22", + "mov x0, x21", + "bfi x0, x20, #11, #3", + "mov x22, x0", "ldrb w23, [x28, #744]", "ldrb w24, [x28, #745]", "ldrb w25, [x28, #746]", "ldrb w26, [x28, #750]", - "lsl w23, w23, #8", - "orr x22, x22, x23", - "lsl w23, w24, #9", - "orr x22, x22, x23", - "lsl w23, w25, #10", - "orr x22, x22, x23", - "lsl w23, w26, #14", - "orr x22, x22, x23", + "bfi x22, x23, #8, #1", + "bfi x22, x24, #9, #1", + "bfi x22, x25, #10, #1", + "bfi x22, x26, #14, #1", "str w22, [x4, #4]", "ldrb w22, [x28, #1010]", "and w23, w22, #0x1", @@ -16046,7 +16040,7 @@ ] }, "fnstsw [rax]": { - "ExpectedInstructionCount": 17, + "ExpectedInstructionCount": 12, "Optimal": "No", "Comment": [ "0xdd !11b /7" @@ -16054,20 +16048,15 @@ "ExpectedArm64ASM": [ "mov w20, #0x0", "ldrb w21, [x28, #747]", - "lsl w21, w21, #11", - "orr x20, x20, x21", + "bfi x20, x21, #11, #3", "ldrb w21, [x28, #744]", "ldrb w22, [x28, #745]", "ldrb w23, [x28, #746]", "ldrb w24, [x28, #750]", - "lsl w21, w21, #8", - "orr x20, x20, x21", - "lsl w21, w22, #9", - "orr x20, x20, x21", - "lsl w21, w23, #10", - "orr x20, x20, x21", - "lsl w21, w24, #14", - "orr x20, x20, x21", + "bfi x20, x21, #8, #1", + "bfi x20, x22, #9, #1", + "bfi x20, x23, #10, #1", + "bfi x20, x24, #14, #1", "strh w20, [x4]" ] }, @@ -22743,7 +22732,7 @@ ] }, "fnstsw ax": { - "ExpectedInstructionCount": 17, + "ExpectedInstructionCount": 12, "Optimal": "No", "Comment": [ "0xdf 11b 0xe0 /4" @@ -22751,20 +22740,15 @@ "ExpectedArm64ASM": [ "mov w20, #0x0", "ldrb w21, [x28, #747]", - "lsl w21, w21, #11", - "orr x20, x20, x21", + "bfi x20, x21, #11, #3", "ldrb w21, [x28, #744]", "ldrb w22, [x28, #745]", "ldrb w23, [x28, #746]", "ldrb w24, [x28, #750]", - "lsl w21, w21, #8", - "orr x20, x20, x21", - "lsl w21, w22, #9", - "orr x20, x20, x21", - "lsl w21, w23, #10", - "orr x20, x20, x21", - "lsl w21, w24, #14", - "orr x20, x20, x21", + "bfi x20, x21, #8, #1", + "bfi x20, x22, #9, #1", + "bfi x20, x23, #10, #1", + "bfi x20, x24, #14, #1", "bfxil x4, x20, #0, #16" ] },