steam-frame/FEX-Emu--FEX
1
0 Fork 0
mirror of https://github.com/FEX-Emu/FEX.git synced 2026-10-14 09:00:40 +02:00
Code Issues Packages Projects Releases 67 Wiki Activity

OpcodeDispatcher: Remove final assumptions about small IR operating sizes

Browse Source 
With Or, Orlshl, Bfe, and Bfi there were some assumptions made that i8
and i16 operations made sense. Which required us to disable the IR
validation for these operations when it was just added.

This removes the final assumptions about these IR operations supporting
these small operating sizes allowing us to enable the IR validation.

Also a very minor optimization by moving a couple extracts from source
before trying to BFI from it, making RA more optimal.
This commit is contained in:
Ryan Houdek committed 2023-09-03 02:25:34 -07:00
1 parent 62fcf6cbd0
commit 5cc6eff62c
3 files changed
+17 -29
Download Patch File Download Diff File Expand all files Collapse all files

No files matched your search

FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
+12 -12
View File
@@ -2571,19 +2571,18 @@ void OpDispatchBuilder::RCROp8x1Bit(OpcodeArgs) {
CalculateDeferredFlags();
OrderedNode *Dest = LoadSource(GPRClass, Op, Op->Dest, Op->Flags, -1);
const auto Size = GetSrcSize(Op);
const auto SizeBit = Size * 8;
const auto SizeBit = GetSrcBitSize(Op);
auto CF = GetRFLAG(FEXCore::X86State::RFLAG_CF_LOC);
uint32_t Shift = 1;
// Rotate and insert CF in the upper bit
OrderedNode *Res = _Bfe(OpSize::i32Bit, 7, 1, Dest);
Res = _Bfi(IR::SizeToOpSize(Size), 1, 7, Res, CF);
// Our new CF will be bit (Shift - 1) of the source
auto NewCF = _Bfe(OpSize::i32Bit, 1, Shift - 1, Dest);
// Rotate and insert CF in the upper bit
OrderedNode *Res = _Bfe(OpSize::i32Bit, 7, 1, Dest);
Res = _Bfi(OpSize::i32Bit, 1, 7, Res, CF);
StoreResult(GPRClass, Op, Res, -1);
SetRFLAG<FEXCore::X86State::RFLAG_CF_LOC>(NewCF);
@@ -2761,16 +2760,17 @@ void OpDispatchBuilder::RCLOp1Bit(OpcodeArgs) {
OrderedNode *Dest = LoadSource(GPRClass, Op, Op->Dest, Op->Flags, -1);
const auto Size = GetSrcBitSize(Op);
const auto OpSize = Size == 64 ? OpSize::i64Bit : OpSize::i32Bit;
auto CF = GetRFLAG(FEXCore::X86State::RFLAG_CF_LOC);
uint32_t Shift = 1;
// Rotate left and insert CF in to lowest bit
OrderedNode *Res = _Lshl(Size == 64 ? OpSize::i64Bit : OpSize::i32Bit, Dest, _Constant(Size, 1));
Res = _Or(IR::SizeToOpSize(std::max<uint8_t>(4u, std::max(GetOpSize(Res), GetOpSize(CF)))), Res, CF);
// Our new CF will be the top bit of the source
auto NewCF = _Bfe(OpSizeFromDst(Op), 1, Size - 1, Dest);
auto NewCF = _Bfe(OpSize, 1, Size - 1, Dest);
// Rotate left and insert CF in to lowest bit
OrderedNode *Res = _Lshl(OpSize, Dest, _Constant(Size, 1));
Res = _Or(OpSize, Res, CF);
StoreResult(GPRClass, Op, Res, -1);
@@ -2779,7 +2779,7 @@ void OpDispatchBuilder::RCLOp1Bit(OpcodeArgs) {
if (Shift == 1) {
// OF is the top two MSBs XOR'd together
// Top two MSBs is CF and top bit of result
SetRFLAG<FEXCore::X86State::RFLAG_OF_LOC>(_Xor(IR::SizeToOpSize(std::max<uint8_t>(4u, GetOpSize(Res))), _Bfe(IR::SizeToOpSize(std::max<uint8_t>(4u, GetOpSize(Res))), 1, Size - 1, Res), NewCF));
SetRFLAG<FEXCore::X86State::RFLAG_OF_LOC>(_Xor(OpSize::i32Bit, _Bfe(OpSize, 1, Size - 1, Res), NewCF));
}
}