From 56841f0e50b0dfb38bf0b5c53274afda63241f5d Mon Sep 17 00:00:00 2001 From: Alyssa Rosenzweig Date: Mon, 13 Nov 2023 22:16:46 -0400 Subject: [PATCH] OpcodeDispatcher: avoid moves with 64bit imul Signed-off-by: Alyssa Rosenzweig --- FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp index d504878a9..f42d0ca59 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp @@ -3057,13 +3057,16 @@ void OpDispatchBuilder::IMUL1SrcOp(OpcodeArgs) { Src2 = _Sbfe(OpSize::i64Bit, Size * 8, 0, Src2); } - auto Dest = _Mul(OpSize::i64Bit, Src1, Src2); + OrderedNode *Dest{}; OrderedNode *ResultHigh{}; if (Size < 8) { + Dest = _Mul(OpSize::i64Bit, Src1, Src2); ResultHigh = _Sbfe(OpSize::i64Bit, Size * 8, Size * 8, Dest); } else { + // Flipped order to save a move ResultHigh = _MulH(OpSize::i64Bit, Src1, Src2); + Dest = _Mul(OpSize::i64Bit, Src1, Src2); } StoreResult(GPRClass, Op, Dest, -1); GenerateFlags_MUL(Op, Dest, ResultHigh); @@ -3103,7 +3106,8 @@ void OpDispatchBuilder::IMULOp(OpcodeArgs) { Src2 = _Sbfe(OpSize::i64Bit, Size * 8, 0, Src2); } - OrderedNode *Result = _Mul(OpSize::i64Bit, Src1, Src2); + // 64-bit special cased to save a move + OrderedNode *Result = Size < 8 ? _Mul(OpSize::i64Bit, Src1, Src2) : nullptr; OrderedNode *ResultHigh{}; if (Size == 1) { // Result is stored in AX @@ -3137,6 +3141,7 @@ void OpDispatchBuilder::IMULOp(OpcodeArgs) { // 64bits stored in RAX // 64bits stored in RDX ResultHigh = _MulH(OpSize::i64Bit, Src1, Src2); + Result = _Mul(OpSize::i64Bit, Src1, Src2); StoreGPRRegister(X86State::REG_RAX, Result); StoreGPRRegister(X86State::REG_RDX, ResultHigh); }