diff --git a/FEXCore/Source/Interface/IR/IR.json b/FEXCore/Source/Interface/IR/IR.json
index 3426cd361..5c9583b48 100644
--- a/FEXCore/Source/Interface/IR/IR.json
+++ b/FEXCore/Source/Interface/IR/IR.json
@@ -500,7 +500,7 @@
         ]
       },
 
-      "SSA = FillRegister SSA:$OriginalValue, u32:$Slot, RegisterClass:$Class": {
+      "SSA = FillRegister OpSize:#Size, OpSize:#ElementSize, SSA:$OriginalValue, u32:$Slot, RegisterClass:$Class": {
         "Desc": ["Fills a register from a spill slot",
                  "Spill slots are register allocated and has live ranges calculated to handle slot calculation",
                  "```diff\n- !Don't use this op. It is for RA to handle spilling and filling!\n```",
@@ -508,6 +508,8 @@
                  "The OriginalValue SSA arg points at the original SSA value spilled, and only exists for",
                  "RA validation purposes"
                 ],
+        "DestSize": "Size",
+        "ElementSize": "ElementSize",
         "EmitValidation": [
           "WalkFindRegClass($OriginalValue) == $Class"
         ]
diff --git a/FEXCore/Source/Interface/IR/Passes/RegisterAllocationPass.cpp b/FEXCore/Source/Interface/IR/Passes/RegisterAllocationPass.cpp
index b2547e20d..c09e3b6c1 100644
--- a/FEXCore/Source/Interface/IR/Passes/RegisterAllocationPass.cpp
+++ b/FEXCore/Source/Interface/IR/Passes/RegisterAllocationPass.cpp
@@ -163,11 +163,7 @@ private:
     LOGMAN_THROW_A_FMT(SlotPlusOne >= 1, "Old must have been spilled");
 
     RegisterClassType RegClass = GetRegClassFromNode(IR, IROp);
-
-    auto Fill = IREmit->_FillRegister(Old, SlotPlusOne - 1, RegClass);
-    Fill.first->Header.Size = IROp->Size;
-    Fill.first->Header.ElementSize = IROp->ElementSize;
-    return Fill;
+    return IREmit->_FillRegister(IROp->Size, IROp->ElementSize, Old, SlotPlusOne - 1, RegClass);
   };
 
   // IP of next-use of each Old source. IPs are measured from the end of the