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Merge pull request #3132 from alyssarosenzweig/opt/orlshl

Browse Source 
Optimize reconstructing x87, harder
This commit is contained in:
Ryan Houdek authored and GitHub committed 2023-09-21 15:02:37 -07:00
2 parents 7d99eb05c6 75ffbc16f2
commit 5444810d64
3 files changed
+118 -164
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FEXCore/Source/Interface/Core/OpcodeDispatcher/X87.cpp
+16 -12
View File
@@ -60,14 +60,18 @@ OrderedNode *OpDispatchBuilder::GetX87Tag(OrderedNode *Value) {
void OpDispatchBuilder::SetX87FTW(OrderedNode *FTW) {
OrderedNode *X87Empty = _Constant(static_cast<uint8_t>(FPState::X87Tag::Empty));
OrderedNode *NewAbridgedFTW = _Constant(0);
OrderedNode *NewAbridgedFTW;
for (int i = 0; i < 8; i++) {
OrderedNode *RegTag = _And(OpSize::i32Bit, _Lshr(OpSize::i32Bit, FTW, _Constant(i * 2)), _Constant(0b11));
OrderedNode *RegValid = _Select(FEXCore::IR::COND_EQ,
OrderedNode *RegTag = _Bfe(OpSize::i32Bit, 2, i * 2, FTW);
OrderedNode *RegValid = _Select(FEXCore::IR::COND_NEQ,
RegTag, X87Empty,
_Constant(0), _Constant(1));
NewAbridgedFTW = _Or(OpSize::i32Bit, NewAbridgedFTW, _Lshl(OpSize::i32Bit, RegValid, _Constant(i)));
_Constant(1), _Constant(0));
if (i)
NewAbridgedFTW = _Orlshl(OpSize::i32Bit, NewAbridgedFTW, RegValid, i);
else
NewAbridgedFTW = RegValid;
}
_StoreContext(1, GPRClass, NewAbridgedFTW, offsetof(FEXCore::Core::CPUState, AbridgedFTW));
@@ -79,7 +83,7 @@ OrderedNode *OpDispatchBuilder::GetX87FTW() {
for (int i = 0; i < 8; i++) {
const auto RegTag = GetX87Tag(_Constant(i), AbridgedFTW);
FTW = _Or(OpSize::i32Bit, FTW, _Lshl(OpSize::i32Bit, RegTag, _Constant(i * 2)));
FTW = _Orlshl(OpSize::i32Bit, FTW, RegTag, i * 2);
}
return FTW;
@@ -100,10 +104,10 @@ OrderedNode *OpDispatchBuilder::ReconstructFSW() {
auto C2 = GetRFLAG(FEXCore::X86State::X87FLAG_C2_LOC);
auto C3 = GetRFLAG(FEXCore::X86State::X87FLAG_C3_LOC);
FSW = _Bfi(OpSize::i64Bit, 1, 8, FSW, C0);
FSW = _Bfi(OpSize::i64Bit, 1, 9, FSW, C1);
FSW = _Bfi(OpSize::i64Bit, 1, 10, FSW, C2);
FSW = _Bfi(OpSize::i64Bit, 1, 14, FSW, C3);
FSW = _Orlshl(OpSize::i64Bit, FSW, C0, 8);
FSW = _Orlshl(OpSize::i64Bit, FSW, C1, 9);
FSW = _Orlshl(OpSize::i64Bit, FSW, C2, 10);
FSW = _Orlshl(OpSize::i64Bit, FSW, C3, 14);
return FSW;
}
@@ -1274,9 +1278,9 @@ void OpDispatchBuilder::X87FXAM(OpcodeArgs) {
auto OneConst = _Constant(1);
// In the case of top being invalid then C3:C2:C0 is 0b101
auto C3 = _Select(FEXCore::IR::COND_EQ,
auto C3 = _Select(FEXCore::IR::COND_NEQ,
TopValid, OneConst,
ZeroConst, OneConst);
OneConst, ZeroConst);
auto C2 = TopValid;
auto C0 = C3; // Mirror C3 until something other than zero is supported
unittests/InstructionCountCI/SecondaryGroup.json
+8 -8
View File
@@ -956,10 +956,10 @@
"ldrb w22, [x28, #745]",
"ldrb w23, [x28, #746]",
"ldrb w24, [x28, #750]",
"bfi x20, x21, #8, #1",
"bfi x20, x22, #9, #1",
"bfi x20, x23, #10, #1",
"bfi x20, x24, #14, #1",
"orr x20, x20, x21, lsl #8",
"orr x20, x20, x22, lsl #9",
"orr x20, x20, x23, lsl #10",
"orr x20, x20, x24, lsl #14",
"strh w20, [x4, #2]",
"ldrb w20, [x28, #1010]",
"strb w20, [x4, #4]",
@@ -1221,10 +1221,10 @@
"ldrb w24, [x28, #745]",
"ldrb w25, [x28, #746]",
"ldrb w26, [x28, #750]",
"bfi x22, x23, #8, #1",
"bfi x22, x24, #9, #1",
"bfi x22, x25, #10, #1",
"bfi x22, x26, #14, #1",
"orr x22, x22, x23, lsl #8",
"orr x22, x22, x24, lsl #9",
"orr x22, x22, x25, lsl #10",
"orr x22, x22, x26, lsl #14",
"strh w22, [x21, #2]",
"ldrb w22, [x28, #1010]",
"strb w22, [x21, #4]",
unittests/InstructionCountCI/x87.json
+94 -144
View File
@@ -5465,7 +5465,7 @@
]
},
"fldenv [rax]": {
"ExpectedInstructionCount": 63,
"ExpectedInstructionCount": 46,
"Optimal": "No",
"Comment": [
"0xd9 !11b /4"
@@ -5485,54 +5485,37 @@
"strb w23, [x28, #746]",
"strb w20, [x28, #750]",
"ldr w20, [x4, #8]",
"mov w21, #0x0",
"and w22, w20, #0x3",
"mov w23, #0x1",
"ubfx w21, w20, #0, #2",
"cmp x21, #0x3 (3)",
"cset x21, ne",
"ubfx w22, w20, #2, #2",
"cmp x22, #0x3 (3)",
"csel x22, x21, x23, eq",
"orr w22, w21, w22",
"lsr w24, w20, #2",
"and w24, w24, #0x3",
"cmp x24, #0x3 (3)",
"csel x24, x21, x23, eq",
"lsl w24, w24, #1",
"orr w22, w22, w24",
"lsr w24, w20, #4",
"and w24, w24, #0x3",
"cmp x24, #0x3 (3)",
"csel x24, x21, x23, eq",
"lsl w24, w24, #2",
"orr w22, w22, w24",
"lsr w24, w20, #6",
"and w24, w24, #0x3",
"cmp x24, #0x3 (3)",
"csel x24, x21, x23, eq",
"lsl w24, w24, #3",
"orr w22, w22, w24",
"lsr w24, w20, #8",
"and w24, w24, #0x3",
"cmp x24, #0x3 (3)",
"csel x24, x21, x23, eq",
"lsl w24, w24, #4",
"orr w22, w22, w24",
"lsr w24, w20, #10",
"and w24, w24, #0x3",
"cmp x24, #0x3 (3)",
"csel x24, x21, x23, eq",
"lsl w24, w24, #5",
"orr w22, w22, w24",
"lsr w24, w20, #12",
"and w24, w24, #0x3",
"cmp x24, #0x3 (3)",
"csel x24, x21, x23, eq",
"lsl w24, w24, #6",
"orr w22, w22, w24",
"lsr w20, w20, #14",
"and w20, w20, #0x3",
"cset x22, ne",
"orr w21, w21, w22, lsl #1",
"ubfx w22, w20, #4, #2",
"cmp x22, #0x3 (3)",
"cset x22, ne",
"orr w21, w21, w22, lsl #2",
"ubfx w22, w20, #6, #2",
"cmp x22, #0x3 (3)",
"cset x22, ne",
"orr w21, w21, w22, lsl #3",
"ubfx w22, w20, #8, #2",
"cmp x22, #0x3 (3)",
"cset x22, ne",
"orr w21, w21, w22, lsl #4",
"ubfx w22, w20, #10, #2",
"cmp x22, #0x3 (3)",
"cset x22, ne",
"orr w21, w21, w22, lsl #5",
"ubfx w22, w20, #12, #2",
"cmp x22, #0x3 (3)",
"cset x22, ne",
"orr w21, w21, w22, lsl #6",
"ubfx w20, w20, #14, #2",
"cmp x20, #0x3 (3)",
"csel x20, x21, x23, eq",
"lsl w20, w20, #7",
"orr w20, w22, w20",
"cset x20, ne",
"orr w20, w21, w20, lsl #7",
"strb w20, [x28, #1010]"
]
},
@@ -5548,7 +5531,7 @@
]
},
"fnstenv [rax]": {
"ExpectedInstructionCount": 69,
"ExpectedInstructionCount": 62,
"Optimal": "No",
"Comment": [
"0xd9 !11b /6"
@@ -5565,10 +5548,10 @@
"ldrb w23, [x28, #745]",
"ldrb w24, [x28, #746]",
"ldrb w25, [x28, #750]",
"bfi x21, x22, #8, #1",
"bfi x21, x23, #9, #1",
"bfi x21, x24, #10, #1",
"bfi x21, x25, #14, #1",
"orr x21, x21, x22, lsl #8",
"orr x21, x21, x23, lsl #9",
"orr x21, x21, x24, lsl #10",
"orr x21, x21, x25, lsl #14",
"str w21, [x4, #4]",
"ldrb w21, [x28, #1010]",
"and w22, w21, #0x1",
@@ -5580,44 +5563,37 @@
"and w24, w24, #0x1",
"cmp x24, #0x0 (0)",
"csel x24, x23, x20, eq",
"lsl w24, w24, #2",
"orr w22, w22, w24",
"orr w22, w22, w24, lsl #2",
"lsr w24, w21, #2",
"and w24, w24, #0x1",
"cmp x24, #0x0 (0)",
"csel x24, x23, x20, eq",
"lsl w24, w24, #4",
"orr w22, w22, w24",
"orr w22, w22, w24, lsl #4",
"lsr w24, w21, #3",
"and w24, w24, #0x1",
"cmp x24, #0x0 (0)",
"csel x24, x23, x20, eq",
"lsl w24, w24, #6",
"orr w22, w22, w24",
"orr w22, w22, w24, lsl #6",
"lsr w24, w21, #4",
"and w24, w24, #0x1",
"cmp x24, #0x0 (0)",
"csel x24, x23, x20, eq",
"lsl w24, w24, #8",
"orr w22, w22, w24",
"orr w22, w22, w24, lsl #8",
"lsr w24, w21, #5",
"and w24, w24, #0x1",
"cmp x24, #0x0 (0)",
"csel x24, x23, x20, eq",
"lsl w24, w24, #10",
"orr w22, w22, w24",
"orr w22, w22, w24, lsl #10",
"lsr w24, w21, #6",
"and w24, w24, #0x1",
"cmp x24, #0x0 (0)",
"csel x24, x23, x20, eq",
"lsl w24, w24, #12",
"orr w22, w22, w24",
"orr w22, w22, w24, lsl #12",
"lsr w21, w21, #7",
"and w21, w21, #0x1",
"cmp x21, #0x0 (0)",
"csel x21, x23, x20, eq",
"lsl w21, w21, #14",
"orr w21, w22, w21",
"orr w21, w22, w21, lsl #14",
"str w21, [x4, #8]",
"str w20, [x4, #12]",
"str w20, [x4, #16]",
@@ -6104,7 +6080,7 @@
]
},
"fxam": {
"ExpectedInstructionCount": 16,
"ExpectedInstructionCount": 14,
"Optimal": "No",
"Comment": [
"0xd9 11b 0xe5 /4"
@@ -6118,11 +6094,9 @@
"strb w21, [x28, #745]",
"ldrb w21, [x28, #1010]",
"lsr w20, w21, w20",
"mov w21, #0x1",
"and w20, w20, #0x1",
"mov w22, #0x0",
"cmp x20, #0x1 (1)",
"csel x21, x22, x21, eq",
"cset x21, ne",
"strb w21, [x28, #744]",
"strb w20, [x28, #746]",
"strb w21, [x28, #750]"
@@ -15775,7 +15749,7 @@
]
},
"frstor [rax]": {
"ExpectedInstructionCount": 122,
"ExpectedInstructionCount": 105,
"Optimal": "No",
"Comment": [
"0xdd !11b /4"
@@ -15795,54 +15769,37 @@
"strb w24, [x28, #746]",
"strb w20, [x28, #750]",
"ldr w20, [x4, #8]",
"mov w22, #0x0",
"and w23, w20, #0x3",
"mov w24, #0x1",
"ubfx w22, w20, #0, #2",
"cmp x22, #0x3 (3)",
"cset x22, ne",
"ubfx w23, w20, #2, #2",
"cmp x23, #0x3 (3)",
"csel x23, x22, x24, eq",
"orr w23, w22, w23",
"lsr w25, w20, #2",
"and w25, w25, #0x3",
"cmp x25, #0x3 (3)",
"csel x25, x22, x24, eq",
"lsl w25, w25, #1",
"orr w23, w23, w25",
"lsr w25, w20, #4",
"and w25, w25, #0x3",
"cmp x25, #0x3 (3)",
"csel x25, x22, x24, eq",
"lsl w25, w25, #2",
"orr w23, w23, w25",
"lsr w25, w20, #6",
"and w25, w25, #0x3",
"cmp x25, #0x3 (3)",
"csel x25, x22, x24, eq",
"lsl w25, w25, #3",
"orr w23, w23, w25",
"lsr w25, w20, #8",
"and w25, w25, #0x3",
"cmp x25, #0x3 (3)",
"csel x25, x22, x24, eq",
"lsl w25, w25, #4",
"orr w23, w23, w25",
"lsr w25, w20, #10",
"and w25, w25, #0x3",
"cmp x25, #0x3 (3)",
"csel x25, x22, x24, eq",
"lsl w25, w25, #5",
"orr w23, w23, w25",
"lsr w25, w20, #12",
"and w25, w25, #0x3",
"cmp x25, #0x3 (3)",
"csel x25, x22, x24, eq",
"lsl w25, w25, #6",
"orr w23, w23, w25",
"lsr w20, w20, #14",
"and w20, w20, #0x3",
"cset x23, ne",
"orr w22, w22, w23, lsl #1",
"ubfx w23, w20, #4, #2",
"cmp x23, #0x3 (3)",
"cset x23, ne",
"orr w22, w22, w23, lsl #2",
"ubfx w23, w20, #6, #2",
"cmp x23, #0x3 (3)",
"cset x23, ne",
"orr w22, w22, w23, lsl #3",
"ubfx w23, w20, #8, #2",
"cmp x23, #0x3 (3)",
"cset x23, ne",
"orr w22, w22, w23, lsl #4",
"ubfx w23, w20, #10, #2",
"cmp x23, #0x3 (3)",
"cset x23, ne",
"orr w22, w22, w23, lsl #5",
"ubfx w23, w20, #12, #2",
"cmp x23, #0x3 (3)",
"cset x23, ne",
"orr w22, w22, w23, lsl #6",
"ubfx w20, w20, #14, #2",
"cmp x20, #0x3 (3)",
"csel x20, x22, x24, eq",
"lsl w20, w20, #7",
"orr w20, w23, w20",
"cset x20, ne",
"orr w20, w22, w20, lsl #7",
"strb w20, [x28, #1010]",
"add x20, x4, #0x1c (28)",
"mov x22, #0xffffffffffffffff",
@@ -15906,7 +15863,7 @@
]
},
"fnsave [rax]": {
"ExpectedInstructionCount": 125,
"ExpectedInstructionCount": 118,
"Optimal": "No",
"Comment": [
"0xdd !11b /6"
@@ -15923,10 +15880,10 @@
"ldrb w24, [x28, #745]",
"ldrb w25, [x28, #746]",
"ldrb w26, [x28, #750]",
"bfi x22, x23, #8, #1",
"bfi x22, x24, #9, #1",
"bfi x22, x25, #10, #1",
"bfi x22, x26, #14, #1",
"orr x22, x22, x23, lsl #8",
"orr x22, x22, x24, lsl #9",
"orr x22, x22, x25, lsl #10",
"orr x22, x22, x26, lsl #14",
"str w22, [x4, #4]",
"ldrb w22, [x28, #1010]",
"and w23, w22, #0x1",
@@ -15938,44 +15895,37 @@
"and w25, w25, #0x1",
"cmp x25, #0x0 (0)",
"csel x25, x24, x21, eq",
"lsl w25, w25, #2",
"orr w23, w23, w25",
"orr w23, w23, w25, lsl #2",
"lsr w25, w22, #2",
"and w25, w25, #0x1",
"cmp x25, #0x0 (0)",
"csel x25, x24, x21, eq",
"lsl w25, w25, #4",
"orr w23, w23, w25",
"orr w23, w23, w25, lsl #4",
"lsr w25, w22, #3",
"and w25, w25, #0x1",
"cmp x25, #0x0 (0)",
"csel x25, x24, x21, eq",
"lsl w25, w25, #6",
"orr w23, w23, w25",
"orr w23, w23, w25, lsl #6",
"lsr w25, w22, #4",
"and w25, w25, #0x1",
"cmp x25, #0x0 (0)",
"csel x25, x24, x21, eq",
"lsl w25, w25, #8",
"orr w23, w23, w25",
"orr w23, w23, w25, lsl #8",
"lsr w25, w22, #5",
"and w25, w25, #0x1",
"cmp x25, #0x0 (0)",
"csel x25, x24, x21, eq",
"lsl w25, w25, #10",
"orr w23, w23, w25",
"orr w23, w23, w25, lsl #10",
"lsr w25, w22, #6",
"and w25, w25, #0x1",
"cmp x25, #0x0 (0)",
"csel x25, x24, x21, eq",
"lsl w25, w25, #12",
"orr w23, w23, w25",
"orr w23, w23, w25, lsl #12",
"lsr w22, w22, #7",
"and w22, w22, #0x1",
"cmp x22, #0x0 (0)",
"csel x22, x24, x21, eq",
"lsl w22, w22, #14",
"orr w22, w23, w22",
"orr w22, w23, w22, lsl #14",
"str w22, [x4, #8]",
"str w21, [x4, #12]",
"str w21, [x4, #16]",
@@ -16053,10 +16003,10 @@
"ldrb w22, [x28, #745]",
"ldrb w23, [x28, #746]",
"ldrb w24, [x28, #750]",
"bfi x20, x21, #8, #1",
"bfi x20, x22, #9, #1",
"bfi x20, x23, #10, #1",
"bfi x20, x24, #14, #1",
"orr x20, x20, x21, lsl #8",
"orr x20, x20, x22, lsl #9",
"orr x20, x20, x23, lsl #10",
"orr x20, x20, x24, lsl #14",
"strh w20, [x4]"
]
},
@@ -22745,10 +22695,10 @@
"ldrb w22, [x28, #745]",
"ldrb w23, [x28, #746]",
"ldrb w24, [x28, #750]",
"bfi x20, x21, #8, #1",
"bfi x20, x22, #9, #1",
"bfi x20, x23, #10, #1",
"bfi x20, x24, #14, #1",
"orr x20, x20, x21, lsl #8",
"orr x20, x20, x22, lsl #9",
"orr x20, x20, x23, lsl #10",
"orr x20, x20, x24, lsl #14",
"bfxil x4, x20, #0, #16"
]
},