From 4be649c44e50dca3ff5b950cbaa57aacb91103d3 Mon Sep 17 00:00:00 2001 From: Ryan Houdek Date: Tue, 10 Oct 2023 12:04:41 -0700 Subject: [PATCH] OpcodeDispatcher: Optimizes < 32-bit register push We don't need zero in the upper bits for a push. Makes a couple variants optimal. Adds missing tests to the 32-bit file, since only 32-bit can push a 32-bit register. --- FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp index 4b5992474..96c67ce4a 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp @@ -512,7 +512,7 @@ void OpDispatchBuilder::PUSHOp(OpcodeArgs) { void OpDispatchBuilder::PUSHREGOp(OpcodeArgs) { const uint8_t Size = GetSrcSize(Op); - OrderedNode *Src = LoadSource(GPRClass, Op, Op->Dest, Op->Flags, -1); + OrderedNode *Src = LoadSource(GPRClass, Op, Op->Dest , Op->Flags, -1, true, false, MemoryAccessType::ACCESS_DEFAULT, true); auto OldSP = LoadGPRRegister(X86State::REG_RSP); const uint8_t GPRSize = CTX->GetGPRSize();