From 4731a5ace4b7c5bb00a676f8f14ac3009ca8f923 Mon Sep 17 00:00:00 2001 From: Ryan Houdek Date: Mon, 14 Sep 2026 14:40:23 -0700 Subject: [PATCH] OpcodeDispatcher: Removes DST/SRC_RAX from SALC --- FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp | 3 ++- FEXCore/Source/Interface/Core/X86Tables/BaseTables.cpp | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp index 1caf079f2..e35fb244f 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp @@ -298,7 +298,8 @@ void OpDispatchBuilder::SALCOp(OpcodeArgs) { auto Result = NZCVSelect(OpSize::i32Bit, CondClass::UGE /* CF = 1 */, _InlineConstant(0xffffffff), _InlineConstant(0)); - StoreResultGPR(Op, Result); + // This inserts in to the low 8-bits. + StoreGPRRegister(X86State::REG_RAX, Result, OpSizeFromDst(Op)); } void OpDispatchBuilder::PUSHOp(OpcodeArgs) { diff --git a/FEXCore/Source/Interface/Core/X86Tables/BaseTables.cpp b/FEXCore/Source/Interface/Core/X86Tables/BaseTables.cpp index 8401547d4..e040edcd0 100644 --- a/FEXCore/Source/Interface/Core/X86Tables/BaseTables.cpp +++ b/FEXCore/Source/Interface/Core/X86Tables/BaseTables.cpp @@ -169,7 +169,7 @@ constexpr std::array Primary_ArchSelect_LUT = {{ }, // ENTRY_D6 { - {"SALC", TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_SF_DST_RAX | FLAGS_SF_SRC_RAX, 0, { .OpDispatch = &IR::OpDispatchBuilder::SALCOp } }, + {"SALC", TYPE_INST, GenFlagsSameSize(SIZE_8BIT), 0, { .OpDispatch = &IR::OpDispatchBuilder::SALCOp } }, {"", TYPE_INVALID, FLAGS_NONE, 0, { .OpDispatch = nullptr } }, }, // ENTRY_EA