diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp index 68b00504c..590b19de1 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp @@ -394,7 +394,7 @@ void OpDispatchBuilder::SecondaryALUOp(OpcodeArgs) { break; } case FEXCore::IR::IROps::OP_XOR: { - Dest = _AtomicFetchXor(Size, Src, DestMem); + Dest = _AtomicFetchXor(IR::SizeToOpSize(Size), Src, DestMem); Result = _Xor(Dest, Src); break; } @@ -3169,7 +3169,7 @@ void OpDispatchBuilder::BTCOp(OpcodeArgs) { if (DestIsLockedMem(Op)) { HandledLock = true; - Result = _AtomicFetchXor(1, BitMask, MemoryLocation); + Result = _AtomicFetchXor(OpSize::i8Bit, BitMask, MemoryLocation); // Now shift in to the correct bit location Result = _Lshr(Result, BitSelect); } else { @@ -4336,7 +4336,7 @@ void OpDispatchBuilder::NEGOp(OpcodeArgs) { OrderedNode *DestMem = LoadSource(GPRClass, Op, Op->Dest, Op->Flags, -1, false); DestMem = AppendSegmentOffset(DestMem, Op->Flags); - Dest = _AtomicFetchNeg(OpSizeFromSrc(Op), DestMem); + Dest = _AtomicFetchNeg(IR::SizeToOpSize(Size), DestMem); Result = _Neg(Size == 8 ? OpSize::i64Bit : OpSize::i32Bit, Dest); } else { diff --git a/FEXCore/include/FEXCore/IR/IREmitter.h b/FEXCore/include/FEXCore/IR/IREmitter.h index 4d48ace9d..0da82bed9 100644 --- a/FEXCore/include/FEXCore/IR/IREmitter.h +++ b/FEXCore/include/FEXCore/IR/IREmitter.h @@ -145,9 +145,6 @@ friend class FEXCore::IR::PassManager; IRPair _AtomicFetchOr(uint8_t Size, OrderedNode *_Value, OrderedNode *_Addr) { return _AtomicFetchOr(static_cast(Size), _Value, _Addr); } - IRPair _AtomicFetchXor(uint8_t Size, OrderedNode *_Value, OrderedNode *_Addr) { - return _AtomicFetchXor(static_cast(Size), _Value, _Addr); - } ///< ALU IRPair _Add(OrderedNode *_Src1, OrderedNode *_Src2) { return _Add(static_cast(std::max(4, std::max(GetOpSize(_Src1), GetOpSize(_Src2)))), _Src1, _Src2);