From c92805475d2bdaaf33bd9f3e763b2a604bfaf093 Mon Sep 17 00:00:00 2001 From: "Pierre-Loup A. Griffais" Date: Thu, 3 Sep 2026 02:00:58 -0700 Subject: [PATCH 1/2] DiskCache: detect inline data, hash around it and patch it on Lookup Only detect certain kinds of mov reg,immediate so far, which was the bulk of Mono JIT activity. --- FEXCore/Source/Interface/Context/Context.h | 2 +- FEXCore/Source/Interface/Core/CodeCache.cpp | 17 ++++- FEXCore/Source/Interface/Core/DiskCache.cpp | 55 +++++++++++++++- FEXCore/Source/Interface/Core/Frontend.cpp | 63 ++++++++++++++++++- FEXCore/Source/Interface/Core/Frontend.h | 11 ++++ FEXCore/Source/Interface/Core/JIT/ALUOps.cpp | 5 ++ .../Interface/Core/JIT/Arm64Relocations.cpp | 12 ++++ FEXCore/Source/Interface/Core/JIT/JITClass.h | 2 + .../Source/Interface/Core/JIT/Relocations.h | 20 ++++++ .../Interface/Core/OpcodeDispatcher.cpp | 3 + .../Source/Interface/Core/OpcodeDispatcher.h | 2 +- .../Interface/Core/X86Tables/X86Tables.h | 10 +++ FEXCore/Source/Interface/IR/IR.json | 7 +++ FEXCore/include/FEXCore/Core/DiskCache.h | 13 +++- 14 files changed, 210 insertions(+), 12 deletions(-) diff --git a/FEXCore/Source/Interface/Context/Context.h b/FEXCore/Source/Interface/Context/Context.h index ec56e0177..ffabdbdae 100644 --- a/FEXCore/Source/Interface/Context/Context.h +++ b/FEXCore/Source/Interface/Context/Context.h @@ -132,7 +132,7 @@ public: // Same but on disk cache packed relocations [[nodiscard]] bool ApplyPackedCodeRelocations(uint64_t GuestDelta, std::span Code, std::span SmallRelocs, - std::span ThunkRelocs, bool ForStorage); + std::span ThunkRelocs); }; class ContextImpl final : public FEXCore::Context::Context, public CPU::SharedCodeBufferManager { diff --git a/FEXCore/Source/Interface/Core/CodeCache.cpp b/FEXCore/Source/Interface/Core/CodeCache.cpp index b3982e47d..5246c0247 100644 --- a/FEXCore/Source/Interface/Core/CodeCache.cpp +++ b/FEXCore/Source/Interface/Core/CodeCache.cpp @@ -538,16 +538,22 @@ ApplyRIPMoveRelocation(ContextImpl& CTX, uint64_t GuestRIP, uint8_t RegisterInde Emitter.LoadConstant(ARMEmitter::Size::i64Bit, ARMEmitter::Register(RegisterIndex), Pointer, CPU::Arm64Emitter::PadType::DOPAD); } +static inline void ApplyPatchableDataRelocation(uint64_t SiteAddress, uint8_t ValueSize, uint8_t RegisterIndex, CPU::Arm64Emitter& Emitter) { + uint64_t Value = 0; + memcpy(&Value, reinterpret_cast(SiteAddress), ValueSize); + Emitter.LoadConstant(ARMEmitter::Size::i64Bit, ARMEmitter::Register(RegisterIndex), Value, CPU::Arm64Emitter::PadType::DOPAD); +} + bool CodeCache::ApplyPackedCodeRelocations(uint64_t GuestEntry, std::span Code, std::span SmallRelocs, - std::span ThunkRelocs, bool ForStorage) { + std::span ThunkRelocs) { CPU::Arm64Emitter Emitter(&CTX, Code.data(), Code.size_bytes()); for (auto& Reloc : SmallRelocs) { LOGMAN_THROW_A_FMT(Reloc.Offset < Code.size_bytes(), "Invalid relocation offset"); Emitter.SetCursorOffset(Reloc.Offset); switch ((CPU::RelocationTypes)Reloc.Type) { case FEXCore::CPU::RelocationTypes::RELOC_NAMED_SYMBOL_LITERAL: { - ApplySymbolLiteralRelocation(CTX, (CPU::RelocNamedSymbolLiteral::NamedSymbol)Reloc.Named.Symbol, GuestEntry, Emitter, ForStorage); + ApplySymbolLiteralRelocation(CTX, (CPU::RelocNamedSymbolLiteral::NamedSymbol)Reloc.Named.Symbol, GuestEntry, Emitter, false); break; } case FEXCore::CPU::RelocationTypes::RELOC_GUEST_RIP_LITERAL: { @@ -558,13 +564,18 @@ bool CodeCache::ApplyPackedCodeRelocations(uint64_t GuestEntry, std::span(WriterThreadFlags); @@ -480,13 +483,23 @@ namespace DiskCache { return std::nullopt; } Thread->FrontendDecoder->DecodeLoop(reinterpret_cast(GuestRIP), AnonPrefixGuestBytes); + const auto* BlockInfo = Thread->FrontendDecoder->GetDecodedBlockInfo(); + XXH3_state_t HashState; XXH3_64bits_reset(&HashState); - for (auto& SubBlock : Thread->FrontendDecoder->GetDecodedBlockInfo()->Blocks) { - XXH3_64bits_update(&HashState, reinterpret_cast(SubBlock.Entry), SubBlock.Size); + for (auto& SubBlock : BlockInfo->Blocks) { if (SubBlock.BlockStatus != Frontend::Decoder::DecodedBlockStatus::SUCCESS) { return std::nullopt; } + uint64_t HashStart = SubBlock.Entry; + // skip over masked in-block data and data/etc gaps between blocks + for (auto& DataMask : SubBlock.DataMasks) { + XXH3_64bits_update(&HashState, reinterpret_cast(HashStart), DataMask.FieldAddress - HashStart); + HashStart = DataMask.FieldAddress + DataMask.ValueSize; + } + if (HashStart != SubBlock.Entry + SubBlock.Size) { + XXH3_64bits_update(&HashState, reinterpret_cast(HashStart), SubBlock.Size - (HashStart - SubBlock.Entry)); + } } GuestCodeKey = XXH3_64bits_digest(&HashState); // if (TotalSize < AnonPrefixGuestBytes) { @@ -635,7 +648,7 @@ namespace DiskCache { EntryPointRip += GuestRIP; } - if (!CTX->CodeCache.ApplyPackedCodeRelocations(GuestRIP, std::as_writable_bytes(HitData.HostCode), SmallRelocs, ThunkRelocs, false)) { + if (!CTX->CodeCache.ApplyPackedCodeRelocations(GuestRIP, std::as_writable_bytes(HitData.HostCode), SmallRelocs, ThunkRelocs)) { return std::nullopt; } @@ -737,6 +750,8 @@ namespace DiskCache { } } + fextl::set DataMaskAddresses; + fextl::vector ExactGuestCodeExtents; uint64_t CurStartExtent = 0, CurEndExtent = 0; const Frontend::Decoder::DecodedBlocks* LastBlock = nullptr; @@ -758,6 +773,16 @@ namespace DiskCache { CurEndExtent = SubBlock.Entry + SubBlock.Size; } } + // split extents according to data masks as well + for (auto& Mask : SubBlock.DataMasks) { + if (Mask.FieldAddress > CurStartExtent) { + ExactGuestCodeExtents.push_back(CurStartExtent - GuestRIP); + ExactGuestCodeExtents.push_back(Mask.FieldAddress - CurStartExtent); + } + CurStartExtent = Mask.FieldAddress + Mask.ValueSize; + + DataMaskAddresses.insert(Mask.FieldAddress); + } LastBlock = &SubBlock; } if (LastBlock && (CurStartExtent != GuestRIP || CurEndExtent != GuestRIP + GuestCode.size())) { @@ -860,6 +885,24 @@ namespace DiskCache { SmallRelocs[SmallIdx++] = SmallReloc; break; } + case CPU::RelocationTypes::RELOC_GUEST_PATCHABLE_DATA_MOVE: { + BlobSmallRelocation SmallReloc = {}; + SmallReloc.Offset = Reloc.Header.Offset; + SmallReloc.Type = uint8_t(Reloc.Header.Type); + SmallReloc.PatchableData.RegisterIndex = Reloc.GuestPatchableData.RegisterIndex; + SmallReloc.PatchableData.ValueSize = Reloc.GuestPatchableData.ValueSize; + SmallReloc.PatchableData.SiteOffset = uint32_t(Reloc.GuestPatchableData.SiteAddress - GuestRIP); + SmallRelocs[SmallIdx++] = SmallReloc; + + // mark the corresponding data mask consumed - we might not find one if they got removed due to the smc workaround + // the hash will just fail on lookup later + auto It = DataMaskAddresses.find(Reloc.GuestPatchableData.SiteAddress); + if (It != DataMaskAddresses.end()) { + DataMaskAddresses.erase(It); + } + + break; + } case CPU::RelocationTypes::RELOC_NAMED_THUNK_MOVE: { BlobThunkRelocation BigReloc = {}; BigReloc.Offset = Reloc.Header.Offset; @@ -871,6 +914,12 @@ namespace DiskCache { } } + if (!DataMaskAddresses.empty()) { + LogMan::Msg::IFmt("DiskCache: DataMask unaccounted for! {:x}", GuestCodeKey); + // this would mean we omitted contents in the hash that we're not going to patch, which would be loading corrupt code + return false; + } + memcpy(BlobData + GuestCodeOffset, GuestCode.data(), GuestCode.size()); fextl::vector IndexBlob; diff --git a/FEXCore/Source/Interface/Core/Frontend.cpp b/FEXCore/Source/Interface/Core/Frontend.cpp index 5829516de..92f5c4fce 100644 --- a/FEXCore/Source/Interface/Core/Frontend.cpp +++ b/FEXCore/Source/Interface/Core/Frontend.cpp @@ -140,6 +140,8 @@ std::pair Decoder::ReadData(uint8_t Size) { uint64_t Res = 0; uint64_t Address = reinterpret_cast(InstStream.InstStream + InstructionSize); + LastFieldReadOffset = (uint8_t)InstructionSize; + LastFieldReadSize = Size; if (CheckRangeExecutable(Address, Size)) { std::memcpy(&Res, &InstStream.AdjustedInstStream[InstructionSize], Size); } else { @@ -1334,6 +1336,13 @@ void Decoder::AddBranchTarget(uint64_t Target) { .BlockStatus = BlockIt->BlockStatus, }; + if (BlockIt->DataMasks.size()) { + auto MaskIt = std::lower_bound(BlockIt->DataMasks.begin(), BlockIt->DataMasks.end(), SplitAddr, + [](const DataMask& Mask, uint64_t Addr) { return Mask.FieldAddress < Addr; }); + SplitBlock.DataMasks.assign(MaskIt, BlockIt->DataMasks.end()); + BlockIt->DataMasks.erase(MaskIt, BlockIt->DataMasks.end()); + } + BlockIt->Size = SplitOffset; BlockIt->NumInstructions = SplitIdx; @@ -1386,7 +1395,48 @@ bool Decoder::CheckIfCacheable(FEXCore::Core::InternalThreadState& Thread, const return !Uncacheable; } +void Decoder::DetectDataMasks(uint64_t OpAddress, DecodedBlocks& Block) { + if (LastFieldReadSize < 4) { + return; + } + + FEXCore::X86Tables::DecodedOperand* LiteralToPatch = nullptr; + + // mov reg,imm + if (DecodeInst->OP >= 0xB8 && DecodeInst->OP <= 0xBF) { + for (auto& Src : DecodeInst->Src) { + if (Src.IsLiteral()) { + LiteralToPatch = &Src; + break; + } + } + + // we could filter to certain high values that are more likely to be pointers/etc? + // const uint64_t Value = Lit->Data.Literal.Value; + // if (LiteralToPatch && Value < 0x1000000ULL) { + // LiteralToPatch = nullptr; + // } + } + + // todo add a bunch more + + if (LiteralToPatch) { + Block.DataMasks.push_back({OpAddress + LastFieldReadOffset, LastFieldReadSize}); + + LiteralToPatch->Type = X86Tables::DecodedOperand::OpType::LiteralPatchable; + LiteralToPatch->Data.LiteralPatchable.FieldOffset = LastFieldReadOffset; + LiteralToPatch->Data.LiteralPatchable.Width = LastFieldReadSize; + } +} + void Decoder::DecodeLoop(const uint8_t* _InstStream, uint64_t GuestSizePause) { + // counter-intuitively, the masks are also needed for lookup on anon prefix decodes, not just stores + bool WantsDataMasks = CTX->DiskCache.IsReadingDiskCache() || CTX->DiskCache.IsWritingDiskCache(); + // remove this if we ever fixup ValidateCode crc constant after relocations + if (CTX->Config.SMCChecks == FEXCore::Config::CONFIG_SMC_FULL) { + WantsDataMasks = false; + } + while (!FinalInstruction && (Paused || !BlocksToDecode.empty())) { bool Pausing = false; fextl::vector::iterator BlockIt; @@ -1461,6 +1511,7 @@ void Decoder::DecodeLoop(const uint8_t* _InstStream, uint64_t GuestSizePause) { BlockInfo.CodePages.insert(CurrentCodePage); } + LastFieldReadSize = 0; BlockIt->BlockStatus = DecodeInstruction(OpAddress); if (HitBadRelocation) { BlockInfo.TotalInstructionCount = 0; @@ -1485,6 +1536,11 @@ void Decoder::DecodeLoop(const uint8_t* _InstStream, uint64_t GuestSizePause) { ++BlockIt->NumInstructions; BlockIt->Size += DecodeInst->InstSize; + // if we weren't provided relocations (guest JIT), try to detect what we can + if (WantsDataMasks && BlockIt->BlockStatus == DecodedBlockStatus::SUCCESS && BlockInfo.Is64BitMode && !Relocations) { + DetectDataMasks(OpAddress, *BlockIt); + } + // Can not continue this block at all on invalid instruction if (BlockIt->BlockStatus != DecodedBlockStatus::SUCCESS) [[unlikely]] { if (!EntryBlock && BlockIt->BlockStatus != DecodedBlockStatus::BAD_RELOCATION) { @@ -1531,7 +1587,12 @@ void Decoder::DecodeLoop(const uint8_t* _InstStream, uint64_t GuestSizePause) { // If the branch target is within our multiblock range then we can keep going on // We don't want to short circuit this since we want to calculate our ranges still // NOTE: This will invalidate BlockIt, this is fine as we immediately break from the loop and EraseBlock cannot be true - BlockIt->ForceFullSMCDetection = CTX->AreMonoHacksActive() && IsBranchMonoTailcall(BlockIt->NumInstructions); + if (CTX->AreMonoHacksActive() && IsBranchMonoTailcall(BlockIt->NumInstructions)) { + BlockIt->ForceFullSMCDetection = true; + // todo abandon patching this for now, as the crc will fail and it will lock up redoing it over and over + // we should fix the crc at relocation if this is important + BlockIt->DataMasks.clear(); + } BranchTargetInMultiblockRange(); } diff --git a/FEXCore/Source/Interface/Core/Frontend.h b/FEXCore/Source/Interface/Core/Frontend.h index 15683fced..5a3ec199f 100644 --- a/FEXCore/Source/Interface/Core/Frontend.h +++ b/FEXCore/Source/Interface/Core/Frontend.h @@ -32,6 +32,11 @@ public: UNIMPLEMENTED_INST, }; + struct DataMask final { + uint64_t FieldAddress; + uint8_t ValueSize; + }; + // New Frontend decoding struct DecodedBlocks final { uint64_t Entry {}; @@ -41,6 +46,7 @@ public: DecodedBlockStatus BlockStatus; bool IsEntryPoint {}; bool ForceFullSMCDetection {}; + fextl::vector DataMasks; }; struct DecodedBlockInformation final { @@ -103,6 +109,8 @@ private: void AddBranchTarget(uint64_t Target); + void DetectDataMasks(uint64_t OpAddress, DecodedBlocks& Block); + bool CheckRangeExecutable(uint64_t Address, uint64_t Size); uint8_t ReadByte(); @@ -133,6 +141,9 @@ private: uint64_t BlockStartOffset {}; bool EraseBlock {}; + uint8_t LastFieldReadOffset; + uint8_t LastFieldReadSize; + uint64_t ExecutableRangeBase {}; uint64_t ExecutableRangeEnd {}; bool ExecutableRangeWritable {}; diff --git a/FEXCore/Source/Interface/Core/JIT/ALUOps.cpp b/FEXCore/Source/Interface/Core/JIT/ALUOps.cpp index 7946ccdd2..3691bcab8 100644 --- a/FEXCore/Source/Interface/Core/JIT/ALUOps.cpp +++ b/FEXCore/Source/Interface/Core/JIT/ALUOps.cpp @@ -64,6 +64,11 @@ DEF_OP(EntrypointOffset) { InsertGuestRIPMove(GetReg(Node), Constant & Mask); } +DEF_OP(PatchableGuestData) { + auto Op = IROp->C(); + InsertGuestPatchableDataMove(GetReg(Node), Op->Value, Op->SiteAddress, (uint8_t)Op->SiteSize); +} + DEF_OP(InlineConstant) { // nop } diff --git a/FEXCore/Source/Interface/Core/JIT/Arm64Relocations.cpp b/FEXCore/Source/Interface/Core/JIT/Arm64Relocations.cpp index 50b8628e2..47c4f1159 100644 --- a/FEXCore/Source/Interface/Core/JIT/Arm64Relocations.cpp +++ b/FEXCore/Source/Interface/Core/JIT/Arm64Relocations.cpp @@ -102,6 +102,18 @@ void Arm64JITCore::InsertGuestRIPMove(ARMEmitter::Register Reg, uint64_t Constan Relocations.emplace_back(MoveABI); } +void Arm64JITCore::InsertGuestPatchableDataMove(ARMEmitter::Register Reg, uint64_t Value, uint64_t SiteAddress, uint8_t ValueSize) { + Relocation MoveABI = Relocation::Default(); + MoveABI.GuestPatchableData.Header = {.Offset = GetCursorOffset(), .Type = FEXCore::CPU::RelocationTypes::RELOC_GUEST_PATCHABLE_DATA_MOVE}; + MoveABI.GuestPatchableData.RegisterIndex = Reg.Idx(); + MoveABI.GuestPatchableData.ValueSize = ValueSize; + MoveABI.GuestPatchableData.SiteAddress = SiteAddress; + + // this might get patched on disk cache load + LoadConstant(ARMEmitter::Size::i64Bit, Reg, Value, FEXCore::CPU::Arm64Emitter::PadType::DOPAD); + Relocations.emplace_back(MoveABI); +} + fextl::vector Arm64JITCore::TakeRelocations(uint64_t GuestBaseAddress) { // Rebase relocations to library base address for (auto& Relocation : Relocations) { diff --git a/FEXCore/Source/Interface/Core/JIT/JITClass.h b/FEXCore/Source/Interface/Core/JIT/JITClass.h index 9d91f6503..2a56a7efe 100644 --- a/FEXCore/Source/Interface/Core/JIT/JITClass.h +++ b/FEXCore/Source/Interface/Core/JIT/JITClass.h @@ -562,6 +562,8 @@ private: */ void InsertGuestRIPMove(ARMEmitter::Register Reg, uint64_t Constant); + void InsertGuestPatchableDataMove(ARMEmitter::Register Reg, uint64_t Value, uint64_t SiteAddress, uint8_t ValueSize); + /** * @brief Inserts a named symbol as a literal in memory * diff --git a/FEXCore/Source/Interface/Core/JIT/Relocations.h b/FEXCore/Source/Interface/Core/JIT/Relocations.h index 9faa8a781..ec268874d 100644 --- a/FEXCore/Source/Interface/Core/JIT/Relocations.h +++ b/FEXCore/Source/Interface/Core/JIT/Relocations.h @@ -25,6 +25,10 @@ enum class RelocationTypes : uint32_t { // 4 instruction constant generation // Aligned to struct RelocGuestRIP RELOC_GUEST_RIP_MOVE, + + // The frontend flagged those regions as patchable by the disk cache + // Aligned to struct RelocGuestPatchableData + RELOC_GUEST_PATCHABLE_DATA_MOVE, }; struct FEX_PACKED RelocationHeader final { @@ -73,6 +77,20 @@ struct RelocGuestRIP final { uint32_t pad2[6] {}; }; +struct RelocGuestPatchableData final { + RelocationHeader Header {}; + + uint8_t RegisterIndex; + + uint8_t ValueSize; + + char Pad[2]; + + uint64_t SiteAddress; + + uint32_t pad2[6] {}; +}; + union Relocation { // Clang 16 Can't default-initialize this union static Relocation Default() { @@ -93,6 +111,8 @@ union Relocation { RelocNamedThunkMove NamedThunkMove; RelocGuestRIP GuestRIP; + + RelocGuestPatchableData GuestPatchableData; }; uint64_t GetNamedSymbolLiteral(FEXCore::Context::ContextImpl&, RelocNamedSymbolLiteral::NamedSymbol); diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp index d2552f433..22c7e46b8 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp @@ -4357,6 +4357,9 @@ AddressMode OpDispatchBuilder::DecodeAddress(const X86Tables::DecodedOp& Op, con A.NonTSO |= IsNonTSOReg(AccessType, Operand.Data.SIB.Base) || IsNonTSOReg(AccessType, Operand.Data.SIB.Index); } else if (Operand.IsLiteralRelocation()) { A.Base = _EntrypointOffset(GPRSize, Operand.Data.LiteralRelocation.EntrypointOffset); + } else if (Operand.IsLiteralPatchable()) { + A.Base = _PatchableGuestData(OpSize::i64Bit, Operand.Data.LiteralPatchable.Value, Op->PC + Operand.Data.LiteralPatchable.FieldOffset, + static_cast(Operand.Data.LiteralPatchable.Width)); } else { LOGMAN_MSG_A_FMT("Unknown Src Type: {}\n", Operand.Type); } diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher.h b/FEXCore/Source/Interface/Core/OpcodeDispatcher.h index 4a298a812..5a5737131 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher.h +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher.h @@ -1521,7 +1521,7 @@ private: [[nodiscard]] static bool IsOperandMem(const X86Tables::DecodedOperand& Operand, bool Load) { // Literals are immediates as sources but memory addresses as destinations. - return !(Load && (Operand.IsLiteral() || Operand.IsLiteralRelocation())) && !Operand.IsGPR(); + return !(Load && (Operand.IsLiteral() || Operand.IsLiteralRelocation() || Operand.IsLiteralPatchable())) && !Operand.IsGPR(); } [[nodiscard]] diff --git a/FEXCore/Source/Interface/Core/X86Tables/X86Tables.h b/FEXCore/Source/Interface/Core/X86Tables/X86Tables.h index 8bf90e6fd..9ab0cfbaa 100644 --- a/FEXCore/Source/Interface/Core/X86Tables/X86Tables.h +++ b/FEXCore/Source/Interface/Core/X86Tables/X86Tables.h @@ -128,6 +128,7 @@ struct DecodedOperand { RIPRelativeRelocation, Literal, LiteralRelocation, + LiteralPatchable, SIB, SIBRelocation }; @@ -159,6 +160,9 @@ struct DecodedOperand { bool IsLiteralRelocation() const { return Type == OpType::LiteralRelocation; } + bool IsLiteralPatchable() const { + return Type == OpType::LiteralPatchable; + } bool IsSIB() const { return Type == OpType::SIB; } @@ -196,6 +200,12 @@ struct DecodedOperand { int64_t EntrypointOffset; } LiteralRelocation; + struct { + uint64_t Value; + uint8_t Size; + uint8_t FieldOffset; + uint8_t Width; + } LiteralPatchable; struct { int64_t Offset; uint8_t Scale; diff --git a/FEXCore/Source/Interface/IR/IR.json b/FEXCore/Source/Interface/IR/IR.json index 5f5b8257d..61d0e0fd0 100644 --- a/FEXCore/Source/Interface/IR/IR.json +++ b/FEXCore/Source/Interface/IR/IR.json @@ -953,6 +953,13 @@ ] }, + "GPR = PatchableGuestData OpSize:#Size, i64:$Value, i64:$SiteAddress, i64:$SiteSize": { + "Desc": ["Loads Value in a patchable way", + "On disk cache load the value is patched from live guest bytes at SiteAddress" + ], + "DestSize": "Size" + }, + "GPR = Constant i64:$Constant, ConstPad:$Pad{IR::ConstPad::NoPad}, i32:$MaxBytes{0}": { "Desc": ["Generates a 64bit constant inside of a GPR", "Unsupported to create a constant in FPR" diff --git a/FEXCore/include/FEXCore/Core/DiskCache.h b/FEXCore/include/FEXCore/Core/DiskCache.h index 0b96bf781..4071a8572 100644 --- a/FEXCore/include/FEXCore/Core/DiskCache.h +++ b/FEXCore/include/FEXCore/Core/DiskCache.h @@ -85,6 +85,11 @@ namespace DiskCache { uint8_t RegisterIndex; uint64_t GuestRIP; } RIPMove; + struct __attribute__((packed)) { + uint8_t RegisterIndex; + uint8_t ValueSize; + uint32_t SiteOffset; + } PatchableData; }; }; @@ -176,10 +181,10 @@ namespace DiskCache { std::span Relocations, const Frontend::Decoder::DecodedBlockInformation* DecodedBlockInfo); bool IsWritingDiskCache() const { - return (bool)RWCacheDB; + return WritingDiskCache; } bool IsReadingDiskCache() const { - return !ROCacheDBs.empty() || RWCacheDB != nullptr; + return ReadingDiskCache; } bool IsValidating() const { return Validation; @@ -189,6 +194,8 @@ namespace DiskCache { bool OpenCacheDB(const fextl::string& CacheDBName, bool ReadOnly); uint64_t MakeBlobKey(Core::InternalThreadState* Thread, const uint64_t ModuleOffset, bool Writable, bool MonoBackpatcher); + bool ReadingDiskCache {}; + bool WritingDiskCache {}; FEXCore::Context::ContextImpl* CTX; XXH128_hash_t BucketHash; fextl::vector> ROCacheDBs; @@ -214,7 +221,7 @@ namespace DiskCache { // TODO: This header is in global installed header path, but uses internal headers. // Migrate this once that is fixed. - static constexpr uint16_t FormatVersion = 16; + static constexpr uint16_t FormatVersion = 17; FEX_DEFAULT_VISIBILITY uint16_t GetFormatVersion(); } // namespace DiskCache From 983c5defc1fcc732cc508619c676e18e5dd13b1f Mon Sep 17 00:00:00 2001 From: "Pierre-Loup A. Griffais" Date: Sun, 6 Sep 2026 23:25:53 -0700 Subject: [PATCH 2/2] InstcountCI: Update --- unittests/InstructionCountCI/AFP/H0F3A.json | 2 +- unittests/InstructionCountCI/AFP/SVE256/Secondary.json | 2 +- unittests/InstructionCountCI/AFP/SVE256/Secondary_REP.json | 2 +- unittests/InstructionCountCI/AFP/SVE256/Secondary_REPNE.json | 2 +- unittests/InstructionCountCI/AFP/Secondary.json | 2 +- unittests/InstructionCountCI/AFP/Secondary_REP.json | 2 +- unittests/InstructionCountCI/AFP/Secondary_REPNE.json | 2 +- unittests/InstructionCountCI/AFP/VEX_map1.json | 2 +- unittests/InstructionCountCI/AFP/VEX_map3.json | 2 +- unittests/InstructionCountCI/AVX128/FMA4.json | 2 +- unittests/InstructionCountCI/AVX128/VEX_map1.json | 2 +- unittests/InstructionCountCI/AVX128/VEX_map1_FCMA.json | 2 +- unittests/InstructionCountCI/AVX128/VEX_map1_SVE128.json | 2 +- unittests/InstructionCountCI/AVX128/VEX_map1_flagm.json | 2 +- unittests/InstructionCountCI/AVX128/VEX_map2.json | 2 +- unittests/InstructionCountCI/AVX128/VEX_map2_AFP.json | 2 +- unittests/InstructionCountCI/AVX128/VEX_map2_SVE128.json | 2 +- unittests/InstructionCountCI/AVX128/VEX_map2_flagm.json | 2 +- unittests/InstructionCountCI/AVX128/VEX_map3.json | 2 +- unittests/InstructionCountCI/AVX128/VEX_map3_SVE128.json | 2 +- unittests/InstructionCountCI/AVX128/VEX_map_group.json | 2 +- unittests/InstructionCountCI/Atomics.json | 2 +- unittests/InstructionCountCI/Crypto/H0F38.json | 2 +- unittests/InstructionCountCI/Crypto/H0F38_SVE128.json | 2 +- unittests/InstructionCountCI/Crypto/H0F3A.json | 2 +- unittests/InstructionCountCI/DDD.json | 2 +- unittests/InstructionCountCI/FEXOpt/AddressingLimitations.json | 2 +- .../InstructionCountCI/FEXOpt/AddressingLimitations_32Bit.json | 2 +- unittests/InstructionCountCI/FEXOpt/MultiInst.json | 2 +- unittests/InstructionCountCI/FEXOpt/MultiInst_32bit.json | 2 +- unittests/InstructionCountCI/FEXOpt/MultiInst_AFP.json | 2 +- unittests/InstructionCountCI/FEXOpt/MultiInst_TSO.json | 2 +- unittests/InstructionCountCI/FEXOpt/MultiInst_TSO_32bit.json | 2 +- unittests/InstructionCountCI/FEXOpt/libnss.json | 2 +- unittests/InstructionCountCI/FlagM/Atomics.json | 2 +- unittests/InstructionCountCI/FlagM/FlagOpts.json | 2 +- unittests/InstructionCountCI/FlagM/H0F38.json | 2 +- unittests/InstructionCountCI/FlagM/HotBlocks.json | 2 +- unittests/InstructionCountCI/FlagM/HotBlocks_32Bit.json | 2 +- unittests/InstructionCountCI/FlagM/HotBlocks_AFP.json | 2 +- unittests/InstructionCountCI/FlagM/HotBlocks_TSO_32Bit.json | 2 +- unittests/InstructionCountCI/FlagM/Primary.json | 2 +- unittests/InstructionCountCI/FlagM/PrimaryGroup.json | 2 +- unittests/InstructionCountCI/FlagM/Primary_32Bit.json | 2 +- unittests/InstructionCountCI/FlagM/Secondary.json | 2 +- unittests/InstructionCountCI/FlagM/SecondaryGroup.json | 2 +- unittests/InstructionCountCI/FlagM/SecondaryModRM.json | 2 +- unittests/InstructionCountCI/FlagM/Secondary_OpSize.json | 2 +- unittests/InstructionCountCI/FlagM/Secondary_REP.json | 2 +- unittests/InstructionCountCI/FlagM/Secondary_REP_CSSC.json | 2 +- unittests/InstructionCountCI/FlagM/VEX_map1.json | 2 +- unittests/InstructionCountCI/FlagM/VEX_map2.json | 2 +- unittests/InstructionCountCI/FlagM/VEX_map_group.json | 2 +- unittests/InstructionCountCI/FlagM/x87-Crysis2Max-fmodel.json | 2 +- unittests/InstructionCountCI/FlagM/x87-HalfLife.json | 2 +- unittests/InstructionCountCI/FlagM/x87-Oblivion.json | 2 +- unittests/InstructionCountCI/FlagM/x87-Psychonauts.json | 2 +- unittests/InstructionCountCI/FlagM/x87.json | 2 +- .../InstructionCountCI/FlagM/x87_f64-Crysis2Max-fmodel.json | 2 +- unittests/InstructionCountCI/FlagM/x87_f64-HalfLife.json | 2 +- unittests/InstructionCountCI/FlagM/x87_f64-Oblivion.json | 2 +- unittests/InstructionCountCI/FlagM/x87_f64-Psychonauts.json | 2 +- unittests/InstructionCountCI/FlagM/x87_f64.json | 2 +- unittests/InstructionCountCI/H0F38.json | 2 +- unittests/InstructionCountCI/H0F3A.json | 2 +- unittests/InstructionCountCI/H0F3A_SVE128.json | 2 +- unittests/InstructionCountCI/MOPS/Primary.json | 2 +- unittests/InstructionCountCI/Primary.json | 2 +- unittests/InstructionCountCI/PrimaryGroup.json | 2 +- unittests/InstructionCountCI/Primary_32Bit.json | 2 +- unittests/InstructionCountCI/RPRES/DDD.json | 2 +- unittests/InstructionCountCI/RPRES/Secondary.json | 2 +- unittests/InstructionCountCI/RPRES/Secondary_REP_AFP.json | 2 +- unittests/InstructionCountCI/RPRES/VEX_map1_AFP.json | 2 +- unittests/InstructionCountCI/Repeat.json | 2 +- unittests/InstructionCountCI/SSE42_Strings.json | 2 +- unittests/InstructionCountCI/Secondary.json | 2 +- unittests/InstructionCountCI/SecondaryGroup.json | 2 +- unittests/InstructionCountCI/SecondaryModRM.json | 2 +- unittests/InstructionCountCI/Secondary_32Bit.json | 2 +- unittests/InstructionCountCI/Secondary_OpSize.json | 2 +- unittests/InstructionCountCI/Secondary_OpSize_FCMA.json | 2 +- unittests/InstructionCountCI/Secondary_OpSize_SVE128.json | 2 +- unittests/InstructionCountCI/Secondary_OpSize_SVE256.json | 2 +- unittests/InstructionCountCI/Secondary_REP.json | 2 +- unittests/InstructionCountCI/Secondary_REPNE.json | 2 +- unittests/InstructionCountCI/Secondary_REPNE_FCMA.json | 2 +- unittests/InstructionCountCI/Secondary_REPNE_SVE128.json | 2 +- unittests/InstructionCountCI/Secondary_REP_FRINTTS.json | 2 +- unittests/InstructionCountCI/Secondary_SVE128.json | 2 +- unittests/InstructionCountCI/VEX_map1.json | 2 +- unittests/InstructionCountCI/VEX_map1_FCMA.json | 2 +- unittests/InstructionCountCI/VEX_map1_FRINTTS.json | 2 +- unittests/InstructionCountCI/VEX_map2.json | 2 +- unittests/InstructionCountCI/VEX_map2_svebitperm.json | 2 +- unittests/InstructionCountCI/VEX_map3.json | 2 +- unittests/InstructionCountCI/VEX_map_group.json | 2 +- unittests/InstructionCountCI/X87ldst-SVE.json | 2 +- unittests/InstructionCountCI/x87.json | 2 +- unittests/InstructionCountCI/x87_32Bit.json | 2 +- unittests/InstructionCountCI/x87_f64.json | 2 +- unittests/InstructionCountCI/x87_f64_32Bit.json | 2 +- 102 files changed, 102 insertions(+), 102 deletions(-) diff --git a/unittests/InstructionCountCI/AFP/H0F3A.json b/unittests/InstructionCountCI/AFP/H0F3A.json index 71d29f7f3..bd34f2ddf 100644 --- a/unittests/InstructionCountCI/AFP/H0F3A.json +++ b/unittests/InstructionCountCI/AFP/H0F3A.json @@ -8,7 +8,7 @@ "SVE128", "SVE256" ], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Instructions": { "roundss xmm0, xmm1, 00000000b": { diff --git a/unittests/InstructionCountCI/AFP/SVE256/Secondary.json b/unittests/InstructionCountCI/AFP/SVE256/Secondary.json index 8096eade0..a37f43b00 100644 --- a/unittests/InstructionCountCI/AFP/SVE256/Secondary.json +++ b/unittests/InstructionCountCI/AFP/SVE256/Secondary.json @@ -7,7 +7,7 @@ "AFP" ], "DisabledHostFeatures": [], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Instructions": { "cvtpi2ps xmm0, [rax]": { diff --git a/unittests/InstructionCountCI/AFP/SVE256/Secondary_REP.json b/unittests/InstructionCountCI/AFP/SVE256/Secondary_REP.json index dca88ea19..52b2ae6e3 100644 --- a/unittests/InstructionCountCI/AFP/SVE256/Secondary_REP.json +++ b/unittests/InstructionCountCI/AFP/SVE256/Secondary_REP.json @@ -9,7 +9,7 @@ "DisabledHostFeatures": [ "RPRES" ], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Instructions": { "cvtsi2ss xmm0, eax": { diff --git a/unittests/InstructionCountCI/AFP/SVE256/Secondary_REPNE.json b/unittests/InstructionCountCI/AFP/SVE256/Secondary_REPNE.json index 94c1a3a6d..1b3e7dd95 100644 --- a/unittests/InstructionCountCI/AFP/SVE256/Secondary_REPNE.json +++ b/unittests/InstructionCountCI/AFP/SVE256/Secondary_REPNE.json @@ -7,7 +7,7 @@ "AFP" ], "DisabledHostFeatures": [], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Instructions": { "cvtsi2sd xmm0, eax": { diff --git a/unittests/InstructionCountCI/AFP/Secondary.json b/unittests/InstructionCountCI/AFP/Secondary.json index 28a907af0..292819b02 100644 --- a/unittests/InstructionCountCI/AFP/Secondary.json +++ b/unittests/InstructionCountCI/AFP/Secondary.json @@ -8,7 +8,7 @@ "SVE128", "SVE256" ], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Instructions": { "cvtpi2ps xmm0, [rax]": { diff --git a/unittests/InstructionCountCI/AFP/Secondary_REP.json b/unittests/InstructionCountCI/AFP/Secondary_REP.json index 9f43f29e4..fe5c07dcd 100644 --- a/unittests/InstructionCountCI/AFP/Secondary_REP.json +++ b/unittests/InstructionCountCI/AFP/Secondary_REP.json @@ -9,7 +9,7 @@ "SVE256", "RPRES" ], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Instructions": { "cvtsi2ss xmm0, eax": { diff --git a/unittests/InstructionCountCI/AFP/Secondary_REPNE.json b/unittests/InstructionCountCI/AFP/Secondary_REPNE.json index d49dbc49a..1dda36183 100644 --- a/unittests/InstructionCountCI/AFP/Secondary_REPNE.json +++ b/unittests/InstructionCountCI/AFP/Secondary_REPNE.json @@ -8,7 +8,7 @@ "SVE128", "SVE256" ], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Instructions": { "cvtsi2sd xmm0, eax": { diff --git a/unittests/InstructionCountCI/AFP/VEX_map1.json b/unittests/InstructionCountCI/AFP/VEX_map1.json index 96f6c975d..c3d8bf981 100644 --- a/unittests/InstructionCountCI/AFP/VEX_map1.json +++ b/unittests/InstructionCountCI/AFP/VEX_map1.json @@ -9,7 +9,7 @@ "DisabledHostFeatures": [ "RPRES" ], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Instructions": { "vsqrtss xmm0, xmm1, xmm2": { diff --git a/unittests/InstructionCountCI/AFP/VEX_map3.json b/unittests/InstructionCountCI/AFP/VEX_map3.json index 5c17589e2..295970a7d 100644 --- a/unittests/InstructionCountCI/AFP/VEX_map3.json +++ b/unittests/InstructionCountCI/AFP/VEX_map3.json @@ -7,7 +7,7 @@ "AFP" ], "DisabledHostFeatures": [], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Instructions": { "vroundss xmm0, xmm1, 00000000b": { diff --git a/unittests/InstructionCountCI/AVX128/FMA4.json b/unittests/InstructionCountCI/AVX128/FMA4.json index 1f9512d7c..4a4b0e8ac 100644 --- a/unittests/InstructionCountCI/AVX128/FMA4.json +++ b/unittests/InstructionCountCI/AVX128/FMA4.json @@ -7,7 +7,7 @@ "SVE256", "SVE128" ], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Instructions": { "vfmaddsubps xmm0, xmm1, xmm2, xmm3": { diff --git a/unittests/InstructionCountCI/AVX128/VEX_map1.json b/unittests/InstructionCountCI/AVX128/VEX_map1.json index 77764a839..46f9bf40b 100644 --- a/unittests/InstructionCountCI/AVX128/VEX_map1.json +++ b/unittests/InstructionCountCI/AVX128/VEX_map1.json @@ -13,7 +13,7 @@ "SVE256", "SVE128" ], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Instructions": { "vmovups xmm0, xmm0": { diff --git a/unittests/InstructionCountCI/AVX128/VEX_map1_FCMA.json b/unittests/InstructionCountCI/AVX128/VEX_map1_FCMA.json index 73a15929b..fd32e9a83 100644 --- a/unittests/InstructionCountCI/AVX128/VEX_map1_FCMA.json +++ b/unittests/InstructionCountCI/AVX128/VEX_map1_FCMA.json @@ -9,7 +9,7 @@ "SVE256", "SVE128" ], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Instructions": { "vaddsubpd xmm0, xmm1, xmm2": { diff --git a/unittests/InstructionCountCI/AVX128/VEX_map1_SVE128.json b/unittests/InstructionCountCI/AVX128/VEX_map1_SVE128.json index 4e99d23b9..8f9294ffc 100644 --- a/unittests/InstructionCountCI/AVX128/VEX_map1_SVE128.json +++ b/unittests/InstructionCountCI/AVX128/VEX_map1_SVE128.json @@ -10,7 +10,7 @@ "FLAGM2", "SVE256" ], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Instructions": { "vmovntps [rax], xmm0": { diff --git a/unittests/InstructionCountCI/AVX128/VEX_map1_flagm.json b/unittests/InstructionCountCI/AVX128/VEX_map1_flagm.json index fc7e94dc1..6e6f52f37 100644 --- a/unittests/InstructionCountCI/AVX128/VEX_map1_flagm.json +++ b/unittests/InstructionCountCI/AVX128/VEX_map1_flagm.json @@ -10,7 +10,7 @@ "SVE128", "SVE256" ], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Instructions": { "vucomiss xmm0, xmm1": { diff --git a/unittests/InstructionCountCI/AVX128/VEX_map2.json b/unittests/InstructionCountCI/AVX128/VEX_map2.json index 1b50a2b97..70152ab68 100644 --- a/unittests/InstructionCountCI/AVX128/VEX_map2.json +++ b/unittests/InstructionCountCI/AVX128/VEX_map2.json @@ -9,7 +9,7 @@ "SVE128", "SVE256" ], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Instructions": { "vpshufb xmm0, xmm1, xmm2": { diff --git a/unittests/InstructionCountCI/AVX128/VEX_map2_AFP.json b/unittests/InstructionCountCI/AVX128/VEX_map2_AFP.json index 4a370a800..5c021fc5e 100644 --- a/unittests/InstructionCountCI/AVX128/VEX_map2_AFP.json +++ b/unittests/InstructionCountCI/AVX128/VEX_map2_AFP.json @@ -8,7 +8,7 @@ "SVE256", "SVE128" ], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Instructions": { "vfmadd132ss xmm0, xmm1, xmm2": { diff --git a/unittests/InstructionCountCI/AVX128/VEX_map2_SVE128.json b/unittests/InstructionCountCI/AVX128/VEX_map2_SVE128.json index 5bdeb6b7b..90879d321 100644 --- a/unittests/InstructionCountCI/AVX128/VEX_map2_SVE128.json +++ b/unittests/InstructionCountCI/AVX128/VEX_map2_SVE128.json @@ -10,7 +10,7 @@ "FLAGM2", "SVE256" ], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Instructions": { "vmovntdqa xmm0, [rax]": { diff --git a/unittests/InstructionCountCI/AVX128/VEX_map2_flagm.json b/unittests/InstructionCountCI/AVX128/VEX_map2_flagm.json index 15cbc5a80..12145dbd2 100644 --- a/unittests/InstructionCountCI/AVX128/VEX_map2_flagm.json +++ b/unittests/InstructionCountCI/AVX128/VEX_map2_flagm.json @@ -11,7 +11,7 @@ "SVE256", "SVEBITPERM" ], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Instructions": { "vtestps xmm0, xmm1": { diff --git a/unittests/InstructionCountCI/AVX128/VEX_map3.json b/unittests/InstructionCountCI/AVX128/VEX_map3.json index 2e08f109f..ff4293805 100644 --- a/unittests/InstructionCountCI/AVX128/VEX_map3.json +++ b/unittests/InstructionCountCI/AVX128/VEX_map3.json @@ -7,7 +7,7 @@ "SVE256", "SVE128" ], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Instructions": { "vpermq ymm0, ymm1, 1": { diff --git a/unittests/InstructionCountCI/AVX128/VEX_map3_SVE128.json b/unittests/InstructionCountCI/AVX128/VEX_map3_SVE128.json index 4d608564e..1427c1b94 100644 --- a/unittests/InstructionCountCI/AVX128/VEX_map3_SVE128.json +++ b/unittests/InstructionCountCI/AVX128/VEX_map3_SVE128.json @@ -8,7 +8,7 @@ "AFP", "SVE256" ], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Instructions": { "vblendvps xmm0, xmm1, xmm2, xmm3": { diff --git a/unittests/InstructionCountCI/AVX128/VEX_map_group.json b/unittests/InstructionCountCI/AVX128/VEX_map_group.json index 8ecf54c37..b6018049f 100644 --- a/unittests/InstructionCountCI/AVX128/VEX_map_group.json +++ b/unittests/InstructionCountCI/AVX128/VEX_map_group.json @@ -9,7 +9,7 @@ "SVE256", "SVE128" ], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Instructions": { "vpsrlw xmm0, xmm1, 0": { diff --git a/unittests/InstructionCountCI/Atomics.json b/unittests/InstructionCountCI/Atomics.json index 2fdb537ed..71e006f4b 100644 --- a/unittests/InstructionCountCI/Atomics.json +++ b/unittests/InstructionCountCI/Atomics.json @@ -9,7 +9,7 @@ "FLAGM", "FLAGM2" ], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Instructions": { "lock add byte [rax], cl": { diff --git a/unittests/InstructionCountCI/Crypto/H0F38.json b/unittests/InstructionCountCI/Crypto/H0F38.json index 6a20a165e..64f87944a 100644 --- a/unittests/InstructionCountCI/Crypto/H0F38.json +++ b/unittests/InstructionCountCI/Crypto/H0F38.json @@ -9,7 +9,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Instructions": { "sha1nexte xmm0, xmm1": { diff --git a/unittests/InstructionCountCI/Crypto/H0F38_SVE128.json b/unittests/InstructionCountCI/Crypto/H0F38_SVE128.json index 8a8586b08..c5f923a27 100644 --- a/unittests/InstructionCountCI/Crypto/H0F38_SVE128.json +++ b/unittests/InstructionCountCI/Crypto/H0F38_SVE128.json @@ -9,7 +9,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Instructions": { "sha1nexte xmm0, xmm1": { diff --git a/unittests/InstructionCountCI/Crypto/H0F3A.json b/unittests/InstructionCountCI/Crypto/H0F3A.json index c91f974f0..8faef2e5a 100644 --- a/unittests/InstructionCountCI/Crypto/H0F3A.json +++ b/unittests/InstructionCountCI/Crypto/H0F3A.json @@ -9,7 +9,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Instructions": { "pclmulqdq xmm0, xmm1, 00000b": { diff --git a/unittests/InstructionCountCI/DDD.json b/unittests/InstructionCountCI/DDD.json index ca04950c4..a0199660a 100644 --- a/unittests/InstructionCountCI/DDD.json +++ b/unittests/InstructionCountCI/DDD.json @@ -10,7 +10,7 @@ "AFP", "RPRES" ], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Comment": [ "These 3DNow! instructions are optimal assuming that FEX doesn't SRA MMX registers", diff --git a/unittests/InstructionCountCI/FEXOpt/AddressingLimitations.json b/unittests/InstructionCountCI/FEXOpt/AddressingLimitations.json index 44840bcf7..f98dbfdbc 100644 --- a/unittests/InstructionCountCI/FEXOpt/AddressingLimitations.json +++ b/unittests/InstructionCountCI/FEXOpt/AddressingLimitations.json @@ -8,7 +8,7 @@ "RPRES", "AFP" ], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Comment": [ "Instructions that explicitly push against the limits of ARM's loadstore instructions" diff --git a/unittests/InstructionCountCI/FEXOpt/AddressingLimitations_32Bit.json b/unittests/InstructionCountCI/FEXOpt/AddressingLimitations_32Bit.json index 43ea9f4b6..ab9c9dd36 100644 --- a/unittests/InstructionCountCI/FEXOpt/AddressingLimitations_32Bit.json +++ b/unittests/InstructionCountCI/FEXOpt/AddressingLimitations_32Bit.json @@ -8,7 +8,7 @@ "RPRES", "AFP" ], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Comment": [ "Instructions that explicitly push against the limits of ARM's loadstore instructions" diff --git a/unittests/InstructionCountCI/FEXOpt/MultiInst.json b/unittests/InstructionCountCI/FEXOpt/MultiInst.json index 0cf9c4d7e..11f507850 100644 --- a/unittests/InstructionCountCI/FEXOpt/MultiInst.json +++ b/unittests/InstructionCountCI/FEXOpt/MultiInst.json @@ -13,7 +13,7 @@ "RPRES", "AFP" ], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Comment": [ "These are instruction combinations that could be more optimal if FEX optimized for them" diff --git a/unittests/InstructionCountCI/FEXOpt/MultiInst_32bit.json b/unittests/InstructionCountCI/FEXOpt/MultiInst_32bit.json index 7ddec6df4..1bb94240f 100644 --- a/unittests/InstructionCountCI/FEXOpt/MultiInst_32bit.json +++ b/unittests/InstructionCountCI/FEXOpt/MultiInst_32bit.json @@ -11,7 +11,7 @@ "RPRES", "AFP" ], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Comment": [ "These are instruction combinations that could be more optimal if FEX optimized for them" diff --git a/unittests/InstructionCountCI/FEXOpt/MultiInst_AFP.json b/unittests/InstructionCountCI/FEXOpt/MultiInst_AFP.json index 2fe2ca755..d0fc59e59 100644 --- a/unittests/InstructionCountCI/FEXOpt/MultiInst_AFP.json +++ b/unittests/InstructionCountCI/FEXOpt/MultiInst_AFP.json @@ -9,7 +9,7 @@ "SVE256", "RPRES" ], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Comment": [ "These are instruction combinations that could be more optimal if FEX optimized for them" diff --git a/unittests/InstructionCountCI/FEXOpt/MultiInst_TSO.json b/unittests/InstructionCountCI/FEXOpt/MultiInst_TSO.json index fc99a4837..df69e1e7f 100644 --- a/unittests/InstructionCountCI/FEXOpt/MultiInst_TSO.json +++ b/unittests/InstructionCountCI/FEXOpt/MultiInst_TSO.json @@ -14,7 +14,7 @@ "RPRES", "AFP" ], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Comment": [ "These are instruction combinations that could be more optimal if FEX optimized for them" diff --git a/unittests/InstructionCountCI/FEXOpt/MultiInst_TSO_32bit.json b/unittests/InstructionCountCI/FEXOpt/MultiInst_TSO_32bit.json index 124994f38..d7b17be40 100644 --- a/unittests/InstructionCountCI/FEXOpt/MultiInst_TSO_32bit.json +++ b/unittests/InstructionCountCI/FEXOpt/MultiInst_TSO_32bit.json @@ -14,7 +14,7 @@ "RPRES", "AFP" ], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Comment": [ "These are instruction combinations that could be more optimal if FEX optimized for them" diff --git a/unittests/InstructionCountCI/FEXOpt/libnss.json b/unittests/InstructionCountCI/FEXOpt/libnss.json index 1b9148d67..4657e71c1 100644 --- a/unittests/InstructionCountCI/FEXOpt/libnss.json +++ b/unittests/InstructionCountCI/FEXOpt/libnss.json @@ -12,7 +12,7 @@ "RPRES", "AFP" ], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Comment": [], "Instructions": { diff --git a/unittests/InstructionCountCI/FlagM/Atomics.json b/unittests/InstructionCountCI/FlagM/Atomics.json index 126a688bd..32ca5e655 100644 --- a/unittests/InstructionCountCI/FlagM/Atomics.json +++ b/unittests/InstructionCountCI/FlagM/Atomics.json @@ -10,7 +10,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Instructions": { "lock add byte [rax], cl": { diff --git a/unittests/InstructionCountCI/FlagM/FlagOpts.json b/unittests/InstructionCountCI/FlagM/FlagOpts.json index 807eee533..5a13a44ef 100644 --- a/unittests/InstructionCountCI/FlagM/FlagOpts.json +++ b/unittests/InstructionCountCI/FlagM/FlagOpts.json @@ -9,7 +9,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Instructions": { "Chained add": { diff --git a/unittests/InstructionCountCI/FlagM/H0F38.json b/unittests/InstructionCountCI/FlagM/H0F38.json index 2aa75b0f6..e885cfac8 100644 --- a/unittests/InstructionCountCI/FlagM/H0F38.json +++ b/unittests/InstructionCountCI/FlagM/H0F38.json @@ -10,7 +10,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Instructions": { "ptest xmm0, xmm1": { diff --git a/unittests/InstructionCountCI/FlagM/HotBlocks.json b/unittests/InstructionCountCI/FlagM/HotBlocks.json index 64b45d17f..56e5ce0b2 100644 --- a/unittests/InstructionCountCI/FlagM/HotBlocks.json +++ b/unittests/InstructionCountCI/FlagM/HotBlocks.json @@ -10,7 +10,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Instructions": { "The Witcher 3": { diff --git a/unittests/InstructionCountCI/FlagM/HotBlocks_32Bit.json b/unittests/InstructionCountCI/FlagM/HotBlocks_32Bit.json index fff95c2f4..5b629819c 100644 --- a/unittests/InstructionCountCI/FlagM/HotBlocks_32Bit.json +++ b/unittests/InstructionCountCI/FlagM/HotBlocks_32Bit.json @@ -10,7 +10,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Instructions": { "Sonic Mania movie player": { diff --git a/unittests/InstructionCountCI/FlagM/HotBlocks_AFP.json b/unittests/InstructionCountCI/FlagM/HotBlocks_AFP.json index 2c51d0f07..7fb0896d8 100644 --- a/unittests/InstructionCountCI/FlagM/HotBlocks_AFP.json +++ b/unittests/InstructionCountCI/FlagM/HotBlocks_AFP.json @@ -10,7 +10,7 @@ "SVE128", "SVE256" ], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Instructions": { "FMOD scalar loop": { diff --git a/unittests/InstructionCountCI/FlagM/HotBlocks_TSO_32Bit.json b/unittests/InstructionCountCI/FlagM/HotBlocks_TSO_32Bit.json index c8c5a5201..37deb2032 100644 --- a/unittests/InstructionCountCI/FlagM/HotBlocks_TSO_32Bit.json +++ b/unittests/InstructionCountCI/FlagM/HotBlocks_TSO_32Bit.json @@ -13,7 +13,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Instructions": { "The Sims 1 hot block": { diff --git a/unittests/InstructionCountCI/FlagM/Primary.json b/unittests/InstructionCountCI/FlagM/Primary.json index 05f02f94c..6baacce55 100644 --- a/unittests/InstructionCountCI/FlagM/Primary.json +++ b/unittests/InstructionCountCI/FlagM/Primary.json @@ -10,7 +10,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Instructions": { "add bl, cl": { diff --git a/unittests/InstructionCountCI/FlagM/PrimaryGroup.json b/unittests/InstructionCountCI/FlagM/PrimaryGroup.json index 98dd80169..46172bf1f 100644 --- a/unittests/InstructionCountCI/FlagM/PrimaryGroup.json +++ b/unittests/InstructionCountCI/FlagM/PrimaryGroup.json @@ -10,7 +10,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Instructions": { "add al, 1": { diff --git a/unittests/InstructionCountCI/FlagM/Primary_32Bit.json b/unittests/InstructionCountCI/FlagM/Primary_32Bit.json index 4b820bf0e..7262cced5 100644 --- a/unittests/InstructionCountCI/FlagM/Primary_32Bit.json +++ b/unittests/InstructionCountCI/FlagM/Primary_32Bit.json @@ -10,7 +10,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Instructions": { "push es": { diff --git a/unittests/InstructionCountCI/FlagM/Secondary.json b/unittests/InstructionCountCI/FlagM/Secondary.json index 46518b04b..9234efa77 100644 --- a/unittests/InstructionCountCI/FlagM/Secondary.json +++ b/unittests/InstructionCountCI/FlagM/Secondary.json @@ -11,7 +11,7 @@ "RPRES", "AFP" ], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Instructions": { "ucomiss xmm0, xmm1": { diff --git a/unittests/InstructionCountCI/FlagM/SecondaryGroup.json b/unittests/InstructionCountCI/FlagM/SecondaryGroup.json index 2202c6e99..8b9ada413 100644 --- a/unittests/InstructionCountCI/FlagM/SecondaryGroup.json +++ b/unittests/InstructionCountCI/FlagM/SecondaryGroup.json @@ -11,7 +11,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Instructions": { "sgdt [rax]": { diff --git a/unittests/InstructionCountCI/FlagM/SecondaryModRM.json b/unittests/InstructionCountCI/FlagM/SecondaryModRM.json index 83ab8f38f..fefcfb50a 100644 --- a/unittests/InstructionCountCI/FlagM/SecondaryModRM.json +++ b/unittests/InstructionCountCI/FlagM/SecondaryModRM.json @@ -11,7 +11,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Instructions": { "xgetbv": { diff --git a/unittests/InstructionCountCI/FlagM/Secondary_OpSize.json b/unittests/InstructionCountCI/FlagM/Secondary_OpSize.json index 0a21189bd..bb6e26ed7 100644 --- a/unittests/InstructionCountCI/FlagM/Secondary_OpSize.json +++ b/unittests/InstructionCountCI/FlagM/Secondary_OpSize.json @@ -11,7 +11,7 @@ "AFP", "FCMA" ], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Instructions": { "ucomisd xmm0, xmm1": { diff --git a/unittests/InstructionCountCI/FlagM/Secondary_REP.json b/unittests/InstructionCountCI/FlagM/Secondary_REP.json index f9804a271..8dd192431 100644 --- a/unittests/InstructionCountCI/FlagM/Secondary_REP.json +++ b/unittests/InstructionCountCI/FlagM/Secondary_REP.json @@ -12,7 +12,7 @@ "AFP", "CSSC" ], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Instructions": { "popcnt ax, bx": { diff --git a/unittests/InstructionCountCI/FlagM/Secondary_REP_CSSC.json b/unittests/InstructionCountCI/FlagM/Secondary_REP_CSSC.json index 692d86683..8fdaba4f3 100644 --- a/unittests/InstructionCountCI/FlagM/Secondary_REP_CSSC.json +++ b/unittests/InstructionCountCI/FlagM/Secondary_REP_CSSC.json @@ -12,7 +12,7 @@ "RPRES", "AFP" ], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Instructions": { "popcnt ax, bx": { diff --git a/unittests/InstructionCountCI/FlagM/VEX_map1.json b/unittests/InstructionCountCI/FlagM/VEX_map1.json index 9834ae914..b78fd20ee 100644 --- a/unittests/InstructionCountCI/FlagM/VEX_map1.json +++ b/unittests/InstructionCountCI/FlagM/VEX_map1.json @@ -12,7 +12,7 @@ "RPRES", "AFP" ], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Instructions": { "vucomiss xmm0, xmm1": { diff --git a/unittests/InstructionCountCI/FlagM/VEX_map2.json b/unittests/InstructionCountCI/FlagM/VEX_map2.json index 50300db77..71d99f070 100644 --- a/unittests/InstructionCountCI/FlagM/VEX_map2.json +++ b/unittests/InstructionCountCI/FlagM/VEX_map2.json @@ -10,7 +10,7 @@ "AFP", "SVEBITPERM" ], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Instructions": { "vtestps xmm0, xmm1": { diff --git a/unittests/InstructionCountCI/FlagM/VEX_map_group.json b/unittests/InstructionCountCI/FlagM/VEX_map_group.json index b5e9613b6..da91736d0 100644 --- a/unittests/InstructionCountCI/FlagM/VEX_map_group.json +++ b/unittests/InstructionCountCI/FlagM/VEX_map_group.json @@ -9,7 +9,7 @@ "DisabledHostFeatures": [ "AFP" ], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Instructions": { "blsr eax, ebx": { diff --git a/unittests/InstructionCountCI/FlagM/x87-Crysis2Max-fmodel.json b/unittests/InstructionCountCI/FlagM/x87-Crysis2Max-fmodel.json index f2592e5a0..7cfd13025 100644 --- a/unittests/InstructionCountCI/FlagM/x87-Crysis2Max-fmodel.json +++ b/unittests/InstructionCountCI/FlagM/x87-Crysis2Max-fmodel.json @@ -10,7 +10,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Instructions": { "Block1": { diff --git a/unittests/InstructionCountCI/FlagM/x87-HalfLife.json b/unittests/InstructionCountCI/FlagM/x87-HalfLife.json index 8397ec305..f91aa0479 100644 --- a/unittests/InstructionCountCI/FlagM/x87-HalfLife.json +++ b/unittests/InstructionCountCI/FlagM/x87-HalfLife.json @@ -10,7 +10,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Instructions": { "Block1": { diff --git a/unittests/InstructionCountCI/FlagM/x87-Oblivion.json b/unittests/InstructionCountCI/FlagM/x87-Oblivion.json index 569bef081..9fba60a14 100644 --- a/unittests/InstructionCountCI/FlagM/x87-Oblivion.json +++ b/unittests/InstructionCountCI/FlagM/x87-Oblivion.json @@ -10,7 +10,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Instructions": { "Block1": { diff --git a/unittests/InstructionCountCI/FlagM/x87-Psychonauts.json b/unittests/InstructionCountCI/FlagM/x87-Psychonauts.json index b60f46be2..66f2074cf 100644 --- a/unittests/InstructionCountCI/FlagM/x87-Psychonauts.json +++ b/unittests/InstructionCountCI/FlagM/x87-Psychonauts.json @@ -10,7 +10,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Instructions": { "Block1": { diff --git a/unittests/InstructionCountCI/FlagM/x87.json b/unittests/InstructionCountCI/FlagM/x87.json index 47ecb9f2c..156507033 100644 --- a/unittests/InstructionCountCI/FlagM/x87.json +++ b/unittests/InstructionCountCI/FlagM/x87.json @@ -11,7 +11,7 @@ "CSSC", "AFP" ], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Instructions": { "fadd dword [rax]": { diff --git a/unittests/InstructionCountCI/FlagM/x87_f64-Crysis2Max-fmodel.json b/unittests/InstructionCountCI/FlagM/x87_f64-Crysis2Max-fmodel.json index 3572774f6..3a82f80f4 100644 --- a/unittests/InstructionCountCI/FlagM/x87_f64-Crysis2Max-fmodel.json +++ b/unittests/InstructionCountCI/FlagM/x87_f64-Crysis2Max-fmodel.json @@ -13,7 +13,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Instructions": { "Block1": { diff --git a/unittests/InstructionCountCI/FlagM/x87_f64-HalfLife.json b/unittests/InstructionCountCI/FlagM/x87_f64-HalfLife.json index 26f24fecd..7f56b2eb4 100644 --- a/unittests/InstructionCountCI/FlagM/x87_f64-HalfLife.json +++ b/unittests/InstructionCountCI/FlagM/x87_f64-HalfLife.json @@ -13,7 +13,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Instructions": { "Block1": { diff --git a/unittests/InstructionCountCI/FlagM/x87_f64-Oblivion.json b/unittests/InstructionCountCI/FlagM/x87_f64-Oblivion.json index 5f74c5fed..111d5f8ae 100644 --- a/unittests/InstructionCountCI/FlagM/x87_f64-Oblivion.json +++ b/unittests/InstructionCountCI/FlagM/x87_f64-Oblivion.json @@ -13,7 +13,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Instructions": { "Block1": { diff --git a/unittests/InstructionCountCI/FlagM/x87_f64-Psychonauts.json b/unittests/InstructionCountCI/FlagM/x87_f64-Psychonauts.json index 707c6f063..46e9ea7c8 100644 --- a/unittests/InstructionCountCI/FlagM/x87_f64-Psychonauts.json +++ b/unittests/InstructionCountCI/FlagM/x87_f64-Psychonauts.json @@ -13,7 +13,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Instructions": { "Block1": { diff --git a/unittests/InstructionCountCI/FlagM/x87_f64.json b/unittests/InstructionCountCI/FlagM/x87_f64.json index 98d6f7514..8d069ce56 100644 --- a/unittests/InstructionCountCI/FlagM/x87_f64.json +++ b/unittests/InstructionCountCI/FlagM/x87_f64.json @@ -13,7 +13,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Instructions": { "fadd dword [rax]": { diff --git a/unittests/InstructionCountCI/H0F38.json b/unittests/InstructionCountCI/H0F38.json index f655aa220..5dd3d0e64 100644 --- a/unittests/InstructionCountCI/H0F38.json +++ b/unittests/InstructionCountCI/H0F38.json @@ -10,7 +10,7 @@ "FLAGM2", "CRYPTO" ], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Instructions": { "pshufb mm0, mm1": { diff --git a/unittests/InstructionCountCI/H0F3A.json b/unittests/InstructionCountCI/H0F3A.json index 5211f2542..ea90b11af 100644 --- a/unittests/InstructionCountCI/H0F3A.json +++ b/unittests/InstructionCountCI/H0F3A.json @@ -8,7 +8,7 @@ "AFP", "CRYPTO" ], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Comment": [ "SSE4.2 string instructions are skipped here.", diff --git a/unittests/InstructionCountCI/H0F3A_SVE128.json b/unittests/InstructionCountCI/H0F3A_SVE128.json index b64ede10e..55accf205 100644 --- a/unittests/InstructionCountCI/H0F3A_SVE128.json +++ b/unittests/InstructionCountCI/H0F3A_SVE128.json @@ -8,7 +8,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Instructions": { "dpps xmm0, xmm1, 00000000b": { diff --git a/unittests/InstructionCountCI/MOPS/Primary.json b/unittests/InstructionCountCI/MOPS/Primary.json index bd891fc43..58eefc894 100644 --- a/unittests/InstructionCountCI/MOPS/Primary.json +++ b/unittests/InstructionCountCI/MOPS/Primary.json @@ -11,7 +11,7 @@ "FLAGM", "FLAGM2" ], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Instructions": { "rep movsb": { diff --git a/unittests/InstructionCountCI/Primary.json b/unittests/InstructionCountCI/Primary.json index 473e4e586..609685bba 100644 --- a/unittests/InstructionCountCI/Primary.json +++ b/unittests/InstructionCountCI/Primary.json @@ -10,7 +10,7 @@ "FLAGM2", "MOPS" ], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Instructions": { "add bl, cl": { diff --git a/unittests/InstructionCountCI/PrimaryGroup.json b/unittests/InstructionCountCI/PrimaryGroup.json index 60c4a602d..054fea7c4 100644 --- a/unittests/InstructionCountCI/PrimaryGroup.json +++ b/unittests/InstructionCountCI/PrimaryGroup.json @@ -9,7 +9,7 @@ "FLAGM", "FLAGM2" ], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Comment": [ "Instructions in this table that are marked optimal don't have their flag calculation part of this assumption", diff --git a/unittests/InstructionCountCI/Primary_32Bit.json b/unittests/InstructionCountCI/Primary_32Bit.json index e1fb7b966..5150ff837 100644 --- a/unittests/InstructionCountCI/Primary_32Bit.json +++ b/unittests/InstructionCountCI/Primary_32Bit.json @@ -9,7 +9,7 @@ "FlagM", "FlagM2" ], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Instructions": { "push es": { diff --git a/unittests/InstructionCountCI/RPRES/DDD.json b/unittests/InstructionCountCI/RPRES/DDD.json index 74c4edba0..2c01a7dca 100644 --- a/unittests/InstructionCountCI/RPRES/DDD.json +++ b/unittests/InstructionCountCI/RPRES/DDD.json @@ -9,7 +9,7 @@ "SVE128", "SVE256" ], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Instructions": { "pfrcpv mm0, mm1": { diff --git a/unittests/InstructionCountCI/RPRES/Secondary.json b/unittests/InstructionCountCI/RPRES/Secondary.json index aee8c8527..55a145542 100644 --- a/unittests/InstructionCountCI/RPRES/Secondary.json +++ b/unittests/InstructionCountCI/RPRES/Secondary.json @@ -9,7 +9,7 @@ "SVE128", "SVE256" ], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Instructions": { "rsqrtps xmm0, xmm1": { diff --git a/unittests/InstructionCountCI/RPRES/Secondary_REP_AFP.json b/unittests/InstructionCountCI/RPRES/Secondary_REP_AFP.json index 4a4df0b07..709d63355 100644 --- a/unittests/InstructionCountCI/RPRES/Secondary_REP_AFP.json +++ b/unittests/InstructionCountCI/RPRES/Secondary_REP_AFP.json @@ -9,7 +9,7 @@ "SVE128", "SVE256" ], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Instructions": { "rsqrtss xmm0, xmm1": { diff --git a/unittests/InstructionCountCI/RPRES/VEX_map1_AFP.json b/unittests/InstructionCountCI/RPRES/VEX_map1_AFP.json index 9af3996f8..c0cd12210 100644 --- a/unittests/InstructionCountCI/RPRES/VEX_map1_AFP.json +++ b/unittests/InstructionCountCI/RPRES/VEX_map1_AFP.json @@ -8,7 +8,7 @@ "AFP" ], "DisabledHostFeatures": [], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Instructions": { "vrsqrtps xmm0, xmm1": { diff --git a/unittests/InstructionCountCI/Repeat.json b/unittests/InstructionCountCI/Repeat.json index c3a1b9ad2..21ecf74e8 100644 --- a/unittests/InstructionCountCI/Repeat.json +++ b/unittests/InstructionCountCI/Repeat.json @@ -6,7 +6,7 @@ "SVE128", "SVE256" ], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Instructions": {} } diff --git a/unittests/InstructionCountCI/SSE42_Strings.json b/unittests/InstructionCountCI/SSE42_Strings.json index c3188bb63..78727d55a 100644 --- a/unittests/InstructionCountCI/SSE42_Strings.json +++ b/unittests/InstructionCountCI/SSE42_Strings.json @@ -33,7 +33,7 @@ " - 1b: ECX = MSB", "[7] - Reserved" ], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Instructions": { "pcmpestrm xmm0, xmm1, 0_0_00_00_00b": { diff --git a/unittests/InstructionCountCI/Secondary.json b/unittests/InstructionCountCI/Secondary.json index 765571dc0..ff4e0dc6f 100644 --- a/unittests/InstructionCountCI/Secondary.json +++ b/unittests/InstructionCountCI/Secondary.json @@ -12,7 +12,7 @@ "FLAGM", "FLAGM2" ], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Comment": [ "MMX instructions are defined as optimal without SRA being used for these instructions.", diff --git a/unittests/InstructionCountCI/SecondaryGroup.json b/unittests/InstructionCountCI/SecondaryGroup.json index 4a020937c..58aec9701 100644 --- a/unittests/InstructionCountCI/SecondaryGroup.json +++ b/unittests/InstructionCountCI/SecondaryGroup.json @@ -11,7 +11,7 @@ "FLAGM", "FLAGM2" ], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Instructions": { "sgdt [rax]": { diff --git a/unittests/InstructionCountCI/SecondaryModRM.json b/unittests/InstructionCountCI/SecondaryModRM.json index 0aecff61e..0f57ae274 100644 --- a/unittests/InstructionCountCI/SecondaryModRM.json +++ b/unittests/InstructionCountCI/SecondaryModRM.json @@ -11,7 +11,7 @@ "FLAGM", "FLAGM2" ], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Instructions": { "xgetbv": { diff --git a/unittests/InstructionCountCI/Secondary_32Bit.json b/unittests/InstructionCountCI/Secondary_32Bit.json index db4c5ba75..eedc3c9fe 100644 --- a/unittests/InstructionCountCI/Secondary_32Bit.json +++ b/unittests/InstructionCountCI/Secondary_32Bit.json @@ -7,7 +7,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Instructions": { "push fs": { diff --git a/unittests/InstructionCountCI/Secondary_OpSize.json b/unittests/InstructionCountCI/Secondary_OpSize.json index 13faf6765..d13dc64be 100644 --- a/unittests/InstructionCountCI/Secondary_OpSize.json +++ b/unittests/InstructionCountCI/Secondary_OpSize.json @@ -12,7 +12,7 @@ "FLAGM", "FLAGM2" ], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Instructions": { "movupd xmm0, xmm0": { diff --git a/unittests/InstructionCountCI/Secondary_OpSize_FCMA.json b/unittests/InstructionCountCI/Secondary_OpSize_FCMA.json index 30c8d22a8..608249ec8 100644 --- a/unittests/InstructionCountCI/Secondary_OpSize_FCMA.json +++ b/unittests/InstructionCountCI/Secondary_OpSize_FCMA.json @@ -9,7 +9,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Instructions": { "addsubpd xmm0, xmm1": { diff --git a/unittests/InstructionCountCI/Secondary_OpSize_SVE128.json b/unittests/InstructionCountCI/Secondary_OpSize_SVE128.json index 2c02a12e9..f80570fe5 100644 --- a/unittests/InstructionCountCI/Secondary_OpSize_SVE128.json +++ b/unittests/InstructionCountCI/Secondary_OpSize_SVE128.json @@ -8,7 +8,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Instructions": { "psrlw xmm0, xmm1": { diff --git a/unittests/InstructionCountCI/Secondary_OpSize_SVE256.json b/unittests/InstructionCountCI/Secondary_OpSize_SVE256.json index c6b9c8dbe..fe4eca349 100644 --- a/unittests/InstructionCountCI/Secondary_OpSize_SVE256.json +++ b/unittests/InstructionCountCI/Secondary_OpSize_SVE256.json @@ -7,7 +7,7 @@ "AFP" ], "DisabledHostFeatures": [], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Instructions": { "pmulhuw xmm0, xmm1": { diff --git a/unittests/InstructionCountCI/Secondary_REP.json b/unittests/InstructionCountCI/Secondary_REP.json index 03ae59a6e..3a1845e17 100644 --- a/unittests/InstructionCountCI/Secondary_REP.json +++ b/unittests/InstructionCountCI/Secondary_REP.json @@ -12,7 +12,7 @@ "FRINTTS", "CSSC" ], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Instructions": { "movss xmm0, xmm1": { diff --git a/unittests/InstructionCountCI/Secondary_REPNE.json b/unittests/InstructionCountCI/Secondary_REPNE.json index 5b2f9c194..6dd4d31c9 100644 --- a/unittests/InstructionCountCI/Secondary_REPNE.json +++ b/unittests/InstructionCountCI/Secondary_REPNE.json @@ -10,7 +10,7 @@ "FCMA", "AFP" ], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Instructions": { "movsd xmm0, xmm1": { diff --git a/unittests/InstructionCountCI/Secondary_REPNE_FCMA.json b/unittests/InstructionCountCI/Secondary_REPNE_FCMA.json index 3f89fa66a..0c7326975 100644 --- a/unittests/InstructionCountCI/Secondary_REPNE_FCMA.json +++ b/unittests/InstructionCountCI/Secondary_REPNE_FCMA.json @@ -9,7 +9,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Instructions": { "addsubps xmm0, xmm1": { diff --git a/unittests/InstructionCountCI/Secondary_REPNE_SVE128.json b/unittests/InstructionCountCI/Secondary_REPNE_SVE128.json index 7e8416c2a..99a297998 100644 --- a/unittests/InstructionCountCI/Secondary_REPNE_SVE128.json +++ b/unittests/InstructionCountCI/Secondary_REPNE_SVE128.json @@ -10,7 +10,7 @@ "FCMA", "AFP" ], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Instructions": { "cvtpd2dq xmm0, xmm1": { diff --git a/unittests/InstructionCountCI/Secondary_REP_FRINTTS.json b/unittests/InstructionCountCI/Secondary_REP_FRINTTS.json index 440a7bd6b..7e14bbb75 100644 --- a/unittests/InstructionCountCI/Secondary_REP_FRINTTS.json +++ b/unittests/InstructionCountCI/Secondary_REP_FRINTTS.json @@ -12,7 +12,7 @@ "FLAGM", "FLAGM2" ], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Instructions": { "cvttss2si eax, xmm0": { diff --git a/unittests/InstructionCountCI/Secondary_SVE128.json b/unittests/InstructionCountCI/Secondary_SVE128.json index b2460c416..7e53b0b66 100644 --- a/unittests/InstructionCountCI/Secondary_SVE128.json +++ b/unittests/InstructionCountCI/Secondary_SVE128.json @@ -8,7 +8,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Instructions": { "movmskps eax, xmm0": { diff --git a/unittests/InstructionCountCI/VEX_map1.json b/unittests/InstructionCountCI/VEX_map1.json index 6e39615f9..a32427da0 100644 --- a/unittests/InstructionCountCI/VEX_map1.json +++ b/unittests/InstructionCountCI/VEX_map1.json @@ -13,7 +13,7 @@ "FLAGM2", "FRINTTS" ], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Instructions": { "vmovups xmm0, xmm0": { diff --git a/unittests/InstructionCountCI/VEX_map1_FCMA.json b/unittests/InstructionCountCI/VEX_map1_FCMA.json index 5a201db16..55661b97f 100644 --- a/unittests/InstructionCountCI/VEX_map1_FCMA.json +++ b/unittests/InstructionCountCI/VEX_map1_FCMA.json @@ -8,7 +8,7 @@ "FCMA" ], "DisabledHostFeatures": [], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Instructions": { "vaddsubpd xmm0, xmm1, xmm2": { diff --git a/unittests/InstructionCountCI/VEX_map1_FRINTTS.json b/unittests/InstructionCountCI/VEX_map1_FRINTTS.json index 1727b4f95..3a20de988 100644 --- a/unittests/InstructionCountCI/VEX_map1_FRINTTS.json +++ b/unittests/InstructionCountCI/VEX_map1_FRINTTS.json @@ -13,7 +13,7 @@ "FLAGM", "FLAGM2" ], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Instructions": { "vcvttss2si eax, xmm0": { diff --git a/unittests/InstructionCountCI/VEX_map2.json b/unittests/InstructionCountCI/VEX_map2.json index 6e5cec6dc..7cc63fcb5 100644 --- a/unittests/InstructionCountCI/VEX_map2.json +++ b/unittests/InstructionCountCI/VEX_map2.json @@ -11,7 +11,7 @@ "FLAGM2", "SVEBITPERM" ], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Instructions": { "vpshufb xmm0, xmm1, xmm2": { diff --git a/unittests/InstructionCountCI/VEX_map2_svebitperm.json b/unittests/InstructionCountCI/VEX_map2_svebitperm.json index 6bcd770ed..ebe8b4023 100644 --- a/unittests/InstructionCountCI/VEX_map2_svebitperm.json +++ b/unittests/InstructionCountCI/VEX_map2_svebitperm.json @@ -11,7 +11,7 @@ "FLAGM", "FLAGM2" ], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Instructions": { "pext eax, ebx, ecx": { diff --git a/unittests/InstructionCountCI/VEX_map3.json b/unittests/InstructionCountCI/VEX_map3.json index c3717347d..7bea2dbc1 100644 --- a/unittests/InstructionCountCI/VEX_map3.json +++ b/unittests/InstructionCountCI/VEX_map3.json @@ -8,7 +8,7 @@ "DisabledHostFeatures": [ "AFP" ], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Instructions": { "vpermq ymm0, ymm1, 1": { diff --git a/unittests/InstructionCountCI/VEX_map_group.json b/unittests/InstructionCountCI/VEX_map_group.json index 9c4c247dc..87954025b 100644 --- a/unittests/InstructionCountCI/VEX_map_group.json +++ b/unittests/InstructionCountCI/VEX_map_group.json @@ -9,7 +9,7 @@ "FLAGM", "FLAGM2" ], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Instructions": { "vpsrlw xmm0, xmm1, 0": { diff --git a/unittests/InstructionCountCI/X87ldst-SVE.json b/unittests/InstructionCountCI/X87ldst-SVE.json index 00112a468..7f0083c9e 100644 --- a/unittests/InstructionCountCI/X87ldst-SVE.json +++ b/unittests/InstructionCountCI/X87ldst-SVE.json @@ -11,7 +11,7 @@ "FLAGM2", "RPRES" ], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Instructions": { "fstp tword [rax]": { diff --git a/unittests/InstructionCountCI/x87.json b/unittests/InstructionCountCI/x87.json index 086e1e108..43d8499d0 100644 --- a/unittests/InstructionCountCI/x87.json +++ b/unittests/InstructionCountCI/x87.json @@ -10,7 +10,7 @@ "FLAGM", "FLAGM2" ], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Instructions": { "fadd dword [rax]": { diff --git a/unittests/InstructionCountCI/x87_32Bit.json b/unittests/InstructionCountCI/x87_32Bit.json index 78b86011d..5a7088503 100644 --- a/unittests/InstructionCountCI/x87_32Bit.json +++ b/unittests/InstructionCountCI/x87_32Bit.json @@ -10,7 +10,7 @@ "FLAGM", "FLAGM2" ], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Instructions": { "Multiple fld/fst": { diff --git a/unittests/InstructionCountCI/x87_f64.json b/unittests/InstructionCountCI/x87_f64.json index 70e152f11..c29a09a63 100644 --- a/unittests/InstructionCountCI/x87_f64.json +++ b/unittests/InstructionCountCI/x87_f64.json @@ -12,7 +12,7 @@ "FLAGM", "FLAGM2" ], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Instructions": { "fadd dword [rax]": { diff --git a/unittests/InstructionCountCI/x87_f64_32Bit.json b/unittests/InstructionCountCI/x87_f64_32Bit.json index bc12b358a..7d17a074a 100644 --- a/unittests/InstructionCountCI/x87_f64_32Bit.json +++ b/unittests/InstructionCountCI/x87_f64_32Bit.json @@ -15,7 +15,7 @@ "SVE256", "CSSC" ], - "BinaryCacheVersion": 16 + "BinaryCacheVersion": 17 }, "Instructions": { "fstp dword [ebx*4+0x204a20]": {