From 428111b44b5e59d12757450c00956cdf33fcbef7 Mon Sep 17 00:00:00 2001
From: Stefanos Kornilios Mitsis Poiitidis <stef@skmp.dev>
Date: Fri, 12 Feb 2021 00:31:10 +0200
Subject: [PATCH] JIT/arm64: fallback support

---
 .../Interface/Core/JIT/Arm64/ALUOps.cpp       |   5 -
 .../Source/Interface/Core/JIT/Arm64/JIT.cpp   | 240 +++++++++++++++++-
 .../Interface/Core/JIT/Arm64/JITClass.h       |   1 -
 3 files changed, 238 insertions(+), 8 deletions(-)

diff --git a/External/FEXCore/Source/Interface/Core/JIT/Arm64/ALUOps.cpp b/External/FEXCore/Source/Interface/Core/JIT/Arm64/ALUOps.cpp
index f0da42c41..ca8b1f5f8 100644
--- a/External/FEXCore/Source/Interface/Core/JIT/Arm64/ALUOps.cpp
+++ b/External/FEXCore/Source/Interface/Core/JIT/Arm64/ALUOps.cpp
@@ -1043,10 +1043,6 @@ DEF_OP(FCmp) {
   }
 }
 
-DEF_OP(F80Cmp) {
-  LogMan::Msg::D("Unimplemented");
-}
-
 #undef DEF_OP
 
 void JITCore::RegisterALUHandlers() {
@@ -1095,7 +1091,6 @@ void JITCore::RegisterALUHandlers() {
   REGISTER_OP(FLOAT_TOGPR_U,     Float_ToGPR_U);
   REGISTER_OP(FLOAT_TOGPR_S,     Float_ToGPR_S);
   REGISTER_OP(FCMP,              FCmp);
-  REGISTER_OP(F80CMP,            F80Cmp);
 
 #undef REGISTER_OP
 }
diff --git a/External/FEXCore/Source/Interface/Core/JIT/Arm64/JIT.cpp b/External/FEXCore/Source/Interface/Core/JIT/Arm64/JIT.cpp
index ac46e2aa2..11a1a7b3e 100644
--- a/External/FEXCore/Source/Interface/Core/JIT/Arm64/JIT.cpp
+++ b/External/FEXCore/Source/Interface/Core/JIT/Arm64/JIT.cpp
@@ -40,8 +40,244 @@ using namespace vixl;
 using namespace vixl::aarch64;
 
 void JITCore::Op_Unhandled(FEXCore::IR::IROp_Header *IROp, uint32_t Node) {
-  auto Name = FEXCore::IR::GetName(IROp->Op);
-  LogMan::Msg::A("Unhandled IR Op: %s", std::string(Name).c_str());
+  FallbackInfo Info;
+  if (!InterpreterOps::GetFallbackHandler(IROp, &Info)) {
+    auto Name = FEXCore::IR::GetName(IROp->Op);
+    LogMan::Msg::A("Unhandled IR Op: %s", std::string(Name).c_str());
+  } else {
+    switch(Info.ABI) {
+      case FABI_F80_F32:{
+        SpillStaticRegs();
+
+        PushDynamicRegsAndLR();
+
+        fmov(v0.S(), GetSrc(IROp->Args[0].ID()).S()) ;
+        LoadConstant(x0, (uintptr_t)Info.fn);
+
+        blr(x0);
+
+        PopDynamicRegsAndLR();
+  
+        FillStaticRegs();
+
+        eor(GetDst(Node).V16B(), GetDst(Node).V16B(), GetDst(Node).V16B());
+        ins(GetDst(Node).V2D(), 0, x0);
+        ins(GetDst(Node).V8H(), 4, w1);
+      }
+      break;
+
+      case FABI_F80_F64:{
+        SpillStaticRegs();
+
+        PushDynamicRegsAndLR();
+
+        mov(v0.D(), GetSrc(IROp->Args[0].ID()).D());
+        LoadConstant(x0, (uintptr_t)Info.fn);
+
+        blr(x0);
+
+        PopDynamicRegsAndLR();
+  
+        FillStaticRegs();
+
+        eor(GetDst(Node).V16B(), GetDst(Node).V16B(), GetDst(Node).V16B());
+        ins(GetDst(Node).V2D(), 0, x0);
+        ins(GetDst(Node).V8H(), 4, w1);
+      }
+      break;
+
+      case FABI_F80_I16:
+      case FABI_F80_I32: {
+        SpillStaticRegs();
+
+        PushDynamicRegsAndLR();
+
+        mov(w0, GetReg<RA_32>(IROp->Args[0].ID()));
+        LoadConstant(x1, (uintptr_t)Info.fn);
+
+        blr(x1);
+
+        PopDynamicRegsAndLR();
+  
+        FillStaticRegs();
+
+        eor(GetDst(Node).V16B(), GetDst(Node).V16B(), GetDst(Node).V16B());
+        ins(GetDst(Node).V2D(), 0, x0);
+        ins(GetDst(Node).V8H(), 4, w1);
+      }
+      break;
+
+      case FABI_F32_F80:{
+        SpillStaticRegs();
+
+        PushDynamicRegsAndLR();
+
+        umov(x0, GetSrc(IROp->Args[0].ID()).V2D(), 0);
+        umov(x1, GetSrc(IROp->Args[0].ID()).V2D(), 1);
+
+        LoadConstant(x2, (uintptr_t)Info.fn);
+
+        blr(x2);
+
+        PopDynamicRegsAndLR();
+  
+        FillStaticRegs();
+
+        fmov(GetDst(Node).S(), v0.S());
+      }
+      break;
+
+      case FABI_F64_F80:{
+        SpillStaticRegs();
+
+        PushDynamicRegsAndLR();
+
+        umov(x0, GetSrc(IROp->Args[0].ID()).V2D(), 0);
+        umov(x1, GetSrc(IROp->Args[0].ID()).V2D(), 1);
+
+        LoadConstant(x2, (uintptr_t)Info.fn);
+
+        blr(x2);
+
+        PopDynamicRegsAndLR();
+  
+        FillStaticRegs();
+
+        mov(GetDst(Node).D(), v0.D());
+      }
+      break;
+
+      case FABI_I16_F80:{
+        SpillStaticRegs();
+
+        PushDynamicRegsAndLR();
+
+        umov(x0, GetSrc(IROp->Args[0].ID()).V2D(), 0);
+        umov(x1, GetSrc(IROp->Args[0].ID()).V2D(), 1);
+
+        LoadConstant(x2, (uintptr_t)Info.fn);
+
+        blr(x2);
+
+        PopDynamicRegsAndLR();
+  
+        FillStaticRegs();
+
+        uxth(GetReg<RA_64>(Node), x0);
+      }
+      break;
+      case FABI_I32_F80:{
+        SpillStaticRegs();
+
+        PushDynamicRegsAndLR();
+
+        umov(x0, GetSrc(IROp->Args[0].ID()).V2D(), 0);
+        umov(x1, GetSrc(IROp->Args[0].ID()).V2D(), 1);
+
+        LoadConstant(x2, (uintptr_t)Info.fn);
+
+        blr(x2);
+
+        PopDynamicRegsAndLR();
+  
+        FillStaticRegs();
+
+        mov(GetReg<RA_32>(Node), w0);
+      }
+      break;
+      case FABI_I64_F80:{
+        SpillStaticRegs();
+
+        PushDynamicRegsAndLR();
+
+        umov(x0, GetSrc(IROp->Args[0].ID()).V2D(), 0);
+        umov(x1, GetSrc(IROp->Args[0].ID()).V2D(), 1);
+
+        LoadConstant(x2, (uintptr_t)Info.fn);
+
+        blr(x2);
+
+        PopDynamicRegsAndLR();
+  
+        FillStaticRegs();
+
+        mov(GetReg<RA_64>(Node), x0);
+      }
+      break;
+      case FABI_I64_F80_F80:{
+        SpillStaticRegs();
+
+        PushDynamicRegsAndLR();
+
+        umov(x0, GetSrc(IROp->Args[0].ID()).V2D(), 0);
+        umov(x1, GetSrc(IROp->Args[0].ID()).V2D(), 1);
+
+        umov(x2, GetSrc(IROp->Args[1].ID()).V2D(), 0);
+        umov(x3, GetSrc(IROp->Args[1].ID()).V2D(), 1);
+        
+        LoadConstant(x4, (uintptr_t)Info.fn);
+
+        blr(x4);
+
+        PopDynamicRegsAndLR();
+  
+        FillStaticRegs();
+
+        mov(GetReg<RA_64>(Node), x0);
+      }
+      break;
+      case FABI_F80_F80:{
+        SpillStaticRegs();
+
+        PushDynamicRegsAndLR();
+
+        umov(x0, GetSrc(IROp->Args[0].ID()).V2D(), 0);
+        umov(x1, GetSrc(IROp->Args[0].ID()).V2D(), 1);
+        
+        LoadConstant(x2, (uintptr_t)Info.fn);
+
+        blr(x2);
+
+        PopDynamicRegsAndLR();
+  
+        FillStaticRegs();
+
+        eor(GetDst(Node).V16B(), GetDst(Node).V16B(), GetDst(Node).V16B());
+        ins(GetDst(Node).V2D(), 0, x0);
+        ins(GetDst(Node).V8H(), 4, w1);
+      }
+      break;
+      case FABI_F80_F80_F80:{
+        SpillStaticRegs();
+
+        PushDynamicRegsAndLR();
+
+        umov(x0, GetSrc(IROp->Args[0].ID()).V2D(), 0);
+        umov(x1, GetSrc(IROp->Args[0].ID()).V2D(), 1);
+
+        umov(x2, GetSrc(IROp->Args[1].ID()).V2D(), 0);
+        umov(x3, GetSrc(IROp->Args[1].ID()).V2D(), 1);
+        
+        LoadConstant(x4, (uintptr_t)Info.fn);
+
+        blr(x4);
+
+        PopDynamicRegsAndLR();
+  
+        FillStaticRegs();
+
+        eor(GetDst(Node).V16B(), GetDst(Node).V16B(), GetDst(Node).V16B());
+        ins(GetDst(Node).V2D(), 0, x0);
+        ins(GetDst(Node).V8H(), 4, w1);
+      }
+      break;
+
+      case FABI_UNKNOWN:
+      default:
+      auto Name = FEXCore::IR::GetName(IROp->Op);
+        LogMan::Msg::A("Unhandled IR Fallback abi: %s %d", std::string(Name).c_str(), Info.ABI);
+    }
+  }
 }
 
 void JITCore::Op_NoOp(FEXCore::IR::IROp_Header *IROp, uint32_t Node) {
diff --git a/External/FEXCore/Source/Interface/Core/JIT/Arm64/JITClass.h b/External/FEXCore/Source/Interface/Core/JIT/Arm64/JITClass.h
index 388ad8963..537ff67f8 100644
--- a/External/FEXCore/Source/Interface/Core/JIT/Arm64/JITClass.h
+++ b/External/FEXCore/Source/Interface/Core/JIT/Arm64/JITClass.h
@@ -311,7 +311,6 @@ private:
   DEF_OP(Float_ToGPR_U);
   DEF_OP(Float_ToGPR_S);
   DEF_OP(FCmp);
-  DEF_OP(F80Cmp);
 
   ///< Atomic ops
   DEF_OP(CASPair);