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OpcodeDispatcher: better handle SIB indexing

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if we have shift and a constant, we can save an instruction

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
This commit is contained in:
Alyssa Rosenzweig committed 2024-08-13 08:41:16 -04:00
1 parent 3429321d59
commit 40812efaae
1 file changed
+5 -7
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FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
+5 -7
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@@ -4298,18 +4298,16 @@ AddressMode OpDispatchBuilder::SelectAddressMode(AddressMode A, bool AtomicTSO,
//
// TODO: Also handle GPR TSO if we can guarantee the constant inlines.
if (SupportsRegIndex) {
if ((A.Base || A.Segment) && A.Offset && !A.Index) {
if ((A.Base || A.Segment) && A.Offset) {
const bool Const_16K = A.Offset > -16384 && A.Offset < 16384 && A.AddrSize == 4 && GPRSize == 4;
if ((A.AddrSize == 8) || Const_16K) {
if (A.Base && A.Segment) {
A.Base = _Add(IR::SizeToOpSize(GPRSize), A.Base, A.Segment);
} else if (A.Segment) {
A.Base = A.Segment;
}
// Peel off the offset
AddressMode B = A;
B.Offset = 0;
return {
.Base = A.Base,
.Base = LoadEffectiveAddress(B, true /* AddSegmentBase */, false),
.Index = _Constant(A.Offset),
.IndexType = MEM_OFFSET_SXTX,
.IndexScale = 1,