diff --git a/External/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/SVEOps.inl b/External/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/SVEOps.inl
index 63a0fa99f..128bba1eb 100644
--- a/External/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/SVEOps.inl
+++ b/External/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/SVEOps.inl
@@ -732,31 +732,31 @@ public:
     LOGMAN_THROW_A_FMT(size == SubRegSize::i8Bit || size == SubRegSize::i16Bit || size == SubRegSize::i32Bit,
                        "saddv may only use 8-bit, 16-bit, or 32-bit elements.");
     constexpr uint32_t Op = 0b0000'0100'0000'0000'0010'0000'0000'0000;
-    SVEReductionOperation(Op, 0b00, size, vd, pg, zn);
+    SVEIntegerReductionOperation(Op, 0b00, size, vd, pg, zn);
   }
   void uaddv(SubRegSize size, DRegister vd, PRegister pg, ZRegister zn) {
     LOGMAN_THROW_A_FMT(size == SubRegSize::i8Bit || size == SubRegSize::i16Bit || size == SubRegSize::i32Bit,
                        "uaddv may only use 8-bit, 16-bit, or 32-bit elements.");
     constexpr uint32_t Op = 0b0000'0100'0000'0000'0010'0000'0000'0000;
-    SVEReductionOperation(Op, 0b01, size, vd, pg, zn);
+    SVEIntegerReductionOperation(Op, 0b01, size, vd, pg, zn);
   }
 
   // SVE integer min/max reduction (predicated)
   void smaxv(SubRegSize size, VRegister vd, PRegister pg, ZRegister zn) {
     constexpr uint32_t Op = 0b0000'0100'0000'1000'001 << 13;
-    SVEReductionOperation(Op, 0b00, size, vd, pg, zn);
+    SVEIntegerReductionOperation(Op, 0b00, size, vd, pg, zn);
   }
   void umaxv(SubRegSize size, VRegister vd, PRegister pg, ZRegister zn) {
     constexpr uint32_t Op = 0b0000'0100'0000'1000'001 << 13;
-    SVEReductionOperation(Op, 0b01, size, vd, pg, zn);
+    SVEIntegerReductionOperation(Op, 0b01, size, vd, pg, zn);
   }
   void sminv(SubRegSize size, VRegister vd, PRegister pg, ZRegister zn) {
     constexpr uint32_t Op = 0b0000'0100'0000'1000'001 << 13;
-    SVEReductionOperation(Op, 0b10, size, vd, pg, zn);
+    SVEIntegerReductionOperation(Op, 0b10, size, vd, pg, zn);
   }
   void uminv(SubRegSize size, VRegister vd, PRegister pg, ZRegister zn) {
     constexpr uint32_t Op = 0b0000'0100'0000'1000'001 << 13;
-    SVEReductionOperation(Op, 0b11, size, vd, pg, zn);
+    SVEIntegerReductionOperation(Op, 0b11, size, vd, pg, zn);
   }
 
   // SVE constructive prefix (predicated)
@@ -772,15 +772,15 @@ public:
   // SVE bitwise logical reduction (predicated)
   void orv(SubRegSize size, VRegister vd, PRegister pg, ZRegister zn) {
     constexpr uint32_t Op = 0b0000'0100'0001'1000'0010'0000'0000'0000;
-    SVEReductionOperation(Op, 0b00, size, vd, pg, zn);
+    SVEIntegerReductionOperation(Op, 0b00, size, vd, pg, zn);
   }
   void eorv(SubRegSize size, VRegister vd, PRegister pg, ZRegister zn) {
     constexpr uint32_t Op = 0b0000'0100'0001'1000'0010'0000'0000'0000;
-    SVEReductionOperation(Op, 0b01, size, vd, pg, zn);
+    SVEIntegerReductionOperation(Op, 0b01, size, vd, pg, zn);
   }
   void andv(SubRegSize size, VRegister vd, PRegister pg, ZRegister zn) {
     constexpr uint32_t Op = 0b0000'0100'0001'1000'0010'0000'0000'0000;
-    SVEReductionOperation(Op, 0b10, size, vd, pg, zn);
+    SVEIntegerReductionOperation(Op, 0b10, size, vd, pg, zn);
   }
 
   // SVE Bitwise Shift - Predicated
@@ -4042,7 +4042,7 @@ private:
     dc32(Instr);
   }
 
-  void SVEReductionOperation(uint32_t op, uint32_t opc, SubRegSize size, VRegister vd, PRegister pg, ZRegister zn) {
+  void SVEIntegerReductionOperation(uint32_t op, uint32_t opc, SubRegSize size, VRegister vd, PRegister pg, ZRegister zn) {
     LOGMAN_THROW_AA_FMT(size != SubRegSize::i128Bit, "Can't use 128-bit element size for reduction operation");
     LOGMAN_THROW_AA_FMT(pg <= PReg::p7, "Integer reduction operation can only use p0-p7 as a governing predicate");