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Merge pull request #3178 from Sonicadvance1/fix_avx_alias_precolour

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Minor AVX optimizations
This commit is contained in:
Mai authored and GitHub committed 2023-10-04 21:31:20 -04:00
2 parents 507cf82dad a408afaeb0
commit 3ba1c7912c
9 files changed
+5488 -7465
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FEXCore/Source/Interface/Core/JIT/Arm64/VectorOps.cpp
+2 -2
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@@ -3551,7 +3551,7 @@ DEF_OP(VSRSHR) {
if (Dst != Vector) {
movprfx(Dst.Z(), Vector.Z());
}
srshr(SubRegSize, Dst.Z(), Mask, Vector.Z(), BitShift);
srshr(SubRegSize, Dst.Z(), Mask, Dst.Z(), BitShift);
} else {
if (OpSize == 8) {
srshr(SubRegSize, Dst.D(), Vector.D(), BitShift);
@@ -3587,7 +3587,7 @@ DEF_OP(VSQSHL) {
if (Dst != Vector) {
movprfx(Dst.Z(), Vector.Z());
}
sqshl(SubRegSize, Dst.Z(), Mask, Vector.Z(), BitShift);
sqshl(SubRegSize, Dst.Z(), Mask, Dst.Z(), BitShift);
} else {
if (OpSize == 8) {
sqshl(SubRegSize, Dst.D(), Vector.D(), BitShift);
FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp
+3 -2
View File
@@ -4803,8 +4803,9 @@ void OpDispatchBuilder::VZEROOp(OpcodeArgs) {
// NOTE: Despite the name being VZEROALL, this will still only ever
// zero out up to the first 16 registers (even on AVX-512, where we have 32 registers)
OrderedNode* ZeroVector = LoadAndCacheNamedVectorConstant(DstSize, FEXCore::IR::NamedVectorConstant::NAMED_VECTOR_ZERO);
for (uint32_t i = 0; i < NumRegs; i++) {
for (uint32_t i = 0; i < NumRegs; i++) {
// Explicitly not caching named vector zero. This ensures that every register gets movi #0.0 directly.
OrderedNode* ZeroVector = _LoadNamedVectorConstant(DstSize, FEXCore::IR::NamedVectorConstant::NAMED_VECTOR_ZERO);
StoreXMMRegister(i, ZeroVector);
}
} else {
FEXCore/Source/Interface/IR/Passes/RegisterAllocationPass.cpp
+6 -3
View File
@@ -474,24 +474,27 @@ namespace {
// Helpers
// Is an OP_STOREREGISTER eligible to write directly to the SRA reg?
auto IsPreWritable = [](uint8_t Size, RegisterClassType StaticClass) {
auto IsPreWritable = [this](uint8_t Size, RegisterClassType StaticClass) {
LOGMAN_THROW_A_FMT(StaticClass == GPRFixedClass || StaticClass == FPRFixedClass, "Unexpected static class {}", StaticClass);
if (StaticClass == GPRFixedClass) {
return Size == 8 || Size == 4;
} else if (StaticClass == FPRFixedClass) {
return Size == 16;
return Size == 16 || (Size == 32 && SupportsAVX);
}
return false; // Unknown
};
// Is an OP_LOADREGISTER eligible to read directly from the SRA reg?
auto IsAliasable = [](uint8_t Size, RegisterClassType StaticClass, uint32_t Offset) {
auto IsAliasable = [this](uint8_t Size, RegisterClassType StaticClass, uint32_t Offset) {
LOGMAN_THROW_A_FMT(StaticClass == GPRFixedClass || StaticClass == FPRFixedClass, "Unexpected static class {}", StaticClass);
if (StaticClass == GPRFixedClass) {
// We need more meta info to support not-size-of-reg
return (Size == 8 || Size == 4) && ((Offset & 7) == 0);
} else if (StaticClass == FPRFixedClass) {
// We need more meta info to support not-size-of-reg
if (Size == 32 && SupportsAVX && (Offset & 31) == 0) {
return true;
}
return (Size == 16 /*|| Size == 8 || Size == 4*/) && ((Offset & 15) == 0);
}
return false; // Unknown
unittests/InstructionCountCI/Secondary_OpSize_SVE256.json
+8 -12
View File
@@ -9,33 +9,29 @@
},
"Instructions": {
"pmulhuw xmm0, xmm1": {
"ExpectedInstructionCount": 5,
"ExpectedInstructionCount": 3,
"Optimal": "No",
"Comment": [
"SVE-256bit changes behaviour slightly",
"0x66 0x0f 0xe4"
],
"ExpectedArm64ASM": [
"mov z2.d, p7/m, z16.d",
"mov z3.d, p7/m, z17.d",
"umulh z2.h, p6/m, z2.h, z3.h",
"mov v2.16b, v2.16b",
"mov z16.d, p7/m, z2.d"
"movprfx z2, z16",
"umulh z2.h, p6/m, z2.h, z17.h",
"mov v16.16b, v2.16b"
]
},
"pmulhw xmm0, xmm1": {
"ExpectedInstructionCount": 5,
"ExpectedInstructionCount": 3,
"Optimal": "No",
"Comment": [
"SVE-256bit changes behaviour slightly",
"0x66 0x0f 0xe5"
],
"ExpectedArm64ASM": [
"mov z2.d, p7/m, z16.d",
"mov z3.d, p7/m, z17.d",
"smulh z2.h, p6/m, z2.h, z3.h",
"mov v2.16b, v2.16b",
"mov z16.d, p7/m, z2.d"
"movprfx z2, z16",
"smulh z2.h, p6/m, z2.h, z17.h",
"mov v16.16b, v2.16b"
]
}
}
unittests/InstructionCountCI/VEX_map1.json
+1899 -2789
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File diff suppressed because it is too large. Load diff
unittests/InstructionCountCI/VEX_map1_FCMA.json
+20 -26
View File
@@ -10,61 +10,55 @@
},
"Instructions": {
"vaddsubpd xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 6,
"ExpectedInstructionCount": 3,
"Optimal": "No",
"Comment": [
"Map 1 0b01 0xd0 128-bit"
],
"ExpectedArm64ASM": [
"mov z2.d, p7/m, z17.d",
"mov z3.d, p7/m, z18.d",
"ext v3.16b, v3.16b, v3.16b, #8",
"fcadd v2.2d, v2.2d, v3.2d, #90",
"mov v2.16b, v2.16b",
"mov z16.d, p7/m, z2.d"
"ext v2.16b, v18.16b, v18.16b, #8",
"fcadd v2.2d, v17.2d, v2.2d, #90",
"mov v16.16b, v2.16b"
]
},
"vaddsubpd ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 5,
"ExpectedInstructionCount": 6,
"Optimal": "No",
"Comment": [
"Map 1 0b01 0xd0 256-bit"
],
"ExpectedArm64ASM": [
"mov z2.d, p7/m, z17.d",
"mov z3.d, p7/m, z18.d",
"ext z3.b, z3.b, z3.b, #8",
"fcadd z2.d, p7/m, z2.d, z3.d, #90",
"mov z16.d, p7/m, z2.d"
"movprfx z1, z18",
"ext z1.b, z1.b, z18.b, #8",
"mov z2.d, z1.d",
"movprfx z0, z17",
"fcadd z0.d, p7/m, z0.d, z2.d, #90",
"mov z16.d, z0.d"
]
},
"vaddsubps xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 6,
"ExpectedInstructionCount": 3,
"Optimal": "No",
"Comment": [
"Map 1 0b11 0xd0 128-bit"
],
"ExpectedArm64ASM": [
"mov z2.d, p7/m, z17.d",
"mov z3.d, p7/m, z18.d",
"rev64 v3.4s, v3.4s",
"fcadd v2.4s, v2.4s, v3.4s, #90",
"mov v2.16b, v2.16b",
"mov z16.d, p7/m, z2.d"
"rev64 v2.4s, v18.4s",
"fcadd v2.4s, v17.4s, v2.4s, #90",
"mov v16.16b, v2.16b"
]
},
"vaddsubps ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 5,
"ExpectedInstructionCount": 4,
"Optimal": "No",
"Comment": [
"Map 1 0b11 0xd0 256-bit"
],
"ExpectedArm64ASM": [
"mov z2.d, p7/m, z17.d",
"mov z3.d, p7/m, z18.d",
"revw z3.d, p7/m, z3.d",
"fcadd z2.s, p7/m, z2.s, z3.s, #90",
"mov z16.d, p7/m, z2.d"
"revw z2.d, p7/m, z18.d",
"movprfx z0, z17",
"fcadd z0.s, p7/m, z0.s, z2.s, #90",
"mov z16.d, z0.d"
]
}
}
unittests/InstructionCountCI/VEX_map2.json
+609 -931
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File diff suppressed because it is too large. Load diff
unittests/InstructionCountCI/VEX_map3.json
+2728 -3391
View File
File diff suppressed because it is too large. Load diff
unittests/InstructionCountCI/VEX_map_group.json
+213 -309
View File
@@ -8,543 +8,459 @@
},
"Instructions": {
"vpsrlw xmm0, xmm1, 0": {
"ExpectedInstructionCount": 3,
"Optimal": "No",
"ExpectedInstructionCount": 1,
"Optimal": "Yes",
"Comment": [
"Map group 12 0b010 128-bit"
],
"ExpectedArm64ASM": [
"mov z2.d, p7/m, z17.d",
"mov v2.16b, v2.16b",
"mov z16.d, p7/m, z2.d"
"mov v16.16b, v17.16b"
]
},
"vpsrlw xmm0, xmm1, 15": {
"ExpectedInstructionCount": 4,
"ExpectedInstructionCount": 2,
"Optimal": "No",
"Comment": [
"Map group 12 0b010 128-bit"
],
"ExpectedArm64ASM": [
"mov z2.d, p7/m, z17.d",
"ushr v2.8h, v2.8h, #15",
"mov v2.16b, v2.16b",
"mov z16.d, p7/m, z2.d"
"ushr v2.8h, v17.8h, #15",
"mov v16.16b, v2.16b"
]
},
"vpsrlw xmm0, xmm1, 16": {
"ExpectedInstructionCount": 4,
"ExpectedInstructionCount": 2,
"Optimal": "No",
"Comment": [
"Map group 12 0b010 128-bit"
],
"ExpectedArm64ASM": [
"mov z2.d, p7/m, z17.d",
"movi v2.2d, #0x0",
"mov v2.16b, v2.16b",
"mov z16.d, p7/m, z2.d"
"mov v16.16b, v2.16b"
]
},
"vpsrlw ymm0, ymm1, 0": {
"ExpectedInstructionCount": 2,
"Optimal": "No",
"ExpectedInstructionCount": 1,
"Optimal": "Yes",
"Comment": [
"Map group 12 0b010 256-bit"
],
"ExpectedArm64ASM": [
"mov z2.d, p7/m, z17.d",
"mov z16.d, p7/m, z2.d"
"mov z16.d, p7/m, z17.d"
]
},
"vpsrlw ymm0, ymm1, 15": {
"ExpectedInstructionCount": 3,
"Optimal": "No",
"ExpectedInstructionCount": 2,
"Optimal": "Yes",
"Comment": [
"Map group 12 0b010 256-bit"
],
"ExpectedArm64ASM": [
"mov z2.d, p7/m, z17.d",
"lsr z2.h, p7/m, z2.h, #15",
"mov z16.d, p7/m, z2.d"
"movprfx z16, z17",
"lsr z16.h, p7/m, z16.h, #15"
]
},
"vpsrlw ymm0, ymm1, 16": {
"ExpectedInstructionCount": 3,
"Optimal": "No",
"ExpectedInstructionCount": 1,
"Optimal": "Yes",
"Comment": [
"Map group 12 0b010 256-bit"
],
"ExpectedArm64ASM": [
"mov z2.d, p7/m, z17.d",
"movi v2.2d, #0x0",
"mov z16.d, p7/m, z2.d"
"movi v16.2d, #0x0"
]
},
"vpsraw xmm0, xmm1, 0": {
"ExpectedInstructionCount": 3,
"Optimal": "No",
"ExpectedInstructionCount": 1,
"Optimal": "Yes",
"Comment": [
"Map group 12 0b100 128-bit"
],
"ExpectedArm64ASM": [
"mov z2.d, p7/m, z17.d",
"mov v2.16b, v2.16b",
"mov z16.d, p7/m, z2.d"
"mov v16.16b, v17.16b"
]
},
"vpsraw xmm0, xmm1, 15": {
"ExpectedInstructionCount": 4,
"ExpectedInstructionCount": 2,
"Optimal": "No",
"Comment": [
"Map group 12 0b100 128-bit"
],
"ExpectedArm64ASM": [
"mov z2.d, p7/m, z17.d",
"sshr v2.8h, v2.8h, #15",
"mov v2.16b, v2.16b",
"mov z16.d, p7/m, z2.d"
"sshr v2.8h, v17.8h, #15",
"mov v16.16b, v2.16b"
]
},
"vpsraw xmm0, xmm1, 16": {
"ExpectedInstructionCount": 4,
"ExpectedInstructionCount": 2,
"Optimal": "No",
"Comment": [
"Map group 12 0b100 128-bit"
],
"ExpectedArm64ASM": [
"mov z2.d, p7/m, z17.d",
"sshr v2.8h, v2.8h, #15",
"mov v2.16b, v2.16b",
"mov z16.d, p7/m, z2.d"
"sshr v2.8h, v17.8h, #15",
"mov v16.16b, v2.16b"
]
},
"vpsraw ymm0, ymm1, 0": {
"ExpectedInstructionCount": 2,
"Optimal": "No",
"ExpectedInstructionCount": 1,
"Optimal": "Yes",
"Comment": [
"Map group 12 0b100 256-bit"
],
"ExpectedArm64ASM": [
"mov z2.d, p7/m, z17.d",
"mov z16.d, p7/m, z2.d"
"mov z16.d, p7/m, z17.d"
]
},
"vpsraw ymm0, ymm1, 15": {
"ExpectedInstructionCount": 3,
"Optimal": "No",
"ExpectedInstructionCount": 2,
"Optimal": "Yes",
"Comment": [
"Map group 12 0b100 256-bit"
],
"ExpectedArm64ASM": [
"mov z2.d, p7/m, z17.d",
"asr z2.h, p7/m, z2.h, #15",
"mov z16.d, p7/m, z2.d"
"movprfx z16, z17",
"asr z16.h, p7/m, z16.h, #15"
]
},
"vpsraw ymm0, ymm1, 16": {
"ExpectedInstructionCount": 3,
"Optimal": "No",
"ExpectedInstructionCount": 2,
"Optimal": "Yes",
"Comment": [
"Map group 12 0b100 256-bit"
],
"ExpectedArm64ASM": [
"mov z2.d, p7/m, z17.d",
"asr z2.h, p7/m, z2.h, #15",
"mov z16.d, p7/m, z2.d"
"movprfx z16, z17",
"asr z16.h, p7/m, z16.h, #15"
]
},
"vpsllw xmm0, xmm1, 0": {
"ExpectedInstructionCount": 3,
"Optimal": "No",
"ExpectedInstructionCount": 1,
"Optimal": "Yes",
"Comment": [
"Map group 12 0b110 128-bit"
],
"ExpectedArm64ASM": [
"mov z2.d, p7/m, z17.d",
"mov v2.16b, v2.16b",
"mov z16.d, p7/m, z2.d"
"mov v16.16b, v17.16b"
]
},
"vpsllw xmm0, xmm1, 15": {
"ExpectedInstructionCount": 4,
"ExpectedInstructionCount": 2,
"Optimal": "No",
"Comment": [
"Map group 12 0b110 128-bit"
],
"ExpectedArm64ASM": [
"mov z2.d, p7/m, z17.d",
"shl v2.8h, v2.8h, #15",
"mov v2.16b, v2.16b",
"mov z16.d, p7/m, z2.d"
"shl v2.8h, v17.8h, #15",
"mov v16.16b, v2.16b"
]
},
"vpsllw xmm0, xmm1, 16": {
"ExpectedInstructionCount": 4,
"ExpectedInstructionCount": 2,
"Optimal": "No",
"Comment": [
"Map group 12 0b110 128-bit"
],
"ExpectedArm64ASM": [
"mov z2.d, p7/m, z17.d",
"movi v2.2d, #0x0",
"mov v2.16b, v2.16b",
"mov z16.d, p7/m, z2.d"
"mov v16.16b, v2.16b"
]
},
"vpsllw ymm0, ymm1, 0": {
"ExpectedInstructionCount": 2,
"Optimal": "No",
"ExpectedInstructionCount": 1,
"Optimal": "Yes",
"Comment": [
"Map group 12 0b110 256-bit"
],
"ExpectedArm64ASM": [
"mov z2.d, p7/m, z17.d",
"mov z16.d, p7/m, z2.d"
"mov z16.d, p7/m, z17.d"
]
},
"vpsllw ymm0, ymm1, 15": {
"ExpectedInstructionCount": 3,
"Optimal": "No",
"ExpectedInstructionCount": 2,
"Optimal": "Yes",
"Comment": [
"Map group 12 0b110 256-bit"
],
"ExpectedArm64ASM": [
"mov z2.d, p7/m, z17.d",
"lsl z2.h, p7/m, z2.h, #15",
"mov z16.d, p7/m, z2.d"
"movprfx z16, z17",
"lsl z16.h, p7/m, z16.h, #15"
]
},
"vpsllw ymm0, ymm1, 16": {
"ExpectedInstructionCount": 3,
"Optimal": "No",
"ExpectedInstructionCount": 1,
"Optimal": "Yes",
"Comment": [
"Map group 12 0b110 256-bit"
],
"ExpectedArm64ASM": [
"mov z2.d, p7/m, z17.d",
"movi v2.2d, #0x0",
"mov z16.d, p7/m, z2.d"
"movi v16.2d, #0x0"
]
},
"vpsrld xmm0, xmm1, 0": {
"ExpectedInstructionCount": 3,
"Optimal": "No",
"ExpectedInstructionCount": 1,
"Optimal": "Yes",
"Comment": [
"Map group 13 0b010 128-bit"
],
"ExpectedArm64ASM": [
"mov z2.d, p7/m, z17.d",
"mov v2.16b, v2.16b",
"mov z16.d, p7/m, z2.d"
"mov v16.16b, v17.16b"
]
},
"vpsrld xmm0, xmm1, 31": {
"ExpectedInstructionCount": 4,
"ExpectedInstructionCount": 2,
"Optimal": "No",
"Comment": [
"Map group 13 0b010 128-bit"
],
"ExpectedArm64ASM": [
"mov z2.d, p7/m, z17.d",
"ushr v2.4s, v2.4s, #31",
"mov v2.16b, v2.16b",
"mov z16.d, p7/m, z2.d"
"ushr v2.4s, v17.4s, #31",
"mov v16.16b, v2.16b"
]
},
"vpsrld xmm0, xmm1, 32": {
"ExpectedInstructionCount": 4,
"ExpectedInstructionCount": 2,
"Optimal": "No",
"Comment": [
"Map group 13 0b010 128-bit"
],
"ExpectedArm64ASM": [
"mov z2.d, p7/m, z17.d",
"movi v2.2d, #0x0",
"mov v2.16b, v2.16b",
"mov z16.d, p7/m, z2.d"
"mov v16.16b, v2.16b"
]
},
"vpsrld ymm0, ymm1, 0": {
"ExpectedInstructionCount": 2,
"Optimal": "No",
"ExpectedInstructionCount": 1,
"Optimal": "Yes",
"Comment": [
"Map group 13 0b010 256-bit"
],
"ExpectedArm64ASM": [
"mov z2.d, p7/m, z17.d",
"mov z16.d, p7/m, z2.d"
"mov z16.d, p7/m, z17.d"
]
},
"vpsrld ymm0, ymm1, 31": {
"ExpectedInstructionCount": 3,
"Optimal": "No",
"ExpectedInstructionCount": 2,
"Optimal": "Yes",
"Comment": [
"Map group 13 0b010 256-bit"
],
"ExpectedArm64ASM": [
"mov z2.d, p7/m, z17.d",
"lsr z2.s, p7/m, z2.s, #31",
"mov z16.d, p7/m, z2.d"
"movprfx z16, z17",
"lsr z16.s, p7/m, z16.s, #31"
]
},
"vpsrld ymm0, ymm1, 32": {
"ExpectedInstructionCount": 3,
"Optimal": "No",
"ExpectedInstructionCount": 1,
"Optimal": "Yes",
"Comment": [
"Map group 13 0b010 256-bit"
],
"ExpectedArm64ASM": [
"mov z2.d, p7/m, z17.d",
"movi v2.2d, #0x0",
"mov z16.d, p7/m, z2.d"
"movi v16.2d, #0x0"
]
},
"vpsrad xmm0, xmm1, 0": {
"ExpectedInstructionCount": 3,
"Optimal": "No",
"ExpectedInstructionCount": 1,
"Optimal": "Yes",
"Comment": [
"Map group 13 0b100 128-bit"
],
"ExpectedArm64ASM": [
"mov z2.d, p7/m, z17.d",
"mov v2.16b, v2.16b",
"mov z16.d, p7/m, z2.d"
"mov v16.16b, v17.16b"
]
},
"vpsrad xmm0, xmm1, 31": {
"ExpectedInstructionCount": 4,
"ExpectedInstructionCount": 2,
"Optimal": "No",
"Comment": [
"Map group 13 0b100 128-bit"
],
"ExpectedArm64ASM": [
"mov z2.d, p7/m, z17.d",
"sshr v2.4s, v2.4s, #31",
"mov v2.16b, v2.16b",
"mov z16.d, p7/m, z2.d"
"sshr v2.4s, v17.4s, #31",
"mov v16.16b, v2.16b"
]
},
"vpsrad xmm0, xmm1, 32": {
"ExpectedInstructionCount": 4,
"ExpectedInstructionCount": 2,
"Optimal": "No",
"Comment": [
"Map group 13 0b100 128-bit"
],
"ExpectedArm64ASM": [
"mov z2.d, p7/m, z17.d",
"sshr v2.4s, v2.4s, #31",
"mov v2.16b, v2.16b",
"mov z16.d, p7/m, z2.d"
"sshr v2.4s, v17.4s, #31",
"mov v16.16b, v2.16b"
]
},
"vpsrad ymm0, ymm1, 0": {
"ExpectedInstructionCount": 2,
"Optimal": "No",
"ExpectedInstructionCount": 1,
"Optimal": "Yes",
"Comment": [
"Map group 13 0b100 256-bit"
],
"ExpectedArm64ASM": [
"mov z2.d, p7/m, z17.d",
"mov z16.d, p7/m, z2.d"
"mov z16.d, p7/m, z17.d"
]
},
"vpsrad ymm0, ymm1, 31": {
"ExpectedInstructionCount": 3,
"Optimal": "No",
"ExpectedInstructionCount": 2,
"Optimal": "Yes",
"Comment": [
"Map group 13 0b100 256-bit"
],
"ExpectedArm64ASM": [
"mov z2.d, p7/m, z17.d",
"asr z2.s, p7/m, z2.s, #31",
"mov z16.d, p7/m, z2.d"
"movprfx z16, z17",
"asr z16.s, p7/m, z16.s, #31"
]
},
"vpsrad ymm0, ymm1, 32": {
"ExpectedInstructionCount": 3,
"Optimal": "No",
"ExpectedInstructionCount": 2,
"Optimal": "Yes",
"Comment": [
"Map group 13 0b100 256-bit"
],
"ExpectedArm64ASM": [
"mov z2.d, p7/m, z17.d",
"asr z2.s, p7/m, z2.s, #31",
"mov z16.d, p7/m, z2.d"
"movprfx z16, z17",
"asr z16.s, p7/m, z16.s, #31"
]
},
"vpslld xmm0, xmm1, 0": {
"ExpectedInstructionCount": 3,
"Optimal": "No",
"ExpectedInstructionCount": 1,
"Optimal": "Yes",
"Comment": [
"Map group 13 0b110 128-bit"
],
"ExpectedArm64ASM": [
"mov z2.d, p7/m, z17.d",
"mov v2.16b, v2.16b",
"mov z16.d, p7/m, z2.d"
"mov v16.16b, v17.16b"
]
},
"vpslld xmm0, xmm1, 31": {
"ExpectedInstructionCount": 4,
"ExpectedInstructionCount": 2,
"Optimal": "No",
"Comment": [
"Map group 13 0b110 128-bit"
],
"ExpectedArm64ASM": [
"mov z2.d, p7/m, z17.d",
"shl v2.4s, v2.4s, #31",
"mov v2.16b, v2.16b",
"mov z16.d, p7/m, z2.d"
"shl v2.4s, v17.4s, #31",
"mov v16.16b, v2.16b"
]
},
"vpslld xmm0, xmm1, 32": {
"ExpectedInstructionCount": 4,
"ExpectedInstructionCount": 2,
"Optimal": "No",
"Comment": [
"Map group 13 0b110 128-bit"
],
"ExpectedArm64ASM": [
"mov z2.d, p7/m, z17.d",
"movi v2.2d, #0x0",
"mov v2.16b, v2.16b",
"mov z16.d, p7/m, z2.d"
"mov v16.16b, v2.16b"
]
},
"vpslld ymm0, ymm1, 0": {
"ExpectedInstructionCount": 2,
"Optimal": "No",
"ExpectedInstructionCount": 1,
"Optimal": "Yes",
"Comment": [
"Map group 13 0b110 256-bit"
],
"ExpectedArm64ASM": [
"mov z2.d, p7/m, z17.d",
"mov z16.d, p7/m, z2.d"
"mov z16.d, p7/m, z17.d"
]
},
"vpslld ymm0, ymm1, 31": {
"ExpectedInstructionCount": 3,
"Optimal": "No",
"ExpectedInstructionCount": 2,
"Optimal": "Yes",
"Comment": [
"Map group 13 0b110 256-bit"
],
"ExpectedArm64ASM": [
"mov z2.d, p7/m, z17.d",
"lsl z2.s, p7/m, z2.s, #31",
"mov z16.d, p7/m, z2.d"
"movprfx z16, z17",
"lsl z16.s, p7/m, z16.s, #31"
]
},
"vpslld ymm0, ymm1, 32": {
"ExpectedInstructionCount": 3,
"Optimal": "No",
"ExpectedInstructionCount": 1,
"Optimal": "Yes",
"Comment": [
"Map group 13 0b110 256-bit"
],
"ExpectedArm64ASM": [
"mov z2.d, p7/m, z17.d",
"movi v2.2d, #0x0",
"mov z16.d, p7/m, z2.d"
"movi v16.2d, #0x0"
]
},
"vpsrlq xmm0, xmm1, 0": {
"ExpectedInstructionCount": 3,
"Optimal": "No",
"ExpectedInstructionCount": 1,
"Optimal": "Yes",
"Comment": [
"Map group 14 0b010 128-bit"
],
"ExpectedArm64ASM": [
"mov z2.d, p7/m, z17.d",
"mov v2.16b, v2.16b",
"mov z16.d, p7/m, z2.d"
"mov v16.16b, v17.16b"
]
},
"vpsrlq xmm0, xmm1, 63": {
"ExpectedInstructionCount": 4,
"ExpectedInstructionCount": 2,
"Optimal": "No",
"Comment": [
"Map group 14 0b010 128-bit"
],
"ExpectedArm64ASM": [
"mov z2.d, p7/m, z17.d",
"ushr v2.2d, v2.2d, #63",
"mov v2.16b, v2.16b",
"mov z16.d, p7/m, z2.d"
"ushr v2.2d, v17.2d, #63",
"mov v16.16b, v2.16b"
]
},
"vpsrlq xmm0, xmm1, 64": {
"ExpectedInstructionCount": 4,
"ExpectedInstructionCount": 2,
"Optimal": "No",
"Comment": [
"Map group 14 0b010 128-bit"
],
"ExpectedArm64ASM": [
"mov z2.d, p7/m, z17.d",
"movi v2.2d, #0x0",
"mov v2.16b, v2.16b",
"mov z16.d, p7/m, z2.d"
"mov v16.16b, v2.16b"
]
},
"vpsrlq ymm0, ymm1, 0": {
"ExpectedInstructionCount": 2,
"Optimal": "No",
"ExpectedInstructionCount": 1,
"Optimal": "Yes",
"Comment": [
"Map group 14 0b010 256-bit"
],
"ExpectedArm64ASM": [
"mov z2.d, p7/m, z17.d",
"mov z16.d, p7/m, z2.d"
"mov z16.d, p7/m, z17.d"
]
},
"vpsrlq ymm0, ymm1, 63": {
"ExpectedInstructionCount": 3,
"Optimal": "No",
"ExpectedInstructionCount": 2,
"Optimal": "Yes",
"Comment": [
"Map group 14 0b010 256-bit"
],
"ExpectedArm64ASM": [
"mov z2.d, p7/m, z17.d",
"lsr z2.d, p7/m, z2.d, #63",
"mov z16.d, p7/m, z2.d"
"movprfx z16, z17",
"lsr z16.d, p7/m, z16.d, #63"
]
},
"vpsrlq ymm0, ymm1, 64": {
"ExpectedInstructionCount": 3,
"Optimal": "No",
"ExpectedInstructionCount": 1,
"Optimal": "Yes",
"Comment": [
"Map group 14 0b010 256-bit"
],
"ExpectedArm64ASM": [
"mov z2.d, p7/m, z17.d",
"movi v2.2d, #0x0",
"mov z16.d, p7/m, z2.d"
"movi v16.2d, #0x0"
]
},
"vpsrldq xmm0, xmm1, 0": {
"ExpectedInstructionCount": 3,
"Optimal": "No",
"ExpectedInstructionCount": 1,
"Optimal": "Yes",
"Comment": [
"Map group 14 0b011 128-bit"
],
"ExpectedArm64ASM": [
"mov z2.d, p7/m, z17.d",
"mov v2.16b, v2.16b",
"mov z16.d, p7/m, z2.d"
"mov v16.16b, v17.16b"
]
},
"vpsrldq xmm0, xmm1, 15": {
"ExpectedInstructionCount": 5,
"Optimal": "No",
"Comment": [
"Map group 14 0b011 128-bit"
],
"ExpectedArm64ASM": [
"mov z2.d, p7/m, z17.d",
"movi v3.2d, #0x0",
"ext v2.16b, v2.16b, v3.16b, #15",
"mov v2.16b, v2.16b",
"mov z16.d, p7/m, z2.d"
]
},
"vpsrldq xmm0, xmm1, 16": {
"ExpectedInstructionCount": 3,
"Optimal": "No",
"Comment": [
@@ -552,19 +468,29 @@
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov v2.16b, v2.16b",
"mov z16.d, p7/m, z2.d"
"ext v2.16b, v17.16b, v2.16b, #15",
"mov v16.16b, v2.16b"
]
},
"vpsrldq xmm0, xmm1, 16": {
"ExpectedInstructionCount": 2,
"Optimal": "No",
"Comment": [
"Map group 14 0b011 128-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov v16.16b, v2.16b"
]
},
"vpsrldq ymm0, ymm1, 0": {
"ExpectedInstructionCount": 2,
"Optimal": "No",
"ExpectedInstructionCount": 1,
"Optimal": "Yes",
"Comment": [
"Map group 14 0b011 256-bit"
],
"ExpectedArm64ASM": [
"mov z2.d, p7/m, z17.d",
"mov z16.d, p7/m, z2.d"
"mov z16.d, p7/m, z17.d"
]
},
"vpsrldq ymm0, ymm1, 15": {
@@ -574,128 +500,101 @@
"Map group 14 0b011 256-bit"
],
"ExpectedArm64ASM": [
"mov z2.d, p7/m, z17.d",
"movi v3.2d, #0x0",
"ext v4.16b, v2.16b, v3.16b, #15",
"ext z2.b, z2.b, z3.b, #31",
"movi v2.2d, #0x0",
"ext v3.16b, v17.16b, v2.16b, #15",
"movprfx z1, z17",
"ext z1.b, z1.b, z2.b, #31",
"mov z2.d, z1.d",
"mov z1.q, q2",
"mov z2.d, z4.d",
"mov z16.d, z3.d",
"not p0.b, p7/z, p6.b",
"mov z2.b, p0/m, z1.b",
"mov z16.d, p7/m, z2.d"
"mov z16.b, p0/m, z1.b"
]
},
"vpsrldq ymm0, ymm1, 16": {
"ExpectedInstructionCount": 2,
"Optimal": "No",
"ExpectedInstructionCount": 1,
"Optimal": "Yes",
"Comment": [
"Map group 14 0b011 256-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov z16.d, p7/m, z2.d"
"movi v16.2d, #0x0"
]
},
"vpsllq xmm0, xmm1, 0": {
"ExpectedInstructionCount": 3,
"Optimal": "No",
"ExpectedInstructionCount": 1,
"Optimal": "Yes",
"Comment": [
"Map group 14 0b110 128-bit"
],
"ExpectedArm64ASM": [
"mov z2.d, p7/m, z17.d",
"mov v2.16b, v2.16b",
"mov z16.d, p7/m, z2.d"
"mov v16.16b, v17.16b"
]
},
"vpsllq xmm0, xmm1, 63": {
"ExpectedInstructionCount": 4,
"ExpectedInstructionCount": 2,
"Optimal": "No",
"Comment": [
"Map group 14 0b110 128-bit"
],
"ExpectedArm64ASM": [
"mov z2.d, p7/m, z17.d",
"shl v2.2d, v2.2d, #63",
"mov v2.16b, v2.16b",
"mov z16.d, p7/m, z2.d"
"shl v2.2d, v17.2d, #63",
"mov v16.16b, v2.16b"
]
},
"vpsllq xmm0, xmm1, 64": {
"ExpectedInstructionCount": 4,
"ExpectedInstructionCount": 2,
"Optimal": "No",
"Comment": [
"Map group 14 0b110 128-bit"
],
"ExpectedArm64ASM": [
"mov z2.d, p7/m, z17.d",
"movi v2.2d, #0x0",
"mov v2.16b, v2.16b",
"mov z16.d, p7/m, z2.d"
"mov v16.16b, v2.16b"
]
},
"vpsllq ymm0, ymm1, 0": {
"ExpectedInstructionCount": 2,
"Optimal": "No",
"ExpectedInstructionCount": 1,
"Optimal": "Yes",
"Comment": [
"Map group 14 0b110 256-bit"
],
"ExpectedArm64ASM": [
"mov z2.d, p7/m, z17.d",
"mov z16.d, p7/m, z2.d"
"mov z16.d, p7/m, z17.d"
]
},
"vpsllq ymm0, ymm1, 63": {
"ExpectedInstructionCount": 3,
"Optimal": "No",
"ExpectedInstructionCount": 2,
"Optimal": "Yes",
"Comment": [
"Map group 14 0b110 256-bit"
],
"ExpectedArm64ASM": [
"mov z2.d, p7/m, z17.d",
"lsl z2.d, p7/m, z2.d, #63",
"mov z16.d, p7/m, z2.d"
"movprfx z16, z17",
"lsl z16.d, p7/m, z16.d, #63"
]
},
"vpsllq ymm0, ymm1, 64": {
"ExpectedInstructionCount": 3,
"Optimal": "No",
"ExpectedInstructionCount": 1,
"Optimal": "Yes",
"Comment": [
"Map group 14 0b110 256-bit"
],
"ExpectedArm64ASM": [
"mov z2.d, p7/m, z17.d",
"movi v2.2d, #0x0",
"mov z16.d, p7/m, z2.d"
"movi v16.2d, #0x0"
]
},
"vpslldq xmm0, xmm1, 0": {
"ExpectedInstructionCount": 3,
"Optimal": "No",
"ExpectedInstructionCount": 1,
"Optimal": "Yes",
"Comment": [
"Map group 14 0b111 128-bit"
],
"ExpectedArm64ASM": [
"mov z2.d, p7/m, z17.d",
"mov v2.16b, v2.16b",
"mov z16.d, p7/m, z2.d"
"mov v16.16b, v17.16b"
]
},
"vpslldq xmm0, xmm1, 15": {
"ExpectedInstructionCount": 5,
"Optimal": "No",
"Comment": [
"Map group 14 0b111 128-bit"
],
"ExpectedArm64ASM": [
"mov z2.d, p7/m, z17.d",
"movi v3.2d, #0x0",
"ext v2.16b, v3.16b, v2.16b, #1",
"mov v2.16b, v2.16b",
"mov z16.d, p7/m, z2.d"
]
},
"vpslldq xmm0, xmm1, 16": {
"ExpectedInstructionCount": 3,
"Optimal": "No",
"Comment": [
@@ -703,50 +602,55 @@
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov v2.16b, v2.16b",
"mov z16.d, p7/m, z2.d"
"ext v2.16b, v2.16b, v17.16b, #1",
"mov v16.16b, v2.16b"
]
},
"vpslldq xmm0, xmm1, 16": {
"ExpectedInstructionCount": 2,
"Optimal": "No",
"Comment": [
"Map group 14 0b111 128-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov v16.16b, v2.16b"
]
},
"vpslldq ymm0, ymm1, 0": {
"ExpectedInstructionCount": 2,
"Optimal": "No",
"ExpectedInstructionCount": 1,
"Optimal": "Yes",
"Comment": [
"Map group 14 0b111 256-bit"
],
"ExpectedArm64ASM": [
"mov z2.d, p7/m, z17.d",
"mov z16.d, p7/m, z2.d"
"mov z16.d, p7/m, z17.d"
]
},
"vpslldq ymm0, ymm1, 15": {
"ExpectedInstructionCount": 11,
"Optimal": "No",
"Comment": [
"Map group 14 0b111 256-bit"
],
"ExpectedArm64ASM": [
"mov z2.d, p7/m, z17.d",
"movi v3.2d, #0x0",
"ext v4.16b, v3.16b, v2.16b, #1",
"movprfx z1, z3",
"ext z1.b, z1.b, z2.b, #17",
"mov z2.d, z1.d",
"mov z1.q, q2",
"mov z2.d, z4.d",
"not p0.b, p7/z, p6.b",
"mov z2.b, p0/m, z1.b",
"mov z16.d, p7/m, z2.d"
]
},
"vpslldq ymm0, ymm1, 16": {
"ExpectedInstructionCount": 2,
"ExpectedInstructionCount": 7,
"Optimal": "No",
"Comment": [
"Map group 14 0b111 256-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov z16.d, p7/m, z2.d"
"ext v3.16b, v2.16b, v17.16b, #1",
"ext z2.b, z2.b, z17.b, #17",
"mov z1.q, q2",
"mov z16.d, z3.d",
"not p0.b, p7/z, p6.b",
"mov z16.b, p0/m, z1.b"
]
},
"vpslldq ymm0, ymm1, 16": {
"ExpectedInstructionCount": 1,
"Optimal": "Yes",
"Comment": [
"Map group 14 0b111 256-bit"
],
"ExpectedArm64ASM": [
"movi v16.2d, #0x0"
]
},
"vldmxcsr [rax]": {