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OpcodeDispatcher: Handle PCMPESTRI/VPCMPESTRI
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@@ -5978,6 +5978,8 @@ void OpDispatchBuilder::InstallHostSpecificOpcodeHandlers() {
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{OPD(3, 0b01, 0x4B), 1, &OpDispatchBuilder::AVXVectorVariableBlend<8>},
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{OPD(3, 0b01, 0x4C), 1, &OpDispatchBuilder::AVXVectorVariableBlend<1>},
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{OPD(3, 0b01, 0x61), 1, &OpDispatchBuilder::VPCMPESTRIOp},
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{OPD(3, 0b01, 0xDF), 1, &OpDispatchBuilder::VAESKeyGenAssistOp},
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};
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#undef OPD
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@@ -7266,6 +7268,8 @@ constexpr uint16_t PF_F2 = 3;
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{OPD(0, PF_3A_66, 0x41), 1, &OpDispatchBuilder::DPPOp<8>},
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{OPD(0, PF_3A_66, 0x42), 1, &OpDispatchBuilder::MPSADBWOp},
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{OPD(0, PF_3A_66, 0x61), 1, &OpDispatchBuilder::VPCMPESTRIOp},
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{OPD(0, PF_3A_NONE, 0xCC), 1, &OpDispatchBuilder::SHA1RNDS4Op},
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};
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#undef PF_3A_NONE
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@@ -487,6 +487,8 @@ public:
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void VPALIGNROp(OpcodeArgs);
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void VPCMPESTRIOp(OpcodeArgs);
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void VPERM2Op(OpcodeArgs);
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void VPERMDOp(OpcodeArgs);
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void VPERMQOp(OpcodeArgs);
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@@ -853,6 +855,11 @@ private:
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const X86Tables::DecodedOperand& Src2,
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const X86Tables::DecodedOperand& Imm);
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OrderedNode* PCMPESTRXOpImpl(OpcodeArgs,
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const X86Tables::DecodedOperand& Src1,
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const X86Tables::DecodedOperand& Src2,
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const X86Tables::DecodedOperand& Imm);
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OrderedNode* PHADDSOpImpl(OpcodeArgs, const X86Tables::DecodedOperand& Src1,
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const X86Tables::DecodedOperand& Src2);
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@@ -4552,4 +4552,77 @@ void OpDispatchBuilder::VPERMILRegOp<4>(OpcodeArgs);
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template
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void OpDispatchBuilder::VPERMILRegOp<8>(OpcodeArgs);
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OrderedNode* OpDispatchBuilder::PCMPESTRXOpImpl(OpcodeArgs,
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const X86Tables::DecodedOperand& Src1Op,
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const X86Tables::DecodedOperand& Src2Op,
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const X86Tables::DecodedOperand& Imm) {
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LOGMAN_THROW_A_FMT(Imm.IsLiteral(), "Imm needs to be a literal");
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const auto Control = Imm.Data.Literal.Value;
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// Will be 4 in the absence of a REX.W bit and 8 in the presence of a REX.W bit.
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const auto SrcSize = GetSrcSize(Op);
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// SSE4.2 string instructions modify flags, so invalidate
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// any previously deferred flags.
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InvalidateDeferredFlags();
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// NOTE: Unlike most other SSE/AVX instructions, the SSE4.2 string and text
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// instructions do *not* require memory operands to be aligned on a 16 byte
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// boundary (see "Other Exceptions" descriptions for the relevant
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// instructions in the Intel Software Development Manual).
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//
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// So, we specify Src2 as having an alignment of 1 to indicate this.
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OrderedNode *Src1 = LoadSource_WithOpSize(FPRClass, Op, Src1Op, 16, Op->Flags, -1);
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OrderedNode *Src2 = LoadSource_WithOpSize(FPRClass, Op, Src2Op, 16, Op->Flags, 1);
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OrderedNode *SrcRAX = LoadGPRRegister(X86State::REG_RAX);
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OrderedNode *SrcRDX = LoadGPRRegister(X86State::REG_RDX);
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OrderedNode *IntermediateResult = _VPCMPESTRX(SrcSize, Src1, Src2, SrcRAX, SrcRDX, Control);
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OrderedNode *ResultNoFlags = _And(IntermediateResult, _Constant(0xFFFF));
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// For the indexed variant of the instructions, if control[6] is set, then we
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// store the index of the most significant bit into ECX. If it's not set,
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// then we store the least significant bit.
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OrderedNode *ZeroConst = _Constant(0);
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const auto ECXResult = [&]() -> OrderedNode* {
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const auto UseMSBIndex = (Control & 0b0100'0000) != 0;
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OrderedNode *IfZero = _Constant(16 >> (Control & 1));
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OrderedNode *IfNotZero = UseMSBIndex ? _FindMSB(ResultNoFlags)
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: _FindLSB(ResultNoFlags);
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return _Select(IR::COND_EQ, ResultNoFlags, ZeroConst,
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IfZero, IfNotZero);
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}();
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// Set all of the necessary flags.
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// We use the top 16-bits of the result to store the flags
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// in the form:
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//
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// Bit: 19 18 17 16
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// [OF | CF | SF | ZF]
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//
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const auto GetFlagBit = [this, IntermediateResult](int BitIndex) {
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return _Bfe(1, BitIndex, IntermediateResult);
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};
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SetRFLAG<X86State::RFLAG_ZF_LOC>(GetFlagBit(16));
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SetRFLAG<X86State::RFLAG_SF_LOC>(GetFlagBit(17));
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SetRFLAG<X86State::RFLAG_CF_LOC>(GetFlagBit(18));
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SetRFLAG<X86State::RFLAG_OF_LOC>(GetFlagBit(19));
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SetRFLAG<X86State::RFLAG_AF_LOC>(ZeroConst);
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SetRFLAG<X86State::RFLAG_PF_LOC>(ZeroConst);
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// ... and we're done!
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return ECXResult;
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}
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void OpDispatchBuilder::VPCMPESTRIOp(OpcodeArgs) {
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OrderedNode *Result = PCMPESTRXOpImpl(Op, Op->Dest, Op->Src[0], Op->Src[1]);
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StoreGPRRegister(X86State::REG_RCX, Result, 4);
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}
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}
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@@ -45,9 +45,9 @@ void InitializeH0F3ATables(Context::OperatingMode Mode) {
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{OPD(0, PF_3A_66, 0x44), 1, X86InstInfo{"PCLMULQDQ", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 1, nullptr}},
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{OPD(0, PF_3A_66, 0x60), 1, X86InstInfo{"PCMPESTRM", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
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{OPD(0, PF_3A_66, 0x61), 1, X86InstInfo{"PCMPESTRI", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
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{OPD(0, PF_3A_66, 0x61), 1, X86InstInfo{"PCMPESTRI", TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_32BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 1, nullptr}},
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{OPD(0, PF_3A_66, 0x62), 1, X86InstInfo{"PCMPISTRM", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
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{OPD(0, PF_3A_66, 0x63), 1, X86InstInfo{"PCMPISTRI", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 1, nullptr}},
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{OPD(0, PF_3A_66, 0x63), 1, X86InstInfo{"PCMPISTRI", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
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{OPD(0, PF_3A_NONE, 0xCC), 1, X86InstInfo{"SHA1RNDS4", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 1, nullptr}},
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@@ -453,9 +453,9 @@ void InitializeVEXTables() {
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{OPD(3, 0b01, 0x5F), 1, X86InstInfo{"VFMSUBADDPD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
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{OPD(3, 0b01, 0x60), 1, X86InstInfo{"VPCMPESTRM", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
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{OPD(3, 0b01, 0x61), 1, X86InstInfo{"VPCMPESTRI", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
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{OPD(3, 0b01, 0x61), 1, X86InstInfo{"VPCMPESTRI", TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_32BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 1, nullptr}},
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{OPD(3, 0b01, 0x62), 1, X86InstInfo{"VPCMPISTRM", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
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{OPD(3, 0b01, 0x63), 1, X86InstInfo{"VPCMPISTRI", TYPE_INST, FLAGS_MODRM | FLAGS_XMM_FLAGS, 1, nullptr}},
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{OPD(3, 0b01, 0x63), 1, X86InstInfo{"VPCMPISTRI", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
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{OPD(3, 0b01, 0x68), 1, X86InstInfo{"VFMADDPS", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
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{OPD(3, 0b01, 0x69), 1, X86InstInfo{"VFMADDPD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
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