From 36e1b5107ebe3322cfa9c1fd744ab46d114aeb4f Mon Sep 17 00:00:00 2001 From: Ryan Houdek Date: Tue, 30 Jun 2026 15:01:46 -0700 Subject: [PATCH] InstcountCI: Update --- unittests/InstructionCountCI/AVX128/FMA4.json | 60 +++++----- .../InstructionCountCI/AVX128/VEX_map1.json | 64 +++++------ .../InstructionCountCI/AVX128/VEX_map2.json | 50 ++++---- .../AVX128/VEX_map2_SVE128.json | 48 ++++---- .../InstructionCountCI/AVX128/VEX_map3.json | 16 +-- .../InstructionCountCI/Crypto/H0F38.json | 2 +- .../InstructionCountCI/Crypto/H0F3A.json | 20 ++-- .../InstructionCountCI/FlagM/HotBlocks.json | 4 +- .../InstructionCountCI/FlagM/Secondary.json | 2 +- .../FlagM/Secondary_OpSize.json | 2 +- .../InstructionCountCI/FlagM/VEX_map1.json | 4 +- .../FlagM/x87-HalfLife.json | 12 +- .../FlagM/x87-Oblivion.json | 74 ++++++------ .../FlagM/x87-Psychonauts.json | 22 ++-- unittests/InstructionCountCI/FlagM/x87.json | 66 +++++------ .../InstructionCountCI/FlagM/x87_f64.json | 52 ++++----- unittests/InstructionCountCI/H0F38.json | 2 +- unittests/InstructionCountCI/H0F3A.json | 14 +-- .../InstructionCountCI/PrimaryGroup.json | 4 +- .../InstructionCountCI/SSE42_Strings.json | 48 ++++---- unittests/InstructionCountCI/Secondary.json | 12 +- .../InstructionCountCI/Secondary_OpSize.json | 10 +- .../InstructionCountCI/Secondary_REP.json | 24 ++-- .../InstructionCountCI/Secondary_REPNE.json | 6 +- unittests/InstructionCountCI/VEX_map1.json | 108 +++++++++--------- .../InstructionCountCI/VEX_map1_FRINTTS.json | 16 +-- unittests/InstructionCountCI/VEX_map2.json | 50 ++++---- unittests/InstructionCountCI/VEX_map3.json | 4 +- unittests/InstructionCountCI/x87.json | 66 +++++------ unittests/InstructionCountCI/x87_f64.json | 52 ++++----- 30 files changed, 443 insertions(+), 471 deletions(-) diff --git a/unittests/InstructionCountCI/AVX128/FMA4.json b/unittests/InstructionCountCI/AVX128/FMA4.json index e6851a1d3..c6c03db35 100644 --- a/unittests/InstructionCountCI/AVX128/FMA4.json +++ b/unittests/InstructionCountCI/AVX128/FMA4.json @@ -19,7 +19,7 @@ "str x20, [x28, #24]", "mov w0, #0x401", "str x0, [x28, #1496]", - "ldr x0, [x28, #2920]", + "ldr x0, [x28, #2952]", "br x0" ] }, @@ -33,7 +33,7 @@ "str x20, [x28, #24]", "mov w0, #0x401", "str x0, [x28, #1496]", - "ldr x0, [x28, #2920]", + "ldr x0, [x28, #2952]", "br x0" ] }, @@ -47,7 +47,7 @@ "str x20, [x28, #24]", "mov w0, #0x401", "str x0, [x28, #1496]", - "ldr x0, [x28, #2920]", + "ldr x0, [x28, #2952]", "br x0" ] }, @@ -61,7 +61,7 @@ "str x20, [x28, #24]", "mov w0, #0x401", "str x0, [x28, #1496]", - "ldr x0, [x28, #2920]", + "ldr x0, [x28, #2952]", "br x0" ] }, @@ -75,7 +75,7 @@ "str x20, [x28, #24]", "mov w0, #0x401", "str x0, [x28, #1496]", - "ldr x0, [x28, #2920]", + "ldr x0, [x28, #2952]", "br x0" ] }, @@ -89,7 +89,7 @@ "str x20, [x28, #24]", "mov w0, #0x401", "str x0, [x28, #1496]", - "ldr x0, [x28, #2920]", + "ldr x0, [x28, #2952]", "br x0" ] }, @@ -103,7 +103,7 @@ "str x20, [x28, #24]", "mov w0, #0x401", "str x0, [x28, #1496]", - "ldr x0, [x28, #2920]", + "ldr x0, [x28, #2952]", "br x0" ] }, @@ -117,7 +117,7 @@ "str x20, [x28, #24]", "mov w0, #0x401", "str x0, [x28, #1496]", - "ldr x0, [x28, #2920]", + "ldr x0, [x28, #2952]", "br x0" ] }, @@ -131,7 +131,7 @@ "str x20, [x28, #24]", "mov w0, #0x401", "str x0, [x28, #1496]", - "ldr x0, [x28, #2920]", + "ldr x0, [x28, #2952]", "br x0" ] }, @@ -145,7 +145,7 @@ "str x20, [x28, #24]", "mov w0, #0x401", "str x0, [x28, #1496]", - "ldr x0, [x28, #2920]", + "ldr x0, [x28, #2952]", "br x0" ] }, @@ -159,7 +159,7 @@ "str x20, [x28, #24]", "mov w0, #0x401", "str x0, [x28, #1496]", - "ldr x0, [x28, #2920]", + "ldr x0, [x28, #2952]", "br x0" ] }, @@ -173,7 +173,7 @@ "str x20, [x28, #24]", "mov w0, #0x401", "str x0, [x28, #1496]", - "ldr x0, [x28, #2920]", + "ldr x0, [x28, #2952]", "br x0" ] }, @@ -187,7 +187,7 @@ "str x20, [x28, #24]", "mov w0, #0x401", "str x0, [x28, #1496]", - "ldr x0, [x28, #2920]", + "ldr x0, [x28, #2952]", "br x0" ] }, @@ -201,7 +201,7 @@ "str x20, [x28, #24]", "mov w0, #0x401", "str x0, [x28, #1496]", - "ldr x0, [x28, #2920]", + "ldr x0, [x28, #2952]", "br x0" ] }, @@ -215,7 +215,7 @@ "str x20, [x28, #24]", "mov w0, #0x401", "str x0, [x28, #1496]", - "ldr x0, [x28, #2920]", + "ldr x0, [x28, #2952]", "br x0" ] }, @@ -229,7 +229,7 @@ "str x20, [x28, #24]", "mov w0, #0x401", "str x0, [x28, #1496]", - "ldr x0, [x28, #2920]", + "ldr x0, [x28, #2952]", "br x0" ] }, @@ -243,7 +243,7 @@ "str x20, [x28, #24]", "mov w0, #0x401", "str x0, [x28, #1496]", - "ldr x0, [x28, #2920]", + "ldr x0, [x28, #2952]", "br x0" ] }, @@ -257,7 +257,7 @@ "str x20, [x28, #24]", "mov w0, #0x401", "str x0, [x28, #1496]", - "ldr x0, [x28, #2920]", + "ldr x0, [x28, #2952]", "br x0" ] }, @@ -271,7 +271,7 @@ "str x20, [x28, #24]", "mov w0, #0x401", "str x0, [x28, #1496]", - "ldr x0, [x28, #2920]", + "ldr x0, [x28, #2952]", "br x0" ] }, @@ -285,7 +285,7 @@ "str x20, [x28, #24]", "mov w0, #0x401", "str x0, [x28, #1496]", - "ldr x0, [x28, #2920]", + "ldr x0, [x28, #2952]", "br x0" ] }, @@ -299,7 +299,7 @@ "str x20, [x28, #24]", "mov w0, #0x401", "str x0, [x28, #1496]", - "ldr x0, [x28, #2920]", + "ldr x0, [x28, #2952]", "br x0" ] }, @@ -313,7 +313,7 @@ "str x20, [x28, #24]", "mov w0, #0x401", "str x0, [x28, #1496]", - "ldr x0, [x28, #2920]", + "ldr x0, [x28, #2952]", "br x0" ] }, @@ -327,7 +327,7 @@ "str x20, [x28, #24]", "mov w0, #0x401", "str x0, [x28, #1496]", - "ldr x0, [x28, #2920]", + "ldr x0, [x28, #2952]", "br x0" ] }, @@ -341,7 +341,7 @@ "str x20, [x28, #24]", "mov w0, #0x401", "str x0, [x28, #1496]", - "ldr x0, [x28, #2920]", + "ldr x0, [x28, #2952]", "br x0" ] }, @@ -355,7 +355,7 @@ "str x20, [x28, #24]", "mov w0, #0x401", "str x0, [x28, #1496]", - "ldr x0, [x28, #2920]", + "ldr x0, [x28, #2952]", "br x0" ] }, @@ -369,7 +369,7 @@ "str x20, [x28, #24]", "mov w0, #0x401", "str x0, [x28, #1496]", - "ldr x0, [x28, #2920]", + "ldr x0, [x28, #2952]", "br x0" ] }, @@ -383,7 +383,7 @@ "str x20, [x28, #24]", "mov w0, #0x401", "str x0, [x28, #1496]", - "ldr x0, [x28, #2920]", + "ldr x0, [x28, #2952]", "br x0" ] }, @@ -397,7 +397,7 @@ "str x20, [x28, #24]", "mov w0, #0x401", "str x0, [x28, #1496]", - "ldr x0, [x28, #2920]", + "ldr x0, [x28, #2952]", "br x0" ] }, @@ -411,7 +411,7 @@ "str x20, [x28, #24]", "mov w0, #0x401", "str x0, [x28, #1496]", - "ldr x0, [x28, #2920]", + "ldr x0, [x28, #2952]", "br x0" ] }, @@ -425,7 +425,7 @@ "str x20, [x28, #24]", "mov w0, #0x401", "str x0, [x28, #1496]", - "ldr x0, [x28, #2920]", + "ldr x0, [x28, #2952]", "br x0" ] } diff --git a/unittests/InstructionCountCI/AVX128/VEX_map1.json b/unittests/InstructionCountCI/AVX128/VEX_map1.json index c93ae529b..ca0aa04fb 100644 --- a/unittests/InstructionCountCI/AVX128/VEX_map1.json +++ b/unittests/InstructionCountCI/AVX128/VEX_map1.json @@ -485,7 +485,7 @@ ], "ExpectedArm64ASM": [ "ushr v2.4s, v16.4s, #31", - "ldr q3, [x28, #3216]", + "ldr q3, [x28, #3264]", "ushl v2.4s, v2.4s, v3.4s", "addv s2, v2.4s", "mov w4, v2.s[0]" @@ -499,7 +499,7 @@ "ExpectedArm64ASM": [ "ldr q2, [x28, #192]", "ushr v3.4s, v16.4s, #31", - "ldr q4, [x28, #3216]", + "ldr q4, [x28, #3264]", "ushl v3.4s, v3.4s, v4.4s", "addv s3, v3.4s", "mov w20, v3.s[0]", @@ -1122,7 +1122,7 @@ "Map 1 0b01 0x70 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2688]", + "ldr x0, [x28, #2720]", "ldr q2, [x0, #16]", "tbl v16.16b, {v17.16b}, v2.16b", "stp xzr, xzr, [x28, #192]" @@ -1134,7 +1134,7 @@ "Map 1 0b01 0x70 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2688]", + "ldr x0, [x28, #2720]", "ldr q2, [x0, #32]", "tbl v16.16b, {v17.16b}, v2.16b", "stp xzr, xzr, [x28, #192]" @@ -1146,7 +1146,7 @@ "Map 1 0b01 0x70 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2688]", + "ldr x0, [x28, #2720]", "ldr q2, [x0, #48]", "tbl v16.16b, {v17.16b}, v2.16b", "stp xzr, xzr, [x28, #192]" @@ -1171,7 +1171,7 @@ ], "ExpectedArm64ASM": [ "ldr q2, [x28, #208]", - "ldr x0, [x28, #2688]", + "ldr x0, [x28, #2720]", "ldr q3, [x0, #16]", "tbl v16.16b, {v17.16b}, v3.16b", "tbl v2.16b, {v2.16b}, v3.16b", @@ -1185,7 +1185,7 @@ ], "ExpectedArm64ASM": [ "ldr q2, [x28, #208]", - "ldr x0, [x28, #2688]", + "ldr x0, [x28, #2720]", "ldr q3, [x0, #32]", "tbl v16.16b, {v17.16b}, v3.16b", "tbl v2.16b, {v2.16b}, v3.16b", @@ -1199,7 +1199,7 @@ ], "ExpectedArm64ASM": [ "ldr q2, [x28, #208]", - "ldr x0, [x28, #2688]", + "ldr x0, [x28, #2720]", "ldr q3, [x0, #48]", "tbl v16.16b, {v17.16b}, v3.16b", "tbl v2.16b, {v2.16b}, v3.16b", @@ -1223,7 +1223,7 @@ "Map 1 0b10 0x70 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2680]", + "ldr x0, [x28, #2712]", "ldr q2, [x0, #16]", "tbl v16.16b, {v17.16b}, v2.16b", "stp xzr, xzr, [x28, #192]" @@ -1235,7 +1235,7 @@ "Map 1 0b10 0x70 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2680]", + "ldr x0, [x28, #2712]", "ldr q2, [x0, #32]", "tbl v16.16b, {v17.16b}, v2.16b", "stp xzr, xzr, [x28, #192]" @@ -1247,7 +1247,7 @@ "Map 1 0b10 0x70 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2680]", + "ldr x0, [x28, #2712]", "ldr q2, [x0, #48]", "tbl v16.16b, {v17.16b}, v2.16b", "stp xzr, xzr, [x28, #192]" @@ -1274,7 +1274,7 @@ ], "ExpectedArm64ASM": [ "ldr q2, [x28, #208]", - "ldr x0, [x28, #2680]", + "ldr x0, [x28, #2712]", "ldr q3, [x0, #16]", "tbl v16.16b, {v17.16b}, v3.16b", "tbl v2.16b, {v2.16b}, v3.16b", @@ -1288,7 +1288,7 @@ ], "ExpectedArm64ASM": [ "ldr q2, [x28, #208]", - "ldr x0, [x28, #2680]", + "ldr x0, [x28, #2712]", "ldr q3, [x0, #32]", "tbl v16.16b, {v17.16b}, v3.16b", "tbl v2.16b, {v2.16b}, v3.16b", @@ -1302,7 +1302,7 @@ ], "ExpectedArm64ASM": [ "ldr q2, [x28, #208]", - "ldr x0, [x28, #2680]", + "ldr x0, [x28, #2712]", "ldr q3, [x0, #48]", "tbl v16.16b, {v17.16b}, v3.16b", "tbl v2.16b, {v2.16b}, v3.16b", @@ -1326,7 +1326,7 @@ "Map 1 0b11 0x70 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2672]", + "ldr x0, [x28, #2704]", "ldr q2, [x0, #16]", "tbl v16.16b, {v17.16b}, v2.16b", "stp xzr, xzr, [x28, #192]" @@ -1338,7 +1338,7 @@ "Map 1 0b11 0x70 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2672]", + "ldr x0, [x28, #2704]", "ldr q2, [x0, #32]", "tbl v16.16b, {v17.16b}, v2.16b", "stp xzr, xzr, [x28, #192]" @@ -1350,7 +1350,7 @@ "Map 1 0b11 0x70 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2672]", + "ldr x0, [x28, #2704]", "ldr q2, [x0, #48]", "tbl v16.16b, {v17.16b}, v2.16b", "stp xzr, xzr, [x28, #192]" @@ -1377,7 +1377,7 @@ ], "ExpectedArm64ASM": [ "ldr q2, [x28, #208]", - "ldr x0, [x28, #2672]", + "ldr x0, [x28, #2704]", "ldr q3, [x0, #16]", "tbl v16.16b, {v17.16b}, v3.16b", "tbl v2.16b, {v2.16b}, v3.16b", @@ -1391,7 +1391,7 @@ ], "ExpectedArm64ASM": [ "ldr q2, [x28, #208]", - "ldr x0, [x28, #2672]", + "ldr x0, [x28, #2704]", "ldr q3, [x0, #32]", "tbl v16.16b, {v17.16b}, v3.16b", "tbl v2.16b, {v2.16b}, v3.16b", @@ -1405,7 +1405,7 @@ ], "ExpectedArm64ASM": [ "ldr q2, [x28, #208]", - "ldr x0, [x28, #2672]", + "ldr x0, [x28, #2704]", "ldr q3, [x0, #48]", "tbl v16.16b, {v17.16b}, v3.16b", "tbl v2.16b, {v2.16b}, v3.16b", @@ -2289,7 +2289,7 @@ "Map 1 0b00 0xC6 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2696]", + "ldr x0, [x28, #2728]", "ldr q2, [x0, #16]", "tbl v16.16b, {v17.16b, v18.16b}, v2.16b", "stp xzr, xzr, [x28, #192]" @@ -2303,7 +2303,7 @@ "ExpectedArm64ASM": [ "ldr q2, [x28, #208]", "ldr q3, [x28, #224]", - "ldr x0, [x28, #2696]", + "ldr x0, [x28, #2728]", "ldr q4, [x0, #16]", "tbl v16.16b, {v17.16b, v18.16b}, v4.16b", "tbl v2.16b, {v2.16b, v3.16b}, v4.16b", @@ -2316,7 +2316,7 @@ "Map 1 0b00 0xC6 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2696]", + "ldr x0, [x28, #2728]", "ldr q2, [x0, #32]", "tbl v16.16b, {v17.16b, v18.16b}, v2.16b", "stp xzr, xzr, [x28, #192]" @@ -2330,7 +2330,7 @@ "ExpectedArm64ASM": [ "ldr q2, [x28, #208]", "ldr q3, [x28, #224]", - "ldr x0, [x28, #2696]", + "ldr x0, [x28, #2728]", "ldr q4, [x0, #32]", "tbl v16.16b, {v17.16b, v18.16b}, v4.16b", "tbl v2.16b, {v2.16b, v3.16b}, v4.16b", @@ -2343,7 +2343,7 @@ "Map 1 0b00 0xC6 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2696]", + "ldr x0, [x28, #2728]", "ldr q2, [x0, #48]", "tbl v16.16b, {v17.16b, v18.16b}, v2.16b", "stp xzr, xzr, [x28, #192]" @@ -2357,7 +2357,7 @@ "ExpectedArm64ASM": [ "ldr q2, [x28, #208]", "ldr q3, [x28, #224]", - "ldr x0, [x28, #2696]", + "ldr x0, [x28, #2728]", "ldr q4, [x0, #48]", "tbl v16.16b, {v17.16b, v18.16b}, v4.16b", "tbl v2.16b, {v2.16b, v3.16b}, v4.16b", @@ -3942,7 +3942,7 @@ "Map 1 0b01 0xd0 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3120]", + "ldr q2, [x28, #3168]", "eor v2.16b, v18.16b, v2.16b", "fadd v16.2d, v17.2d, v2.2d", "stp xzr, xzr, [x28, #192]" @@ -3956,7 +3956,7 @@ "ExpectedArm64ASM": [ "ldr q2, [x28, #208]", "ldr q3, [x28, #224]", - "ldr q4, [x28, #3120]", + "ldr q4, [x28, #3168]", "eor v5.16b, v18.16b, v4.16b", "fadd v16.2d, v17.2d, v5.2d", "eor v3.16b, v3.16b, v4.16b", @@ -3970,7 +3970,7 @@ "Map 1 0b11 0xd0 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3088]", + "ldr q2, [x28, #3136]", "eor v2.16b, v18.16b, v2.16b", "fadd v16.4s, v17.4s, v2.4s", "stp xzr, xzr, [x28, #192]" @@ -3984,7 +3984,7 @@ "ExpectedArm64ASM": [ "ldr q2, [x28, #208]", "ldr q3, [x28, #224]", - "ldr q4, [x28, #3088]", + "ldr q4, [x28, #3136]", "eor v5.16b, v18.16b, v4.16b", "fadd v16.4s, v17.4s, v5.4s", "eor v3.16b, v3.16b, v4.16b", @@ -4155,7 +4155,7 @@ "Map 1 0b01 0xd7 256-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3344]", + "ldr q2, [x28, #3392]", "cmlt v3.16b, v16.16b, #0", "and v2.16b, v3.16b, v2.16b", "addp v2.16b, v2.16b, v2.16b", @@ -4171,7 +4171,7 @@ ], "ExpectedArm64ASM": [ "ldr q2, [x28, #192]", - "ldr q3, [x28, #3344]", + "ldr q3, [x28, #3392]", "cmlt v4.16b, v16.16b, #0", "and v4.16b, v4.16b, v3.16b", "addp v4.16b, v4.16b, v4.16b", diff --git a/unittests/InstructionCountCI/AVX128/VEX_map2.json b/unittests/InstructionCountCI/AVX128/VEX_map2.json index c740ff2bf..42993f2c1 100644 --- a/unittests/InstructionCountCI/AVX128/VEX_map2.json +++ b/unittests/InstructionCountCI/AVX128/VEX_map2.json @@ -1917,7 +1917,7 @@ "Map 2 0b01 0x41 256-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3056]", + "ldr q2, [x28, #3104]", "zip1 v3.8h, v2.8h, v17.8h", "zip2 v2.8h, v2.8h, v17.8h", "umin v2.4s, v3.4s, v2.4s", @@ -4485,7 +4485,7 @@ "Map 2 0b01 0x96 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3088]", + "ldr q2, [x28, #3136]", "eor v2.16b, v17.16b, v2.16b", "mov v0.16b, v2.16b", "fmla v0.4s, v16.4s, v18.4s", @@ -4502,7 +4502,7 @@ "ldr q2, [x28, #192]", "ldr q3, [x28, #208]", "ldr q4, [x28, #224]", - "ldr q5, [x28, #3088]", + "ldr q5, [x28, #3136]", "eor v6.16b, v17.16b, v5.16b", "mov v0.16b, v6.16b", "fmla v0.4s, v16.4s, v18.4s", @@ -4518,7 +4518,7 @@ "Map 2 0b01 0x96 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3120]", + "ldr q2, [x28, #3168]", "eor v2.16b, v17.16b, v2.16b", "mov v0.16b, v2.16b", "fmla v0.2d, v16.2d, v18.2d", @@ -4535,7 +4535,7 @@ "ldr q2, [x28, #192]", "ldr q3, [x28, #208]", "ldr q4, [x28, #224]", - "ldr q5, [x28, #3120]", + "ldr q5, [x28, #3168]", "eor v6.16b, v17.16b, v5.16b", "mov v0.16b, v6.16b", "fmla v0.2d, v16.2d, v18.2d", @@ -4551,7 +4551,7 @@ "Map 2 0b01 0x97 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3152]", + "ldr q2, [x28, #3200]", "eor v2.16b, v17.16b, v2.16b", "mov v0.16b, v2.16b", "fmla v0.4s, v16.4s, v18.4s", @@ -4568,7 +4568,7 @@ "ldr q2, [x28, #192]", "ldr q3, [x28, #208]", "ldr q4, [x28, #224]", - "ldr q5, [x28, #3152]", + "ldr q5, [x28, #3200]", "eor v6.16b, v17.16b, v5.16b", "mov v0.16b, v6.16b", "fmla v0.4s, v16.4s, v18.4s", @@ -4584,7 +4584,7 @@ "Map 2 0b01 0x97 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3184]", + "ldr q2, [x28, #3232]", "eor v2.16b, v17.16b, v2.16b", "mov v0.16b, v2.16b", "fmla v0.2d, v16.2d, v18.2d", @@ -4601,7 +4601,7 @@ "ldr q2, [x28, #192]", "ldr q3, [x28, #208]", "ldr q4, [x28, #224]", - "ldr q5, [x28, #3184]", + "ldr q5, [x28, #3232]", "eor v6.16b, v17.16b, v5.16b", "mov v0.16b, v6.16b", "fmla v0.2d, v16.2d, v18.2d", @@ -5541,7 +5541,7 @@ "Map 2 0b01 0xa6 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3088]", + "ldr q2, [x28, #3136]", "eor v2.16b, v18.16b, v2.16b", "mov v0.16b, v2.16b", "fmla v0.4s, v17.4s, v16.4s", @@ -5558,7 +5558,7 @@ "ldr q2, [x28, #192]", "ldr q3, [x28, #208]", "ldr q4, [x28, #224]", - "ldr q5, [x28, #3088]", + "ldr q5, [x28, #3136]", "eor v6.16b, v18.16b, v5.16b", "mov v0.16b, v6.16b", "fmla v0.4s, v17.4s, v16.4s", @@ -5574,7 +5574,7 @@ "Map 2 0b01 0xa6 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3120]", + "ldr q2, [x28, #3168]", "eor v2.16b, v18.16b, v2.16b", "mov v0.16b, v2.16b", "fmla v0.2d, v17.2d, v16.2d", @@ -5591,7 +5591,7 @@ "ldr q2, [x28, #192]", "ldr q3, [x28, #208]", "ldr q4, [x28, #224]", - "ldr q5, [x28, #3120]", + "ldr q5, [x28, #3168]", "eor v6.16b, v18.16b, v5.16b", "mov v0.16b, v6.16b", "fmla v0.2d, v17.2d, v16.2d", @@ -5607,7 +5607,7 @@ "Map 2 0b01 0xa7 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3152]", + "ldr q2, [x28, #3200]", "eor v2.16b, v18.16b, v2.16b", "mov v0.16b, v2.16b", "fmla v0.4s, v17.4s, v16.4s", @@ -5624,7 +5624,7 @@ "ldr q2, [x28, #192]", "ldr q3, [x28, #208]", "ldr q4, [x28, #224]", - "ldr q5, [x28, #3152]", + "ldr q5, [x28, #3200]", "eor v6.16b, v18.16b, v5.16b", "mov v0.16b, v6.16b", "fmla v0.4s, v17.4s, v16.4s", @@ -5640,7 +5640,7 @@ "Map 2 0b01 0xa7 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3184]", + "ldr q2, [x28, #3232]", "eor v2.16b, v18.16b, v2.16b", "mov v0.16b, v2.16b", "fmla v0.2d, v17.2d, v16.2d", @@ -5657,7 +5657,7 @@ "ldr q2, [x28, #192]", "ldr q3, [x28, #208]", "ldr q4, [x28, #224]", - "ldr q5, [x28, #3184]", + "ldr q5, [x28, #3232]", "eor v6.16b, v18.16b, v5.16b", "mov v0.16b, v6.16b", "fmla v0.2d, v17.2d, v16.2d", @@ -5673,7 +5673,7 @@ "Map 2 0b01 0xb6 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3088]", + "ldr q2, [x28, #3136]", "eor v2.16b, v16.16b, v2.16b", "mov v16.16b, v2.16b", "fmla v16.4s, v17.4s, v18.4s", @@ -5689,7 +5689,7 @@ "ldr q2, [x28, #192]", "ldr q3, [x28, #208]", "ldr q4, [x28, #224]", - "ldr q5, [x28, #3088]", + "ldr q5, [x28, #3136]", "eor v6.16b, v16.16b, v5.16b", "mov v16.16b, v6.16b", "fmla v16.4s, v17.4s, v18.4s", @@ -5704,7 +5704,7 @@ "Map 2 0b01 0xb6 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3120]", + "ldr q2, [x28, #3168]", "eor v2.16b, v16.16b, v2.16b", "mov v16.16b, v2.16b", "fmla v16.2d, v17.2d, v18.2d", @@ -5720,7 +5720,7 @@ "ldr q2, [x28, #192]", "ldr q3, [x28, #208]", "ldr q4, [x28, #224]", - "ldr q5, [x28, #3120]", + "ldr q5, [x28, #3168]", "eor v6.16b, v16.16b, v5.16b", "mov v16.16b, v6.16b", "fmla v16.2d, v17.2d, v18.2d", @@ -5735,7 +5735,7 @@ "Map 2 0b01 0xb7 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3152]", + "ldr q2, [x28, #3200]", "eor v2.16b, v16.16b, v2.16b", "mov v16.16b, v2.16b", "fmla v16.4s, v17.4s, v18.4s", @@ -5751,7 +5751,7 @@ "ldr q2, [x28, #192]", "ldr q3, [x28, #208]", "ldr q4, [x28, #224]", - "ldr q5, [x28, #3152]", + "ldr q5, [x28, #3200]", "eor v6.16b, v16.16b, v5.16b", "mov v16.16b, v6.16b", "fmla v16.4s, v17.4s, v18.4s", @@ -5766,7 +5766,7 @@ "Map 2 0b01 0xb7 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3184]", + "ldr q2, [x28, #3232]", "eor v2.16b, v16.16b, v2.16b", "mov v16.16b, v2.16b", "fmla v16.2d, v17.2d, v18.2d", @@ -5782,7 +5782,7 @@ "ldr q2, [x28, #192]", "ldr q3, [x28, #208]", "ldr q4, [x28, #224]", - "ldr q5, [x28, #3184]", + "ldr q5, [x28, #3232]", "eor v6.16b, v16.16b, v5.16b", "mov v16.16b, v6.16b", "fmla v16.2d, v17.2d, v18.2d", diff --git a/unittests/InstructionCountCI/AVX128/VEX_map2_SVE128.json b/unittests/InstructionCountCI/AVX128/VEX_map2_SVE128.json index 573447f6a..b6e904f79 100644 --- a/unittests/InstructionCountCI/AVX128/VEX_map2_SVE128.json +++ b/unittests/InstructionCountCI/AVX128/VEX_map2_SVE128.json @@ -2843,7 +2843,7 @@ "Map 2 0b01 0x96 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3088]", + "ldr q2, [x28, #3136]", "eor v2.16b, v17.16b, v2.16b", "mov v0.16b, v2.16b", "fmla v0.4s, v16.4s, v18.4s", @@ -2860,7 +2860,7 @@ "ldr q2, [x28, #192]", "ldr q3, [x28, #208]", "ldr q4, [x28, #224]", - "ldr q5, [x28, #3088]", + "ldr q5, [x28, #3136]", "eor v6.16b, v17.16b, v5.16b", "mov v0.16b, v6.16b", "fmla v0.4s, v16.4s, v18.4s", @@ -2876,7 +2876,7 @@ "Map 2 0b01 0x96 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3120]", + "ldr q2, [x28, #3168]", "eor v2.16b, v17.16b, v2.16b", "mov v0.16b, v2.16b", "fmla v0.2d, v16.2d, v18.2d", @@ -2893,7 +2893,7 @@ "ldr q2, [x28, #192]", "ldr q3, [x28, #208]", "ldr q4, [x28, #224]", - "ldr q5, [x28, #3120]", + "ldr q5, [x28, #3168]", "eor v6.16b, v17.16b, v5.16b", "mov v0.16b, v6.16b", "fmla v0.2d, v16.2d, v18.2d", @@ -2909,7 +2909,7 @@ "Map 2 0b01 0x97 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3152]", + "ldr q2, [x28, #3200]", "eor v2.16b, v17.16b, v2.16b", "mov v0.16b, v2.16b", "fmla v0.4s, v16.4s, v18.4s", @@ -2926,7 +2926,7 @@ "ldr q2, [x28, #192]", "ldr q3, [x28, #208]", "ldr q4, [x28, #224]", - "ldr q5, [x28, #3152]", + "ldr q5, [x28, #3200]", "eor v6.16b, v17.16b, v5.16b", "mov v0.16b, v6.16b", "fmla v0.4s, v16.4s, v18.4s", @@ -2942,7 +2942,7 @@ "Map 2 0b01 0x97 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3184]", + "ldr q2, [x28, #3232]", "eor v2.16b, v17.16b, v2.16b", "mov v0.16b, v2.16b", "fmla v0.2d, v16.2d, v18.2d", @@ -2959,7 +2959,7 @@ "ldr q2, [x28, #192]", "ldr q3, [x28, #208]", "ldr q4, [x28, #224]", - "ldr q5, [x28, #3184]", + "ldr q5, [x28, #3232]", "eor v6.16b, v17.16b, v5.16b", "mov v0.16b, v6.16b", "fmla v0.2d, v16.2d, v18.2d", @@ -3879,7 +3879,7 @@ "Map 2 0b01 0xa6 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3088]", + "ldr q2, [x28, #3136]", "eor v2.16b, v18.16b, v2.16b", "mov v0.16b, v2.16b", "fmla v0.4s, v17.4s, v16.4s", @@ -3896,7 +3896,7 @@ "ldr q2, [x28, #192]", "ldr q3, [x28, #208]", "ldr q4, [x28, #224]", - "ldr q5, [x28, #3088]", + "ldr q5, [x28, #3136]", "eor v6.16b, v18.16b, v5.16b", "mov v0.16b, v6.16b", "fmla v0.4s, v17.4s, v16.4s", @@ -3912,7 +3912,7 @@ "Map 2 0b01 0xa6 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3120]", + "ldr q2, [x28, #3168]", "eor v2.16b, v18.16b, v2.16b", "mov v0.16b, v2.16b", "fmla v0.2d, v17.2d, v16.2d", @@ -3929,7 +3929,7 @@ "ldr q2, [x28, #192]", "ldr q3, [x28, #208]", "ldr q4, [x28, #224]", - "ldr q5, [x28, #3120]", + "ldr q5, [x28, #3168]", "eor v6.16b, v18.16b, v5.16b", "mov v0.16b, v6.16b", "fmla v0.2d, v17.2d, v16.2d", @@ -3945,7 +3945,7 @@ "Map 2 0b01 0xa7 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3152]", + "ldr q2, [x28, #3200]", "eor v2.16b, v18.16b, v2.16b", "mov v0.16b, v2.16b", "fmla v0.4s, v17.4s, v16.4s", @@ -3962,7 +3962,7 @@ "ldr q2, [x28, #192]", "ldr q3, [x28, #208]", "ldr q4, [x28, #224]", - "ldr q5, [x28, #3152]", + "ldr q5, [x28, #3200]", "eor v6.16b, v18.16b, v5.16b", "mov v0.16b, v6.16b", "fmla v0.4s, v17.4s, v16.4s", @@ -3978,7 +3978,7 @@ "Map 2 0b01 0xa7 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3184]", + "ldr q2, [x28, #3232]", "eor v2.16b, v18.16b, v2.16b", "mov v0.16b, v2.16b", "fmla v0.2d, v17.2d, v16.2d", @@ -3995,7 +3995,7 @@ "ldr q2, [x28, #192]", "ldr q3, [x28, #208]", "ldr q4, [x28, #224]", - "ldr q5, [x28, #3184]", + "ldr q5, [x28, #3232]", "eor v6.16b, v18.16b, v5.16b", "mov v0.16b, v6.16b", "fmla v0.2d, v17.2d, v16.2d", @@ -4011,7 +4011,7 @@ "Map 2 0b01 0xb6 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3088]", + "ldr q2, [x28, #3136]", "eor v2.16b, v16.16b, v2.16b", "mov v16.16b, v2.16b", "fmla v16.4s, v17.4s, v18.4s", @@ -4027,7 +4027,7 @@ "ldr q2, [x28, #192]", "ldr q3, [x28, #208]", "ldr q4, [x28, #224]", - "ldr q5, [x28, #3088]", + "ldr q5, [x28, #3136]", "eor v6.16b, v16.16b, v5.16b", "mov v16.16b, v6.16b", "fmla v16.4s, v17.4s, v18.4s", @@ -4042,7 +4042,7 @@ "Map 2 0b01 0xb6 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3120]", + "ldr q2, [x28, #3168]", "eor v2.16b, v16.16b, v2.16b", "mov v16.16b, v2.16b", "fmla v16.2d, v17.2d, v18.2d", @@ -4058,7 +4058,7 @@ "ldr q2, [x28, #192]", "ldr q3, [x28, #208]", "ldr q4, [x28, #224]", - "ldr q5, [x28, #3120]", + "ldr q5, [x28, #3168]", "eor v6.16b, v16.16b, v5.16b", "mov v16.16b, v6.16b", "fmla v16.2d, v17.2d, v18.2d", @@ -4073,7 +4073,7 @@ "Map 2 0b01 0xb7 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3152]", + "ldr q2, [x28, #3200]", "eor v2.16b, v16.16b, v2.16b", "mov v16.16b, v2.16b", "fmla v16.4s, v17.4s, v18.4s", @@ -4089,7 +4089,7 @@ "ldr q2, [x28, #192]", "ldr q3, [x28, #208]", "ldr q4, [x28, #224]", - "ldr q5, [x28, #3152]", + "ldr q5, [x28, #3200]", "eor v6.16b, v16.16b, v5.16b", "mov v16.16b, v6.16b", "fmla v16.4s, v17.4s, v18.4s", @@ -4104,7 +4104,7 @@ "Map 2 0b01 0xb7 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3184]", + "ldr q2, [x28, #3232]", "eor v2.16b, v16.16b, v2.16b", "mov v16.16b, v2.16b", "fmla v16.2d, v17.2d, v18.2d", @@ -4120,7 +4120,7 @@ "ldr q2, [x28, #192]", "ldr q3, [x28, #208]", "ldr q4, [x28, #224]", - "ldr q5, [x28, #3184]", + "ldr q5, [x28, #3232]", "eor v6.16b, v16.16b, v5.16b", "mov v16.16b, v6.16b", "fmla v16.2d, v17.2d, v18.2d", diff --git a/unittests/InstructionCountCI/AVX128/VEX_map3.json b/unittests/InstructionCountCI/AVX128/VEX_map3.json index f83d508fc..9aae1135c 100644 --- a/unittests/InstructionCountCI/AVX128/VEX_map3.json +++ b/unittests/InstructionCountCI/AVX128/VEX_map3.json @@ -337,7 +337,7 @@ "Map 3 0b01 0x02 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3248]", + "ldr q2, [x28, #3296]", "tbx v16.16b, {v17.16b}, v2.16b", "stp xzr, xzr, [x28, #192]" ] @@ -348,7 +348,7 @@ "Map 3 0b01 0x02 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3264]", + "ldr q2, [x28, #3312]", "tbx v16.16b, {v17.16b}, v2.16b", "stp xzr, xzr, [x28, #192]" ] @@ -369,7 +369,7 @@ "Map 3 0b01 0x02 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3280]", + "ldr q2, [x28, #3328]", "tbx v16.16b, {v17.16b}, v2.16b", "stp xzr, xzr, [x28, #192]" ] @@ -391,7 +391,7 @@ "Map 3 0b01 0x02 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3296]", + "ldr q2, [x28, #3344]", "tbx v16.16b, {v17.16b}, v2.16b", "stp xzr, xzr, [x28, #192]" ] @@ -412,7 +412,7 @@ "Map 3 0b01 0x02 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3312]", + "ldr q2, [x28, #3360]", "tbx v16.16b, {v17.16b}, v2.16b", "stp xzr, xzr, [x28, #192]" ] @@ -423,7 +423,7 @@ "Map 3 0b01 0x02 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3328]", + "ldr q2, [x28, #3376]", "tbx v16.16b, {v17.16b}, v2.16b", "stp xzr, xzr, [x28, #192]" ] @@ -3493,7 +3493,7 @@ ], "ExpectedArm64ASM": [ "movi v2.2d, #0x0", - "ldr q3, [x28, #3232]", + "ldr q3, [x28, #3280]", "mov v16.16b, v17.16b", "aese v16.16b, v2.16b", "tbl v16.16b, {v16.16b}, v3.16b", @@ -3507,7 +3507,7 @@ ], "ExpectedArm64ASM": [ "movi v2.2d, #0x0", - "ldr q3, [x28, #3232]", + "ldr q3, [x28, #3280]", "mov v16.16b, v17.16b", "aese v16.16b, v2.16b", "tbl v16.16b, {v16.16b}, v3.16b", diff --git a/unittests/InstructionCountCI/Crypto/H0F38.json b/unittests/InstructionCountCI/Crypto/H0F38.json index 0b306c561..c37ffaa84 100644 --- a/unittests/InstructionCountCI/Crypto/H0F38.json +++ b/unittests/InstructionCountCI/Crypto/H0F38.json @@ -31,7 +31,7 @@ "0x66 0x0f 0x38 0xca" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2688]", + "ldr x0, [x28, #2720]", "ldr q2, [x0, #432]", "tbl v3.16b, {v16.16b}, v2.16b", "tbl v4.16b, {v17.16b}, v2.16b", diff --git a/unittests/InstructionCountCI/Crypto/H0F3A.json b/unittests/InstructionCountCI/Crypto/H0F3A.json index 525ed59e6..207cc5c0a 100644 --- a/unittests/InstructionCountCI/Crypto/H0F3A.json +++ b/unittests/InstructionCountCI/Crypto/H0F3A.json @@ -55,7 +55,7 @@ "0x66 0x0f 0x3a 0xdf" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3232]", + "ldr q2, [x28, #3280]", "movi v3.2d, #0x0", "mov v16.16b, v17.16b", "aese v16.16b, v3.16b", @@ -68,7 +68,7 @@ "0x66 0x0f 0x3a 0xdf" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3232]", + "ldr q2, [x28, #3280]", "movi v3.2d, #0x0", "mov v16.16b, v17.16b", "aese v16.16b, v3.16b", @@ -84,9 +84,9 @@ "0x66 0x0f 0x3a 0xcc" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3616]", + "ldr q2, [x28, #3664]", "movi v3.2d, #0x0", - "ldr x0, [x28, #2688]", + "ldr x0, [x28, #2720]", "ldr q4, [x0, #432]", "tbl v5.16b, {v16.16b}, v4.16b", "tbl v6.16b, {v17.16b}, v4.16b", @@ -101,9 +101,9 @@ "0x66 0x0f 0x3a 0xcc" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3632]", + "ldr q2, [x28, #3680]", "movi v3.2d, #0x0", - "ldr x0, [x28, #2688]", + "ldr x0, [x28, #2720]", "ldr q4, [x0, #432]", "tbl v5.16b, {v16.16b}, v4.16b", "tbl v6.16b, {v17.16b}, v4.16b", @@ -118,9 +118,9 @@ "0x66 0x0f 0x3a 0xcc" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3648]", + "ldr q2, [x28, #3696]", "movi v3.2d, #0x0", - "ldr x0, [x28, #2688]", + "ldr x0, [x28, #2720]", "ldr q4, [x0, #432]", "tbl v5.16b, {v16.16b}, v4.16b", "tbl v6.16b, {v17.16b}, v4.16b", @@ -135,9 +135,9 @@ "0x66 0x0f 0x3a 0xcc" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3664]", + "ldr q2, [x28, #3712]", "movi v3.2d, #0x0", - "ldr x0, [x28, #2688]", + "ldr x0, [x28, #2720]", "ldr q4, [x0, #432]", "tbl v5.16b, {v16.16b}, v4.16b", "tbl v6.16b, {v17.16b}, v4.16b", diff --git a/unittests/InstructionCountCI/FlagM/HotBlocks.json b/unittests/InstructionCountCI/FlagM/HotBlocks.json index 1e73005ff..00df113f4 100644 --- a/unittests/InstructionCountCI/FlagM/HotBlocks.json +++ b/unittests/InstructionCountCI/FlagM/HotBlocks.json @@ -895,8 +895,8 @@ "mov v0.16b, v16.16b", "mov v1.16b, v17.16b", "mov w0, #0xd", - "ldr x1, [x28, #2344]", - "ldr x3, [x28, #2352]", + "ldr x1, [x28, #2376]", + "ldr x3, [x28, #2384]", "blr x1", "ldr x30, [sp], #16", "mov w20, w0", diff --git a/unittests/InstructionCountCI/FlagM/Secondary.json b/unittests/InstructionCountCI/FlagM/Secondary.json index 150bd20bd..4e3aa8267 100644 --- a/unittests/InstructionCountCI/FlagM/Secondary.json +++ b/unittests/InstructionCountCI/FlagM/Secondary.json @@ -1608,7 +1608,7 @@ "mov w20, #0xffff", "strb w20, [x28, #1202]", "ldr d2, [x28, #1056]", - "ldr d3, [x28, #3344]", + "ldr d3, [x28, #3392]", "cmlt v2.16b, v2.16b, #0", "and v2.8b, v2.8b, v3.8b", "addp v2.16b, v2.16b, v2.16b", diff --git a/unittests/InstructionCountCI/FlagM/Secondary_OpSize.json b/unittests/InstructionCountCI/FlagM/Secondary_OpSize.json index c5ddb4d3c..16bcda967 100644 --- a/unittests/InstructionCountCI/FlagM/Secondary_OpSize.json +++ b/unittests/InstructionCountCI/FlagM/Secondary_OpSize.json @@ -37,7 +37,7 @@ "ExpectedInstructionCount": 7, "Comment": "0x66 0x0f 0xd7", "ExpectedArm64ASM": [ - "ldr q2, [x28, #3344]", + "ldr q2, [x28, #3392]", "cmlt v3.16b, v16.16b, #0", "and v2.16b, v3.16b, v2.16b", "addp v2.16b, v2.16b, v2.16b", diff --git a/unittests/InstructionCountCI/FlagM/VEX_map1.json b/unittests/InstructionCountCI/FlagM/VEX_map1.json index 0c1ad3cda..188cc5044 100644 --- a/unittests/InstructionCountCI/FlagM/VEX_map1.json +++ b/unittests/InstructionCountCI/FlagM/VEX_map1.json @@ -68,7 +68,7 @@ "Map 1 0b01 0xd7 256-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3344]", + "ldr q2, [x28, #3392]", "cmlt v3.16b, v16.16b, #0", "and v2.16b, v3.16b, v2.16b", "addp v2.16b, v2.16b, v2.16b", @@ -83,7 +83,7 @@ "Map 1 0b01 0xd7 256-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2504]", + "ldr x0, [x28, #2536]", "ld1b {z2.b}, p7/z, [x0]", "mrs x0, nzcv", "mov z0.d, #0", diff --git a/unittests/InstructionCountCI/FlagM/x87-HalfLife.json b/unittests/InstructionCountCI/FlagM/x87-HalfLife.json index 1d6fcfa58..9b98b98d7 100644 --- a/unittests/InstructionCountCI/FlagM/x87-HalfLife.json +++ b/unittests/InstructionCountCI/FlagM/x87-HalfLife.json @@ -557,7 +557,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", - "ldr q3, [x28, #3600]", + "ldr q3, [x28, #3648]", "bic v2.16b, v2.16b, v3.16b", "ldr s3, [x4]", "str x30, [sp, #-16]!", @@ -567,7 +567,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v3.16b, v0.16b", - "ldr q4, [x28, #3600]", + "ldr q4, [x28, #3648]", "bic v3.16b, v3.16b, v4.16b", "strb wzr, [x28, #1049]", "str x30, [sp, #-16]!", @@ -598,7 +598,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", - "ldr q3, [x28, #3600]", + "ldr q3, [x28, #3648]", "bic v2.16b, v2.16b, v3.16b", "ldr s3, [x4, #4]", "str x30, [sp, #-16]!", @@ -608,7 +608,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v3.16b, v0.16b", - "ldr q5, [x28, #3600]", + "ldr q5, [x28, #3648]", "bic v3.16b, v3.16b, v5.16b", "strb wzr, [x28, #1049]", "str x30, [sp, #-16]!", @@ -639,7 +639,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", - "ldr q3, [x28, #3600]", + "ldr q3, [x28, #3648]", "bic v2.16b, v2.16b, v3.16b", "ldr s3, [x4, #8]", "str x30, [sp, #-16]!", @@ -649,7 +649,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v3.16b, v0.16b", - "ldr q6, [x28, #3600]", + "ldr q6, [x28, #3648]", "bic v3.16b, v3.16b, v6.16b", "strb wzr, [x28, #1049]", "str x30, [sp, #-16]!", diff --git a/unittests/InstructionCountCI/FlagM/x87-Oblivion.json b/unittests/InstructionCountCI/FlagM/x87-Oblivion.json index 66dab58db..5ea94aa08 100644 --- a/unittests/InstructionCountCI/FlagM/x87-Oblivion.json +++ b/unittests/InstructionCountCI/FlagM/x87-Oblivion.json @@ -3789,7 +3789,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", - "ldr q9, [x28, #3600]", + "ldr q9, [x28, #3648]", "eor v2.16b, v2.16b, v9.16b", "str x30, [sp, #-16]!", "mov v0.16b, v2.16b", @@ -3839,7 +3839,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", - "ldr q9, [x28, #3600]", + "ldr q9, [x28, #3648]", "eor v2.16b, v2.16b, v9.16b", "ldr s9, [x8, #28]", "str x30, [sp, #-16]!", @@ -4002,7 +4002,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", - "ldr q9, [x28, #3600]", + "ldr q9, [x28, #3648]", "eor v2.16b, v2.16b, v9.16b", "str x30, [sp, #-16]!", "mov v0.16b, v2.16b", @@ -4052,7 +4052,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", - "ldr q9, [x28, #3600]", + "ldr q9, [x28, #3648]", "eor v2.16b, v2.16b, v9.16b", "ldr s9, [x8, #60]", "str x30, [sp, #-16]!", @@ -4238,7 +4238,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", - "ldr q9, [x28, #3600]", + "ldr q9, [x28, #3648]", "eor v2.16b, v2.16b, v9.16b", "str x30, [sp, #-16]!", "mov v0.16b, v2.16b", @@ -4259,7 +4259,7 @@ "ldr x30, [sp], #16", "mov v9.16b, v0.16b", "str s2, [x8, #176]", - "ldr q2, [x28, #3600]", + "ldr q2, [x28, #3648]", "eor v2.16b, v9.16b, v2.16b", "ldr s9, [x8, #8]", "str x30, [sp, #-16]!", @@ -7530,7 +7530,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v8.16b, v0.16b", - "ldr q10, [x28, #3600]", + "ldr q10, [x28, #3648]", "eor v8.16b, v8.16b, v10.16b", "str x30, [sp, #-16]!", "mov v0.16b, v8.16b", @@ -7621,7 +7621,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v8.16b, v0.16b", - "ldr q11, [x28, #3600]", + "ldr q11, [x28, #3648]", "eor v8.16b, v8.16b, v11.16b", "str x30, [sp, #-16]!", "mov v0.16b, v8.16b", @@ -7679,7 +7679,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v8.16b, v0.16b", - "ldr q11, [x28, #3600]", + "ldr q11, [x28, #3648]", "eor v8.16b, v8.16b, v11.16b", "str x30, [sp, #-16]!", "mov v0.16b, v8.16b", @@ -7952,7 +7952,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v7.16b, v0.16b", - "ldr q9, [x28, #3600]", + "ldr q9, [x28, #3648]", "eor v7.16b, v7.16b, v9.16b", "str x30, [sp, #-16]!", "mov v0.16b, v7.16b", @@ -8112,7 +8112,7 @@ "ldr x30, [sp], #16", "fmov s2, s0", "str s2, [x4, #1024]", - "ldr q2, [x28, #3600]", + "ldr q2, [x28, #3648]", "eor v2.16b, v3.16b, v2.16b", "str x30, [sp, #-16]!", "mov v0.16b, v2.16b", @@ -8130,7 +8130,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", - "ldr q3, [x28, #3600]", + "ldr q3, [x28, #3648]", "eor v2.16b, v2.16b, v3.16b", "str x30, [sp, #-16]!", "mov v0.16b, v2.16b", @@ -8141,7 +8141,7 @@ "fmov s2, s0", "str s2, [x4, #1152]", "strb wzr, [x28, #1049]", - "ldr q2, [x28, #3600]", + "ldr q2, [x28, #3648]", "eor v2.16b, v6.16b, v2.16b", "str x30, [sp, #-16]!", "mov v0.16b, v2.16b", @@ -8159,7 +8159,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", - "ldr q3, [x28, #3600]", + "ldr q3, [x28, #3648]", "eor v2.16b, v2.16b, v3.16b", "str x30, [sp, #-16]!", "mov v0.16b, v2.16b", @@ -8177,7 +8177,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", - "ldr q3, [x28, #3600]", + "ldr q3, [x28, #3648]", "eor v2.16b, v2.16b, v3.16b", "str x30, [sp, #-16]!", "mov v0.16b, v2.16b", @@ -8188,7 +8188,7 @@ "fmov s2, s0", "str s2, [x4, #1344]", "strb wzr, [x28, #1049]", - "ldr q2, [x28, #3600]", + "ldr q2, [x28, #3648]", "eor v2.16b, v11.16b, v2.16b", "str x30, [sp, #-16]!", "mov v0.16b, v2.16b", @@ -8206,7 +8206,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", - "ldr q3, [x28, #3600]", + "ldr q3, [x28, #3648]", "eor v2.16b, v2.16b, v3.16b", "str x30, [sp, #-16]!", "mov v0.16b, v2.16b", @@ -8217,7 +8217,7 @@ "fmov s2, s0", "str s2, [x4, #1472]", "strb wzr, [x28, #1049]", - "ldr q2, [x28, #3600]", + "ldr q2, [x28, #3648]", "eor v2.16b, v10.16b, v2.16b", "str x30, [sp, #-16]!", "mov v0.16b, v2.16b", @@ -8228,7 +8228,7 @@ "fmov s2, s0", "str s2, [x4, #1536]", "strb wzr, [x28, #1049]", - "ldr q2, [x28, #3600]", + "ldr q2, [x28, #3648]", "eor v2.16b, v9.16b, v2.16b", "str x30, [sp, #-16]!", "mov v0.16b, v2.16b", @@ -8239,7 +8239,7 @@ "fmov s2, s0", "str s2, [x4, #1600]", "strb wzr, [x28, #1049]", - "ldr q2, [x28, #3600]", + "ldr q2, [x28, #3648]", "eor v2.16b, v8.16b, v2.16b", "str x30, [sp, #-16]!", "mov v0.16b, v2.16b", @@ -8249,7 +8249,7 @@ "ldr x30, [sp], #16", "fmov s2, s0", "str s2, [x4, #1664]", - "ldr q2, [x28, #3600]", + "ldr q2, [x28, #3648]", "eor v2.16b, v7.16b, v2.16b", "str x30, [sp, #-16]!", "mov v0.16b, v2.16b", @@ -12538,7 +12538,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", - "ldr q3, [x28, #3600]", + "ldr q3, [x28, #3648]", "eor v3.16b, v2.16b, v3.16b", "ldr s4, [x4]", "str x30, [sp, #-16]!", @@ -12580,7 +12580,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v4.16b, v0.16b", - "ldr q5, [x28, #3600]", + "ldr q5, [x28, #3648]", "eor v5.16b, v4.16b, v5.16b", "str x30, [sp, #-16]!", "mov v0.16b, v3.16b", @@ -12615,7 +12615,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v5.16b, v0.16b", - "ldr q6, [x28, #3600]", + "ldr q6, [x28, #3648]", "eor v6.16b, v5.16b, v6.16b", "str x30, [sp, #-16]!", "mov v0.16b, v3.16b", @@ -12650,7 +12650,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v6.16b, v0.16b", - "ldr q7, [x28, #3600]", + "ldr q7, [x28, #3648]", "eor v7.16b, v6.16b, v7.16b", "str x30, [sp, #-16]!", "mov v0.16b, v3.16b", @@ -12685,7 +12685,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v7.16b, v0.16b", - "ldr q8, [x28, #3600]", + "ldr q8, [x28, #3648]", "eor v8.16b, v7.16b, v8.16b", "str x30, [sp, #-16]!", "mov v0.16b, v3.16b", @@ -12720,7 +12720,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v8.16b, v0.16b", - "ldr q9, [x28, #3600]", + "ldr q9, [x28, #3648]", "eor v9.16b, v8.16b, v9.16b", "str x30, [sp, #-16]!", "mov v0.16b, v3.16b", @@ -12755,7 +12755,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v9.16b, v0.16b", - "ldr q10, [x28, #3600]", + "ldr q10, [x28, #3648]", "eor v9.16b, v9.16b, v10.16b", "str x30, [sp, #-16]!", "mov v0.16b, v3.16b", @@ -12789,7 +12789,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v9.16b, v0.16b", - "ldr q10, [x28, #3600]", + "ldr q10, [x28, #3648]", "eor v9.16b, v9.16b, v10.16b", "str x30, [sp, #-16]!", "mov v0.16b, v3.16b", @@ -12823,7 +12823,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v9.16b, v0.16b", - "ldr q10, [x28, #3600]", + "ldr q10, [x28, #3648]", "eor v9.16b, v9.16b, v10.16b", "str x30, [sp, #-16]!", "mov v0.16b, v3.16b", @@ -20012,7 +20012,7 @@ "mov x8, x26", "str s2, [x8, #16]", "uxtb w7, w4", - "ldr q2, [x28, #3376]", + "ldr q2, [x28, #3424]", "str w7, [x8, #56]", "str x30, [sp, #-16]!", "mov v0.16b, v2.16b", @@ -21708,7 +21708,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", - "ldr q3, [x28, #3600]", + "ldr q3, [x28, #3648]", "eor v2.16b, v2.16b, v3.16b", "add x14, x28, x20, lsl #4", "ldr q3, [x14, #1056]", @@ -21763,7 +21763,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", - "ldr q5, [x28, #3600]", + "ldr q5, [x28, #3648]", "eor v2.16b, v2.16b, v5.16b", "mov w14, #0x7b90", "movk w14, #0xa7, lsl #16", @@ -21827,7 +21827,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", - "ldr q6, [x28, #3600]", + "ldr q6, [x28, #3648]", "eor v2.16b, v2.16b, v6.16b", "mov w15, #0x7b80", "movk w15, #0xa7, lsl #16", @@ -21955,7 +21955,7 @@ "fmov s7, s0", "str s7, [x8, #64]", "strb wzr, [x28, #1049]", - "ldr q7, [x28, #3600]", + "ldr q7, [x28, #3648]", "eor v7.16b, v6.16b, v7.16b", "str x30, [sp, #-16]!", "mov v0.16b, v7.16b", @@ -21979,7 +21979,7 @@ "fmov s7, s0", "str s7, [x8, #68]", "strb wzr, [x28, #1049]", - "ldr q7, [x28, #3600]", + "ldr q7, [x28, #3648]", "eor v2.16b, v2.16b, v7.16b", "str x30, [sp, #-16]!", "mov v0.16b, v5.16b", @@ -22005,7 +22005,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", - "ldr q5, [x28, #3600]", + "ldr q5, [x28, #3648]", "eor v5.16b, v2.16b, v5.16b", "ldr d7, [x15]", "str x30, [sp, #-16]!", diff --git a/unittests/InstructionCountCI/FlagM/x87-Psychonauts.json b/unittests/InstructionCountCI/FlagM/x87-Psychonauts.json index 8650f1be7..0da094095 100644 --- a/unittests/InstructionCountCI/FlagM/x87-Psychonauts.json +++ b/unittests/InstructionCountCI/FlagM/x87-Psychonauts.json @@ -10858,7 +10858,7 @@ "add w22, w20, #0x7 (7)", "and w22, w22, #0x7", "add x23, x28, x22, lsl #4", - "ldr q4, [x28, #3600]", + "ldr q4, [x28, #3648]", "eor v3.16b, v3.16b, v4.16b", "str x30, [sp, #-16]!", "mov v0.16b, v3.16b", @@ -10903,7 +10903,7 @@ "add w22, w22, #0x7 (7)", "and w22, w22, #0x7", "add x12, x28, x22, lsl #4", - "ldr q5, [x28, #3600]", + "ldr q5, [x28, #3648]", "eor v4.16b, v4.16b, v5.16b", "ldur s5, [x5, #-4]", "str x30, [sp, #-16]!", @@ -11028,7 +11028,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v5.16b, v0.16b", - "ldr q6, [x28, #3600]", + "ldr q6, [x28, #3648]", "eor v5.16b, v5.16b, v6.16b", "ldr s6, [x5, #4]", "str x30, [sp, #-16]!", @@ -12174,7 +12174,7 @@ "ldr x30, [sp], #16", "mov v4.16b, v0.16b", "ldr w9, [x8, #48]", - "ldr q5, [x28, #3600]", + "ldr q5, [x28, #3648]", "eor v4.16b, v4.16b, v5.16b", "ldr s5, [x9, #12]", "str x30, [sp, #-16]!", @@ -12302,7 +12302,7 @@ "ldr x30, [sp], #16", "mov v5.16b, v0.16b", "ldr w9, [x8, #48]", - "ldr q6, [x28, #3600]", + "ldr q6, [x28, #3648]", "eor v5.16b, v5.16b, v6.16b", "ldr s6, [x9, #4]", "str x30, [sp, #-16]!", @@ -14021,7 +14021,7 @@ "add w22, w20, #0x7 (7)", "and w22, w22, #0x7", "add x23, x28, x22, lsl #4", - "ldr q4, [x28, #3600]", + "ldr q4, [x28, #3648]", "eor v3.16b, v3.16b, v4.16b", "str x30, [sp, #-16]!", "mov v0.16b, v3.16b", @@ -22326,7 +22326,7 @@ "add w22, w22, #0x7 (7)", "and w22, w22, #0x7", "add x13, x28, x22, lsl #4", - "ldr q6, [x28, #3600]", + "ldr q6, [x28, #3648]", "eor v5.16b, v5.16b, v6.16b", "add w14, w4, w10, lsl #2", "ldur s6, [x14, #-4]", @@ -22927,7 +22927,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v5.16b, v0.16b", - "ldr q6, [x28, #3600]", + "ldr q6, [x28, #3648]", "eor v5.16b, v5.16b, v6.16b", "add w15, w4, w10, lsl #2", "ldr s6, [x15, #4]", @@ -23397,7 +23397,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v6.16b, v0.16b", - "ldr q7, [x28, #3600]", + "ldr q7, [x28, #3648]", "eor v6.16b, v6.16b, v7.16b", "str x30, [sp, #-16]!", "mov v0.16b, v5.16b", @@ -23485,7 +23485,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v5.16b, v0.16b", - "ldr q6, [x28, #3600]", + "ldr q6, [x28, #3648]", "eor v5.16b, v5.16b, v6.16b", "add w15, w4, w10, lsl #2", "ldr s6, [x15, #12]", @@ -25586,7 +25586,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v6.16b, v0.16b", - "ldr q7, [x28, #3600]", + "ldr q7, [x28, #3648]", "eor v6.16b, v6.16b, v7.16b", "str x30, [sp, #-16]!", "mov v0.16b, v5.16b", diff --git a/unittests/InstructionCountCI/FlagM/x87.json b/unittests/InstructionCountCI/FlagM/x87.json index 32e7b0afe..e600dd398 100644 --- a/unittests/InstructionCountCI/FlagM/x87.json +++ b/unittests/InstructionCountCI/FlagM/x87.json @@ -2468,7 +2468,7 @@ "ldrb w20, [x28, #1051]", "add x20, x28, x20, lsl #4", "ldr q2, [x20, #1056]", - "ldr q3, [x28, #3600]", + "ldr q3, [x28, #3648]", "eor v2.16b, v2.16b, v3.16b", "str q2, [x20, #1056]" ] @@ -2482,7 +2482,7 @@ "ldrb w20, [x28, #1051]", "add x20, x28, x20, lsl #4", "ldr q2, [x20, #1056]", - "ldr q3, [x28, #3600]", + "ldr q3, [x28, #3648]", "bic v2.16b, v2.16b, v3.16b", "str q2, [x20, #1056]" ] @@ -2548,7 +2548,7 @@ "0xd9 11b 0xe8 /5" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3376]", + "ldr q2, [x28, #3424]", "ldrb w20, [x28, #1051]", "add w20, w20, #0x7 (7)", "and w20, w20, #0x7", @@ -2568,7 +2568,7 @@ "0xd9 11b 0xe9 /5" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3392]", + "ldr q2, [x28, #3440]", "ldrb w20, [x28, #1051]", "add w20, w20, #0x7 (7)", "and w20, w20, #0x7", @@ -2588,7 +2588,7 @@ "0xd9 11b 0xea /5" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3408]", + "ldr q2, [x28, #3456]", "ldrb w20, [x28, #1051]", "add w20, w20, #0x7 (7)", "and w20, w20, #0x7", @@ -2608,7 +2608,7 @@ "0xd9 11b 0xeb /5" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3424]", + "ldr q2, [x28, #3472]", "ldrb w20, [x28, #1051]", "add w20, w20, #0x7 (7)", "and w20, w20, #0x7", @@ -2628,7 +2628,7 @@ "0xd9 11b 0xec /5" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3440]", + "ldr q2, [x28, #3488]", "ldrb w20, [x28, #1051]", "add w20, w20, #0x7 (7)", "and w20, w20, #0x7", @@ -2648,7 +2648,7 @@ "0xd9 11b 0xed /5" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3456]", + "ldr q2, [x28, #3504]", "ldrb w20, [x28, #1051]", "add w20, w20, #0x7 (7)", "and w20, w20, #0x7", @@ -2742,7 +2742,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", - "ldr q3, [x28, #3376]", + "ldr q3, [x28, #3424]", "add w20, w20, #0x7 (7)", "and w20, w20, #0x7", "strb wzr, [x28, #1050]", @@ -2773,8 +2773,8 @@ "str x30, [sp, #-16]!", "mov v0.16b, v3.16b", "mov v1.16b, v2.16b", - "ldr x0, [x28, #2104]", - "ldr x3, [x28, #2112]", + "ldr x0, [x28, #2120]", + "ldr x3, [x28, #2128]", "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", @@ -2836,8 +2836,8 @@ "str x30, [sp, #-16]!", "mov v0.16b, v3.16b", "mov v1.16b, v2.16b", - "ldr x0, [x28, #2120]", - "ldr x3, [x28, #2128]", + "ldr x0, [x28, #2136]", + "ldr x3, [x28, #2144]", "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", @@ -2885,8 +2885,8 @@ "str x30, [sp, #-16]!", "mov v0.16b, v3.16b", "mov v1.16b, v2.16b", - "ldr x0, [x28, #2136]", - "ldr x3, [x28, #2144]", + "ldr x0, [x28, #2152]", + "ldr x3, [x28, #2160]", "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", @@ -2895,38 +2895,28 @@ ] }, "fyl2xp1": { - "ExpectedInstructionCount": 27, + "ExpectedInstructionCount": 17, "Comment": [ "0xd9 11b 0xf9 /7" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3376]", "ldrb w20, [x28, #1051]", - "add x21, x28, x20, lsl #4", - "ldr q3, [x21, #1056]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x22, x28, x21, lsl #4", + "ldr q2, [x22, #1056]", + "add x20, x28, x20, lsl #4", + "ldr q3, [x20, #1056]", "str x30, [sp, #-16]!", "mov v0.16b, v3.16b", "mov v1.16b, v2.16b", - "ldr x0, [x28, #2024]", - "ldr x3, [x28, #2032]", + "ldr x0, [x28, #2104]", + "ldr x3, [x28, #2112]", "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "add x22, x28, x20, lsl #4", - "ldr q3, [x22, #1056]", - "str x30, [sp, #-16]!", - "mov v0.16b, v2.16b", - "mov v1.16b, v3.16b", - "ldr x0, [x28, #2088]", - "ldr x3, [x28, #2096]", - "blr x0", - "ldr x30, [sp], #16", - "mov v3.16b, v0.16b", - "strb w20, [x28, #1051]", - "str q3, [x22, #1056]", - "str q2, [x21, #1056]" + "strb w21, [x28, #1051]", + "str q2, [x22, #1056]" ] }, "fsqrt": { @@ -3014,8 +3004,8 @@ "str x30, [sp, #-16]!", "mov v0.16b, v3.16b", "mov v1.16b, v2.16b", - "ldr x0, [x28, #2152]", - "ldr x3, [x28, #2160]", + "ldr x0, [x28, #2168]", + "ldr x3, [x28, #2176]", "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", diff --git a/unittests/InstructionCountCI/FlagM/x87_f64.json b/unittests/InstructionCountCI/FlagM/x87_f64.json index a352f2498..2d87d3606 100644 --- a/unittests/InstructionCountCI/FlagM/x87_f64.json +++ b/unittests/InstructionCountCI/FlagM/x87_f64.json @@ -2151,7 +2151,7 @@ "add x20, x28, x20, lsl #4", "ldr d2, [x20, #1056]", "fmov d0, d2", - "ldr x0, [x28, #3008]", + "ldr x0, [x28, #3040]", "str x30, [sp, #-16]!", "blr x0", "ldr x30, [sp], #16", @@ -2174,7 +2174,7 @@ "ldr d3, [x20, #1056]", "fmov d0, d3", "fmov d1, d2", - "ldr x0, [x28, #3032]", + "ldr x0, [x28, #3064]", "str x30, [sp, #-16]!", "blr x0", "ldr x30, [sp], #16", @@ -2193,7 +2193,7 @@ "add x21, x28, x20, lsl #4", "ldr d2, [x21, #1056]", "fmov d0, d2", - "ldr x0, [x28, #3000]", + "ldr x0, [x28, #3032]", "str x30, [sp, #-16]!", "blr x0", "ldr x30, [sp], #16", @@ -2229,7 +2229,7 @@ "ldr d3, [x21, #1056]", "fmov d0, d3", "fmov d1, d2", - "ldr x0, [x28, #3024]", + "ldr x0, [x28, #3056]", "str x30, [sp, #-16]!", "blr x0", "ldr x30, [sp], #16", @@ -2301,7 +2301,7 @@ "ldr d3, [x20, #1056]", "fmov d0, d3", "fmov d1, d2", - "ldr x0, [x28, #3048]", + "ldr x0, [x28, #3088]", "str x30, [sp, #-16]!", "blr x0", "ldr x30, [sp], #16", @@ -2349,7 +2349,7 @@ "ldr d3, [x20, #1056]", "fmov d0, d3", "fmov d1, d2", - "ldr x0, [x28, #3040]", + "ldr x0, [x28, #3080]", "str x30, [sp, #-16]!", "blr x0", "ldr x30, [sp], #16", @@ -2359,31 +2359,27 @@ ] }, "fyl2xp1": { - "ExpectedInstructionCount": 20, + "ExpectedInstructionCount": 16, "Comment": [ "0xd9 11b 0xf9 /7" ], "ExpectedArm64ASM": [ - "mov x20, #0x3ff0000000000000", - "fmov d2, x20", "ldrb w20, [x28, #1051]", - "add x21, x28, x20, lsl #4", - "ldr d3, [x21, #1056]", - "fadd d2, d3, d2", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "add x22, x28, x20, lsl #4", - "ldr d3, [x22, #1056]", - "fmov d0, d2", - "fmov d1, d3", - "ldr x0, [x28, #3032]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x22, x28, x21, lsl #4", + "ldr d2, [x22, #1056]", + "add x20, x28, x20, lsl #4", + "ldr d3, [x20, #1056]", + "fmov d0, d3", + "fmov d1, d2", + "ldr x0, [x28, #3072]", "str x30, [sp, #-16]!", "blr x0", "ldr x30, [sp], #16", - "fmov d3, d0", - "strb w20, [x28, #1051]", - "str d3, [x22, #1056]", - "str d2, [x21, #1056]" + "fmov d2, d0", + "strb w21, [x28, #1051]", + "str d2, [x22, #1056]" ] }, "fsqrt": { @@ -2409,13 +2405,13 @@ "add x21, x28, x20, lsl #4", "ldr d2, [x21, #1056]", "fmov d0, d2", - "ldr x0, [x28, #2984]", + "ldr x0, [x28, #3016]", "str x30, [sp, #-16]!", "blr x0", "ldr x30, [sp], #16", "fmov d3, d0", "fmov d0, d2", - "ldr x0, [x28, #2992]", + "ldr x0, [x28, #3024]", "str x30, [sp, #-16]!", "blr x0", "ldr x30, [sp], #16", @@ -2462,7 +2458,7 @@ "ldr d3, [x20, #1056]", "fmov d0, d3", "fmov d1, d2", - "ldr x0, [x28, #3016]", + "ldr x0, [x28, #3048]", "str x30, [sp, #-16]!", "blr x0", "ldr x30, [sp], #16", @@ -2480,7 +2476,7 @@ "add x20, x28, x20, lsl #4", "ldr d2, [x20, #1056]", "fmov d0, d2", - "ldr x0, [x28, #2984]", + "ldr x0, [x28, #3016]", "str x30, [sp, #-16]!", "blr x0", "ldr x30, [sp], #16", @@ -2499,7 +2495,7 @@ "add x20, x28, x20, lsl #4", "ldr d2, [x20, #1056]", "fmov d0, d2", - "ldr x0, [x28, #2992]", + "ldr x0, [x28, #3024]", "str x30, [sp, #-16]!", "blr x0", "ldr x30, [sp], #16", diff --git a/unittests/InstructionCountCI/H0F38.json b/unittests/InstructionCountCI/H0F38.json index ea75c5d3e..bd7bbcc1d 100644 --- a/unittests/InstructionCountCI/H0F38.json +++ b/unittests/InstructionCountCI/H0F38.json @@ -685,7 +685,7 @@ "0x66 0x0f 0x38 0x41" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3056]", + "ldr q2, [x28, #3104]", "zip1 v3.8h, v2.8h, v17.8h", "zip2 v2.8h, v2.8h, v17.8h", "umin v2.4s, v3.4s, v2.4s", diff --git a/unittests/InstructionCountCI/H0F3A.json b/unittests/InstructionCountCI/H0F3A.json index 55f92cc4d..78219eede 100644 --- a/unittests/InstructionCountCI/H0F3A.json +++ b/unittests/InstructionCountCI/H0F3A.json @@ -327,7 +327,7 @@ "0x66 0x0f 0x3a 0x0c" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3248]", + "ldr q2, [x28, #3296]", "tbx v16.16b, {v17.16b}, v2.16b" ] }, @@ -337,7 +337,7 @@ "0x66 0x0f 0x3a 0x0c" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3264]", + "ldr q2, [x28, #3312]", "tbx v16.16b, {v17.16b}, v2.16b" ] }, @@ -356,7 +356,7 @@ "0x66 0x0f 0x3a 0x0c" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3280]", + "ldr q2, [x28, #3328]", "tbx v16.16b, {v17.16b}, v2.16b" ] }, @@ -376,7 +376,7 @@ "0x66 0x0f 0x3a 0x0c" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3296]", + "ldr q2, [x28, #3344]", "tbx v16.16b, {v17.16b}, v2.16b" ] }, @@ -395,7 +395,7 @@ "0x66 0x0f 0x3a 0x0c" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3312]", + "ldr q2, [x28, #3360]", "tbx v16.16b, {v17.16b}, v2.16b" ] }, @@ -405,7 +405,7 @@ "0x66 0x0f 0x3a 0x0c" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3328]", + "ldr q2, [x28, #3376]", "tbx v16.16b, {v17.16b}, v2.16b" ] }, @@ -474,7 +474,7 @@ "0x66 0x0f 0x3a 0x0e" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2720]", + "ldr x0, [x28, #2752]", "ldr q2, [x0, #3440]", "tbx v16.16b, {v17.16b}, v2.16b" ] diff --git a/unittests/InstructionCountCI/PrimaryGroup.json b/unittests/InstructionCountCI/PrimaryGroup.json index 6181e6ede..c220512fe 100644 --- a/unittests/InstructionCountCI/PrimaryGroup.json +++ b/unittests/InstructionCountCI/PrimaryGroup.json @@ -2786,7 +2786,7 @@ "mov x0, x5", "mov x1, x4", "mov x2, x6", - "ldr x3, [x28, #2968]", + "ldr x3, [x28, #3000]", "str x30, [sp, #-16]!", "blr x3", "ldr x30, [sp], #16", @@ -2837,7 +2837,7 @@ "mov x0, x5", "mov x1, x4", "mov x2, x6", - "ldr x3, [x28, #2976]", + "ldr x3, [x28, #3008]", "str x30, [sp, #-16]!", "blr x3", "ldr x30, [sp], #16", diff --git a/unittests/InstructionCountCI/SSE42_Strings.json b/unittests/InstructionCountCI/SSE42_Strings.json index 0c7eedf07..01187606d 100644 --- a/unittests/InstructionCountCI/SSE42_Strings.json +++ b/unittests/InstructionCountCI/SSE42_Strings.json @@ -42,8 +42,8 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr x3, [x28, #2328]", - "ldr x0, [x28, #2336]", + "ldr x3, [x28, #2360]", + "ldr x0, [x28, #2368]", "stp x0, x30, [sp, #-16]!", "mov x0, x4", "mov x1, x5", @@ -68,8 +68,8 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr x3, [x28, #2328]", - "ldr x0, [x28, #2336]", + "ldr x3, [x28, #2360]", + "ldr x0, [x28, #2368]", "stp x0, x30, [sp, #-16]!", "mov x0, x4", "mov x1, x5", @@ -94,8 +94,8 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr x3, [x28, #2328]", - "ldr x0, [x28, #2336]", + "ldr x3, [x28, #2360]", + "ldr x0, [x28, #2368]", "stp x0, x30, [sp, #-16]!", "mov x0, x4", "mov x1, x5", @@ -152,8 +152,8 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr x3, [x28, #2328]", - "ldr x0, [x28, #2336]", + "ldr x3, [x28, #2360]", + "ldr x0, [x28, #2368]", "stp x0, x30, [sp, #-16]!", "mov x0, x4", "mov x1, x5", @@ -194,8 +194,8 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr x3, [x28, #2328]", - "ldr x0, [x28, #2336]", + "ldr x3, [x28, #2360]", + "ldr x0, [x28, #2368]", "stp x0, x30, [sp, #-16]!", "mov x0, x4", "mov x1, x5", @@ -224,8 +224,8 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr x3, [x28, #2328]", - "ldr x0, [x28, #2336]", + "ldr x3, [x28, #2360]", + "ldr x0, [x28, #2368]", "stp x0, x30, [sp, #-16]!", "mov x0, x4", "mov x1, x5", @@ -258,8 +258,8 @@ "mov v0.16b, v16.16b", "mov v1.16b, v17.16b", "mov w0, #0x0", - "ldr x1, [x28, #2344]", - "ldr x3, [x28, #2352]", + "ldr x1, [x28, #2376]", + "ldr x3, [x28, #2384]", "blr x1", "ldr x30, [sp], #16", "mov w20, w0", @@ -282,8 +282,8 @@ "mov v0.16b, v16.16b", "mov v1.16b, v17.16b", "mov w0, #0x1", - "ldr x1, [x28, #2344]", - "ldr x3, [x28, #2352]", + "ldr x1, [x28, #2376]", + "ldr x3, [x28, #2384]", "blr x1", "ldr x30, [sp], #16", "mov w20, w0", @@ -306,8 +306,8 @@ "mov v0.16b, v16.16b", "mov v1.16b, v17.16b", "mov w0, #0x40", - "ldr x1, [x28, #2344]", - "ldr x3, [x28, #2352]", + "ldr x1, [x28, #2376]", + "ldr x3, [x28, #2384]", "blr x1", "ldr x30, [sp], #16", "mov w20, w0", @@ -362,8 +362,8 @@ "mov v0.16b, v16.16b", "mov v1.16b, v17.16b", "mov w0, #0x41", - "ldr x1, [x28, #2344]", - "ldr x3, [x28, #2352]", + "ldr x1, [x28, #2376]", + "ldr x3, [x28, #2384]", "blr x1", "ldr x30, [sp], #16", "mov w20, w0", @@ -402,8 +402,8 @@ "mov v0.16b, v16.16b", "mov v1.16b, v17.16b", "mov w0, #0x0", - "ldr x1, [x28, #2344]", - "ldr x3, [x28, #2352]", + "ldr x1, [x28, #2376]", + "ldr x3, [x28, #2384]", "blr x1", "ldr x30, [sp], #16", "mov w20, w0", @@ -430,8 +430,8 @@ "mov v0.16b, v16.16b", "mov v1.16b, v17.16b", "mov w0, #0x1", - "ldr x1, [x28, #2344]", - "ldr x3, [x28, #2352]", + "ldr x1, [x28, #2376]", + "ldr x3, [x28, #2384]", "blr x1", "ldr x30, [sp], #16", "mov w20, w0", diff --git a/unittests/InstructionCountCI/Secondary.json b/unittests/InstructionCountCI/Secondary.json index 7fb3cc633..4543a411c 100644 --- a/unittests/InstructionCountCI/Secondary.json +++ b/unittests/InstructionCountCI/Secondary.json @@ -651,7 +651,7 @@ "Comment": "0x0f 0x50", "ExpectedArm64ASM": [ "ushr v2.4s, v16.4s, #31", - "ldr q3, [x28, #3216]", + "ldr q3, [x28, #3264]", "ushl v2.4s, v2.4s, v3.4s", "addv s2, v2.4s", "mov w4, v2.s[0]" @@ -662,7 +662,7 @@ "Comment": "0x0f 0x50", "ExpectedArm64ASM": [ "ushr v2.4s, v16.4s, #31", - "ldr q3, [x28, #3216]", + "ldr q3, [x28, #3264]", "ushl v2.4s, v2.4s, v3.4s", "addv s2, v2.4s", "mov w4, v2.s[0]" @@ -3546,7 +3546,7 @@ "ExpectedInstructionCount": 3, "Comment": "0x0f 0xc6", "ExpectedArm64ASM": [ - "ldr x0, [x28, #2696]", + "ldr x0, [x28, #2728]", "ldr q2, [x0, #16]", "tbl v16.16b, {v16.16b, v17.16b}, v2.16b" ] @@ -3555,7 +3555,7 @@ "ExpectedInstructionCount": 5, "Comment": "0x0f 0xc6", "ExpectedArm64ASM": [ - "ldr x0, [x28, #2696]", + "ldr x0, [x28, #2728]", "ldr q2, [x0, #16]", "mov v0.16b, v17.16b", "mov v1.16b, v16.16b", @@ -3567,7 +3567,7 @@ "Comment": "0x0f 0xc6", "ExpectedArm64ASM": [ "ldr q2, [x4]", - "ldr x0, [x28, #2696]", + "ldr x0, [x28, #2728]", "ldr q3, [x0, #16]", "mov v0.16b, v16.16b", "mov v1.16b, v2.16b", @@ -3695,7 +3695,7 @@ "mov w20, #0xffff", "strb w20, [x28, #1202]", "ldr d2, [x28, #1056]", - "ldr d3, [x28, #3344]", + "ldr d3, [x28, #3392]", "cmlt v2.16b, v2.16b, #0", "and v2.8b, v2.8b, v3.8b", "addp v2.16b, v2.16b, v2.16b", diff --git a/unittests/InstructionCountCI/Secondary_OpSize.json b/unittests/InstructionCountCI/Secondary_OpSize.json index e7bb49f1b..27341f77f 100644 --- a/unittests/InstructionCountCI/Secondary_OpSize.json +++ b/unittests/InstructionCountCI/Secondary_OpSize.json @@ -525,7 +525,7 @@ "0x66 0x0f 0x70" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2688]", + "ldr x0, [x28, #2720]", "ldr q2, [x0, #16]", "tbl v16.16b, {v17.16b}, v2.16b" ] @@ -539,7 +539,7 @@ ], "ExpectedArm64ASM": [ "ldr q2, [x4]", - "ldr x0, [x28, #2688]", + "ldr x0, [x28, #2720]", "ldr q3, [x0, #16]", "tbl v16.16b, {v2.16b}, v3.16b" ] @@ -677,7 +677,7 @@ ], "ExpectedArm64ASM": [ "ldr q2, [x4]", - "ldr x0, [x28, #2688]", + "ldr x0, [x28, #2720]", "ldr q3, [x0, #2480]", "tbl v16.16b, {v2.16b}, v3.16b" ] @@ -1259,7 +1259,7 @@ "ExpectedInstructionCount": 3, "Comment": "0x66 0x0f 0xd0", "ExpectedArm64ASM": [ - "ldr q2, [x28, #3120]", + "ldr q2, [x28, #3168]", "eor v2.16b, v17.16b, v2.16b", "fadd v16.2d, v16.2d, v2.2d" ] @@ -1315,7 +1315,7 @@ "ExpectedInstructionCount": 7, "Comment": "0x66 0x0f 0xd7", "ExpectedArm64ASM": [ - "ldr q2, [x28, #3344]", + "ldr q2, [x28, #3392]", "cmlt v3.16b, v16.16b, #0", "and v2.16b, v3.16b, v2.16b", "addp v2.16b, v2.16b, v2.16b", diff --git a/unittests/InstructionCountCI/Secondary_REP.json b/unittests/InstructionCountCI/Secondary_REP.json index b184fd947..522cf621a 100644 --- a/unittests/InstructionCountCI/Secondary_REP.json +++ b/unittests/InstructionCountCI/Secondary_REP.json @@ -118,7 +118,7 @@ "ExpectedArm64ASM": [ "fcvtzs w20, s16", "mov w21, #0x80000000", - "ldr s2, [x28, #3472]", + "ldr s2, [x28, #3520]", "mrs x22, nzcv", "fcmp s2, s16", "csel w4, w20, w21, gt", @@ -132,7 +132,7 @@ "ldr s2, [x6]", "fcvtzs w20, s2", "mov w21, #0x80000000", - "ldr s3, [x28, #3472]", + "ldr s3, [x28, #3520]", "mrs x22, nzcv", "fcmp s3, s2", "csel w4, w20, w21, gt", @@ -145,7 +145,7 @@ "ExpectedArm64ASM": [ "fcvtzs x20, s16", "mov x21, #0x8000000000000000", - "ldr s2, [x28, #3504]", + "ldr s2, [x28, #3552]", "mrs x22, nzcv", "fcmp s2, s16", "csel x4, x20, x21, gt", @@ -159,7 +159,7 @@ "ldr s2, [x6]", "fcvtzs x20, s2", "mov x21, #0x8000000000000000", - "ldr s3, [x28, #3504]", + "ldr s3, [x28, #3552]", "mrs x22, nzcv", "fcmp s3, s2", "csel x4, x20, x21, gt", @@ -173,7 +173,7 @@ "frinti s2, s16", "fcvtzs w20, s2", "mov w21, #0x80000000", - "ldr s3, [x28, #3472]", + "ldr s3, [x28, #3520]", "mrs x22, nzcv", "fcmp s3, s2", "csel w4, w20, w21, gt", @@ -188,7 +188,7 @@ "frinti s2, s2", "fcvtzs w20, s2", "mov w21, #0x80000000", - "ldr s3, [x28, #3472]", + "ldr s3, [x28, #3520]", "mrs x22, nzcv", "fcmp s3, s2", "csel w4, w20, w21, gt", @@ -202,7 +202,7 @@ "frinti s2, s16", "fcvtzs x20, s2", "mov x21, #0x8000000000000000", - "ldr s3, [x28, #3504]", + "ldr s3, [x28, #3552]", "mrs x22, nzcv", "fcmp s3, s2", "csel x4, x20, x21, gt", @@ -217,7 +217,7 @@ "frinti s2, s2", "fcvtzs x20, s2", "mov x21, #0x8000000000000000", - "ldr s3, [x28, #3504]", + "ldr s3, [x28, #3552]", "mrs x22, nzcv", "fcmp s3, s2", "csel x4, x20, x21, gt", @@ -296,8 +296,8 @@ "ExpectedInstructionCount": 6, "Comment": "0xf3 0x0f 0x5b", "ExpectedArm64ASM": [ - "ldr q2, [x28, #3568]", - "ldr q3, [x28, #3472]", + "ldr q2, [x28, #3616]", + "ldr q3, [x28, #3520]", "fcvtzs v4.4s, v17.4s", "fcmgt v3.4s, v3.4s, v17.4s", "mov v16.16b, v3.16b", @@ -397,7 +397,7 @@ "0xf3 0x0f 0x70" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2680]", + "ldr x0, [x28, #2712]", "ldr q2, [x0, #1280]", "tbl v16.16b, {v17.16b}, v2.16b" ] @@ -410,7 +410,7 @@ "0xf3 0x0f 0x70" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2680]", + "ldr x0, [x28, #2712]", "ldr q2, [x0, #16]", "tbl v16.16b, {v17.16b}, v2.16b" ] diff --git a/unittests/InstructionCountCI/Secondary_REPNE.json b/unittests/InstructionCountCI/Secondary_REPNE.json index 2c07fef7f..ab2eb0678 100644 --- a/unittests/InstructionCountCI/Secondary_REPNE.json +++ b/unittests/InstructionCountCI/Secondary_REPNE.json @@ -290,7 +290,7 @@ "0xf2 0x0f 0x70" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2672]", + "ldr x0, [x28, #2704]", "ldr q2, [x0, #1280]", "tbl v16.16b, {v17.16b}, v2.16b" ] @@ -303,7 +303,7 @@ "0xf2 0x0f 0x70" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2672]", + "ldr x0, [x28, #2704]", "ldr q2, [x0, #16]", "tbl v16.16b, {v17.16b}, v2.16b" ] @@ -503,7 +503,7 @@ "ExpectedInstructionCount": 3, "Comment": "0xf2 0x0f 0xd0", "ExpectedArm64ASM": [ - "ldr q2, [x28, #3088]", + "ldr q2, [x28, #3136]", "eor v2.16b, v17.16b, v2.16b", "fadd v16.4s, v16.4s, v2.4s" ] diff --git a/unittests/InstructionCountCI/VEX_map1.json b/unittests/InstructionCountCI/VEX_map1.json index 8b4a76254..176f5f94b 100644 --- a/unittests/InstructionCountCI/VEX_map1.json +++ b/unittests/InstructionCountCI/VEX_map1.json @@ -1064,7 +1064,7 @@ "Map 1 0b01 0x70 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2688]", + "ldr x0, [x28, #2720]", "ldr q2, [x0, #16]", "tbl v16.16b, {v17.16b}, v2.16b" ] @@ -1075,7 +1075,7 @@ "Map 1 0b01 0x70 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2688]", + "ldr x0, [x28, #2720]", "ldr q2, [x0, #32]", "tbl v16.16b, {v17.16b}, v2.16b" ] @@ -1086,7 +1086,7 @@ "Map 1 0b01 0x70 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2688]", + "ldr x0, [x28, #2720]", "ldr q2, [x0, #48]", "tbl v16.16b, {v17.16b}, v2.16b" ] @@ -1122,7 +1122,7 @@ ], "ExpectedArm64ASM": [ "mov z2.q, z17.q[1]", - "ldr x0, [x28, #2688]", + "ldr x0, [x28, #2720]", "ldr q3, [x0, #16]", "tbl v2.16b, {v2.16b}, v3.16b", "tbl v3.16b, {v17.16b}, v3.16b", @@ -1139,7 +1139,7 @@ ], "ExpectedArm64ASM": [ "mov z2.q, z17.q[1]", - "ldr x0, [x28, #2688]", + "ldr x0, [x28, #2720]", "ldr q3, [x0, #32]", "tbl v2.16b, {v2.16b}, v3.16b", "tbl v3.16b, {v17.16b}, v3.16b", @@ -1156,7 +1156,7 @@ ], "ExpectedArm64ASM": [ "mov z2.q, z17.q[1]", - "ldr x0, [x28, #2688]", + "ldr x0, [x28, #2720]", "ldr q3, [x0, #48]", "tbl v2.16b, {v2.16b}, v3.16b", "tbl v3.16b, {v17.16b}, v3.16b", @@ -1195,7 +1195,7 @@ "Map 1 0b10 0x70 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2680]", + "ldr x0, [x28, #2712]", "ldr q2, [x0, #16]", "tbl v16.16b, {v17.16b}, v2.16b" ] @@ -1206,7 +1206,7 @@ "Map 1 0b10 0x70 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2680]", + "ldr x0, [x28, #2712]", "ldr q2, [x0, #32]", "tbl v16.16b, {v17.16b}, v2.16b" ] @@ -1217,7 +1217,7 @@ "Map 1 0b10 0x70 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2680]", + "ldr x0, [x28, #2712]", "ldr q2, [x0, #48]", "tbl v16.16b, {v17.16b}, v2.16b" ] @@ -1255,7 +1255,7 @@ ], "ExpectedArm64ASM": [ "mov z2.q, z17.q[1]", - "ldr x0, [x28, #2680]", + "ldr x0, [x28, #2712]", "ldr q3, [x0, #16]", "tbl v2.16b, {v2.16b}, v3.16b", "tbl v3.16b, {v17.16b}, v3.16b", @@ -1272,7 +1272,7 @@ ], "ExpectedArm64ASM": [ "mov z2.q, z17.q[1]", - "ldr x0, [x28, #2680]", + "ldr x0, [x28, #2712]", "ldr q3, [x0, #32]", "tbl v2.16b, {v2.16b}, v3.16b", "tbl v3.16b, {v17.16b}, v3.16b", @@ -1289,7 +1289,7 @@ ], "ExpectedArm64ASM": [ "mov z2.q, z17.q[1]", - "ldr x0, [x28, #2680]", + "ldr x0, [x28, #2712]", "ldr q3, [x0, #48]", "tbl v2.16b, {v2.16b}, v3.16b", "tbl v3.16b, {v17.16b}, v3.16b", @@ -1328,7 +1328,7 @@ "Map 1 0b11 0x70 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2672]", + "ldr x0, [x28, #2704]", "ldr q2, [x0, #16]", "tbl v16.16b, {v17.16b}, v2.16b" ] @@ -1339,7 +1339,7 @@ "Map 1 0b11 0x70 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2672]", + "ldr x0, [x28, #2704]", "ldr q2, [x0, #32]", "tbl v16.16b, {v17.16b}, v2.16b" ] @@ -1350,7 +1350,7 @@ "Map 1 0b11 0x70 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2672]", + "ldr x0, [x28, #2704]", "ldr q2, [x0, #48]", "tbl v16.16b, {v17.16b}, v2.16b" ] @@ -1388,7 +1388,7 @@ ], "ExpectedArm64ASM": [ "mov z2.q, z17.q[1]", - "ldr x0, [x28, #2672]", + "ldr x0, [x28, #2704]", "ldr q3, [x0, #16]", "tbl v2.16b, {v2.16b}, v3.16b", "tbl v3.16b, {v17.16b}, v3.16b", @@ -1405,7 +1405,7 @@ ], "ExpectedArm64ASM": [ "mov z2.q, z17.q[1]", - "ldr x0, [x28, #2672]", + "ldr x0, [x28, #2704]", "ldr q3, [x0, #32]", "tbl v2.16b, {v2.16b}, v3.16b", "tbl v3.16b, {v17.16b}, v3.16b", @@ -1422,7 +1422,7 @@ ], "ExpectedArm64ASM": [ "mov z2.q, z17.q[1]", - "ldr x0, [x28, #2672]", + "ldr x0, [x28, #2704]", "ldr q3, [x0, #48]", "tbl v2.16b, {v2.16b}, v3.16b", "tbl v3.16b, {v17.16b}, v3.16b", @@ -2223,7 +2223,7 @@ "Map 1 0b00 0xC6 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2696]", + "ldr x0, [x28, #2728]", "ldr q2, [x0, #16]", "tbl v16.16b, {v17.16b, v18.16b}, v2.16b" ] @@ -2234,7 +2234,7 @@ "Map 1 0b00 0xC6 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2696]", + "ldr x0, [x28, #2728]", "ldr q2, [x0, #32]", "tbl v16.16b, {v17.16b, v18.16b}, v2.16b" ] @@ -2245,7 +2245,7 @@ "Map 1 0b00 0xC6 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2696]", + "ldr x0, [x28, #2728]", "ldr q2, [x0, #48]", "tbl v16.16b, {v17.16b, v18.16b}, v2.16b" ] @@ -2300,7 +2300,7 @@ "ExpectedArm64ASM": [ "mov z2.q, z17.q[1]", "mov z3.q, z18.q[1]", - "ldr x0, [x28, #2696]", + "ldr x0, [x28, #2728]", "ldr q4, [x0, #16]", "tbl v5.16b, {v17.16b, v18.16b}, v4.16b", "tbl v2.16b, {v2.16b, v3.16b}, v4.16b", @@ -2318,7 +2318,7 @@ "ExpectedArm64ASM": [ "mov z2.q, z17.q[1]", "mov z3.q, z18.q[1]", - "ldr x0, [x28, #2696]", + "ldr x0, [x28, #2728]", "ldr q4, [x0, #32]", "tbl v5.16b, {v17.16b, v18.16b}, v4.16b", "tbl v2.16b, {v2.16b, v3.16b}, v4.16b", @@ -2336,7 +2336,7 @@ "ExpectedArm64ASM": [ "mov z2.q, z17.q[1]", "mov z3.q, z18.q[1]", - "ldr x0, [x28, #2696]", + "ldr x0, [x28, #2728]", "ldr q4, [x0, #48]", "tbl v5.16b, {v17.16b, v18.16b}, v4.16b", "tbl v2.16b, {v2.16b, v3.16b}, v4.16b", @@ -2865,7 +2865,7 @@ "ExpectedArm64ASM": [ "fcvtzs w20, s16", "mov w21, #0x80000000", - "ldr s2, [x28, #3472]", + "ldr s2, [x28, #3520]", "mrs x22, nzcv", "fcmp s2, s16", "csel w4, w20, w21, gt", @@ -2880,7 +2880,7 @@ "ExpectedArm64ASM": [ "fcvtzs x20, s16", "mov x21, #0x8000000000000000", - "ldr s2, [x28, #3504]", + "ldr s2, [x28, #3552]", "mrs x22, nzcv", "fcmp s2, s16", "csel x4, x20, x21, gt", @@ -2895,7 +2895,7 @@ "ExpectedArm64ASM": [ "fcvtzs w20, d16", "mov w21, #0x80000000", - "ldr d2, [x28, #3520]", + "ldr d2, [x28, #3568]", "mrs x22, nzcv", "fcmp d2, d16", "csel w4, w20, w21, gt", @@ -2910,7 +2910,7 @@ "ExpectedArm64ASM": [ "fcvtzs x20, d16", "mov x21, #0x8000000000000000", - "ldr d2, [x28, #3552]", + "ldr d2, [x28, #3600]", "mrs x22, nzcv", "fcmp d2, d16", "csel x4, x20, x21, gt", @@ -2926,7 +2926,7 @@ "frinti s2, s16", "fcvtzs w20, s2", "mov w21, #0x80000000", - "ldr s3, [x28, #3472]", + "ldr s3, [x28, #3520]", "mrs x22, nzcv", "fcmp s3, s2", "csel w4, w20, w21, gt", @@ -2942,7 +2942,7 @@ "frinti s2, s16", "fcvtzs x20, s2", "mov x21, #0x8000000000000000", - "ldr s3, [x28, #3504]", + "ldr s3, [x28, #3552]", "mrs x22, nzcv", "fcmp s3, s2", "csel x4, x20, x21, gt", @@ -2958,7 +2958,7 @@ "frinti d2, d16", "fcvtzs w20, d2", "mov w21, #0x80000000", - "ldr d3, [x28, #3520]", + "ldr d3, [x28, #3568]", "mrs x22, nzcv", "fcmp d3, d2", "csel w4, w20, w21, gt", @@ -2974,7 +2974,7 @@ "frinti d2, d16", "fcvtzs x20, d2", "mov x21, #0x8000000000000000", - "ldr d3, [x28, #3552]", + "ldr d3, [x28, #3600]", "mrs x22, nzcv", "fcmp d3, d2", "csel x4, x20, x21, gt", @@ -3323,8 +3323,8 @@ ], "ExpectedArm64ASM": [ "frinti v2.4s, v17.4s", - "ldr q3, [x28, #3568]", - "ldr q4, [x28, #3472]", + "ldr q3, [x28, #3616]", + "ldr q4, [x28, #3520]", "fcvtzs v5.4s, v2.4s", "fcmgt v2.4s, v4.4s, v2.4s", "mov v16.16b, v2.16b", @@ -3338,9 +3338,9 @@ ], "ExpectedArm64ASM": [ "frinti z2.s, p7/m, z17.s", - "ldr x0, [x28, #2616]", + "ldr x0, [x28, #2648]", "ld1b {z3.b}, p7/z, [x0]", - "ldr x0, [x28, #2568]", + "ldr x0, [x28, #2600]", "ld1b {z4.b}, p7/z, [x0]", "fcvtzs z5.s, p7/m, z2.s", "fcmgt p0.s, p7/z, z4.s, z2.s", @@ -3358,8 +3358,8 @@ "Map 1 0b10 0x5b 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3568]", - "ldr q3, [x28, #3472]", + "ldr q2, [x28, #3616]", + "ldr q3, [x28, #3520]", "fcvtzs v4.4s, v17.4s", "fcmgt v3.4s, v3.4s, v17.4s", "mov v16.16b, v3.16b", @@ -3372,9 +3372,9 @@ "Map 1 0b10 0x5b 256-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2616]", + "ldr x0, [x28, #2648]", "ld1b {z2.b}, p7/z, [x0]", - "ldr x0, [x28, #2568]", + "ldr x0, [x28, #2600]", "ld1b {z3.b}, p7/z, [x0]", "fcvtzs z4.s, p7/m, z17.s", "fcmgt p0.s, p7/z, z3.s, z17.s", @@ -4109,7 +4109,7 @@ "Map 1 0b01 0xd0 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3120]", + "ldr q2, [x28, #3168]", "eor v2.16b, v18.16b, v2.16b", "fadd v16.2d, v17.2d, v2.2d" ] @@ -4120,7 +4120,7 @@ "Map 1 0b01 0xd0 256-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2392]", + "ldr x0, [x28, #2424]", "ld1b {z2.b}, p7/z, [x0]", "eor z2.d, z18.d, z2.d", "fadd z16.d, z17.d, z2.d" @@ -4132,7 +4132,7 @@ "Map 1 0b11 0xd0 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3088]", + "ldr q2, [x28, #3136]", "eor v2.16b, v18.16b, v2.16b", "fadd v16.4s, v17.4s, v2.4s" ] @@ -4143,7 +4143,7 @@ "Map 1 0b11 0xd0 256-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2376]", + "ldr x0, [x28, #2408]", "ld1b {z2.b}, p7/z, [x0]", "eor z2.d, z18.d, z2.d", "fadd z16.s, z17.s, z2.s" @@ -4269,7 +4269,7 @@ "Map 1 0b01 0xd7 256-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3344]", + "ldr q2, [x28, #3392]", "cmlt v3.16b, v16.16b, #0", "and v2.16b, v3.16b, v2.16b", "addp v2.16b, v2.16b, v2.16b", @@ -4284,7 +4284,7 @@ "Map 1 0b01 0xd7 256-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2504]", + "ldr x0, [x28, #2536]", "ld1b {z2.b}, p7/z, [x0]", "mrs x0, nzcv", "mov z0.d, #0", @@ -4661,8 +4661,8 @@ "Map 1 0b01 0xe6 128-bit" ], "ExpectedArm64ASM": [ - "ldr d2, [x28, #3568]", - "ldr q3, [x28, #3520]", + "ldr d2, [x28, #3616]", + "ldr q3, [x28, #3568]", "fcvtzs z4.s, p6/m, z17.d", "uzp1 z4.s, z4.s, z4.s", "mov v4.8b, v4.8b", @@ -4678,8 +4678,8 @@ "Map 1 0b01 0xe6 256-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3568]", - "ldr x0, [x28, #2592]", + "ldr q2, [x28, #3616]", + "ldr x0, [x28, #2624]", "ld1b {z3.b}, p7/z, [x0]", "fcvtzs z4.s, p7/m, z17.d", "uzp1 z4.s, z4.s, z4.s", @@ -4722,8 +4722,8 @@ ], "ExpectedArm64ASM": [ "frinti v2.2d, v17.2d", - "ldr d3, [x28, #3568]", - "ldr q4, [x28, #3520]", + "ldr d3, [x28, #3616]", + "ldr q4, [x28, #3568]", "fcvtzs z5.s, p6/m, z2.d", "uzp1 z5.s, z5.s, z5.s", "mov v5.8b, v5.8b", @@ -4740,8 +4740,8 @@ ], "ExpectedArm64ASM": [ "frinti z2.d, p7/m, z17.d", - "ldr q3, [x28, #3568]", - "ldr x0, [x28, #2592]", + "ldr q3, [x28, #3616]", + "ldr x0, [x28, #2624]", "ld1b {z4.b}, p7/z, [x0]", "fcvtzs z5.s, p7/m, z2.d", "uzp1 z5.s, z5.s, z5.s", diff --git a/unittests/InstructionCountCI/VEX_map1_FRINTTS.json b/unittests/InstructionCountCI/VEX_map1_FRINTTS.json index c20308a7f..cb3dcc854 100644 --- a/unittests/InstructionCountCI/VEX_map1_FRINTTS.json +++ b/unittests/InstructionCountCI/VEX_map1_FRINTTS.json @@ -112,9 +112,9 @@ ], "ExpectedArm64ASM": [ "frinti z2.s, p7/m, z17.s", - "ldr x0, [x28, #2616]", + "ldr x0, [x28, #2648]", "ld1b {z3.b}, p7/z, [x0]", - "ldr x0, [x28, #2568]", + "ldr x0, [x28, #2600]", "ld1b {z4.b}, p7/z, [x0]", "fcvtzs z5.s, p7/m, z2.s", "fcmgt p0.s, p7/z, z4.s, z2.s", @@ -142,9 +142,9 @@ "Map 1 0b10 0x5b 256-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2616]", + "ldr x0, [x28, #2648]", "ld1b {z2.b}, p7/z, [x0]", - "ldr x0, [x28, #2568]", + "ldr x0, [x28, #2600]", "ld1b {z3.b}, p7/z, [x0]", "fcvtzs z4.s, p7/m, z17.s", "fcmgt p0.s, p7/z, z3.s, z17.s", @@ -173,8 +173,8 @@ "Map 1 0b01 0xe6 256-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3568]", - "ldr x0, [x28, #2592]", + "ldr q2, [x28, #3616]", + "ldr x0, [x28, #2624]", "ld1b {z3.b}, p7/z, [x0]", "fcvtzs z4.s, p7/m, z17.d", "uzp1 z4.s, z4.s, z4.s", @@ -208,8 +208,8 @@ ], "ExpectedArm64ASM": [ "frinti z2.d, p7/m, z17.d", - "ldr q3, [x28, #3568]", - "ldr x0, [x28, #2592]", + "ldr q3, [x28, #3616]", + "ldr x0, [x28, #2624]", "ld1b {z4.b}, p7/z, [x0]", "fcvtzs z5.s, p7/m, z2.d", "uzp1 z5.s, z5.s, z5.s", diff --git a/unittests/InstructionCountCI/VEX_map2.json b/unittests/InstructionCountCI/VEX_map2.json index 988e3bc47..b77149139 100644 --- a/unittests/InstructionCountCI/VEX_map2.json +++ b/unittests/InstructionCountCI/VEX_map2.json @@ -1601,7 +1601,7 @@ "Map 2 0b01 0x41 256-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3056]", + "ldr q2, [x28, #3104]", "zip1 v3.8h, v2.8h, v17.8h", "zip2 v2.8h, v2.8h, v17.8h", "umin v2.4s, v3.4s, v2.4s", @@ -3655,7 +3655,7 @@ "Map 2 0b01 0x96 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3088]", + "ldr q2, [x28, #3136]", "eor v2.16b, v17.16b, v2.16b", "fmla v2.4s, v16.4s, v18.4s", "mov v16.16b, v2.16b" @@ -3667,7 +3667,7 @@ "Map 2 0b01 0x96 256-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2376]", + "ldr x0, [x28, #2408]", "ld1b {z2.b}, p7/z, [x0]", "eor z2.d, z17.d, z2.d", "mov z0.d, z2.d", @@ -3681,7 +3681,7 @@ "Map 2 0b01 0x96 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3120]", + "ldr q2, [x28, #3168]", "eor v2.16b, v17.16b, v2.16b", "fmla v2.2d, v16.2d, v18.2d", "mov v16.16b, v2.16b" @@ -3693,7 +3693,7 @@ "Map 2 0b01 0x96 256-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2392]", + "ldr x0, [x28, #2424]", "ld1b {z2.b}, p7/z, [x0]", "eor z2.d, z17.d, z2.d", "mov z0.d, z2.d", @@ -3707,7 +3707,7 @@ "Map 2 0b01 0x97 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3152]", + "ldr q2, [x28, #3200]", "eor v2.16b, v17.16b, v2.16b", "fmla v2.4s, v16.4s, v18.4s", "mov v16.16b, v2.16b" @@ -3719,7 +3719,7 @@ "Map 2 0b01 0x97 256-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2408]", + "ldr x0, [x28, #2440]", "ld1b {z2.b}, p7/z, [x0]", "eor z2.d, z17.d, z2.d", "mov z0.d, z2.d", @@ -3733,7 +3733,7 @@ "Map 2 0b01 0x97 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3184]", + "ldr q2, [x28, #3232]", "eor v2.16b, v17.16b, v2.16b", "fmla v2.2d, v16.2d, v18.2d", "mov v16.16b, v2.16b" @@ -3745,7 +3745,7 @@ "Map 2 0b01 0x97 256-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2424]", + "ldr x0, [x28, #2456]", "ld1b {z2.b}, p7/z, [x0]", "eor z2.d, z17.d, z2.d", "mov z0.d, z2.d", @@ -4607,7 +4607,7 @@ "Map 2 0b01 0xa6 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3088]", + "ldr q2, [x28, #3136]", "eor v2.16b, v18.16b, v2.16b", "fmla v2.4s, v17.4s, v16.4s", "mov v16.16b, v2.16b" @@ -4619,7 +4619,7 @@ "Map 2 0b01 0xa6 256-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2376]", + "ldr x0, [x28, #2408]", "ld1b {z2.b}, p7/z, [x0]", "eor z2.d, z18.d, z2.d", "mov z0.d, z2.d", @@ -4633,7 +4633,7 @@ "Map 2 0b01 0xa6 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3120]", + "ldr q2, [x28, #3168]", "eor v2.16b, v18.16b, v2.16b", "fmla v2.2d, v17.2d, v16.2d", "mov v16.16b, v2.16b" @@ -4645,7 +4645,7 @@ "Map 2 0b01 0xa6 256-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2392]", + "ldr x0, [x28, #2424]", "ld1b {z2.b}, p7/z, [x0]", "eor z2.d, z18.d, z2.d", "mov z0.d, z2.d", @@ -4659,7 +4659,7 @@ "Map 2 0b01 0xa7 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3152]", + "ldr q2, [x28, #3200]", "eor v2.16b, v18.16b, v2.16b", "fmla v2.4s, v17.4s, v16.4s", "mov v16.16b, v2.16b" @@ -4671,7 +4671,7 @@ "Map 2 0b01 0xa7 256-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2408]", + "ldr x0, [x28, #2440]", "ld1b {z2.b}, p7/z, [x0]", "eor z2.d, z18.d, z2.d", "mov z0.d, z2.d", @@ -4685,7 +4685,7 @@ "Map 2 0b01 0xa7 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3184]", + "ldr q2, [x28, #3232]", "eor v2.16b, v18.16b, v2.16b", "fmla v2.2d, v17.2d, v16.2d", "mov v16.16b, v2.16b" @@ -4697,7 +4697,7 @@ "Map 2 0b01 0xa7 256-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2424]", + "ldr x0, [x28, #2456]", "ld1b {z2.b}, p7/z, [x0]", "eor z2.d, z18.d, z2.d", "mov z0.d, z2.d", @@ -4711,7 +4711,7 @@ "Map 2 0b01 0xb6 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3088]", + "ldr q2, [x28, #3136]", "eor v2.16b, v16.16b, v2.16b", "fmla v2.4s, v17.4s, v18.4s", "mov v16.16b, v2.16b" @@ -4723,7 +4723,7 @@ "Map 2 0b01 0xb6 256-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2376]", + "ldr x0, [x28, #2408]", "ld1b {z2.b}, p7/z, [x0]", "eor z2.d, z16.d, z2.d", "mov z16.d, z2.d", @@ -4736,7 +4736,7 @@ "Map 2 0b01 0xb6 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3120]", + "ldr q2, [x28, #3168]", "eor v2.16b, v16.16b, v2.16b", "fmla v2.2d, v17.2d, v18.2d", "mov v16.16b, v2.16b" @@ -4748,7 +4748,7 @@ "Map 2 0b01 0xb6 256-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2392]", + "ldr x0, [x28, #2424]", "ld1b {z2.b}, p7/z, [x0]", "eor z2.d, z16.d, z2.d", "mov z16.d, z2.d", @@ -4761,7 +4761,7 @@ "Map 2 0b01 0xb7 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3152]", + "ldr q2, [x28, #3200]", "eor v2.16b, v16.16b, v2.16b", "fmla v2.4s, v17.4s, v18.4s", "mov v16.16b, v2.16b" @@ -4773,7 +4773,7 @@ "Map 2 0b01 0xb7 256-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2408]", + "ldr x0, [x28, #2440]", "ld1b {z2.b}, p7/z, [x0]", "eor z2.d, z16.d, z2.d", "mov z16.d, z2.d", @@ -4786,7 +4786,7 @@ "Map 2 0b01 0xb7 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3184]", + "ldr q2, [x28, #3232]", "eor v2.16b, v16.16b, v2.16b", "fmla v2.2d, v17.2d, v18.2d", "mov v16.16b, v2.16b" @@ -4798,7 +4798,7 @@ "Map 2 0b01 0xb7 256-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2424]", + "ldr x0, [x28, #2456]", "ld1b {z2.b}, p7/z, [x0]", "eor z2.d, z16.d, z2.d", "mov z16.d, z2.d", diff --git a/unittests/InstructionCountCI/VEX_map3.json b/unittests/InstructionCountCI/VEX_map3.json index 9becf3ec3..18385ecf2 100644 --- a/unittests/InstructionCountCI/VEX_map3.json +++ b/unittests/InstructionCountCI/VEX_map3.json @@ -4582,7 +4582,7 @@ "Map 3 0b01 0xdf 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3232]", + "ldr q2, [x28, #3280]", "movi v3.2d, #0x0", "mov v16.16b, v17.16b", "aese v16.16b, v3.16b", @@ -4595,7 +4595,7 @@ "Map 3 0b01 0xdf 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3232]", + "ldr q2, [x28, #3280]", "movi v3.2d, #0x0", "mov v16.16b, v17.16b", "aese v16.16b, v3.16b", diff --git a/unittests/InstructionCountCI/x87.json b/unittests/InstructionCountCI/x87.json index 6d706bb89..f99f52979 100644 --- a/unittests/InstructionCountCI/x87.json +++ b/unittests/InstructionCountCI/x87.json @@ -2467,7 +2467,7 @@ "ldrb w20, [x28, #1051]", "add x20, x28, x20, lsl #4", "ldr q2, [x20, #1056]", - "ldr q3, [x28, #3600]", + "ldr q3, [x28, #3648]", "eor v2.16b, v2.16b, v3.16b", "str q2, [x20, #1056]" ] @@ -2481,7 +2481,7 @@ "ldrb w20, [x28, #1051]", "add x20, x28, x20, lsl #4", "ldr q2, [x20, #1056]", - "ldr q3, [x28, #3600]", + "ldr q3, [x28, #3648]", "bic v2.16b, v2.16b, v3.16b", "str q2, [x20, #1056]" ] @@ -2547,7 +2547,7 @@ "0xd9 11b 0xe8 /5" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3376]", + "ldr q2, [x28, #3424]", "ldrb w20, [x28, #1051]", "add w20, w20, #0x7 (7)", "and w20, w20, #0x7", @@ -2567,7 +2567,7 @@ "0xd9 11b 0xe9 /5" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3392]", + "ldr q2, [x28, #3440]", "ldrb w20, [x28, #1051]", "add w20, w20, #0x7 (7)", "and w20, w20, #0x7", @@ -2587,7 +2587,7 @@ "0xd9 11b 0xea /5" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3408]", + "ldr q2, [x28, #3456]", "ldrb w20, [x28, #1051]", "add w20, w20, #0x7 (7)", "and w20, w20, #0x7", @@ -2607,7 +2607,7 @@ "0xd9 11b 0xeb /5" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3424]", + "ldr q2, [x28, #3472]", "ldrb w20, [x28, #1051]", "add w20, w20, #0x7 (7)", "and w20, w20, #0x7", @@ -2627,7 +2627,7 @@ "0xd9 11b 0xec /5" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3440]", + "ldr q2, [x28, #3488]", "ldrb w20, [x28, #1051]", "add w20, w20, #0x7 (7)", "and w20, w20, #0x7", @@ -2647,7 +2647,7 @@ "0xd9 11b 0xed /5" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3456]", + "ldr q2, [x28, #3504]", "ldrb w20, [x28, #1051]", "add w20, w20, #0x7 (7)", "and w20, w20, #0x7", @@ -2741,7 +2741,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", - "ldr q3, [x28, #3376]", + "ldr q3, [x28, #3424]", "add w20, w20, #0x7 (7)", "and w20, w20, #0x7", "strb wzr, [x28, #1050]", @@ -2772,8 +2772,8 @@ "str x30, [sp, #-16]!", "mov v0.16b, v3.16b", "mov v1.16b, v2.16b", - "ldr x0, [x28, #2104]", - "ldr x3, [x28, #2112]", + "ldr x0, [x28, #2120]", + "ldr x3, [x28, #2128]", "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", @@ -2835,8 +2835,8 @@ "str x30, [sp, #-16]!", "mov v0.16b, v3.16b", "mov v1.16b, v2.16b", - "ldr x0, [x28, #2120]", - "ldr x3, [x28, #2128]", + "ldr x0, [x28, #2136]", + "ldr x3, [x28, #2144]", "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", @@ -2884,8 +2884,8 @@ "str x30, [sp, #-16]!", "mov v0.16b, v3.16b", "mov v1.16b, v2.16b", - "ldr x0, [x28, #2136]", - "ldr x3, [x28, #2144]", + "ldr x0, [x28, #2152]", + "ldr x3, [x28, #2160]", "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", @@ -2894,38 +2894,28 @@ ] }, "fyl2xp1": { - "ExpectedInstructionCount": 27, + "ExpectedInstructionCount": 17, "Comment": [ "0xd9 11b 0xf9 /7" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3376]", "ldrb w20, [x28, #1051]", - "add x21, x28, x20, lsl #4", - "ldr q3, [x21, #1056]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x22, x28, x21, lsl #4", + "ldr q2, [x22, #1056]", + "add x20, x28, x20, lsl #4", + "ldr q3, [x20, #1056]", "str x30, [sp, #-16]!", "mov v0.16b, v3.16b", "mov v1.16b, v2.16b", - "ldr x0, [x28, #2024]", - "ldr x3, [x28, #2032]", + "ldr x0, [x28, #2104]", + "ldr x3, [x28, #2112]", "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "add x22, x28, x20, lsl #4", - "ldr q3, [x22, #1056]", - "str x30, [sp, #-16]!", - "mov v0.16b, v2.16b", - "mov v1.16b, v3.16b", - "ldr x0, [x28, #2088]", - "ldr x3, [x28, #2096]", - "blr x0", - "ldr x30, [sp], #16", - "mov v3.16b, v0.16b", - "strb w20, [x28, #1051]", - "str q3, [x22, #1056]", - "str q2, [x21, #1056]" + "strb w21, [x28, #1051]", + "str q2, [x22, #1056]" ] }, "fsqrt": { @@ -3013,8 +3003,8 @@ "str x30, [sp, #-16]!", "mov v0.16b, v3.16b", "mov v1.16b, v2.16b", - "ldr x0, [x28, #2152]", - "ldr x3, [x28, #2160]", + "ldr x0, [x28, #2168]", + "ldr x3, [x28, #2176]", "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", diff --git a/unittests/InstructionCountCI/x87_f64.json b/unittests/InstructionCountCI/x87_f64.json index 7b4292f73..956109968 100644 --- a/unittests/InstructionCountCI/x87_f64.json +++ b/unittests/InstructionCountCI/x87_f64.json @@ -2169,7 +2169,7 @@ "add x20, x28, x20, lsl #4", "ldr d2, [x20, #1056]", "fmov d0, d2", - "ldr x0, [x28, #3008]", + "ldr x0, [x28, #3040]", "str x30, [sp, #-16]!", "blr x0", "ldr x30, [sp], #16", @@ -2192,7 +2192,7 @@ "ldr d3, [x20, #1056]", "fmov d0, d3", "fmov d1, d2", - "ldr x0, [x28, #3032]", + "ldr x0, [x28, #3064]", "str x30, [sp, #-16]!", "blr x0", "ldr x30, [sp], #16", @@ -2211,7 +2211,7 @@ "add x21, x28, x20, lsl #4", "ldr d2, [x21, #1056]", "fmov d0, d2", - "ldr x0, [x28, #3000]", + "ldr x0, [x28, #3032]", "str x30, [sp, #-16]!", "blr x0", "ldr x30, [sp], #16", @@ -2247,7 +2247,7 @@ "ldr d3, [x21, #1056]", "fmov d0, d3", "fmov d1, d2", - "ldr x0, [x28, #3024]", + "ldr x0, [x28, #3056]", "str x30, [sp, #-16]!", "blr x0", "ldr x30, [sp], #16", @@ -2319,7 +2319,7 @@ "ldr d3, [x20, #1056]", "fmov d0, d3", "fmov d1, d2", - "ldr x0, [x28, #3048]", + "ldr x0, [x28, #3088]", "str x30, [sp, #-16]!", "blr x0", "ldr x30, [sp], #16", @@ -2367,7 +2367,7 @@ "ldr d3, [x20, #1056]", "fmov d0, d3", "fmov d1, d2", - "ldr x0, [x28, #3040]", + "ldr x0, [x28, #3080]", "str x30, [sp, #-16]!", "blr x0", "ldr x30, [sp], #16", @@ -2377,31 +2377,27 @@ ] }, "fyl2xp1": { - "ExpectedInstructionCount": 20, + "ExpectedInstructionCount": 16, "Comment": [ "0xd9 11b 0xf9 /7" ], "ExpectedArm64ASM": [ - "mov x20, #0x3ff0000000000000", - "fmov d2, x20", "ldrb w20, [x28, #1051]", - "add x21, x28, x20, lsl #4", - "ldr d3, [x21, #1056]", - "fadd d2, d3, d2", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "add x22, x28, x20, lsl #4", - "ldr d3, [x22, #1056]", - "fmov d0, d2", - "fmov d1, d3", - "ldr x0, [x28, #3032]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x22, x28, x21, lsl #4", + "ldr d2, [x22, #1056]", + "add x20, x28, x20, lsl #4", + "ldr d3, [x20, #1056]", + "fmov d0, d3", + "fmov d1, d2", + "ldr x0, [x28, #3072]", "str x30, [sp, #-16]!", "blr x0", "ldr x30, [sp], #16", - "fmov d3, d0", - "strb w20, [x28, #1051]", - "str d3, [x22, #1056]", - "str d2, [x21, #1056]" + "fmov d2, d0", + "strb w21, [x28, #1051]", + "str d2, [x22, #1056]" ] }, "fsqrt": { @@ -2427,13 +2423,13 @@ "add x21, x28, x20, lsl #4", "ldr d2, [x21, #1056]", "fmov d0, d2", - "ldr x0, [x28, #2984]", + "ldr x0, [x28, #3016]", "str x30, [sp, #-16]!", "blr x0", "ldr x30, [sp], #16", "fmov d3, d0", "fmov d0, d2", - "ldr x0, [x28, #2992]", + "ldr x0, [x28, #3024]", "str x30, [sp, #-16]!", "blr x0", "ldr x30, [sp], #16", @@ -2480,7 +2476,7 @@ "ldr d3, [x20, #1056]", "fmov d0, d3", "fmov d1, d2", - "ldr x0, [x28, #3016]", + "ldr x0, [x28, #3048]", "str x30, [sp, #-16]!", "blr x0", "ldr x30, [sp], #16", @@ -2498,7 +2494,7 @@ "add x20, x28, x20, lsl #4", "ldr d2, [x20, #1056]", "fmov d0, d2", - "ldr x0, [x28, #2984]", + "ldr x0, [x28, #3016]", "str x30, [sp, #-16]!", "blr x0", "ldr x30, [sp], #16", @@ -2517,7 +2513,7 @@ "add x20, x28, x20, lsl #4", "ldr d2, [x20, #1056]", "fmov d0, d2", - "ldr x0, [x28, #2992]", + "ldr x0, [x28, #3024]", "str x30, [sp, #-16]!", "blr x0", "ldr x30, [sp], #16",