From 35ee12e7e9c875068efe71344e4bfd614578345d Mon Sep 17 00:00:00 2001 From: Lioncache Date: Thu, 27 Mar 2025 17:26:56 -0400 Subject: [PATCH] Addressing: Amend binary AND into logical AND in SelectAddressMode() Bitwise AND here is a little odd and was likely intended to be a logical AND. --- FEXCore/Source/Interface/Core/Addressing.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/FEXCore/Source/Interface/Core/Addressing.cpp b/FEXCore/Source/Interface/Core/Addressing.cpp index ae4155125..2d804a0b2 100644 --- a/FEXCore/Source/Interface/Core/Addressing.cpp +++ b/FEXCore/Source/Interface/Core/Addressing.cpp @@ -127,7 +127,7 @@ AddressMode SelectAddressMode(IREmitter* IREmit, AddressMode A, IR::OpSize GPRSi } else { if (OffsetIsSIMM9 || OffsetIsUnsignedScaled) { return InlineImmOffsetLoadstore(A); - } else if (!Is32Bit && A.Base && (A.Index || A.Segment) & !A.Offset && (A.IndexScale == 1 || A.IndexScale == AccessSizeAsImm)) { + } else if (!Is32Bit && A.Base && (A.Index || A.Segment) && !A.Offset && (A.IndexScale == 1 || A.IndexScale == AccessSizeAsImm)) { return ScaledRegisterLoadstore(A); } }